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a06ea964
NC		 1/* aarch64-tbl.h -- AArch64 opcode description table and instruction
2 operand description table.
6f2750fe 3 Copyright (C) 2012-2016 Free Software Foundation, Inc.
a06ea964
NC		 4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22#include "aarch64-opc.h"
23
24/* Operand type. */
25
26#define OPND(x) AARCH64_OPND_##x
27#define OP0() {}
28#define OP1(a) {OPND(a)}
29#define OP2(a,b) {OPND(a), OPND(b)}
30#define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
31#define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
32#define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
33
34#define QLF(x) AARCH64_OPND_QLF_##x
35#define QLF1(a) {QLF(a)}
36#define QLF2(a,b) {QLF(a), QLF(b)}
37#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
38#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
39#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
40
41/* Qualifiers list. */
42
43/* e.g. MSR <systemreg>, <Xt>. */
44#define QL_SRC_X \
45{ \
46 QLF2(NIL,X), \
47}
48
49/* e.g. MRS <Xt>, <systemreg>. */
50#define QL_DST_X \
51{ \
52 QLF2(X,NIL), \
53}
54
55/* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
56#define QL_SYS \
57{ \
58 QLF5(NIL,NIL,NIL,NIL,X), \
59}
60
61/* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
62#define QL_SYSL \
63{ \
64 QLF5(X,NIL,NIL,NIL,NIL), \
65}
66
67/* e.g. ADRP <Xd>, <label>. */
68#define QL_ADRP \
69{ \
70 QLF2(X,NIL), \
71}
72
73/* e.g. B.<cond> <label>. */
74#define QL_PCREL_NIL \
75{ \
76 QLF1(NIL), \
77}
78
79/* e.g. TBZ <Xt>, #<imm>, <label>. */
80#define QL_PCREL_14 \
81{ \
82 QLF3(X,imm_0_63,NIL), \
83}
84
85/* e.g. BL <label>. */
86#define QL_PCREL_26 \
87{ \
88 QLF1(NIL), \
89}
90
91/* e.g. LDRSW <Xt>, <label>. */
92#define QL_X_PCREL \
93{ \
94 QLF2(X,NIL), \
95}
96
97/* e.g. LDR <Wt>, <label>. */
98#define QL_R_PCREL \
99{ \
100 QLF2(W,NIL), \
101 QLF2(X,NIL), \
102}
103
104/* e.g. LDR <Dt>, <label>. */
105#define QL_FP_PCREL \
106{ \
107 QLF2(S_S,NIL), \
108 QLF2(S_D,NIL), \
109 QLF2(S_Q,NIL), \
110}
111
112/* e.g. PRFM <prfop>, <label>. */
113#define QL_PRFM_PCREL \
114{ \
115 QLF2(NIL,NIL), \
116}
117
118/* e.g. BR <Xn>. */
119#define QL_I1X \
120{ \
121 QLF1(X), \
122}
123
124/* e.g. RBIT <Wd>, <Wn>. */
125#define QL_I2SAME \
126{ \
127 QLF2(W,W), \
128 QLF2(X,X), \
129}
130
131/* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */
132#define QL_I2_EXT \
133{ \
134 QLF2(W,W), \
135 QLF2(X,W), \
136 QLF2(X,X), \
137}
138
139/* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */
140#define QL_I2SP \
141{ \
142 QLF2(WSP,W), \
143 QLF2(W,WSP), \
144 QLF2(SP,X), \
145 QLF2(X,SP), \
146}
147
148/* e.g. REV <Wd>, <Wn>. */
149#define QL_I2SAMEW \
150{ \
151 QLF2(W,W), \
152}
153
154/* e.g. REV32 <Xd>, <Xn>. */
155#define QL_I2SAMEX \
156{ \
157 QLF2(X,X), \
158}
159
160#define QL_I2SAMER \
161{ \
162 QLF2(W,W), \
163 QLF2(X,X), \
164}
165
e60bb1dd
YZ		 166/* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
167#define QL_I3SAMEW \
168{ \
169 QLF3(W,W,W), \
170}
171
a06ea964
NC		 172/* e.g. SMULH <Xd>, <Xn>, <Xm>. */
173#define QL_I3SAMEX \
174{ \
175 QLF3(X,X,X), \
176}
177
e60bb1dd
YZ		 178/* e.g. CRC32X <Wd>, <Wn>, <Xm>. */
179#define QL_I3WWX \
180{ \
181 QLF3(W,W,X), \
182}
183
a06ea964
NC		 184/* e.g. UDIV <Xd>, <Xn>, <Xm>. */
185#define QL_I3SAMER \
186{ \
187 QLF3(W,W,W), \
188 QLF3(X,X,X), \
189}
190
191/* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */
192#define QL_I3_EXT \
193{ \
194 QLF3(W,W,W), \
195 QLF3(X,X,W), \
196 QLF3(X,X,X), \
197}
198
199/* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */
200#define QL_I4SAMER \
201{ \
202 QLF4(W,W,W,W), \
203 QLF4(X,X,X,X), \
204}
205
206/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
207#define QL_I3SAMEL \
208{ \
209 QLF3(X,W,W), \
210}
211
212/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
213#define QL_I4SAMEL \
214{ \
215 QLF4(X,W,W,X), \
216}
217
218/* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */
219#define QL_CSEL \
220{ \
221 QLF4(W, W, W, NIL), \
222 QLF4(X, X, X, NIL), \
223}
224
225/* e.g. CSET <Wd>, <cond>. */
226#define QL_DST_R \
227{ \
228 QLF2(W, NIL), \
229 QLF2(X, NIL), \
230}
231
232/* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */
233#define QL_BF \
234{ \
235 QLF4(W,W,imm_0_31,imm_0_31), \
236 QLF4(X,X,imm_0_63,imm_0_63), \
237}
238
d685192a
MW		 239/* e.g. BFC <Wd>, #<immr>, #<imms>. */
240#define QL_BF1 \
241{ \
242 QLF3 (W, imm_0_31, imm_1_32), \
243 QLF3 (X, imm_0_63, imm_1_64), \
244}
245
a06ea964
NC		 246/* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
247#define QL_BF2 \
248{ \
249 QLF4(W,W,imm_0_31,imm_1_32), \
250 QLF4(X,X,imm_0_63,imm_1_64), \
251}
252
253/* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */
254#define QL_FIX2FP \
255{ \
256 QLF3(S_D,W,imm_1_32), \
257 QLF3(S_S,W,imm_1_32), \
258 QLF3(S_D,X,imm_1_64), \
259 QLF3(S_S,X,imm_1_64), \
260}
261
622b9eb1
MW		 262/* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */
263#define QL_FIX2FP_H \
264{ \
265 QLF3 (S_H, W, imm_1_32), \
266 QLF3 (S_H, X, imm_1_64), \
267}
268
a06ea964
NC		 269/* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */
270#define QL_FP2FIX \
271{ \
272 QLF3(W,S_D,imm_1_32), \
273 QLF3(W,S_S,imm_1_32), \
274 QLF3(X,S_D,imm_1_64), \
275 QLF3(X,S_S,imm_1_64), \
276}
277
622b9eb1
MW		 278/* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */
279#define QL_FP2FIX_H \
280{ \
281 QLF3 (W, S_H, imm_1_32), \
282 QLF3 (X, S_H, imm_1_64), \
283}
284
a06ea964
NC		 285/* e.g. SCVTF <Dd>, <Wn>. */
286#define QL_INT2FP \
287{ \
288 QLF2(S_D,W), \
289 QLF2(S_S,W), \
290 QLF2(S_D,X), \
291 QLF2(S_S,X), \
292}
293
622b9eb1
MW		 294/* e.g. SCVTF <Hd>, <Wn>. */
295#define QL_INT2FP_H \
296{ \
297 QLF2 (S_H, W), \
298 QLF2 (S_H, X), \
299}
300
a06ea964
NC		 301/* e.g. FCVTNS <Xd>, <Dn>. */
302#define QL_FP2INT \
303{ \
304 QLF2(W,S_D), \
305 QLF2(W,S_S), \
306 QLF2(X,S_D), \
307 QLF2(X,S_S), \
308}
309
622b9eb1
MW		 310/* e.g. FCVTNS <Hd>, <Wn>. */
311#define QL_FP2INT_H \
312{ \
313 QLF2 (W, S_H), \
314 QLF2 (X, S_H), \
315}
316
a06ea964
NC		 317/* e.g. FMOV <Xd>, <Vn>.D[1]. */
318#define QL_XVD1 \
319{ \
320 QLF2(X,S_D), \
321}
322
323/* e.g. FMOV <Vd>.D[1], <Xn>. */
324#define QL_VD1X \
325{ \
326 QLF2(S_D,X), \
327}
328
329/* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */
330#define QL_EXTR \
331{ \
332 QLF4(W,W,W,imm_0_31), \
333 QLF4(X,X,X,imm_0_63), \
334}
335
336/* e.g. LSL <Wd>, <Wn>, #<uimm>. */
337#define QL_SHIFT \
338{ \
339 QLF3(W,W,imm_0_31), \
340 QLF3(X,X,imm_0_63), \
341}
342
343/* e.g. UXTH <Xd>, <Wn>. */
344#define QL_EXT \
345{ \
346 QLF2(W,W), \
347 QLF2(X,W), \
348}
349
350/* e.g. UXTW <Xd>, <Wn>. */
351#define QL_EXT_W \
352{ \
353 QLF2(X,W), \
354}
355
356/* e.g. SQSHL <V><d>, <V><n>, #<shift>. */
357#define QL_SSHIFT \
358{ \
359 QLF3(S_B , S_B , S_B ), \
360 QLF3(S_H , S_H , S_H ), \
361 QLF3(S_S , S_S , S_S ), \
362 QLF3(S_D , S_D , S_D ) \
363}
364
365/* e.g. SSHR <V><d>, <V><n>, #<shift>. */
366#define QL_SSHIFT_D \
367{ \
368 QLF3(S_D , S_D , S_D ) \
369}
370
371/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
372#define QL_SSHIFT_SD \
373{ \
374 QLF3(S_S , S_S , S_S ), \
375 QLF3(S_D , S_D , S_D ) \
376}
377
4fd0a9fd
MW		 378/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
379#define QL_SSHIFT_H \
380{ \
381 QLF3 (S_H, S_H, S_H) \
382}
383
a06ea964
NC		 384/* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
385#define QL_SSHIFTN \
386{ \
387 QLF3(S_B , S_H , S_B ), \
388 QLF3(S_H , S_S , S_H ), \
389 QLF3(S_S , S_D , S_S ), \
390}
391
392/* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>.
393 The register operand variant qualifiers are deliberately used for the
394 immediate operand to ease the operand encoding/decoding and qualifier
395 sequence matching. */
396#define QL_VSHIFT \
397{ \
398 QLF3(V_8B , V_8B , V_8B ), \
399 QLF3(V_16B, V_16B, V_16B), \
400 QLF3(V_4H , V_4H , V_4H ), \
401 QLF3(V_8H , V_8H , V_8H ), \
402 QLF3(V_2S , V_2S , V_2S ), \
403 QLF3(V_4S , V_4S , V_4S ), \
404 QLF3(V_2D , V_2D , V_2D ) \
405}
406
407/* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
408#define QL_VSHIFT_SD \
409{ \
410 QLF3(V_2S , V_2S , V_2S ), \
411 QLF3(V_4S , V_4S , V_4S ), \
412 QLF3(V_2D , V_2D , V_2D ) \
413}
414
b5b0f34c
MW		 415/* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
416#define QL_VSHIFT_H \
417{ \
418 QLF3 (V_4H, V_4H, V_4H), \
419 QLF3 (V_8H, V_8H, V_8H) \
420}
421
a06ea964
NC		 422/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
423#define QL_VSHIFTN \
424{ \
425 QLF3(V_8B , V_8H , V_8B ), \
426 QLF3(V_4H , V_4S , V_4H ), \
427 QLF3(V_2S , V_2D , V_2S ), \
428}
429
430/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
431#define QL_VSHIFTN2 \
432{ \
433 QLF3(V_16B, V_8H, V_16B), \
434 QLF3(V_8H , V_4S , V_8H ), \
435 QLF3(V_4S , V_2D , V_4S ), \
436}
437
438/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.
439 the 3rd qualifier is used to help the encoding. */
440#define QL_VSHIFTL \
441{ \
442 QLF3(V_8H , V_8B , V_8B ), \
443 QLF3(V_4S , V_4H , V_4H ), \
444 QLF3(V_2D , V_2S , V_2S ), \
445}
446
447/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
448#define QL_VSHIFTL2 \
449{ \
450 QLF3(V_8H , V_16B, V_16B), \
451 QLF3(V_4S , V_8H , V_8H ), \
452 QLF3(V_2D , V_4S , V_4S ), \
453}
454
455/* e.g. TBL. */
456#define QL_TABLE \
457{ \
458 QLF3(V_8B , V_16B, V_8B ), \
459 QLF3(V_16B, V_16B, V_16B), \
460}
461
462/* e.g. SHA1H. */
463#define QL_2SAMES \
464{ \
465 QLF2(S_S, S_S), \
466}
467
468/* e.g. ABS <V><d>, <V><n>. */
469#define QL_2SAMED \
470{ \
471 QLF2(S_D, S_D), \
472}
473
474/* e.g. CMGT <V><d>, <V><n>, #0. */
475#define QL_SISD_CMP_0 \
476{ \
477 QLF3(S_D, S_D, NIL), \
478}
479
480/* e.g. FCMEQ <V><d>, <V><n>, #0. */
481#define QL_SISD_FCMP_0 \
482{ \
483 QLF3(S_S, S_S, NIL), \
484 QLF3(S_D, S_D, NIL), \
485}
486
80776b29
MW		 487/* e.g. FCMEQ <V><d>, <V><n>, #0. */
488#define QL_SISD_FCMP_H_0 \
489{ \
490 QLF3 (S_H, S_H, NIL), \
491}
492
a06ea964
NC		 493/* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
494#define QL_SISD_PAIR \
495{ \
496 QLF2(S_S, V_2S), \
497 QLF2(S_D, V_2D), \
498}
499
b195470d
MW		 500/* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
501#define QL_SISD_PAIR_H \
502{ \
503 QLF2 (S_H, V_2H), \
504}
505
a06ea964
NC		 506/* e.g. ADDP <V><d>, <Vn>.<T>. */
507#define QL_SISD_PAIR_D \
508{ \
509 QLF2(S_D, V_2D), \
510}
511
512/* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */
513#define QL_S_2SAME \
514{ \
515 QLF2(S_B, S_B), \
516 QLF2(S_H, S_H), \
517 QLF2(S_S, S_S), \
518 QLF2(S_D, S_D), \
519}
520
521/* e.g. FCVTNS <V><d>, <V><n>. */
522#define QL_S_2SAMESD \
523{ \
524 QLF2(S_S, S_S), \
525 QLF2(S_D, S_D), \
526}
527
80776b29
MW		 528/* e.g. FCVTNS <V><d>, <V><n>. */
529#define QL_S_2SAMEH \
530{ \
531 QLF2 (S_H, S_H), \
532}
533
a06ea964
NC		 534/* e.g. SQXTN <Vb><d>, <Va><n>. */
535#define QL_SISD_NARROW \
536{ \
537 QLF2(S_B, S_H), \
538 QLF2(S_H, S_S), \
539 QLF2(S_S, S_D), \
540}
541
542/* e.g. FCVTXN <Vb><d>, <Va><n>. */
543#define QL_SISD_NARROW_S \
544{ \
545 QLF2(S_S, S_D), \
546}
547
548/* e.g. FCVT. */
549#define QL_FCVT \
550{ \
551 QLF2(S_S, S_H), \
552 QLF2(S_S, S_D), \
553 QLF2(S_D, S_H), \
554 QLF2(S_D, S_S), \
555 QLF2(S_H, S_S), \
556 QLF2(S_H, S_D), \
557}
558
559/* FMOV <Dd>, <Dn>. */
560#define QL_FP2 \
561{ \
562 QLF2(S_S, S_S), \
563 QLF2(S_D, S_D), \
564}
565
622b9eb1
MW		 566/* FMOV <Hd>, <Hn>. */
567#define QL_FP2_H \
568{ \
569 QLF2 (S_H, S_H), \
570}
571
a06ea964
NC		 572/* e.g. SQADD <V><d>, <V><n>, <V><m>. */
573#define QL_S_3SAME \
574{ \
575 QLF3(S_B, S_B, S_B), \
576 QLF3(S_H, S_H, S_H), \
577 QLF3(S_S, S_S, S_S), \
578 QLF3(S_D, S_D, S_D), \
579}
580
581/* e.g. CMGE <V><d>, <V><n>, <V><m>. */
582#define QL_S_3SAMED \
583{ \
584 QLF3(S_D, S_D, S_D), \
585}
586
587/* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */
588#define QL_SISD_HS \
589{ \
590 QLF3(S_H, S_H, S_H), \
591 QLF3(S_S, S_S, S_S), \
592}
593
594/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */
595#define QL_SISDL_HS \
596{ \
597 QLF3(S_S, S_H, S_H), \
598 QLF3(S_D, S_S, S_S), \
599}
600
601/* FMUL <Sd>, <Sn>, <Sm>. */
602#define QL_FP3 \
603{ \
604 QLF3(S_S, S_S, S_S), \
605 QLF3(S_D, S_D, S_D), \
606}
607
622b9eb1
MW		 608/* FMUL <Hd>, <Hn>, <Hm>. */
609#define QL_FP3_H \
610{ \
611 QLF3 (S_H, S_H, S_H), \
612}
613
a06ea964
NC		 614/* FMADD <Dd>, <Dn>, <Dm>, <Da>. */
615#define QL_FP4 \
616{ \
617 QLF4(S_S, S_S, S_S, S_S), \
618 QLF4(S_D, S_D, S_D, S_D), \
619}
620
622b9eb1
MW		 621/* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */
622#define QL_FP4_H \
623{ \
624 QLF4 (S_H, S_H, S_H, S_H), \
625}
626
a06ea964
NC		 627/* e.g. FCMP <Dn>, #0.0. */
628#define QL_DST_SD \
629{ \
630 QLF2(S_S, NIL), \
631 QLF2(S_D, NIL), \
632}
633
622b9eb1
MW		 634/* e.g. FCMP <Hn>, #0.0. */
635#define QL_DST_H \
636{ \
637 QLF2 (S_H, NIL), \
638}
639
a06ea964
NC		 640/* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */
641#define QL_FP_COND \
642{ \
643 QLF4(S_S, S_S, S_S, NIL), \
644 QLF4(S_D, S_D, S_D, NIL), \
645}
646
622b9eb1
MW		 647/* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */
648#define QL_FP_COND_H \
649{ \
650 QLF4 (S_H, S_H, S_H, NIL), \
651}
652
a06ea964
NC		 653/* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */
654#define QL_CCMP \
655{ \
656 QLF4(W, W, NIL, NIL), \
657 QLF4(X, X, NIL, NIL), \
658}
659
660/* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */
661#define QL_CCMP_IMM \
662{ \
663 QLF4(W, NIL, NIL, NIL), \
664 QLF4(X, NIL, NIL, NIL), \
665}
666
667/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
668#define QL_FCCMP \
669{ \
670 QLF4(S_S, S_S, NIL, NIL), \
671 QLF4(S_D, S_D, NIL, NIL), \
672}
673
622b9eb1
MW		 674/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
675#define QL_FCCMP_H \
676{ \
677 QLF4 (S_H, S_H, NIL, NIL), \
678}
679
a06ea964
NC		 680/* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */
681#define QL_DUP_VX \
682{ \
683 QLF2(V_8B , S_B ), \
684 QLF2(V_16B, S_B ), \
685 QLF2(V_4H , S_H ), \
686 QLF2(V_8H , S_H ), \
687 QLF2(V_2S , S_S ), \
688 QLF2(V_4S , S_S ), \
689 QLF2(V_2D , S_D ), \
690}
691
692/* e.g. DUP <Vd>.<T>, <Wn>. */
693#define QL_DUP_VR \
694{ \
695 QLF2(V_8B , W ), \
696 QLF2(V_16B, W ), \
697 QLF2(V_4H , W ), \
698 QLF2(V_8H , W ), \
699 QLF2(V_2S , W ), \
700 QLF2(V_4S , W ), \
701 QLF2(V_2D , X ), \
702}
703
704/* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */
705#define QL_INS_XR \
706{ \
707 QLF2(S_H , W ), \
708 QLF2(S_S , W ), \
709 QLF2(S_D , X ), \
710 QLF2(S_B , W ), \
711}
712
713/* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */
714#define QL_SMOV \
715{ \
716 QLF2(W , S_H), \
717 QLF2(X , S_H), \
718 QLF2(X , S_S), \
719 QLF2(W , S_B), \
720 QLF2(X , S_B), \
721}
722
723/* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */
724#define QL_UMOV \
725{ \
726 QLF2(W , S_H), \
727 QLF2(W , S_S), \
728 QLF2(X , S_D), \
729 QLF2(W , S_B), \
730}
731
732/* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */
733#define QL_MOV \
734{ \
735 QLF2(W , S_S), \
736 QLF2(X , S_D), \
737}
738
739/* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */
740#define QL_V2SAME \
741{ \
742 QLF2(V_8B , V_8B ), \
743 QLF2(V_16B, V_16B), \
744 QLF2(V_4H , V_4H ), \
745 QLF2(V_8H , V_8H ), \
746 QLF2(V_2S , V_2S ), \
747 QLF2(V_4S , V_4S ), \
748 QLF2(V_2D , V_2D ), \
749}
750
751/* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */
752#define QL_V2SAMES \
753{ \
754 QLF2(V_2S , V_2S ), \
755 QLF2(V_4S , V_4S ), \
756}
757
758/* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */
759#define QL_V2SAMEBH \
760{ \
761 QLF2(V_8B , V_8B ), \
762 QLF2(V_16B, V_16B), \
763 QLF2(V_4H , V_4H ), \
764 QLF2(V_8H , V_8H ), \
765}
766
767/* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */
768#define QL_V2SAMESD \
769{ \
770 QLF2(V_2S , V_2S ), \
771 QLF2(V_4S , V_4S ), \
772 QLF2(V_2D , V_2D ), \
773}
774
775/* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */
776#define QL_V2SAMEBHS \
777{ \
778 QLF2(V_8B , V_8B ), \
779 QLF2(V_16B, V_16B), \
780 QLF2(V_4H , V_4H ), \
781 QLF2(V_8H , V_8H ), \
782 QLF2(V_2S , V_2S ), \
783 QLF2(V_4S , V_4S ), \
784}
785
f3aa142b
MW		 786/* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */
787#define QL_V2SAMEH \
788{ \
789 QLF2 (V_4H, V_4H), \
790 QLF2 (V_8H, V_8H), \
791}
792
a06ea964
NC		 793/* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */
794#define QL_V2SAMEB \
795{ \
796 QLF2(V_8B , V_8B ), \
797 QLF2(V_16B, V_16B), \
798}
799
800/* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */
801#define QL_V2PAIRWISELONGBHS \
802{ \
803 QLF2(V_4H , V_8B ), \
804 QLF2(V_8H , V_16B), \
805 QLF2(V_2S , V_4H ), \
806 QLF2(V_4S , V_8H ), \
807 QLF2(V_1D , V_2S ), \
808 QLF2(V_2D , V_4S ), \
809}
810
811/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
812#define QL_V2LONGBHS \
813{ \
814 QLF2(V_8H , V_8B ), \
815 QLF2(V_4S , V_4H ), \
816 QLF2(V_2D , V_2S ), \
817}
818
819/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
820#define QL_V2LONGBHS2 \
821{ \
822 QLF2(V_8H , V_16B), \
823 QLF2(V_4S , V_8H ), \
824 QLF2(V_2D , V_4S ), \
825}
826
827/* */
828#define QL_V3SAME \
829{ \
830 QLF3(V_8B , V_8B , V_8B ), \
831 QLF3(V_16B, V_16B, V_16B), \
832 QLF3(V_4H , V_4H , V_4H ), \
833 QLF3(V_8H , V_8H , V_8H ), \
834 QLF3(V_2S , V_2S , V_2S ), \
835 QLF3(V_4S , V_4S , V_4S ), \
836 QLF3(V_2D , V_2D , V_2D ) \
837}
838
839/* e.g. SHADD. */
840#define QL_V3SAMEBHS \
841{ \
842 QLF3(V_8B , V_8B , V_8B ), \
843 QLF3(V_16B, V_16B, V_16B), \
844 QLF3(V_4H , V_4H , V_4H ), \
845 QLF3(V_8H , V_8H , V_8H ), \
846 QLF3(V_2S , V_2S , V_2S ), \
847 QLF3(V_4S , V_4S , V_4S ), \
848}
849
850/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
851#define QL_V2NARRS \
852{ \
853 QLF2(V_2S , V_2D ), \
854}
855
856/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
857#define QL_V2NARRS2 \
858{ \
859 QLF2(V_4S , V_2D ), \
860}
861
862/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
863#define QL_V2NARRHS \
864{ \
865 QLF2(V_4H , V_4S ), \
866 QLF2(V_2S , V_2D ), \
867}
868
869/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
870#define QL_V2NARRHS2 \
871{ \
872 QLF2(V_8H , V_4S ), \
873 QLF2(V_4S , V_2D ), \
874}
875
876/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
877#define QL_V2LONGHS \
878{ \
879 QLF2(V_4S , V_4H ), \
880 QLF2(V_2D , V_2S ), \
881}
882
883/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
884#define QL_V2LONGHS2 \
885{ \
886 QLF2(V_4S , V_8H ), \
887 QLF2(V_2D , V_4S ), \
888}
889
890/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
891#define QL_V2NARRBHS \
892{ \
893 QLF2(V_8B , V_8H ), \
894 QLF2(V_4H , V_4S ), \
895 QLF2(V_2S , V_2D ), \
896}
897
898/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
899#define QL_V2NARRBHS2 \
900{ \
901 QLF2(V_16B, V_8H ), \
902 QLF2(V_8H , V_4S ), \
903 QLF2(V_4S , V_2D ), \
904}
905
906/* e.g. ORR. */
907#define QL_V2SAMEB \
908{ \
909 QLF2(V_8B , V_8B ), \
910 QLF2(V_16B, V_16B), \
911}
912
913/* e.g. AESE. */
914#define QL_V2SAME16B \
915{ \
916 QLF2(V_16B, V_16B), \
917}
918
919/* e.g. SHA1SU1. */
920#define QL_V2SAME4S \
921{ \
922 QLF2(V_4S, V_4S), \
923}
924
925/* e.g. SHA1SU0. */
926#define QL_V3SAME4S \
927{ \
928 QLF3(V_4S, V_4S, V_4S), \
929}
930
931/* e.g. SHADD. */
932#define QL_V3SAMEB \
933{ \
934 QLF3(V_8B , V_8B , V_8B ), \
935 QLF3(V_16B, V_16B, V_16B), \
936}
937
938/* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */
939#define QL_VEXT \
940{ \
941 QLF4(V_8B , V_8B , V_8B , imm_0_7), \
942 QLF4(V_16B, V_16B, V_16B, imm_0_15), \
943}
944
945/* e.g. . */
946#define QL_V3SAMEHS \
947{ \
948 QLF3(V_4H , V_4H , V_4H ), \
949 QLF3(V_8H , V_8H , V_8H ), \
950 QLF3(V_2S , V_2S , V_2S ), \
951 QLF3(V_4S , V_4S , V_4S ), \
952}
953
954/* */
955#define QL_V3SAMESD \
956{ \
957 QLF3(V_2S , V_2S , V_2S ), \
958 QLF3(V_4S , V_4S , V_4S ), \
959 QLF3(V_2D , V_2D , V_2D ) \
960}
961
51d543ed
MW		 962/* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */
963#define QL_V3SAMEH \
964{ \
965 QLF3 (V_4H , V_4H , V_4H ), \
966 QLF3 (V_8H , V_8H , V_8H ), \
967}
968
a06ea964
NC		 969/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
970#define QL_V3LONGHS \
971{ \
972 QLF3(V_4S , V_4H , V_4H ), \
973 QLF3(V_2D , V_2S , V_2S ), \
974}
975
976/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
977#define QL_V3LONGHS2 \
978{ \
979 QLF3(V_4S , V_8H , V_8H ), \
980 QLF3(V_2D , V_4S , V_4S ), \
981}
982
983/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
984#define QL_V3LONGBHS \
985{ \
986 QLF3(V_8H , V_8B , V_8B ), \
987 QLF3(V_4S , V_4H , V_4H ), \
988 QLF3(V_2D , V_2S , V_2S ), \
989}
990
991/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
992#define QL_V3LONGBHS2 \
993{ \
994 QLF3(V_8H , V_16B , V_16B ), \
995 QLF3(V_4S , V_8H , V_8H ), \
996 QLF3(V_2D , V_4S , V_4S ), \
997}
998
999/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
1000#define QL_V3WIDEBHS \
1001{ \
1002 QLF3(V_8H , V_8H , V_8B ), \
1003 QLF3(V_4S , V_4S , V_4H ), \
1004 QLF3(V_2D , V_2D , V_2S ), \
1005}
1006
1007/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
1008#define QL_V3WIDEBHS2 \
1009{ \
1010 QLF3(V_8H , V_8H , V_16B ), \
1011 QLF3(V_4S , V_4S , V_8H ), \
1012 QLF3(V_2D , V_2D , V_4S ), \
1013}
1014
1015/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
1016#define QL_V3NARRBHS \
1017{ \
1018 QLF3(V_8B , V_8H , V_8H ), \
1019 QLF3(V_4H , V_4S , V_4S ), \
1020 QLF3(V_2S , V_2D , V_2D ), \
1021}
1022
1023/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
1024#define QL_V3NARRBHS2 \
1025{ \
1026 QLF3(V_16B , V_8H , V_8H ), \
1027 QLF3(V_8H , V_4S , V_4S ), \
1028 QLF3(V_4S , V_2D , V_2D ), \
1029}
1030
1031/* e.g. PMULL. */
1032#define QL_V3LONGB \
1033{ \
1034 QLF3(V_8H , V_8B , V_8B ), \
1035}
1036
1037/* e.g. PMULL crypto. */
1038#define QL_V3LONGD \
1039{ \
1040 QLF3(V_1Q , V_1D , V_1D ), \
1041}
1042
1043/* e.g. PMULL2. */
1044#define QL_V3LONGB2 \
1045{ \
1046 QLF3(V_8H , V_16B, V_16B), \
1047}
1048
1049/* e.g. PMULL2 crypto. */
1050#define QL_V3LONGD2 \
1051{ \
1052 QLF3(V_1Q , V_2D , V_2D ), \
1053}
1054
1055/* e.g. SHA1C. */
1056#define QL_SHAUPT \
1057{ \
1058 QLF3(S_Q, S_S, V_4S), \
1059}
1060
1061/* e.g. SHA256H2. */
1062#define QL_SHA256UPT \
1063{ \
1064 QLF3(S_Q, S_Q, V_4S), \
1065}
1066
1067/* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */
1068#define QL_W1_LDST_EXC \
1069{ \
1070 QLF2(W, NIL), \
1071}
1072
1073/* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */
1074#define QL_R1NIL \
1075{ \
1076 QLF2(W, NIL), \
1077 QLF2(X, NIL), \
1078}
1079
1080/* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
1081#define QL_W2_LDST_EXC \
1082{ \
1083 QLF3(W, W, NIL), \
1084}
1085
1086/* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */
1087#define QL_R2_LDST_EXC \
1088{ \
1089 QLF3(W, W, NIL), \
1090 QLF3(W, X, NIL), \
1091}
1092
1093/* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1094#define QL_R2NIL \
1095{ \
1096 QLF3(W, W, NIL), \
1097 QLF3(X, X, NIL), \
1098}
1099
ee804238
JW		 1100/* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */
1101#define QL_R4NIL \
1102{ \
1103 QLF5(W, W, W, W, NIL), \
1104 QLF5(X, X, X, X, NIL), \
1105}
1106
a06ea964
NC		 1107/* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1108#define QL_R3_LDST_EXC \
1109{ \
1110 QLF4(W, W, W, NIL), \
1111 QLF4(W, X, X, NIL), \
1112}
1113
1114/* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1115#define QL_LDST_FP \
1116{ \
1117 QLF2(S_B, S_B), \
1118 QLF2(S_H, S_H), \
1119 QLF2(S_S, S_S), \
1120 QLF2(S_D, S_D), \
1121 QLF2(S_Q, S_Q), \
1122}
1123
1124/* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1125#define QL_LDST_R \
1126{ \
1127 QLF2(W, S_S), \
1128 QLF2(X, S_D), \
1129}
1130
1131/* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1132#define QL_LDST_W8 \
1133{ \
1134 QLF2(W, S_B), \
1135}
1136
1137/* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1138#define QL_LDST_R8 \
1139{ \
1140 QLF2(W, S_B), \
1141 QLF2(X, S_B), \
1142}
1143
1144/* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1145#define QL_LDST_W16 \
1146{ \
1147 QLF2(W, S_H), \
1148}
1149
1150/* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1151#define QL_LDST_X32 \
1152{ \
1153 QLF2(X, S_S), \
1154}
1155
1156/* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1157#define QL_LDST_R16 \
1158{ \
1159 QLF2(W, S_H), \
1160 QLF2(X, S_H), \
1161}
1162
1163/* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1164#define QL_LDST_PRFM \
1165{ \
1166 QLF2(NIL, S_D), \
1167}
1168
1169/* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
1170#define QL_LDST_PAIR_X32 \
1171{ \
1172 QLF3(X, X, S_S), \
1173}
1174
1175/* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
1176#define QL_LDST_PAIR_R \
1177{ \
1178 QLF3(W, W, S_S), \
1179 QLF3(X, X, S_D), \
1180}
1181
1182/* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
1183#define QL_LDST_PAIR_FP \
1184{ \
1185 QLF3(S_S, S_S, S_S), \
1186 QLF3(S_D, S_D, S_D), \
1187 QLF3(S_Q, S_Q, S_Q), \
1188}
1189
1190/* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1191#define QL_SIMD_LDST \
1192{ \
1193 QLF2(V_8B, NIL), \
1194 QLF2(V_16B, NIL), \
1195 QLF2(V_4H, NIL), \
1196 QLF2(V_8H, NIL), \
1197 QLF2(V_2S, NIL), \
1198 QLF2(V_4S, NIL), \
1199 QLF2(V_2D, NIL), \
1200}
1201
1202/* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1203#define QL_SIMD_LDST_ANY \
1204{ \
1205 QLF2(V_8B, NIL), \
1206 QLF2(V_16B, NIL), \
1207 QLF2(V_4H, NIL), \
1208 QLF2(V_8H, NIL), \
1209 QLF2(V_2S, NIL), \
1210 QLF2(V_4S, NIL), \
1211 QLF2(V_1D, NIL), \
1212 QLF2(V_2D, NIL), \
1213}
1214
1215/* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */
1216#define QL_SIMD_LDSTONE \
1217{ \
1218 QLF2(S_B, NIL), \
1219 QLF2(S_H, NIL), \
1220 QLF2(S_S, NIL), \
1221 QLF2(S_D, NIL), \
1222}
1223
1224/* e.g. ADDV <V><d>, <Vn>.<T>. */
1225#define QL_XLANES \
1226{ \
1227 QLF2(S_B, V_8B), \
1228 QLF2(S_B, V_16B), \
1229 QLF2(S_H, V_4H), \
1230 QLF2(S_H, V_8H), \
1231 QLF2(S_S, V_4S), \
1232}
1233
1234/* e.g. FMINV <V><d>, <Vn>.<T>. */
1235#define QL_XLANES_FP \
1236{ \
1237 QLF2(S_S, V_4S), \
1238}
1239
bb515fea
MW		 1240/* e.g. FMINV <V><d>, <Vn>.<T>. */
1241#define QL_XLANES_FP_H \
1242{ \
1243 QLF2 (S_H, V_4H), \
1244 QLF2 (S_H, V_8H), \
1245}
1246
a06ea964
NC		 1247/* e.g. SADDLV <V><d>, <Vn>.<T>. */
1248#define QL_XLANES_L \
1249{ \
1250 QLF2(S_H, V_8B), \
1251 QLF2(S_H, V_16B), \
1252 QLF2(S_S, V_4H), \
1253 QLF2(S_S, V_8H), \
1254 QLF2(S_D, V_4S), \
1255}
1256
1257/* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */
1258#define QL_ELEMENT \
1259{ \
1260 QLF3(V_4H, V_4H, S_H), \
1261 QLF3(V_8H, V_8H, S_H), \
1262 QLF3(V_2S, V_2S, S_S), \
1263 QLF3(V_4S, V_4S, S_S), \
1264}
1265
1266/* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1267#define QL_ELEMENT_L \
1268{ \
1269 QLF3(V_4S, V_4H, S_H), \
1270 QLF3(V_2D, V_2S, S_S), \
1271}
1272
1273/* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1274#define QL_ELEMENT_L2 \
1275{ \
1276 QLF3(V_4S, V_8H, S_H), \
1277 QLF3(V_2D, V_4S, S_S), \
1278}
1279
1280/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1281#define QL_ELEMENT_FP \
1282{ \
1283 QLF3(V_2S, V_2S, S_S), \
1284 QLF3(V_4S, V_4S, S_S), \
1285 QLF3(V_2D, V_2D, S_D), \
1286}
1287
42f23f62
MW		 1288/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1289#define QL_ELEMENT_FP_H \
1290{ \
1291 QLF3 (V_4H, V_4H, S_H), \
1292 QLF3 (V_8H, V_8H, S_H), \
1293}
1294
a06ea964
NC		 1295/* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */
1296#define QL_SIMD_IMM_S0W \
1297{ \
1298 QLF2(V_2S, LSL), \
1299 QLF2(V_4S, LSL), \
1300}
1301
1302/* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */
1303#define QL_SIMD_IMM_S1W \
1304{ \
1305 QLF2(V_2S, MSL), \
1306 QLF2(V_4S, MSL), \
1307}
1308
1309/* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */
1310#define QL_SIMD_IMM_S0H \
1311{ \
1312 QLF2(V_4H, LSL), \
1313 QLF2(V_8H, LSL), \
1314}
1315
1316/* e.g. FMOV <Vd>.<T>, #<imm>. */
1317#define QL_SIMD_IMM_S \
1318{ \
1319 QLF2(V_2S, NIL), \
1320 QLF2(V_4S, NIL), \
1321}
1322
f5555712 1323/* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */
a06ea964
NC		 1324#define QL_SIMD_IMM_B \
1325{ \
f5555712
YZ		 1326 QLF2(V_8B, LSL), \
1327 QLF2(V_16B, LSL), \
a06ea964
NC		 1328}
1329/* e.g. MOVI <Dd>, #<imm>. */
1330#define QL_SIMD_IMM_D \
1331{ \
1332 QLF2(S_D, NIL), \
1333}
1334
4b5fc357
MW		 1335/* e.g. FMOV <Vd>.<T>, #<imm>. */
1336#define QL_SIMD_IMM_H \
1337{ \
1338 QLF2 (V_4H, NIL), \
1339 QLF2 (V_8H, NIL), \
1340}
1341
a06ea964
NC		 1342/* e.g. MOVI <Vd>.2D, #<imm>. */
1343#define QL_SIMD_IMM_V2D \
1344{ \
1345 QLF2(V_2D, NIL), \
1346}
1347\f
1348/* Opcode table. */
1349
1350static const aarch64_feature_set aarch64_feature_v8 =
1351 AARCH64_FEATURE (AARCH64_FEATURE_V8, 0);
1352static const aarch64_feature_set aarch64_feature_fp =
1353 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
1354static const aarch64_feature_set aarch64_feature_simd =
1355 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
1356static const aarch64_feature_set aarch64_feature_crypto =
1357 AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
e60bb1dd
YZ		 1358static const aarch64_feature_set aarch64_feature_crc =
1359 AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
ee804238
JW		 1360static const aarch64_feature_set aarch64_feature_lse =
1361 AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
290806fd
MW		 1362static const aarch64_feature_set aarch64_feature_lor =
1363 AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
9e1f0fa7
MW		 1364static const aarch64_feature_set aarch64_feature_rdma =
1365 AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
c8a6db6f
MW		 1366static const aarch64_feature_set aarch64_feature_ras =
1367 AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
d685192a
MW		 1368static const aarch64_feature_set aarch64_feature_v8_2 =
1369 AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
3bd894a7
MW		 1370static const aarch64_feature_set aarch64_feature_fp_f16 =
1371 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
40d16a76
MW		 1372static const aarch64_feature_set aarch64_feature_simd_f16 =
1373 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
1e6f4800
MW		 1374static const aarch64_feature_set aarch64_feature_stat_profile =
1375 AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
a06ea964
NC		 1376
1377#define CORE &aarch64_feature_v8
1378#define FP &aarch64_feature_fp
1379#define SIMD &aarch64_feature_simd
1380#define CRYPTO &aarch64_feature_crypto
e60bb1dd 1381#define CRC &aarch64_feature_crc
ee804238 1382#define LSE &aarch64_feature_lse
290806fd 1383#define LOR &aarch64_feature_lor
9e1f0fa7 1384#define RDMA &aarch64_feature_rdma
3bd894a7 1385#define FP_F16 &aarch64_feature_fp_f16
40d16a76 1386#define SIMD_F16 &aarch64_feature_simd_f16
c8a6db6f 1387#define RAS &aarch64_feature_ras
1e6f4800 1388#define STAT_PROFILE &aarch64_feature_stat_profile
d685192a 1389#define ARMV8_2 &aarch64_feature_v8_2
a06ea964
NC		 1390
1391struct aarch64_opcode aarch64_opcode_table[] =
1392{
1393 /* Add/subtract (with carry). */
1394 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1395 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1396 {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1397 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1398 {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1399 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1400 /* Add/subtract (extended register). */
1401 {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1402 {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1403 {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1404 {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1405 {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1406 {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1407 /* Add/subtract (immediate). */
1408 {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1409 {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
1410 {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1411 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1412 {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF},
1413 {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1414 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1415 /* Add/subtract (shifted register). */
1416 {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
1417 {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1418 {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1419 {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1420 {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1421 {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1422 {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1423 {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1424 /* AdvSIMD across lanes. */
1425 {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1426 {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1427 {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1428 {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1429 {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1430 {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1431 {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1432 {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
bb515fea
MW		 1433 {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall, 0, SIMD_F16,
1434 OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
a06ea964 1435 {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
bb515fea
MW		 1436 {"fmaxv", 0xe30f800, 0xbffffc00, asimdall, 0, SIMD_F16,
1437 OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
a06ea964 1438 {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
bb515fea
MW		 1439 {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall, 0, SIMD_F16,
1440 OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
a06ea964 1441 {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
bb515fea
MW		 1442 {"fminv", 0xeb0f800, 0xbffffc00, asimdall, 0, SIMD_F16,
1443 OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
a06ea964
NC		 1444 /* AdvSIMD three different. */
1445 {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1446 {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1447 {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1448 {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1449 {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1450 {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1451 {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1452 {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1453 {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1454 {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1455 {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1456 {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1457 {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1458 {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1459 {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1460 {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1461 {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1462 {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1463 {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1464 {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1465 {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1466 {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1467 {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1468 {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1469 {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1470 {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1471 {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1472 {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1473 {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0},
1474 {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0},
1475 {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0},
1476 {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0},
1477 {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1478 {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1479 {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1480 {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1481 {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1482 {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1483 {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1484 {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1485 {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1486 {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1487 {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1488 {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1489 {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1490 {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1491 {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1492 {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1493 {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1494 {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1495 {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1496 {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1497 {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1498 {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1499 /* AdvSIMD vector x indexed element. */
1500 {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1501 {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1502 {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1503 {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1504 {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1505 {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1506 {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1507 {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1508 {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1509 {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1510 {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1511 {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1512 {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1513 {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1514 {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1515 {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1516 {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1517 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964 1518 {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1519 {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1520 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964 1521 {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1522 {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1523 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964
NC		 1524 {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1525 {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1526 {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1527 {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1528 {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1529 {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1530 {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1531 {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1532 {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1533 {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1534 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
9e1f0fa7
MW		 1535 {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1536 {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
a06ea964 1537 /* AdvSIMD EXT. */
922c5db5 1538 {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
a06ea964
NC		 1539 /* AdvSIMD modified immediate. */
1540 {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1541 {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1542 {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1543 {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1544 {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
f5555712 1545 {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ},
a06ea964 1546 {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
4b5fc357
MW		 1547 {"fmov", 0xf00fc00, 0xbff8fc00, asimdimm, 0, SIMD_F16,
1548 OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ},
a06ea964
NC		 1549 {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1550 {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1551 {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1552 {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1553 {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
1554 {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ},
1555 {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1556 {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1557 /* AdvSIMD copy. */
1558 {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T},
1559 {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T},
1560 {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q},
1561 {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
1562 {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q},
1563 {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS},
1564 {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS},
1565 {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS},
1566 {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS},
1567 /* AdvSIMD two-reg misc. */
1568 {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1569 {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1570 {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1571 {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1572 {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1573 {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1574 {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1575 {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1576 {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1577 {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1578 {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1579 {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1580 {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1581 {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1582 {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1583 {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1584 {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC},
1585 {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC},
1586 {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
1587 {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
1588 {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1589 {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1590 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1591 {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1592 {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1593 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1594 {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1595 {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1596 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1597 {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1598 {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1599 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1600 {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1601 {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1602 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1603 {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1604 {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1605 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1606 {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1607 {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1608 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1609 {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1610 {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1611 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1612 {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1613 {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1614 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
a06ea964 1615 {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1616 {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1617 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1618 {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1619 {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1620 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1621 {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1622 {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1623 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1624 {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1625 {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1626 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1627 {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1628 {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1629 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1630 {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1631 {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1632 {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1633 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1634 {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
1635 {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1636 {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1637 {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1638 {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1639 {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1640 {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1641 {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1642 {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1643 {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1644 {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1645 {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ},
1646 {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ},
1647 {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1648 {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1649 {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
1650 {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
1651 {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1652 {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1653 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1654 {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1655 {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1656 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1657 {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1658 {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1659 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1660 {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1661 {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1662 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1663 {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1664 {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1665 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1666 {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1667 {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1668 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1669 {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
1670 {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
1671 {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
f17c8bfc 1672 {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1673 {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1674 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1675 {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1676 {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1677 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
a06ea964 1678 {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1679 {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1680 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1681 {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1682 {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1683 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1684 {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1685 {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1686 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1687 {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1688 {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1689 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1690 {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1691 {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1692 {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1693 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1694 {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1695 {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1696 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1697 /* AdvSIMD ZIP/UZP/TRN. */
1698 {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1699 {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1700 {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1701 {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1702 {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1703 {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1704 /* AdvSIMD three same. */
1705 {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1706 {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1707 {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1708 {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1709 {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1710 {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1711 {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1712 {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1713 {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1714 {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1715 {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1716 {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1717 {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1718 {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1719 {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1720 {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1721 {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1722 {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1723 {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1724 {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1725 {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1726 {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1727 {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1728 {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1729 {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1730 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1731 {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1732 {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1733 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1734 {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1735 {"fadd", 0xe401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1736 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1737 {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1738 {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1739 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1740 {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1741 {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1742 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1743 {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1744 {"fmax", 0xe403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1745 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1746 {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1747 {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1748 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1749 {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1750 {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1751 {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1752 {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1753 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1754 {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1755 {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1756 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1757 {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1758 {"fsub", 0xec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1759 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1760 {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1761 {"fmin", 0xec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1762 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1763 {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1764 {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1765 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1766 {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
1767 {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
1768 {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1769 {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1770 {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1771 {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1772 {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1773 {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1774 {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1775 {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1776 {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1777 {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1778 {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1779 {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1780 {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1781 {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1782 {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1783 {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1784 {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1785 {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1786 {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1787 {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1788 {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1789 {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1790 {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1791 {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1792 {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1793 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1794 {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1795 {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1796 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1797 {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1798 {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1799 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1800 {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1801 {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1802 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1803 {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1804 {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1805 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1806 {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1807 {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1808 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1809 {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1810 {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1811 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1812 {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1813 {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1814 {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1815 {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1816 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1817 {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1818 {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1819 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1820 {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1821 {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1822 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1823 {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1824 {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1825 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1826 {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1827 {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1828 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1829 {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1830 {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
9e1f0fa7
MW		 1831 /* AdvSIMD three same extension. */
1832 {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1833 {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
a06ea964
NC		 1834 /* AdvSIMD shift by immediate. */
1835 {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1836 {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1837 {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1838 {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1839 {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1840 {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1841 {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1842 {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1843 {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1844 {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1845 {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1846 {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1847 {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1848 {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
e30181a5
YZ		 1849 {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1850 {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1851 {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1852 {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
a06ea964 1853 {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
b5b0f34c
MW		 1854 {"scvtf", 0xf10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16,
1855 OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
a06ea964 1856 {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
b5b0f34c
MW		 1857 {"fcvtzs", 0xf10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16,
1858 OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
a06ea964
NC		 1859 {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1860 {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1861 {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1862 {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1863 {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1864 {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1865 {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1866 {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1867 {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1868 {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1869 {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1870 {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1871 {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1872 {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1873 {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1874 {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
e30181a5
YZ		 1875 {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1876 {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1877 {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1878 {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
a06ea964 1879 {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
b5b0f34c
MW		 1880 {"ucvtf", 0x2f10e400, 0xbf80fc00, asimdshf, 0, SIMD_F16,
1881 OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
a06ea964 1882 {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
b5b0f34c
MW		 1883 {"fcvtzu", 0x2f10fc00, 0xbf80fc00, asimdshf, 0, SIMD_F16,
1884 OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_H, 0},
a06ea964
NC		 1885 /* AdvSIMD TBL/TBX. */
1886 {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1887 {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1888 /* AdvSIMD scalar three different. */
1889 {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1890 {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1891 {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1892 /* AdvSIMD scalar x indexed element. */
1893 {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1894 {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1895 {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1896 {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1897 {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1898 {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
5f7728b7
MW		 1899 {"fmla", 0x5f001000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1900 OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
a06ea964 1901 {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
5f7728b7
MW		 1902 {"fmls", 0x5f005000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1903 OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
a06ea964 1904 {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
5f7728b7
MW		 1905 {"fmul", 0x5f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1906 OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
a06ea964 1907 {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
5f7728b7
MW		 1908 {"fmulx", 0x7f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1909 OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
9e1f0fa7
MW		 1910 {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1911 {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
a06ea964
NC		 1912 /* AdvSIMD load/store multiple structures. */
1913 {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1914 {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1915 {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1916 {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1917 {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1918 {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1919 {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1920 {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1921 /* AdvSIMD load/store multiple structures (post-indexed). */
1922 {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1923 {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1924 {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1925 {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1926 {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1927 {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1928 {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1929 {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1930 /* AdvSIMD load/store single structure. */
1931 {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1932 {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1933 {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1934 {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1935 {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1936 {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1937 {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1938 {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1939 {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1940 {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1941 {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1942 {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1943 /* AdvSIMD load/store single structure (post-indexed). */
1944 {"st1", 0xd800000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1945 {"st3", 0xd802000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1946 {"st2", 0xda00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1947 {"st4", 0xda02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1948 {"ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1949 {"ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1950 {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1951 {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1952 {"ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1953 {"ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1954 {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1955 {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1956 /* AdvSIMD scalar two-reg misc. */
1957 {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1958 {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1959 {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1960 {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1961 {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1962 {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
1963 {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1964 {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1965 {"fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1966 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1967 {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1968 {"fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1969 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1970 {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1971 {"fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1972 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1973 {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1974 {"scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1975 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
f17c8bfc 1976 {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1977 {"fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1978 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 1979 {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1980 {"fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1981 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 1982 {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1983 {"fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1984 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 1985 {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1986 {"fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1987 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1988 {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1989 {"fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1990 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1991 {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1992 {"frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1993 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1994 {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1995 {"frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1996 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964
NC		 1997 {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1998 {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1999 {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
2000 {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
2001 {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
2002 {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
2003 {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
2004 {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC},
2005 {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2006 {"fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2007 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 2008 {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2009 {"fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2010 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 2011 {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2012 {"fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2013 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 2014 {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2015 {"ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2016 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
f17c8bfc 2017 {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 2018 {"fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2019 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 2020 {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 2021 {"fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2022 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 2023 {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2024 {"fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2025 OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 2026 {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2027 {"fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2028 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 2029 {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 2030 {"frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
2031 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964
NC		 2032 /* AdvSIMD scalar copy. */
2033 {"dup", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS},
2034 {"mov", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_ALIAS},
2035 /* AdvSIMD scalar pairwise. */
2036 {"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ},
2037 {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
b195470d
MW		 2038 {"fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, 0, SIMD_F16,
2039 OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
a06ea964 2040 {"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
b195470d
MW		 2041 {"faddp", 0x5e30d800, 0xfffffc00, asisdpair, 0, SIMD_F16,
2042 OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
a06ea964 2043 {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
b195470d
MW		 2044 {"fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, 0, SIMD_F16,
2045 OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
a06ea964 2046 {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
b195470d
MW		 2047 {"fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, 0, SIMD_F16,
2048 OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
a06ea964 2049 {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
b195470d
MW		 2050 {"fminp", 0x5eb0f800, 0xfffffc00, asisdpair, 0, SIMD_F16,
2051 OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
a06ea964
NC		 2052 /* AdvSIMD scalar three same. */
2053 {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2054 {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2055 {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2056 {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2057 {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2058 {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2059 {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2060 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2061 {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2062 {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2063 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2064 {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2065 {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2066 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2067 {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2068 {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2069 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964
NC		 2070 {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2071 {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2072 {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2073 {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2074 {"add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2075 {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2076 {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2077 {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2078 {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2079 {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2080 {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2081 {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2082 {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2083 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2084 {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2085 {"facge", 0x7e402c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2086 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2087 {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2088 {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2089 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2090 {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2091 {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2092 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2093 {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2094 {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2095 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964
NC		 2096 {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2097 {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2098 {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2099 {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2100 {"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2101 {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
9e1f0fa7
MW		 2102 /* AdvSIMDs scalar three same extension. */
2103 {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2104 {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
a06ea964
NC		 2105 /* AdvSIMD scalar shift by immediate. */
2106 {"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2107 {"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2108 {"srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2109 {"srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2110 {"shl", 0x5f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2111 {"sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2112 {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2113 {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2114 {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
4fd0a9fd
MW		 2115 {"scvtf", 0x5f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
2116 OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
a06ea964 2117 {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
4fd0a9fd
MW		 2118 {"fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
2119 OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
a06ea964
NC		 2120 {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2121 {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2122 {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2123 {"ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2124 {"sri", 0x7f004400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2125 {"sli", 0x7f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2126 {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2127 {"uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2128 {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2129 {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2130 {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2131 {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2132 {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
4fd0a9fd
MW		 2133 {"ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
2134 OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
a06ea964 2135 {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
4fd0a9fd
MW		 2136 {"fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
2137 OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
a06ea964
NC		 2138 /* Bitfield. */
2139 {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2140 {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2141 {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2142 {"sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2143 {"sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2144 {"sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3},
2145 {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2146 {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2147 {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
d685192a
MW		 2148 {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2,
2149 OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV},
a06ea964
NC		 2150 {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2151 {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2152 {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2153 {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2154 {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2155 {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2156 {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2157 {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2158 /* Unconditional branch (immediate). */
2159 {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2160 {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2161 /* Unconditional branch (register). */
2162 {"br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2163 {"blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2164 {"ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)},
2165 {"eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2166 {"drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2167 /* Compare & branch (immediate). */
2168 {"cbz", 0x34000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2169 {"cbnz", 0x35000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2170 /* Conditional branch (immediate). */
2171 {"b.c", 0x54000000, 0xff000010, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND},
2172 /* Conditional compare (immediate). */
2173 {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2174 {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2175 /* Conditional compare (register). */
2176 {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2177 {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2178 /* Conditional select. */
2179 {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
2180 {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283
YZ		 2181 {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2182 {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964 2183 {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283
YZ		 2184 {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2185 {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964 2186 {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283 2187 {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
a06ea964
NC		 2188 /* Crypto AES. */
2189 {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2190 {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2191 {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2192 {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2193 /* Crypto two-reg SHA. */
2194 {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Fd, Fn), QL_2SAMES, 0},
2195 {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2196 {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2197 /* Crypto three-reg SHA. */
2198 {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2199 {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2200 {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2201 {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2202 {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2203 {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2204 {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2205 /* Data-processing (1 source). */
2206 {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2207 {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2208 {"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
64357d2e
MW		 2209 {"rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, CORE,
2210 OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1},
2211 {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2,
2212 OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS},
a06ea964
NC		 2213 {"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2214 {"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2215 {"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
2216 /* Data-processing (2 source). */
2217 {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2218 {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2219 {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2220 {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2221 {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2222 {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2223 {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2224 {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2225 {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2226 {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
e60bb1dd
YZ		 2227 /* CRC instructions. */
2228 {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2229 {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2230 {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2231 {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
2232 {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2233 {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2234 {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2235 {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
a06ea964
NC		 2236 /* Data-processing (3 source). */
2237 {"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2238 {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2239 {"msub", 0x1b008000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2240 {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2241 {"smaddl", 0x9b200000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2242 {"smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2243 {"smsubl", 0x9b208000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2244 {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2245 {"smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2246 {"umaddl", 0x9ba00000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2247 {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2248 {"umsubl", 0x9ba08000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2249 {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2250 {"umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2251 /* Excep'n generation. */
2252 {"svc", 0xd4000001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2253 {"hvc", 0xd4000002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2254 {"smc", 0xd4000003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2255 {"brk", 0xd4200000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2256 {"hlt", 0xd4400000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2257 {"dcps1", 0xd4a00001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2258 {"dcps2", 0xd4a00002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2259 {"dcps3", 0xd4a00003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2260 /* Extract. */
2261 {"extr", 0x13800000, 0x7fa00000, extract, 0, CORE, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N},
2262 {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV},
2263 /* Floating-point<->fixed-point conversions. */
2264 {"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2265 {"scvtf", 0x1ec20000, 0x7f3f0000, float2fix, 0, FP_F16,
2266 OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
a06ea964 2267 {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2268 {"ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, 0, FP_F16,
2269 OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
a06ea964 2270 {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
622b9eb1
MW		 2271 {"fcvtzs", 0x1ed80000, 0x7f3f0000, float2fix, 0, FP_F16,
2272 OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
a06ea964 2273 {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
622b9eb1
MW		 2274 {"fcvtzu", 0x1ed90000, 0x7f3f0000, float2fix, 0, FP_F16,
2275 OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
a06ea964
NC		 2276 /* Floating-point<->integer conversions. */
2277 {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2278 {"fcvtns", 0x1ee00000, 0x7f3ffc00, float2int, 0, FP_F16,
2279 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2280 {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2281 {"fcvtnu", 0x1ee10000, 0x7f3ffc00, float2int, 0, FP_F16,
2282 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2283 {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2284 {"scvtf", 0x1ee20000, 0x7f3ffc00, float2int, 0, FP_F16,
2285 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2286 {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2287 {"ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, 0, FP_F16,
2288 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2289 {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2290 {"fcvtas", 0x1ee40000, 0x7f3ffc00, float2int, 0, FP_F16,
2291 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2292 {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2293 {"fcvtau", 0x1ee50000, 0x7f3ffc00, float2int, 0, FP_F16,
2294 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2295 {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2296 {"fmov", 0x1ee60000, 0x7f3ffc00, float2int, 0, FP_F16,
2297 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2298 {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2299 {"fmov", 0x1ee70000, 0x7f3ffc00, float2int, 0, FP_F16,
2300 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2301 {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2302 {"fcvtps", 0x1ee80000, 0x7f3ffc00, float2int, 0, FP_F16,
2303 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2304 {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2305 {"fcvtpu", 0x1ee90000, 0x7f3ffc00, float2int, 0, FP_F16,
2306 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2307 {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2308 {"fcvtms", 0x1ef00000, 0x7f3ffc00, float2int, 0, FP_F16,
2309 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2310 {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2311 {"fcvtmu", 0x1ef10000, 0x7f3ffc00, float2int, 0, FP_F16,
2312 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2313 {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2314 {"fcvtzs", 0x1ef80000, 0x7f3ffc00, float2int, 0, FP_F16,
2315 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2316 {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2317 {"fcvtzu", 0x1ef90000, 0x7f3ffc00, float2int, 0, FP_F16,
2318 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964
NC		 2319 {"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0},
2320 {"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0},
2321 /* Floating-point conditional compare. */
2322 {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
622b9eb1
MW		 2323 {"fccmp", 0x1ee00400, 0xff200c10, floatccmp, 0, FP_F16,
2324 OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
a06ea964 2325 {"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
622b9eb1
MW		 2326 {"fccmpe", 0x1ee00410, 0xff200c10, floatccmp, 0, FP_F16,
2327 OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
a06ea964
NC		 2328 /* Floating-point compare. */
2329 {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2330 {"fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, 0, FP_F16,
2331 OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
a06ea964 2332 {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2333 {"fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, 0, FP_F16,
2334 OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
a06ea964 2335 {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2336 {"fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, 0, FP_F16,
2337 OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
a06ea964 2338 {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2339 {"fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, 0, FP_F16,
2340 OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2341 /* Floating-point data-processing (1 source). */
2342 {"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2343 {"fmov", 0x1ee04000, 0xff3ffc00, floatdp1, 0, FP_F16,
2344 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2345 {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2346 {"fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2347 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2348 {"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2349 {"fneg", 0x1ee14000, 0xff3ffc00, floatdp1, 0, FP_F16,
2350 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2351 {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2352 {"fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2353 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2354 {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC},
2355 {"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2356 {"frintn", 0x1ee44000, 0xff3ffc00, floatdp1, 0, FP_F16,
2357 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2358 {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2359 {"frintp", 0x1ee4c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2360 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2361 {"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2362 {"frintm", 0x1ee54000, 0xff3ffc00, floatdp1, 0, FP_F16,
2363 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2364 {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2365 {"frintz", 0x1ee5c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2366 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2367 {"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2368 {"frinta", 0x1ee64000, 0xff3ffc00, floatdp1, 0, FP_F16,
2369 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2370 {"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2371 {"frintx", 0x1ee74000, 0xff3ffc00, floatdp1, 0, FP_F16,
2372 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2373 {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2374 {"frinti", 0x1ee7c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2375 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2376 /* Floating-point data-processing (2 source). */
2377 {"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2378 {"fmul", 0x1ee00800, 0xff20fc00, floatdp2, 0, FP_F16,
2379 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2380 {"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2381 {"fdiv", 0x1ee01800, 0xff20fc00, floatdp2, 0, FP_F16,
2382 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2383 {"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2384 {"fadd", 0x1ee02800, 0xff20fc00, floatdp2, 0, FP_F16,
2385 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2386 {"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2387 {"fsub", 0x1ee03800, 0xff20fc00, floatdp2, 0, FP_F16,
2388 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2389 {"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2390 {"fmax", 0x1ee04800, 0xff20fc00, floatdp2, 0, FP_F16,
2391 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2392 {"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2393 {"fmin", 0x1ee05800, 0xff20fc00, floatdp2, 0, FP_F16,
2394 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2395 {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2396 {"fmaxnm", 0x1ee06800, 0xff20fc00, floatdp2, 0, FP_F16,
2397 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2398 {"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2399 {"fminnm", 0x1ee07800, 0xff20fc00, floatdp2, 0, FP_F16,
2400 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2401 {"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2402 {"fnmul", 0x1ee08800, 0xff20fc00, floatdp2, 0, FP_F16,
2403 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964
NC		 2404 /* Floating-point data-processing (3 source). */
2405 {"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2406 {"fmadd", 0x1fc00000, 0xff208000, floatdp3, 0, FP_F16,
2407 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2408 {"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2409 {"fmsub", 0x1fc08000, 0xff208000, floatdp3, 0, FP_F16,
2410 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2411 {"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2412 {"fnmadd", 0x1fe00000, 0xff208000, floatdp3, 0, FP_F16,
2413 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2414 {"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2415 {"fnmsub", 0x1fe08000, 0xff208000, floatdp3, 0, FP_F16,
2416 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964
NC		 2417 /* Floating-point immediate. */
2418 {"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2419 {"fmov", 0x1ee01000, 0xff201fe0, floatimm, 0, FP_F16,
2420 OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE},
a06ea964
NC		 2421 /* Floating-point conditional select. */
2422 {"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE},
622b9eb1
MW		 2423 {"fcsel", 0x1ee00c00, 0xff200c00, floatsel, 0, FP_F16,
2424 OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE},
a06ea964
NC		 2425 /* Load/store register (immediate indexed). */
2426 {"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2427 {"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2428 {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2429 {"str", 0x3c000400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2430 {"ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2431 {"strh", 0x78000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2432 {"ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2433 {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2434 {"str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2435 {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2436 {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2437 /* Load/store register (unsigned immediate). */
2438 {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2439 {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2440 {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE},
2441 {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2442 {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2443 {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2444 {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2445 {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE},
2446 {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2447 {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2448 {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0},
2449 {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0},
2450 /* Load/store register (register offset). */
2451 {"strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2452 {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2453 {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE},
2454 {"str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2455 {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2456 {"strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2457 {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2458 {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE},
2459 {"str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2460 {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2461 {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0},
2462 {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0},
2463 /* Load/store register (unprivileged). */
2464 {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2465 {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2466 {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2467 {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2468 {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2469 {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2470 {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2471 {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2472 {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2473 /* Load/store register (unscaled immediate). */
c8f89a34
JW		 2474 {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2475 {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2476 {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2477 {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2478 {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2479 {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2480 {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2481 {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2482 {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2483 {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2484 {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2485 {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0},
a06ea964
NC		 2486 /* Load/store exclusive. */
2487 {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2488 {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2489 {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2490 {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2491 {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
ee804238 2492 {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2493 {"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2494 {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2495 {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2496 {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2497 {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
ee804238 2498 {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2499 {"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2500 {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2501 {"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2502 {"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2503 {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2504 {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2505 {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2506 {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2507 {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
ee804238 2508 {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
290806fd
MW		 2509 /* Limited Ordering Regions load/store instructions. */
2510 {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2511 {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2512 {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2513 {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2514 {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2515 {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2516 /* Load/store no-allocate pair (offset). */
2517 {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2518 {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2519 {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2520 {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2521 /* Load/store register pair (offset). */
2522 {"stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2523 {"ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2524 {"stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2525 {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2526 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2527 /* Load/store register pair (indexed). */
2528 {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2529 {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2530 {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2531 {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2532 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2533 /* Load register (literal). */
2534 {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q},
2535 {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0},
2536 {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0},
2537 {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0},
2538 /* Logical (immediate). */
2539 {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2540 {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF},
2541 {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
fb098a1e 2542 {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964
NC		 2543 {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF},
2544 {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2545 {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF},
2546 /* Logical (shifted register). */
2547 {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2548 {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2549 {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
8678914f 2550 {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
a06ea964
NC		 2551 {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO},
2552 {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2553 {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2554 {"eor", 0x4a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2555 {"eon", 0x4a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2556 {"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2557 {"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2558 {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
ee804238
JW		 2559 /* LSE extension (atomic). */
2560 {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2561 {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2562 {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2563 {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2564 {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2565 {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2566 {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2567 {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2568 {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2569 {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2570 {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2571 {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2572 {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2573 {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2574 {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2575 {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2576 {"swpb", 0x38208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2577 {"swph", 0x78208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2578 {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2579 {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2580 {"swplb", 0x38608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2581 {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2582 {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2583 {"swplh", 0x78608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2584 {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2585 {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2586 {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2587 {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2588 {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2589 {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2590 {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2591 {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2592 {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2593 {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2594 {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2595 {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2596 {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2597 {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2598 {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2599 {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2600 {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2601 {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2602 {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2603 {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2604 {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2605 {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2606 {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2607 {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2608 {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2609 {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2610 {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2611 {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2612 {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2613 {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2614 {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2615 {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2616 {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2617 {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2618 {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2619 {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2620 {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2621 {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2622 {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2623 {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2624 {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2625 {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2626 {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2627 {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2628 {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2629 {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2630 {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2631 {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2632 {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2633 {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2634 {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2635 {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2636 {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2637 {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2638 {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2639 {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2640 {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2641 {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2642 {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2643 {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2644 {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2645 {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2646 {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2647 {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2648 {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2649 {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2650 {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2651 {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2652 {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2653 {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2654 {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2655 {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2656 {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2657 {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2658 {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2659 {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2660 {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2661 {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2662 {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2663 {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2664 {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2665 {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2666 {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2667 {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2668 {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2669 {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2670 {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2671 {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2672 {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2673 {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2674 {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2675 {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2676 {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2677 {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2678 {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2679 {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2680 {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2681 {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2682 {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2683 {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2684 {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2685 {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2686 {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2687 {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2688 {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2689 {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2690 {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2691 {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2692 {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2693 {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2694 {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2695 {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2696 {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2697 {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2698 {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2699 {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2700 {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2701 {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2702 {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2703 {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2704 {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2705 {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2706 {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2707 {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2708 {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2709 {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2710 {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2711 {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2712 {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2713 {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2714 {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2715 {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2716 {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2717 {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2718 {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2719 {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2720 {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2721 {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2722 {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2723 {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2724 {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2725 {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2726 {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2727 {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2728 {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2729 {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2730 {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2731 {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
a06ea964
NC		 2732 /* Move wide (immediate). */
2733 {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
fb098a1e 2734 {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
a06ea964 2735 {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
fb098a1e 2736 {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
a06ea964
NC		 2737 {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF},
2738 /* PC-rel. addressing. */
2739 {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0},
2740 {"adrp", 0x90000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0},
2741 /* System. */
2742 {"msr", 0xd500401f, 0xfff8f01f, ic_system, 0, CORE, OP2 (PSTATEFIELD, UIMM4), {}, 0},
2743 {"hint", 0xd503201f, 0xfffff01f, ic_system, 0, CORE, OP1 (UIMM7), {}, F_HAS_ALIAS},
2744 {"nop", 0xd503201f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2745 {"yield", 0xd503203f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2746 {"wfe", 0xd503205f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2747 {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2748 {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2749 {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
c8a6db6f 2750 {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
1e6f4800
MW		 2751 {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE,
2752 OP1 (BARRIER_PSB), {}, F_ALIAS },
a06ea964
NC		 2753 {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2754 {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2755 {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2756 {"isb", 0xd50330df, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2757 {"sys", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)},
2758 {"at", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS},
2759 {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
2760 {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
2761 {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
df7b4545 2762 {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
a06ea964 2763 {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
df7b4545 2764 {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
a06ea964
NC		 2765 /* Test & branch (immediate). */
2766 {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2767 {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2768 /* The old UAL conditional branch mnemonics (to aid portability). */
2769 {"beq", 0x54000000, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2770 {"bne", 0x54000001, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2771 {"bcs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2772 {"bhs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2773 {"bcc", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2774 {"blo", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2775 {"bmi", 0x54000004, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2776 {"bpl", 0x54000005, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2777 {"bvs", 0x54000006, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2778 {"bvc", 0x54000007, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2779 {"bhi", 0x54000008, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2780 {"bls", 0x54000009, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2781 {"bge", 0x5400000a, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2782 {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2783 {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2784 {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2785
2786 {0, 0, 0, 0, 0, 0, {}, {}, 0},
2787};
2788
2789#ifdef AARCH64_OPERANDS
2790#undef AARCH64_OPERANDS
2791#endif
2792
2793/* Macro-based operand decription; this will be fed into aarch64-gen for it
2794 to generate the structure aarch64_operands and the function
2795 aarch64_insert_operand and aarch64_extract_operand.
2796
2797 These inserters and extracters in the description execute the conversion
2798 between the aarch64_opnd_info and value in the operand-related instruction
2799 field(s). */
2800
2801/* Y expects arguments (left to right) to be operand class, inserter/extractor
2802 name suffix, operand name, flags, related bitfield(s) and description.
2803 X only differs from Y by having the operand inserter and extractor names
2804 listed separately. */
2805
2806#define AARCH64_OPERANDS \
2807 Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \
2808 Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \
2809 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
2810 Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
2811 Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
2812 Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
2813 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
2814 X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
2815 "an integer register") \
2816 Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \
2817 "an integer or stack pointer register") \
2818 Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
2819 "an integer or stack pointer register") \
ee804238
JW		 2820 X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
2821 "the second reg of a pair") \
a06ea964
NC		 2822 Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
2823 "an integer register with optional extension") \
2824 Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
2825 "an integer register with optional shift") \
2826 Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \
2827 Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \
2828 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
2829 Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \
2830 Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \
2831 Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \
2832 Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
2833 Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
2834 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
2835 Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
2836 Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
2837 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
2838 Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \
2839 "the top half of a 128-bit FP/SIMD register") \
2840 Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \
2841 "the top half of a 128-bit FP/SIMD register") \
2842 Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \
2843 "a SIMD vector element") \
2844 Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \
2845 "a SIMD vector element") \
2846 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
2847 "a SIMD vector element") \
2848 Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \
2849 "a SIMD vector register list") \
2850 Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \
2851 "a SIMD vector register list") \
2852 Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \
2853 "a SIMD vector register list") \
2854 Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \
2855 "a SIMD vector element list") \
2856 Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \
2857 "a 4-bit opcode field named for historical reasons C0 - C15") \
2858 Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \
2859 "a 4-bit opcode field named for historical reasons C0 - C15") \
2860 Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
2861 "an immediate as the index of the least significant byte") \
2862 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
2863 "a left shift amount for an AdvSIMD register") \
2864 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \
2865 "a right shift amount for an AdvSIMD register") \
2866 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \
2867 "an immediate") \
2868 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \
2869 "an 8-bit unsigned immediate with optional shift") \
2870 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \
2871 "an 8-bit floating-point constant") \
2872 X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \
2873 "an immediate shift amount of 8, 16 or 32") \
2874 X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \
2875 X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \
2876 Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \
2877 "an 8-bit floating-point constant") \
2878 Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \
2879 "the right rotate amount") \
2880 Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \
2881 "the leftmost bit number to be moved from the source") \
2882 Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
2883 "the width of the bit-field") \
2884 Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
2885 Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
2886 "a 3-bit unsigned immediate") \
2887 Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
2888 "a 3-bit unsigned immediate") \
2889 Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
2890 "a 4-bit unsigned immediate") \
2891 Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
2892 "a 7-bit unsigned immediate") \
2893 Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
2894 "the bit number to be tested") \
2895 Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
2896 "a 16-bit unsigned immediate") \
2897 Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
2898 "a 5-bit unsigned immediate") \
2899 Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \
2900 "a flag bit specifier giving an alternative value for each flag") \
2901 Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \
2902 "Logical immediate") \
2903 Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \
2904 "a 12-bit unsigned immediate with optional left shift of 12 bits")\
2905 Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \
2906 "a 16-bit immediate with optional left shift") \
2907 Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
2908 "the number of bits after the binary point in the fixed-point value")\
2909 X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
68a64283
YZ		 2910 Y(COND, cond, "COND", 0, F(), "a condition") \
2911 Y(COND, cond, "COND1", 0, F(), \
2912 "one of the standard conditions, excluding AL and NV.") \
a06ea964
NC		 2913 X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
2914 "21-bit PC-relative address of a 4KB page") \
2915 Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2916 F(FLD_imm14), "14-bit PC-relative address") \
2917 Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2918 F(FLD_imm19), "19-bit PC-relative address") \
2919 Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \
2920 "21-bit PC-relative address") \
2921 Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2922 F(FLD_imm26), "26-bit PC-relative address") \
2923 Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
2924 "an address with base register (no offset)") \
2925 Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
2926 "an address with register offset") \
2927 Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
2928 "an address with 7-bit signed immediate offset") \
2929 Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \
2930 "an address with 9-bit signed immediate offset") \
2931 Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
2932 "an address with 9-bit negative or unaligned immediate offset") \
2933 Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
2934 "an address with scaled, unsigned immediate offset") \
2935 Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
2936 "an address with base register (no offset)") \
2937 Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
2938 "a post-indexed address with immediate or register increment") \
2939 Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
2940 Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
2941 "a PSTATE field name") \
2942 Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
2943 "an address translation operation specifier") \
2944 Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \
2945 "a data cache maintenance operation specifier") \
2946 Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \
9ed608f9 2947 "an instruction cache maintenance operation specifier") \
a06ea964
NC		 2948 Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
2949 "a TBL invalidation operation specifier") \
2950 Y(SYSTEM, barrier, "BARRIER", 0, F(), \
2951 "a barrier option name") \
2952 Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
2953 "the ISB option name SY or an optional 4-bit unsigned immediate") \
2954 Y(SYSTEM, prfop, "PRFOP", 0, F(), \
1e6f4800
MW		 2955 "a prefetch operation specifier") \
2956 Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \
2957 "the PSB option name CSYNC")
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