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PR24435, buffer overflow reading dynamic entries
[thirdparty/binutils-gdb.git] / opcodes / arc-opc.c
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252b5132 1/* Opcode table for the ARC.
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
abe7c33b 33/* Insert RA register into a 32-bit opcode, with checks. */
c0c31e91 34
abe7c33b 35static unsigned long long
c0c31e91
RZ		 36insert_ra_chk (unsigned long long insn,
37 long long value,
38 const char ** errmsg)
abe7c33b
CZ		 39{
40 if (value == 60)
41 *errmsg = _("LP_COUNT register cannot be used as destination register");
42
43 return insn | (value & 0x3F);
44}
c0c31e91 45
886a2506 46/* Insert RB register into a 32-bit opcode. */
c0c31e91 47
bdfe53e3 48static unsigned long long
c0c31e91
RZ		 49insert_rb (unsigned long long insn,
50 long long value,
51 const char ** errmsg ATTRIBUTE_UNUSED)
252b5132 52{
886a2506
NC		 53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
54}
0d2bcfaf 55
abe7c33b 56/* Insert RB register with checks. */
c0c31e91 57
abe7c33b 58static unsigned long long
c0c31e91
RZ		 59insert_rb_chk (unsigned long long insn,
60 long long value,
61 const char ** errmsg)
abe7c33b
CZ		 62{
63 if (value == 60)
64 *errmsg = _("LP_COUNT register cannot be used as destination register");
65
66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
67}
68
c0c31e91
RZ		 69static long long
70extract_rb (unsigned long long insn,
71 bfd_boolean * invalid)
886a2506
NC		 72{
73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 74
886a2506
NC		 75 if (value == 0x3e && invalid)
76 *invalid = TRUE; /* A limm operand, it should be extracted in a
77 different way. */
252b5132 78
886a2506
NC		 79 return value;
80}
252b5132 81
bdfe53e3 82static unsigned long long
c0c31e91
RZ		 83insert_rad (unsigned long long insn,
84 long long value,
85 const char ** errmsg)
886a2506
NC		 86{
87 if (value & 0x01)
abe7c33b
CZ		 88 *errmsg = _("cannot use odd number destination register");
89 if (value == 60)
90 *errmsg = _("LP_COUNT register cannot be used as destination register");
0d2bcfaf 91
886a2506
NC		 92 return insn | (value & 0x3F);
93}
0d2bcfaf 94
bdfe53e3 95static unsigned long long
c0c31e91
RZ		 96insert_rcd (unsigned long long insn,
97 long long value,
98 const char ** errmsg)
886a2506
NC		 99{
100 if (value & 0x01)
abe7c33b 101 *errmsg = _("cannot use odd number source register");
0d2bcfaf 102
886a2506
NC		 103 return insn | ((value & 0x3F) << 6);
104}
252b5132 105
886a2506 106/* Dummy insert ZERO operand function. */
252b5132 107
bdfe53e3 108static unsigned long long
c0c31e91
RZ		 109insert_za (unsigned long long insn,
110 long long value,
111 const char ** errmsg)
886a2506
NC		 112{
113 if (value)
114 *errmsg = _("operand is not zero");
115 return insn;
116}
252b5132 117
886a2506
NC		 118/* Insert Y-bit in bbit/br instructions. This function is called only
119 when solving fixups. */
252b5132 120
bdfe53e3 121static unsigned long long
c0c31e91
RZ		 122insert_Ybit (unsigned long long insn,
123 long long value,
124 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 125{
126 if (value > 0)
127 insn |= 0x08;
252b5132 128
886a2506
NC		 129 return insn;
130}
252b5132 131
886a2506
NC		 132/* Insert Y-bit in bbit/br instructions. This function is called only
133 when solving fixups. */
252b5132 134
bdfe53e3 135static unsigned long long
c0c31e91
RZ		 136insert_NYbit (unsigned long long insn,
137 long long value,
138 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 139{
140 if (value < 0)
141 insn |= 0x08;
0d2bcfaf 142
886a2506
NC		 143 return insn;
144}
252b5132 145
886a2506 146/* Insert H register into a 16-bit opcode. */
252b5132 147
bdfe53e3 148static unsigned long long
c0c31e91
RZ		 149insert_rhv1 (unsigned long long insn,
150 long long value,
151 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 152{
153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
154}
252b5132 155
c0c31e91
RZ		 156static long long
157extract_rhv1 (unsigned long long insn,
158 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506 159{
02f3be19 160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 161
886a2506
NC		 162 return value;
163}
252b5132 164
886a2506 165/* Insert H register into a 16-bit opcode. */
252b5132 166
bdfe53e3 167static unsigned long long
c0c31e91
RZ		 168insert_rhv2 (unsigned long long insn,
169 long long value,
170 const char ** errmsg)
0d2bcfaf 171{
886a2506 172 if (value == 0x1E)
7cbc739c 173 *errmsg = _("register R30 is a limm indicator");
dc958481 174 else if (value < 0 || value > 31)
175 *errmsg = _("register out of range");
886a2506
NC		 176 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
177}
252b5132 178
c0c31e91
RZ		 179static long long
180extract_rhv2 (unsigned long long insn,
181 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 182{
183 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 184
886a2506
NC		 185 return value;
186}
0d2bcfaf 187
bdfe53e3 188static unsigned long long
c0c31e91
RZ		 189insert_r0 (unsigned long long insn,
190 long long value,
191 const char ** errmsg)
886a2506
NC		 192{
193 if (value != 0)
7cbc739c 194 *errmsg = _("register must be R0");
47b0e7ad
NC		 195 return insn;
196}
252b5132 197
c0c31e91 198static long long
bdfe53e3 199extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 200 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 201{
886a2506 202 return 0;
47b0e7ad 203}
252b5132 204
252b5132 205
bdfe53e3 206static unsigned long long
c0c31e91
RZ		 207insert_r1 (unsigned long long insn,
208 long long value,
209 const char ** errmsg)
252b5132 210{
886a2506 211 if (value != 1)
7cbc739c 212 *errmsg = _("register must be R1");
47b0e7ad 213 return insn;
252b5132
RH		 214}
215
c0c31e91 216static long long
bdfe53e3 217extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 218 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 219{
886a2506 220 return 1;
252b5132
RH		 221}
222
bdfe53e3 223static unsigned long long
c0c31e91
RZ		 224insert_r2 (unsigned long long insn,
225 long long value,
226 const char ** errmsg)
252b5132 227{
886a2506 228 if (value != 2)
7cbc739c 229 *errmsg = _("register must be R2");
47b0e7ad 230 return insn;
252b5132
RH		 231}
232
c0c31e91 233static long long
bdfe53e3 234extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 235 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 236{
886a2506 237 return 2;
252b5132
RH		 238}
239
bdfe53e3 240static unsigned long long
c0c31e91
RZ		 241insert_r3 (unsigned long long insn,
242 long long value,
243 const char ** errmsg)
252b5132 244{
886a2506 245 if (value != 3)
7cbc739c 246 *errmsg = _("register must be R3");
47b0e7ad 247 return insn;
0d2bcfaf
NC		 248}
249
c0c31e91 250static long long
bdfe53e3 251extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 252 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 253{
886a2506 254 return 3;
0d2bcfaf
NC		 255}
256
bdfe53e3 257static unsigned long long
c0c31e91
RZ		 258insert_sp (unsigned long long insn,
259 long long value,
260 const char ** errmsg)
252b5132 261{
886a2506 262 if (value != 28)
7cbc739c 263 *errmsg = _("register must be SP");
252b5132
RH		 264 return insn;
265}
266
c0c31e91 267static long long
bdfe53e3 268extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 269 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 270{
886a2506 271 return 28;
0d2bcfaf
NC		 272}
273
bdfe53e3 274static unsigned long long
c0c31e91
RZ		 275insert_gp (unsigned long long insn,
276 long long value,
277 const char ** errmsg)
0d2bcfaf 278{
886a2506 279 if (value != 26)
7cbc739c 280 *errmsg = _("register must be GP");
886a2506 281 return insn;
0d2bcfaf
NC		 282}
283
c0c31e91 284static long long
bdfe53e3 285extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 286 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 287{
886a2506 288 return 26;
0d2bcfaf
NC		 289}
290
bdfe53e3 291static unsigned long long
c0c31e91
RZ		 292insert_pcl (unsigned long long insn,
293 long long value,
294 const char ** errmsg)
252b5132 295{
886a2506 296 if (value != 63)
7cbc739c 297 *errmsg = _("register must be PCL");
252b5132
RH		 298 return insn;
299}
300
c0c31e91 301static long long
bdfe53e3 302extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 303 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 304{
886a2506 305 return 63;
0d2bcfaf
NC		 306}
307
bdfe53e3 308static unsigned long long
c0c31e91
RZ		 309insert_blink (unsigned long long insn,
310 long long value,
311 const char ** errmsg)
252b5132 312{
886a2506 313 if (value != 31)
7cbc739c 314 *errmsg = _("register must be BLINK");
252b5132
RH		 315 return insn;
316}
317
c0c31e91 318static long long
bdfe53e3 319extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 320 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 321{
886a2506 322 return 31;
0d2bcfaf
NC		 323}
324
bdfe53e3 325static unsigned long long
c0c31e91
RZ		 326insert_ilink1 (unsigned long long insn,
327 long long value,
328 const char ** errmsg)
0d2bcfaf 329{
886a2506 330 if (value != 29)
7cbc739c 331 *errmsg = _("register must be ILINK1");
252b5132
RH		 332 return insn;
333}
334
c0c31e91 335static long long
bdfe53e3 336extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 337 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 338{
886a2506 339 return 29;
252b5132
RH		 340}
341
bdfe53e3 342static unsigned long long
c0c31e91
RZ		 343insert_ilink2 (unsigned long long insn,
344 long long value,
345 const char ** errmsg)
252b5132 346{
886a2506 347 if (value != 30)
7cbc739c 348 *errmsg = _("register must be ILINK2");
252b5132
RH		 349 return insn;
350}
351
c0c31e91 352static long long
bdfe53e3 353extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 354 bfd_boolean * invalid ATTRIBUTE_UNUSED)
355{
356 return 30;
357}
252b5132 358
bdfe53e3 359static unsigned long long
c0c31e91
RZ		 360insert_ras (unsigned long long insn,
361 long long value,
362 const char ** errmsg)
252b5132 363{
886a2506 364 switch (value)
0d2bcfaf 365 {
886a2506
NC		 366 case 0:
367 case 1:
368 case 2:
369 case 3:
370 insn |= value;
371 break;
372 case 12:
373 case 13:
374 case 14:
375 case 15:
376 insn |= (value - 8);
377 break;
378 default:
7cbc739c 379 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 380 break;
0d2bcfaf 381 }
252b5132
RH		 382 return insn;
383}
252b5132 384
c0c31e91
RZ		 385static long long
386extract_ras (unsigned long long insn,
387 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 388{
886a2506 389 int value = insn & 0x07;
c0c31e91 390
886a2506
NC		 391 if (value > 3)
392 return (value + 8);
393 else
394 return value;
47b0e7ad
NC		 395}
396
bdfe53e3 397static unsigned long long
c0c31e91
RZ		 398insert_rbs (unsigned long long insn,
399 long long value,
400 const char ** errmsg)
252b5132 401{
886a2506 402 switch (value)
47b0e7ad 403 {
886a2506
NC		 404 case 0:
405 case 1:
406 case 2:
407 case 3:
408 insn |= value << 8;
409 break;
410 case 12:
411 case 13:
412 case 14:
413 case 15:
414 insn |= ((value - 8)) << 8;
415 break;
416 default:
7cbc739c 417 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 418 break;
47b0e7ad 419 }
886a2506 420 return insn;
252b5132
RH		 421}
422
c0c31e91
RZ		 423static long long
424extract_rbs (unsigned long long insn,
425 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 426{
886a2506 427 int value = (insn >> 8) & 0x07;
c0c31e91 428
886a2506
NC		 429 if (value > 3)
430 return (value + 8);
431 else
432 return value;
433}
252b5132 434
bdfe53e3 435static unsigned long long
c0c31e91
RZ		 436insert_rcs (unsigned long long insn,
437 long long value,
438 const char ** errmsg)
886a2506
NC		 439{
440 switch (value)
252b5132 441 {
886a2506
NC		 442 case 0:
443 case 1:
444 case 2:
445 case 3:
446 insn |= value << 5;
447 break;
448 case 12:
449 case 13:
450 case 14:
451 case 15:
452 insn |= ((value - 8)) << 5;
453 break;
454 default:
7cbc739c 455 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 456 break;
252b5132 457 }
886a2506
NC		 458 return insn;
459}
47b0e7ad 460
c0c31e91
RZ		 461static long long
462extract_rcs (unsigned long long insn,
463 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 464{
465 int value = (insn >> 5) & 0x07;
c0c31e91 466
886a2506
NC		 467 if (value > 3)
468 return (value + 8);
252b5132 469 else
886a2506
NC		 470 return value;
471}
47b0e7ad 472
bdfe53e3 473static unsigned long long
c0c31e91
RZ		 474insert_simm3s (unsigned long long insn,
475 long long value,
476 const char ** errmsg)
886a2506
NC		 477{
478 int tmp = 0;
479 switch (value)
47b0e7ad 480 {
886a2506
NC		 481 case -1:
482 tmp = 0x07;
47b0e7ad 483 break;
886a2506
NC		 484 case 0:
485 tmp = 0x00;
486 break;
487 case 1:
488 tmp = 0x01;
47b0e7ad 489 break;
886a2506
NC		 490 case 2:
491 tmp = 0x02;
47b0e7ad 492 break;
886a2506
NC		 493 case 3:
494 tmp = 0x03;
495 break;
496 case 4:
497 tmp = 0x04;
498 break;
499 case 5:
500 tmp = 0x05;
501 break;
502 case 6:
503 tmp = 0x06;
504 break;
505 default:
7cbc739c 506 *errmsg = _("accepted values are from -1 to 6");
47b0e7ad
NC		 507 break;
508 }
509
886a2506
NC		 510 insn |= tmp << 8;
511 return insn;
47b0e7ad
NC		 512}
513
c0c31e91
RZ		 514static long long
515extract_simm3s (unsigned long long insn,
516 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 517{
886a2506 518 int value = (insn >> 8) & 0x07;
c0c31e91 519
886a2506
NC		 520 if (value == 7)
521 return -1;
47b0e7ad 522 else
886a2506 523 return value;
47b0e7ad
NC		 524}
525
bdfe53e3 526static unsigned long long
c0c31e91
RZ		 527insert_rrange (unsigned long long insn,
528 long long value,
529 const char ** errmsg)
47b0e7ad 530{
886a2506
NC		 531 int reg1 = (value >> 16) & 0xFFFF;
532 int reg2 = value & 0xFFFF;
c0c31e91 533
886a2506 534 if (reg1 != 13)
7cbc739c 535 *errmsg = _("first register of the range should be r13");
c0c31e91 536 else if (reg2 < 13 || reg2 > 26)
7cbc739c 537 *errmsg = _("last register of the range doesn't fit");
c0c31e91
RZ		 538 else
539 insn |= ((reg2 - 12) & 0x0F) << 1;
886a2506 540 return insn;
47b0e7ad
NC		 541}
542
c0c31e91
RZ		 543static long long
544extract_rrange (unsigned long long insn,
545 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 546{
547 return (insn >> 1) & 0x0F;
548}
47b0e7ad 549
126124cc
CZ		 550static unsigned long long
551insert_r13el (unsigned long long insn,
552 long long int value,
553 const char **errmsg)
554{
555 if (value != 13)
556 {
7cbc739c 557 *errmsg = _("invalid register number, should be fp");
126124cc
CZ		 558 return insn;
559 }
560
561 insn |= 0x02;
562 return insn;
563}
564
bdfe53e3 565static unsigned long long
c0c31e91
RZ		 566insert_fpel (unsigned long long insn,
567 long long value,
568 const char ** errmsg)
47b0e7ad 569{
886a2506
NC		 570 if (value != 27)
571 {
7cbc739c 572 *errmsg = _("invalid register number, should be fp");
886a2506
NC		 573 return insn;
574 }
47b0e7ad 575
886a2506
NC		 576 insn |= 0x0100;
577 return insn;
47b0e7ad
NC		 578}
579
c0c31e91
RZ		 580static long long
581extract_fpel (unsigned long long insn,
582 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 583{
886a2506 584 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 585}
586
bdfe53e3 587static unsigned long long
c0c31e91
RZ		 588insert_blinkel (unsigned long long insn,
589 long long value,
590 const char ** errmsg)
47b0e7ad 591{
886a2506 592 if (value != 31)
47b0e7ad 593 {
7cbc739c 594 *errmsg = _("invalid register number, should be blink");
886a2506 595 return insn;
47b0e7ad 596 }
47b0e7ad 597
886a2506
NC		 598 insn |= 0x0200;
599 return insn;
47b0e7ad
NC		 600}
601
c0c31e91
RZ		 602static long long
603extract_blinkel (unsigned long long insn,
604 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 605{
886a2506
NC		 606 return (insn & 0x0200) ? 31 : -1;
607}
47b0e7ad 608
bdfe53e3 609static unsigned long long
c0c31e91
RZ		 610insert_pclel (unsigned long long insn,
611 long long value,
612 const char ** errmsg)
886a2506
NC		 613{
614 if (value != 63)
47b0e7ad 615 {
7cbc739c 616 *errmsg = _("invalid register number, should be pcl");
886a2506 617 return insn;
47b0e7ad 618 }
47b0e7ad 619
886a2506
NC		 620 insn |= 0x0400;
621 return insn;
622}
47b0e7ad 623
c0c31e91
RZ		 624static long long
625extract_pclel (unsigned long long insn,
626 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 627{
886a2506 628 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 629}
47b0e7ad 630
886a2506 631#define INSERT_W6
c0c31e91 632
886a2506
NC		 633/* mask = 00000000000000000000111111000000
634 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
c0c31e91 635
bdfe53e3 636static unsigned long long
c0c31e91
RZ		 637insert_w6 (unsigned long long insn,
638 long long value,
639 const char ** errmsg ATTRIBUTE_UNUSED)
47b0e7ad 640{
886a2506 641 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 642
886a2506
NC		 643 return insn;
644}
47b0e7ad 645
886a2506 646#define EXTRACT_W6
c0c31e91 647
886a2506 648/* mask = 00000000000000000000111111000000. */
c0c31e91
RZ		 649
650static long long
651extract_w6 (unsigned long long insn,
652 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 653{
04e65276 654 int value = 0;
47b0e7ad 655
886a2506 656 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 657
04e65276
CZ		 658 /* Extend the sign. */
659 int signbit = 1 << 5;
660 value = (value ^ signbit) - signbit;
661
886a2506
NC		 662 return value;
663}
47b0e7ad 664
886a2506 665#define INSERT_G_S
c0c31e91 666
886a2506
NC		 667/* mask = 0000011100022000
668 insn = 01000ggghhhGG0HH. */
c0c31e91 669
bdfe53e3 670static unsigned long long
c0c31e91
RZ		 671insert_g_s (unsigned long long insn,
672 long long value,
673 const char ** errmsg ATTRIBUTE_UNUSED)
47b0e7ad 674{
886a2506
NC		 675 insn |= ((value >> 0) & 0x0007) << 8;
676 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 677
886a2506
NC		 678 return insn;
679}
252b5132 680
886a2506 681#define EXTRACT_G_S
c0c31e91 682
886a2506 683/* mask = 0000011100022000. */
c0c31e91
RZ		 684
685static long long
686extract_g_s (unsigned long long insn,
687 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 688{
689 int value = 0;
c0c31e91 690 int signbit = 1 << (6 - 1);
252b5132 691
886a2506
NC		 692 value |= ((insn >> 8) & 0x0007) << 0;
693 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 694
886a2506 695 /* Extend the sign. */
886a2506 696 value = (value ^ signbit) - signbit;
252b5132 697
886a2506 698 return value;
252b5132
RH		 699}
700
e23e8ebe 701/* ARC NPS400 Support: See comment near head of file. */
bdfe53e3
AB		 702#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
703static unsigned long long \
704insert_nps_3bit_reg_at_##OFFSET##_##NAME \
c0c31e91
RZ		 705 (unsigned long long insn, \
706 long long value, \
707 const char ** errmsg) \
bdfe53e3
AB		 708{ \
709 switch (value) \
710 { \
711 case 0: \
712 case 1: \
713 case 2: \
714 case 3: \
715 insn |= value << (OFFSET); \
716 break; \
717 case 12: \
718 case 13: \
719 case 14: \
720 case 15: \
721 insn |= (value - 8) << (OFFSET); \
722 break; \
723 default: \
7cbc739c 724 *errmsg = _("register must be either r0-r3 or r12-r15"); \
bdfe53e3
AB		 725 break; \
726 } \
727 return insn; \
728} \
729 \
c0c31e91 730static long long \
bdfe53e3 731extract_nps_3bit_reg_at_##OFFSET##_##NAME \
c0c31e91
RZ		 732 (unsigned long long insn, \
733 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
bdfe53e3
AB		 734{ \
735 int value = (insn >> (OFFSET)) & 0x07; \
736 if (value > 3) \
737 value += 8; \
738 return value; \
739} \
740
741MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
742MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
743MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
744MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
745
746MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
747MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
748MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
749MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
750
751static unsigned long long
c0c31e91
RZ		 752insert_nps_bitop_size_2b (unsigned long long insn,
753 long long value,
754 const char ** errmsg)
820f03ff
AB		 755{
756 switch (value)
757 {
758 case 1:
759 value = 0;
760 break;
761 case 2:
762 value = 1;
763 break;
764 case 4:
765 value = 2;
766 break;
767 case 8:
768 value = 3;
769 break;
770 default:
771 value = 0;
7cbc739c 772 *errmsg = _("invalid size, should be 1, 2, 4, or 8");
820f03ff
AB		 773 break;
774 }
775
776 insn |= value << 10;
777 return insn;
778}
779
c0c31e91
RZ		 780static long long
781extract_nps_bitop_size_2b (unsigned long long insn,
782 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 783{
784 return 1 << ((insn >> 10) & 0x3);
785}
786
bdfe53e3 787static unsigned long long
c0c31e91
RZ		 788insert_nps_bitop_uimm8 (unsigned long long insn,
789 long long value,
790 const char ** errmsg ATTRIBUTE_UNUSED)
820f03ff
AB		 791{
792 insn |= ((value >> 5) & 7) << 12;
793 insn |= (value & 0x1f);
794 return insn;
795}
796
c0c31e91
RZ		 797static long long
798extract_nps_bitop_uimm8 (unsigned long long insn,
799 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 800{
801 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
802}
803
bdfe53e3 804static unsigned long long
c0c31e91
RZ		 805insert_nps_rflt_uimm6 (unsigned long long insn,
806 long long value,
807 const char ** errmsg)
820f03ff
AB		 808{
809 switch (value)
810 {
811 case 1:
812 case 2:
813 case 4:
814 break;
815
816 default:
817 *errmsg = _("invalid immediate, must be 1, 2, or 4");
818 value = 0;
819 }
820
821 insn |= (value << 6);
822 return insn;
823}
824
c0c31e91
RZ		 825static long long
826extract_nps_rflt_uimm6 (unsigned long long insn,
827 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 828{
829 return (insn >> 6) & 0x3f;
830}
831
bdfe53e3 832static unsigned long long
c0c31e91
RZ		 833insert_nps_dst_pos_and_size (unsigned long long insn,
834 long long value,
835 const char ** errmsg ATTRIBUTE_UNUSED)
820f03ff
AB		 836{
837 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
838 return insn;
839}
840
c0c31e91
RZ		 841static long long
842extract_nps_dst_pos_and_size (unsigned long long insn,
843 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 844{
845 return (insn & 0x1f);
846}
847
bdfe53e3 848static unsigned long long
c0c31e91
RZ		 849insert_nps_cmem_uimm16 (unsigned long long insn,
850 long long value,
851 const char ** errmsg)
4b0c052e
AB		 852{
853 int top = (value >> 16) & 0xffff;
c0c31e91 854
4b0c052e
AB		 855 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
856 *errmsg = _("invalid value for CMEM ld/st immediate");
857 insn |= (value & 0xffff);
858 return insn;
859}
860
c0c31e91
RZ		 861static long long
862extract_nps_cmem_uimm16 (unsigned long long insn,
863 bfd_boolean * invalid ATTRIBUTE_UNUSED)
4b0c052e
AB		 864{
865 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
866}
867
c0c31e91
RZ		 868static unsigned long long
869insert_nps_imm_offset (unsigned long long insn,
870 long long value,
871 const char ** errmsg)
645d3342
RZ		 872{
873 switch (value)
874 {
875 case 0:
876 case 16:
877 case 32:
878 case 48:
879 case 64:
880 value = value >> 4;
881 break;
882 default:
7cbc739c 883 *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
645d3342
RZ		 884 value = 0;
885 }
886 insn |= (value << 10);
887 return insn;
888}
889
c0c31e91
RZ		 890static long long
891extract_nps_imm_offset (unsigned long long insn,
892 bfd_boolean * invalid ATTRIBUTE_UNUSED)
645d3342
RZ		 893{
894 return ((insn >> 10) & 0x7) * 16;
895}
896
897static unsigned long long
c0c31e91
RZ		 898insert_nps_imm_entry (unsigned long long insn,
899 long long value,
900 const char ** errmsg)
645d3342
RZ		 901{
902 switch (value)
903 {
904 case 16:
905 value = 0;
906 break;
907 case 32:
908 value = 1;
909 break;
910 case 64:
911 value = 2;
912 break;
913 case 128:
914 value = 3;
915 break;
916 default:
7cbc739c 917 *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
645d3342
RZ		 918 value = 0;
919 }
920 insn |= (value << 2);
921 return insn;
922}
923
c0c31e91
RZ		 924static long long
925extract_nps_imm_entry (unsigned long long insn,
926 bfd_boolean * invalid ATTRIBUTE_UNUSED)
645d3342
RZ		 927{
928 int imm_entry = ((insn >> 2) & 0x7);
929 return (1 << (imm_entry + 4));
930}
931
c0c31e91
RZ		 932static unsigned long long
933insert_nps_size_16bit (unsigned long long insn,
934 long long value,
935 const char ** errmsg)
936{
937 if ((value < 1) || (value > 64))
938 {
7cbc739c 939 *errmsg = _("invalid size value must be on range 1-64.");
c0c31e91
RZ		 940 value = 0;
941 }
942 value = value & 0x3f;
943 insn |= (value << 6);
944 return insn;
945}
946
947static long long
948extract_nps_size_16bit (unsigned long long insn,
949 bfd_boolean * invalid ATTRIBUTE_UNUSED)
950{
951 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
952}
953
954
955#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
956static unsigned long long \
957insert_nps_##NAME##_pos (unsigned long long insn, \
958 long long value, \
959 const char ** errmsg) \
537aefaf
AB		 960{ \
961 switch (value) \
962 { \
963 case 0: \
964 case 8: \
965 case 16: \
966 case 24: \
967 value = value / 8; \
968 break; \
969 default: \
7cbc739c 970 *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
537aefaf
AB		 971 value = 0; \
972 } \
c0c31e91 973 insn |= (value << SHIFT); \
537aefaf
AB		 974 return insn; \
975} \
976 \
c0c31e91
RZ		 977static long long \
978extract_nps_##NAME##_pos (unsigned long long insn, \
979 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
980{ \
981 return ((insn >> SHIFT) & 0x3) * 8; \
537aefaf
AB		 982}
983
984MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
985MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
986
c0c31e91
RZ		 987#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
988static unsigned long long \
989insert_nps_##NAME (unsigned long long insn, \
990 long long value, \
991 const char ** errmsg) \
537aefaf 992 { \
9ba75c88 993 if (value < LOWER || value > UPPER) \
537aefaf 994 { \
7cbc739c 995 *errmsg = _("invalid size, value must be " \
537aefaf
AB		 996 #LOWER " to " #UPPER "."); \
997 return insn; \
998 } \
999 value -= BIAS; \
1000 insn |= (value << SHIFT); \
1001 return insn; \
1002 } \
1003 \
c0c31e91
RZ		 1004static long long \
1005extract_nps_##NAME (unsigned long long insn, \
1006 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 1007{ \
1008 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
1009}
1010
db18dbab
GM		 1011MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
1012MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
1013MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
1014MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
1015MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
1016MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
1017MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
1018MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
1019MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
1020MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
1021MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf 1022
c0c31e91
RZ		 1023static long long
1024extract_nps_qcmp_m3 (unsigned long long insn,
1025 bfd_boolean * invalid)
537aefaf
AB		 1026{
1027 int m3 = (insn >> 5) & 0xf;
1028 if (m3 == 0xf)
1029 *invalid = TRUE;
1030 return m3;
1031}
1032
c0c31e91
RZ		 1033static long long
1034extract_nps_qcmp_m2 (unsigned long long insn,
1035 bfd_boolean * invalid)
537aefaf
AB		 1036{
1037 bfd_boolean tmp_invalid = FALSE;
1038 int m2 = (insn >> 15) & 0x1;
1039 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1040
1041 if (m2 == 0 && m3 == 0xf)
1042 *invalid = TRUE;
1043 return m2;
1044}
1045
c0c31e91
RZ		 1046static long long
1047extract_nps_qcmp_m1 (unsigned long long insn,
1048 bfd_boolean * invalid)
537aefaf
AB		 1049{
1050 bfd_boolean tmp_invalid = FALSE;
1051 int m1 = (insn >> 14) & 0x1;
1052 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1053 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1054
1055 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1056 *invalid = TRUE;
1057 return m1;
1058}
1059
bdfe53e3 1060static unsigned long long
c0c31e91
RZ		 1061insert_nps_calc_entry_size (unsigned long long insn,
1062 long long value,
1063 const char ** errmsg)
537aefaf
AB		 1064{
1065 unsigned pwr;
1066
1067 if (value < 1 || value > 256)
1068 {
1069 *errmsg = _("value out of range 1 - 256");
1070 return 0;
1071 }
1072
1073 for (pwr = 0; (value & 1) == 0; value >>= 1)
1074 ++pwr;
1075
1076 if (value != 1)
1077 {
1078 *errmsg = _("value must be power of 2");
1079 return 0;
1080 }
1081
1082 return insn | (pwr << 8);
1083}
1084
c0c31e91
RZ		 1085static long long
1086extract_nps_calc_entry_size (unsigned long long insn,
1087 bfd_boolean * invalid ATTRIBUTE_UNUSED)
537aefaf
AB		 1088{
1089 unsigned entry_size = (insn >> 8) & 0xf;
1090 return 1 << entry_size;
1091}
1092
bdfe53e3 1093static unsigned long long
c0c31e91
RZ		 1094insert_nps_bitop_mod4 (unsigned long long insn,
1095 long long value,
1096 const char ** errmsg ATTRIBUTE_UNUSED)
4eb6f892 1097{
bdfe53e3 1098 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
4eb6f892
AB		 1099}
1100
c0c31e91
RZ		 1101static long long
1102extract_nps_bitop_mod4 (unsigned long long insn,
1103 bfd_boolean * invalid ATTRIBUTE_UNUSED)
4eb6f892 1104{
bdfe53e3 1105 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
4eb6f892
AB		 1106}
1107
bdfe53e3 1108static unsigned long long
c0c31e91
RZ		 1109insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1110 long long value,
1111 const char ** errmsg ATTRIBUTE_UNUSED)
4eb6f892 1112{
bdfe53e3 1113 return insn | (value << 42) | (value << 37);
4eb6f892
AB		 1114}
1115
c0c31e91
RZ		 1116static long long
1117extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1118 bfd_boolean * invalid)
4eb6f892 1119{
bdfe53e3 1120 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
4eb6f892 1121 *invalid = TRUE;
bdfe53e3 1122 return ((insn >> 37) & 0x1f);
4eb6f892
AB		 1123}
1124
bdfe53e3 1125static unsigned long long
c0c31e91
RZ		 1126insert_nps_bitop_ins_ext (unsigned long long insn,
1127 long long value,
1128 const char ** errmsg)
4eb6f892
AB		 1129{
1130 if (value < 0 || value > 28)
7cbc739c 1131 *errmsg = _("value must be in the range 0 to 28");
4eb6f892
AB		 1132 return insn | (value << 20);
1133}
1134
c0c31e91
RZ		 1135static long long
1136extract_nps_bitop_ins_ext (unsigned long long insn,
1137 bfd_boolean * invalid)
4eb6f892
AB		 1138{
1139 int value = (insn >> 20) & 0x1f;
c0c31e91 1140
4eb6f892
AB		 1141 if (value > 28)
1142 *invalid = TRUE;
1143 return value;
1144}
1145
14053c19 1146#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
c0c31e91
RZ		 1147static unsigned long long \
1148insert_nps_##NAME (unsigned long long insn, \
1149 long long value, \
1150 const char ** errmsg) \
14053c19
GM		 1151{ \
1152 if (value < 1 || value > UPPER) \
7cbc739c 1153 *errmsg = _("value must be in the range 1 to " #UPPER); \
14053c19
GM		 1154 if (value == UPPER) \
1155 value = 0; \
1156 return insn | (value << SHIFT); \
1157} \
1158 \
c0c31e91
RZ		 1159static long long \
1160extract_nps_##NAME (unsigned long long insn, \
1161 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
14053c19
GM		 1162{ \
1163 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1164 if (value == 0) \
1165 value = UPPER; \
1166 return value; \
1167}
1168
db18dbab
GM		 1169MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1170MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1171MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1172MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1173MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1174MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
5a736821 1175MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
14053c19 1176
bdfe53e3 1177static unsigned long long
c0c31e91
RZ		 1178insert_nps_min_hofs (unsigned long long insn,
1179 long long value,
1180 const char ** errmsg)
14053c19
GM		 1181{
1182 if (value < 0 || value > 240)
7cbc739c 1183 *errmsg = _("value must be in the range 0 to 240");
14053c19 1184 if ((value % 16) != 0)
7cbc739c 1185 *errmsg = _("value must be a multiple of 16");
14053c19
GM		 1186 value = value / 16;
1187 return insn | (value << 6);
1188}
1189
c0c31e91
RZ		 1190static long long
1191extract_nps_min_hofs (unsigned long long insn,
1192 bfd_boolean * invalid ATTRIBUTE_UNUSED)
14053c19
GM		 1193{
1194 int value = (insn >> 6) & 0xF;
1195 return value * 16;
1196}
1197
c0c31e91 1198#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
bdfe53e3 1199static unsigned long long \
c0c31e91
RZ		 1200insert_nps_##NAME (unsigned long long insn, \
1201 long long value, \
1202 const char ** errmsg) \
db18dbab
GM		 1203{ \
1204 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
7cbc739c 1205 *errmsg = _("invalid address type for operand"); \
db18dbab
GM		 1206 return insn; \
1207} \
1208 \
c0c31e91
RZ		 1209static long long \
1210extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1211 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
db18dbab
GM		 1212{ \
1213 return ARC_NPS400_ADDRTYPE_##VALUE; \
1214}
1215
1216MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1217MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1218MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1219MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1220MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1221MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1222MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1223MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1224MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1225MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1226MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1227MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1228MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1229MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1230MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1231MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1232
5a736821 1233static unsigned long long
c0c31e91
RZ		 1234insert_nps_rbdouble_64 (unsigned long long insn,
1235 long long value,
1236 const char ** errmsg)
5a736821
GM		 1237{
1238 if (value < 0 || value > 31)
7cbc739c 1239 *errmsg = _("value must be in the range 0 to 31");
5a736821
GM		 1240 return insn | (value << 43) | (value << 48);
1241}
1242
1243
c0c31e91
RZ		 1244static long long
1245extract_nps_rbdouble_64 (unsigned long long insn,
1246 bfd_boolean * invalid)
5a736821
GM		 1247{
1248 int value1 = (insn >> 43) & 0x1F;
1249 int value2 = (insn >> 48) & 0x1F;
1250
1251 if (value1 != value2)
1252 *invalid = TRUE;
1253
1254 return value1;
1255}
1256
c0c31e91
RZ		 1257static unsigned long long
1258insert_nps_misc_imm_offset (unsigned long long insn,
1259 long long value,
1260 const char ** errmsg)
1261{
1262 if (value & 0x3)
1263 {
7cbc739c 1264 *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
c0c31e91
RZ		 1265 value = 0;
1266 }
1267 insn |= (value << 6);
1268 return insn;
1269}
1270
1271static long long int
1272extract_nps_misc_imm_offset (unsigned long long insn,
1273 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1274{
1275 return ((insn >> 8) & 0x1f) * 4;
1276}
1277
7179e0e6
CZ		 1278static long long int
1279extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
1280 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1281{
1282 int value = 0;
1283
1284 value |= ((insn >> 6) & 0x003f) << 0;
1285 value |= ((insn >> 0) & 0x003f) << 6;
1286
1287 return value;
1288}
1289
886a2506
NC		 1290/* Include the generic extract/insert functions. Order is important
1291 as some of the functions present in the .h may be disabled via
1292 defines. */
1293#include "arc-fxi.h"
252b5132 1294
886a2506 1295/* The flag operands table.
252b5132 1296
886a2506
NC		 1297 The format of the table is
1298 NAME CODE BITS SHIFT FAVAIL. */
1299const struct arc_flag_operand arc_flag_operands[] =
1300{
1301#define F_NULL 0
1302 { 0, 0, 0, 0, 0},
1303#define F_ALWAYS (F_NULL + 1)
1304 { "al", 0, 0, 0, 0 },
1305#define F_RA (F_ALWAYS + 1)
1306 { "ra", 0, 0, 0, 0 },
1307#define F_EQUAL (F_RA + 1)
1308 { "eq", 1, 5, 0, 1 },
1309#define F_ZERO (F_EQUAL + 1)
1310 { "z", 1, 5, 0, 0 },
1311#define F_NOTEQUAL (F_ZERO + 1)
1312 { "ne", 2, 5, 0, 1 },
1313#define F_NOTZERO (F_NOTEQUAL + 1)
1314 { "nz", 2, 5, 0, 0 },
1315#define F_POZITIVE (F_NOTZERO + 1)
1316 { "p", 3, 5, 0, 1 },
1317#define F_PL (F_POZITIVE + 1)
1318 { "pl", 3, 5, 0, 0 },
1319#define F_NEGATIVE (F_PL + 1)
1320 { "n", 4, 5, 0, 1 },
1321#define F_MINUS (F_NEGATIVE + 1)
1322 { "mi", 4, 5, 0, 0 },
1323#define F_CARRY (F_MINUS + 1)
1324 { "c", 5, 5, 0, 1 },
1325#define F_CARRYSET (F_CARRY + 1)
1326 { "cs", 5, 5, 0, 0 },
1327#define F_LOWER (F_CARRYSET + 1)
1328 { "lo", 5, 5, 0, 0 },
1329#define F_CARRYCLR (F_LOWER + 1)
1330 { "cc", 6, 5, 0, 0 },
1331#define F_NOTCARRY (F_CARRYCLR + 1)
1332 { "nc", 6, 5, 0, 1 },
1333#define F_HIGHER (F_NOTCARRY + 1)
1334 { "hs", 6, 5, 0, 0 },
1335#define F_OVERFLOWSET (F_HIGHER + 1)
1336 { "vs", 7, 5, 0, 0 },
1337#define F_OVERFLOW (F_OVERFLOWSET + 1)
1338 { "v", 7, 5, 0, 1 },
1339#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1340 { "nv", 8, 5, 0, 1 },
1341#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1342 { "vc", 8, 5, 0, 0 },
1343#define F_GT (F_OVERFLOWCLR + 1)
1344 { "gt", 9, 5, 0, 1 },
1345#define F_GE (F_GT + 1)
1346 { "ge", 10, 5, 0, 1 },
1347#define F_LT (F_GE + 1)
1348 { "lt", 11, 5, 0, 1 },
1349#define F_LE (F_LT + 1)
1350 { "le", 12, 5, 0, 1 },
1351#define F_HI (F_LE + 1)
1352 { "hi", 13, 5, 0, 1 },
1353#define F_LS (F_HI + 1)
1354 { "ls", 14, 5, 0, 1 },
1355#define F_PNZ (F_LS + 1)
1356 { "pnz", 15, 5, 0, 1 },
c0c31e91
RZ		 1357#define F_NJ (F_PNZ + 1)
1358 { "nj", 21, 5, 0, 1 },
1359#define F_NM (F_NJ + 1)
1360 { "nm", 23, 5, 0, 1 },
1361#define F_NO_T (F_NM + 1)
1362 { "nt", 24, 5, 0, 1 },
886a2506
NC		 1363
1364 /* FLAG. */
c0c31e91 1365#define F_FLAG (F_NO_T + 1)
886a2506
NC		 1366 { "f", 1, 1, 15, 1 },
1367#define F_FFAKE (F_FLAG + 1)
1368 { "f", 0, 0, 0, 1 },
1369
1370 /* Delay slot. */
1371#define F_ND (F_FFAKE + 1)
1372 { "nd", 0, 1, 5, 0 },
1373#define F_D (F_ND + 1)
1374 { "d", 1, 1, 5, 1 },
1375#define F_DFAKE (F_D + 1)
1376 { "d", 0, 0, 0, 1 },
2b848ebd
CZ		 1377#define F_DNZ_ND (F_DFAKE + 1)
1378 { "nd", 0, 1, 16, 0 },
1379#define F_DNZ_D (F_DNZ_ND + 1)
1380 { "d", 1, 1, 16, 1 },
886a2506
NC		 1381
1382 /* Data size. */
2b848ebd 1383#define F_SIZEB1 (F_DNZ_D + 1)
886a2506
NC		 1384 { "b", 1, 2, 1, 1 },
1385#define F_SIZEB7 (F_SIZEB1 + 1)
1386 { "b", 1, 2, 7, 1 },
1387#define F_SIZEB17 (F_SIZEB7 + 1)
1388 { "b", 1, 2, 17, 1 },
1389#define F_SIZEW1 (F_SIZEB17 + 1)
1390 { "w", 2, 2, 1, 0 },
1391#define F_SIZEW7 (F_SIZEW1 + 1)
1392 { "w", 2, 2, 7, 0 },
1393#define F_SIZEW17 (F_SIZEW7 + 1)
1394 { "w", 2, 2, 17, 0 },
1395
1396 /* Sign extension. */
1397#define F_SIGN6 (F_SIZEW17 + 1)
1398 { "x", 1, 1, 6, 1 },
1399#define F_SIGN16 (F_SIGN6 + 1)
1400 { "x", 1, 1, 16, 1 },
1401#define F_SIGNX (F_SIGN16 + 1)
1402 { "x", 0, 0, 0, 1 },
1403
1404 /* Address write-back modes. */
1405#define F_A3 (F_SIGNX + 1)
1406 { "a", 1, 2, 3, 0 },
1407#define F_A9 (F_A3 + 1)
1408 { "a", 1, 2, 9, 0 },
1409#define F_A22 (F_A9 + 1)
1410 { "a", 1, 2, 22, 0 },
1411#define F_AW3 (F_A22 + 1)
1412 { "aw", 1, 2, 3, 1 },
1413#define F_AW9 (F_AW3 + 1)
1414 { "aw", 1, 2, 9, 1 },
1415#define F_AW22 (F_AW9 + 1)
1416 { "aw", 1, 2, 22, 1 },
1417#define F_AB3 (F_AW22 + 1)
1418 { "ab", 2, 2, 3, 1 },
1419#define F_AB9 (F_AB3 + 1)
1420 { "ab", 2, 2, 9, 1 },
1421#define F_AB22 (F_AB9 + 1)
1422 { "ab", 2, 2, 22, 1 },
1423#define F_AS3 (F_AB22 + 1)
1424 { "as", 3, 2, 3, 1 },
1425#define F_AS9 (F_AS3 + 1)
1426 { "as", 3, 2, 9, 1 },
1427#define F_AS22 (F_AS9 + 1)
1428 { "as", 3, 2, 22, 1 },
1429#define F_ASFAKE (F_AS22 + 1)
1430 { "as", 0, 0, 0, 1 },
1431
1432 /* Cache bypass. */
1433#define F_DI5 (F_ASFAKE + 1)
1434 { "di", 1, 1, 5, 1 },
1435#define F_DI11 (F_DI5 + 1)
1436 { "di", 1, 1, 11, 1 },
b437d035
AB		 1437#define F_DI14 (F_DI11 + 1)
1438 { "di", 1, 1, 14, 1 },
1439#define F_DI15 (F_DI14 + 1)
886a2506
NC		 1440 { "di", 1, 1, 15, 1 },
1441
1442 /* ARCv2 specific. */
1443#define F_NT (F_DI15 + 1)
1444 { "nt", 0, 1, 3, 1},
1445#define F_T (F_NT + 1)
1446 { "t", 1, 1, 3, 1},
1447#define F_H1 (F_T + 1)
1448 { "h", 2, 2, 1, 1 },
1449#define F_H7 (F_H1 + 1)
1450 { "h", 2, 2, 7, 1 },
1451#define F_H17 (F_H7 + 1)
1452 { "h", 2, 2, 17, 1 },
6ec7c1ae
CZ		 1453#define F_SIZED (F_H17 + 1)
1454 { "dd", 8, 0, 0, 0 }, /* Fake. */
886a2506
NC		 1455
1456 /* Fake Flags. */
6ec7c1ae 1457#define F_NE (F_SIZED + 1)
886a2506 1458 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1459
1460 /* ARC NPS400 Support: See comment near head of file. */
1461#define F_NPS_CL (F_NE + 1)
1462 { "cl", 0, 0, 0, 1 },
1463
645d3342
RZ		 1464#define F_NPS_NA (F_NPS_CL + 1)
1465 { "na", 1, 1, 9, 1 },
1466
c0c31e91
RZ		 1467#define F_NPS_SR (F_NPS_NA + 1)
1468 { "s", 1, 1, 13, 1 },
1469
1470#define F_NPS_M (F_NPS_SR + 1)
1471 { "m", 1, 1, 7, 1 },
1472
1473#define F_NPS_FLAG (F_NPS_M + 1)
e23e8ebe 1474 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1475
1476#define F_NPS_R (F_NPS_FLAG + 1)
1477 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1478
1479#define F_NPS_RW (F_NPS_R + 1)
1480 { "rw", 0, 1, 7, 1 },
1481
1482#define F_NPS_RD (F_NPS_RW + 1)
1483 { "rd", 1, 1, 7, 1 },
1484
1485#define F_NPS_WFT (F_NPS_RD + 1)
1486 { "wft", 0, 0, 0, 1 },
1487
1488#define F_NPS_IE1 (F_NPS_WFT + 1)
1489 { "ie1", 1, 2, 8, 1 },
1490
1491#define F_NPS_IE2 (F_NPS_IE1 + 1)
1492 { "ie2", 2, 2, 8, 1 },
1493
1494#define F_NPS_IE12 (F_NPS_IE2 + 1)
1495 { "ie12", 3, 2, 8, 1 },
1496
1497#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1498 { "rd", 0, 1, 6, 1 },
1499
1500#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1501 { "wr", 1, 1, 6, 1 },
1502
1503#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1504 { "off", 0, 0, 0, 1 },
1505
1506#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1507 { "restore", 0, 0, 0, 1 },
1508
537aefaf
AB		 1509#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1510 { "sx", 1, 1, 14, 1 },
1511
1512#define F_NPS_AR (F_NPS_SX + 1)
1513 { "ar", 0, 1, 0, 1 },
1514
1515#define F_NPS_AL (F_NPS_AR + 1)
1516 { "al", 1, 1, 0, 1 },
14053c19
GM		 1517
1518#define F_NPS_S (F_NPS_AL + 1)
1519 { "s", 0, 0, 0, 1 },
1520
1521#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1522 { "rd", 0, 1, 15, 1 },
1523
1524#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1525 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1526
1527#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1528 { "p0", 0, 0, 0, 1 },
1529
1530#define F_NPS_P1 (F_NPS_P0 + 1)
1531 { "p1", 0, 0, 0, 1 },
1532
1533#define F_NPS_P2 (F_NPS_P1 + 1)
1534 { "p2", 0, 0, 0, 1 },
1535
1536#define F_NPS_P3 (F_NPS_P2 + 1)
1537 { "p3", 0, 0, 0, 1 },
28215275
GM		 1538
1539#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1540 { "di", 0, 0, 0, 1 },
1541
1542#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1543 { "cl", 1, 1, 6, 1 },
1544
1545#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1546 { "cl", 1, 1, 16, 1 },
1547
1548#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1549 { "x2", 1, 2, 9, 1 },
1550
1551#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1552 { "x2", 1, 2, 22, 1 },
1553
1554#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1555 { "x4", 2, 2, 9, 1 },
1556
1557#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1558 { "x4", 2, 2, 22, 1 },
c0c31e91
RZ		 1559
1560#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
1561 { "core", 1, 3, 6, 1 },
1562
1563#define F_NPS_CLSR (F_NPS_CORE + 1)
1564 { "clsr", 2, 3, 6, 1 },
1565
1566#define F_NPS_ALL (F_NPS_CLSR + 1)
1567 { "all", 3, 3, 6, 1 },
1568
1569#define F_NPS_GIC (F_NPS_ALL + 1)
1570 { "gic", 4, 3, 6, 1 },
1571
1572#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
1573 { "gic", 5, 3, 6, 1 },
886a2506 1574};
252b5132 1575
886a2506 1576const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1577
886a2506 1578/* Table of the flag classes.
252b5132 1579
886a2506
NC		 1580 The format of the table is
1581 CLASS {FLAG_CODE}. */
1582const struct arc_flag_class arc_flag_classes[] =
1583{
1584#define C_EMPTY 0
1ae8ab47 1585 { F_CLASS_NONE, { F_NULL } },
886a2506 1586
6ec7c1ae
CZ		 1587#define C_CC_EQ (C_EMPTY + 1)
1588 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1589
1590#define C_CC_GE (C_CC_EQ + 1)
1591 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1592
1593#define C_CC_GT (C_CC_GE + 1)
1594 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1595
1596#define C_CC_HI (C_CC_GT + 1)
1597 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1598
1599#define C_CC_HS (C_CC_HI + 1)
1600 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1601
1602#define C_CC_LE (C_CC_HS + 1)
1603 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1604
1605#define C_CC_LO (C_CC_LE + 1)
1606 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1607
1608#define C_CC_LS (C_CC_LO + 1)
1609 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1610
1611#define C_CC_LT (C_CC_LS + 1)
1612 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1613
1614#define C_CC_NE (C_CC_LT + 1)
1615 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1616
1617#define C_AA_AB (C_CC_NE + 1)
1618 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1619
1620#define C_AA_AW (C_AA_AB + 1)
1621 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1622
1623#define C_ZZ_D (C_AA_AW + 1)
1624 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1625
1626#define C_ZZ_H (C_ZZ_D + 1)
1627 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1628
1629#define C_ZZ_B (C_ZZ_H + 1)
1630 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1631
1632#define C_CC (C_ZZ_B + 1)
d9eca1df 1633 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1634 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1635 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1636 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1637 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1638 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
c0c31e91 1639 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
886a2506
NC		 1640
1641#define C_AA_ADDR3 (C_CC + 1)
1642#define C_AA27 (C_CC + 1)
6ec7c1ae 1643 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1644#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1645#define C_AA21 (C_AA_ADDR3 + 1)
6ec7c1ae 1646 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1647#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1648#define C_AA8 (C_AA_ADDR9 + 1)
6ec7c1ae 1649 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1650
1651#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1652 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1653#define C_FHARD (C_F + 1)
1ae8ab47 1654 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1655
1656#define C_T (C_FHARD + 1)
1ae8ab47 1657 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1658#define C_D (C_T + 1)
1ae8ab47 1659 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
2b848ebd
CZ		 1660#define C_DNZ_D (C_D + 1)
1661 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
886a2506 1662
2b848ebd 1663#define C_DHARD (C_DNZ_D + 1)
1ae8ab47 1664 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1665
1666#define C_DI20 (C_DHARD + 1)
1ae8ab47 1667 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
b437d035
AB		 1668#define C_DI14 (C_DI20 + 1)
1669 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1670#define C_DI16 (C_DI14 + 1)
1ae8ab47 1671 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1672#define C_DI26 (C_DI16 + 1)
1ae8ab47 1673 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1674
1675#define C_X25 (C_DI26 + 1)
1ae8ab47 1676 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1677#define C_X15 (C_X25 + 1)
1ae8ab47 1678 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1679#define C_XHARD (C_X15 + 1)
1680#define C_X (C_X15 + 1)
1ae8ab47 1681 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1682
1683#define C_ZZ13 (C_X + 1)
1ae8ab47 1684 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1685#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1686 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1687#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1688 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1689
1690#define C_AS (C_ZZ29 + 1)
1ae8ab47 1691 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1692
1693#define C_NE (C_AS + 1)
1ae8ab47 1694 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1695
1696 /* ARC NPS400 Support: See comment near head of file. */
1697#define C_NPS_CL (C_NE + 1)
1698 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1699
645d3342
RZ		 1700#define C_NPS_NA (C_NPS_CL + 1)
1701 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1702
c0c31e91
RZ		 1703#define C_NPS_SR (C_NPS_NA + 1)
1704 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
1705
1706#define C_NPS_M (C_NPS_SR + 1)
1707 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
1708
1709#define C_NPS_F (C_NPS_M + 1)
e23e8ebe 1710 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1711
1712#define C_NPS_R (C_NPS_F + 1)
1713 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1714
1715#define C_NPS_SCHD_RW (C_NPS_R + 1)
1716 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1717
1718#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1719 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1720
1721#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1722 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1723
1724#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1725 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1726
1727#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1728 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1729
1730#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1731 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1732
537aefaf
AB		 1733#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1734 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1735
1736#define C_NPS_AR_AL (C_NPS_SX + 1)
1737 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1738
1739#define C_NPS_S (C_NPS_AR_AL + 1)
1740 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1741
1742#define C_NPS_ZNCV (C_NPS_S + 1)
1743 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1744
1745#define C_NPS_P0 (C_NPS_ZNCV + 1)
1746 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1747
1748#define C_NPS_P1 (C_NPS_P0 + 1)
1749 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1750
1751#define C_NPS_P2 (C_NPS_P1 + 1)
1752 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1753
1754#define C_NPS_P3 (C_NPS_P2 + 1)
1755 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1756
1757#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1758 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1759
1760#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1761 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1762
1763#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1764 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1765
1766#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1767 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1768
1769#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1770 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
c0c31e91
RZ		 1771
1772#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
1773 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
1774
1775#define C_NPS_CLSR (C_NPS_CORE + 1)
1776 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
1777
1778#define C_NPS_ALL (C_NPS_CLSR + 1)
1779 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
1780
1781#define C_NPS_GIC (C_NPS_ALL + 1)
1782 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
1783
1784#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
1785 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
886a2506 1786};
252b5132 1787
b99747ae
CZ		 1788const unsigned char flags_none[] = { 0 };
1789const unsigned char flags_f[] = { C_F };
1790const unsigned char flags_cc[] = { C_CC };
1791const unsigned char flags_ccf[] = { C_CC, C_F };
1792
886a2506 1793/* The operands table.
252b5132 1794
886a2506 1795 The format of the operands table is:
47b0e7ad 1796
886a2506
NC		 1797 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1798const struct arc_operand arc_operands[] =
0d2bcfaf 1799{
886a2506
NC		 1800 /* The fields are bits, shift, insert, extract, flags. The zero
1801 index is used to indicate end-of-list. */
1802#define UNUSED 0
1803 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1804
1805#define IGNORED (UNUSED + 1)
1806 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1807
886a2506
NC		 1808 /* The plain integer register fields. Used by 32 bit
1809 instructions. */
4eb6f892 1810#define RA (IGNORED + 1)
886a2506 1811 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
abe7c33b
CZ		 1812#define RA_CHK (RA + 1)
1813 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1814#define RB (RA_CHK + 1)
886a2506 1815 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
abe7c33b
CZ		 1816#define RB_CHK (RB + 1)
1817 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1818#define RC (RB_CHK + 1)
886a2506
NC		 1819 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1820#define RBdup (RC + 1)
1821 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1822
1823#define RAD (RBdup + 1)
1824 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1825#define RCD (RAD + 1)
1826 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1827
1828 /* The plain integer register fields. Used by short
1829 instructions. */
1830#define RA16 (RCD + 1)
1831#define RA_S (RCD + 1)
1832 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1833#define RB16 (RA16 + 1)
1834#define RB_S (RA16 + 1)
1835 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1836#define RB16dup (RB16 + 1)
1837#define RB_Sdup (RB16 + 1)
1838 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1839#define RC16 (RB16dup + 1)
1840#define RC_S (RB16dup + 1)
1841 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1842#define R6H (RC16 + 1) /* 6bit register field 'h' used
1843 by V1 cpus. */
1844 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1845#define R5H (R6H + 1) /* 5bit register field 'h' used
1846 by V2 cpus. */
1847#define RH_S (R6H + 1) /* 5bit register field 'h' used
1848 by V2 cpus. */
1849 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1850#define R5Hdup (R5H + 1)
1851#define RH_Sdup (R5H + 1)
1852 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1853 insert_rhv2, extract_rhv2 },
1854
1855#define RG (R5Hdup + 1)
1856#define G_S (R5Hdup + 1)
1857 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1858
1859 /* Fix registers. */
1860#define R0 (RG + 1)
1861#define R0_S (RG + 1)
1862 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1863#define R1 (R0 + 1)
1864#define R1_S (R0 + 1)
1865 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1866#define R2 (R1 + 1)
1867#define R2_S (R1 + 1)
1868 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1869#define R3 (R2 + 1)
1870#define R3_S (R2 + 1)
1871 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1872#define RSP (R3 + 1)
886a2506
NC		 1873#define SP_S (R3 + 1)
1874 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1875#define SPdup (RSP + 1)
1876#define SP_Sdup (RSP + 1)
886a2506
NC		 1877 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1878#define GP (SPdup + 1)
1879#define GP_S (SPdup + 1)
1880 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1881
1882#define PCL_S (GP + 1)
1883 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1884
1885#define BLINK (PCL_S + 1)
1886#define BLINK_S (PCL_S + 1)
1887 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1888
1889#define ILINK1 (BLINK + 1)
1890 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1891#define ILINK2 (ILINK1 + 1)
1892 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1893
1894 /* Long immediate. */
1895#define LIMM (ILINK2 + 1)
1896#define LIMM_S (ILINK2 + 1)
1897 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1898#define LIMMdup (LIMM + 1)
1899 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1900
1901 /* Special operands. */
1902#define ZA (LIMMdup + 1)
1903#define ZB (LIMMdup + 1)
1904#define ZA_S (LIMMdup + 1)
1905#define ZB_S (LIMMdup + 1)
1906#define ZC_S (LIMMdup + 1)
1907 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1908
1909#define RRANGE_EL (ZA + 1)
1910 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1911 insert_rrange, extract_rrange},
126124cc
CZ		 1912#define R13_EL (RRANGE_EL + 1)
1913 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1914 insert_r13el, extract_rrange },
1915#define FP_EL (R13_EL + 1)
886a2506
NC		 1916 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1917 insert_fpel, extract_fpel },
1918#define BLINK_EL (FP_EL + 1)
1919 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1920 insert_blinkel, extract_blinkel },
1921#define PCL_EL (BLINK_EL + 1)
1922 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1923 insert_pclel, extract_pclel },
1924
1925 /* Fake operand to handle the T flag. */
1926#define BRAKET (PCL_EL + 1)
1927#define BRAKETdup (PCL_EL + 1)
1928 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1929
1930 /* Fake operand to handle the T flag. */
1931#define FKT_T (BRAKET + 1)
1932 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1933 /* Fake operand to handle the T flag. */
1934#define FKT_NT (FKT_T + 1)
1935 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1936
1937 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1938#define UIMM6_20 (FKT_NT + 1)
1939 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1940
cc07cda6
CZ		 1941 /* Exactly like the above but used by relaxation. */
1942#define UIMM6_20R (UIMM6_20 + 1)
1943 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1944 insert_uimm6_20, extract_uimm6_20},
1945
886a2506 1946 /* SIMM12_20 mask = 00000000000000000000111111222222. */
cc07cda6 1947#define SIMM12_20 (UIMM6_20R + 1)
886a2506
NC		 1948 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1949
cc07cda6
CZ		 1950 /* Exactly like the above but used by relaxation. */
1951#define SIMM12_20R (SIMM12_20 + 1)
1952 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1953 insert_simm12_20, extract_simm12_20},
1954
7179e0e6
CZ		 1955 /* UIMM12_20 mask = 00000000000000000000111111222222. */
1956#define UIMM12_20 (SIMM12_20R + 1)
1957 {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
1958
886a2506 1959 /* SIMM3_5_S mask = 0000011100000000. */
7179e0e6 1960#define SIMM3_5_S (UIMM12_20 + 1)
886a2506
NC		 1961 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1962 insert_simm3s, extract_simm3s},
1963
1964 /* UIMM7_A32_11_S mask = 0000000000011111. */
1965#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1966 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1967 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1968 extract_uimm7_a32_11_s},
1969
cc07cda6
CZ		 1970 /* The same as above but used by relaxation. */
1971#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1972 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1973 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1974 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1975
886a2506 1976 /* UIMM7_9_S mask = 0000000001111111. */
cc07cda6 1977#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
886a2506
NC		 1978 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1979
1980 /* UIMM3_13_S mask = 0000000000000111. */
1981#define UIMM3_13_S (UIMM7_9_S + 1)
1982 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1983
cc07cda6
CZ		 1984 /* Exactly like the above but used for relaxation. */
1985#define UIMM3_13R_S (UIMM3_13_S + 1)
1986 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1987 insert_uimm3_13_s, extract_uimm3_13_s},
1988
886a2506 1989 /* SIMM11_A32_7_S mask = 0000000111111111. */
cc07cda6 1990#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
886a2506
NC		 1991 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1992 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1993
1994 /* UIMM6_13_S mask = 0000000002220111. */
1995#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1996 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1997 /* UIMM5_11_S mask = 0000000000011111. */
1998#define UIMM5_11_S (UIMM6_13_S + 1)
1999 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
2000 extract_uimm5_11_s},
2001
2002 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
2003#define SIMM9_A16_8 (UIMM5_11_S + 1)
2004 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2005 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
2006 extract_simm9_a16_8},
2007
2008 /* UIMM6_8 mask = 00000000000000000000111111000000. */
2009#define UIMM6_8 (SIMM9_A16_8 + 1)
2010 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
2011
2012 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
2013#define SIMM21_A16_5 (UIMM6_8 + 1)
2014 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
50d2740d 2015 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
886a2506
NC		 2016 insert_simm21_a16_5, extract_simm21_a16_5},
2017
2018 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
2019#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
2020 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
2021 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
2022 insert_simm25_a16_5, extract_simm25_a16_5},
2023
2024 /* SIMM10_A16_7_S mask = 0000000111111111. */
2025#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
2026 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2027 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
2028 extract_simm10_a16_7_s},
2029
2030#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
2031 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2032 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
2033
2034 /* SIMM7_A16_10_S mask = 0000000000111111. */
2035#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
2036 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2037 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
2038 extract_simm7_a16_10_s},
2039
2040 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
2041#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
2042 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2043 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
2044 extract_simm21_a32_5},
2045
2046 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
2047#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
2048 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2049 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
2050 extract_simm25_a32_5},
2051
2052 /* SIMM13_A32_5_S mask = 0000011111111111. */
2053#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
2054 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2055 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
2056 extract_simm13_a32_5_s},
2057
2058 /* SIMM8_A16_9_S mask = 0000000001111111. */
2059#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
2060 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2061 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
2062 extract_simm8_a16_9_s},
2063
684d5a10
JEM		 2064/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
2065#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
2066 {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
2067 | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
2068 extract_uimm10_6_s},
2069
886a2506 2070 /* UIMM3_23 mask = 00000000000000000000000111000000. */
684d5a10 2071#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
886a2506
NC		 2072 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
2073
2074 /* UIMM10_6_S mask = 0000001111111111. */
2075#define UIMM10_6_S (UIMM3_23 + 1)
2076 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
2077
2078 /* UIMM6_11_S mask = 0000002200011110. */
2079#define UIMM6_11_S (UIMM10_6_S + 1)
2080 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
2081
2082 /* SIMM9_8 mask = 00000000111111112000000000000000. */
2083#define SIMM9_8 (UIMM6_11_S + 1)
2084 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
2085 insert_simm9_8, extract_simm9_8},
2086
cc07cda6
CZ		 2087 /* The same as above but used by relaxation. */
2088#define SIMM9_8R (SIMM9_8 + 1)
2089 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
2090 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
2091
886a2506 2092 /* UIMM10_A32_8_S mask = 0000000011111111. */
cc07cda6 2093#define UIMM10_A32_8_S (SIMM9_8R + 1)
886a2506
NC		 2094 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2095 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
2096 extract_uimm10_a32_8_s},
2097
2098 /* SIMM9_7_S mask = 0000000111111111. */
2099#define SIMM9_7_S (UIMM10_A32_8_S + 1)
2100 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
2101 extract_simm9_7_s},
2102
2103 /* UIMM6_A16_11_S mask = 0000000000011111. */
2104#define UIMM6_A16_11_S (SIMM9_7_S + 1)
2105 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2106 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
2107 extract_uimm6_a16_11_s},
2108
2109 /* UIMM5_A32_11_S mask = 0000020000011000. */
2110#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
2111 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2112 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
2113 extract_uimm5_a32_11_s},
2114
2115 /* SIMM11_A32_13_S mask = 0000022222200111. */
2116#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
2117 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2118 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
2119
2120 /* UIMM7_13_S mask = 0000000022220111. */
2121#define UIMM7_13_S (SIMM11_A32_13_S + 1)
2122 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
2123
2124 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
2125#define UIMM6_A16_21 (UIMM7_13_S + 1)
2126 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2127 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
2128
2129 /* UIMM7_11_S mask = 0000022200011110. */
2130#define UIMM7_11_S (UIMM6_A16_21 + 1)
2131 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
2132
2133 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
2134#define UIMM7_A16_20 (UIMM7_11_S + 1)
2135 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2136 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
2137 extract_uimm7_a16_20},
2138
2139 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
2140#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
2141 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2142 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
2143 extract_simm13_a16_20},
2144
2145 /* UIMM8_8_S mask = 0000000011111111. */
2146#define UIMM8_8_S (SIMM13_A16_20 + 1)
2147 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
2148
cc07cda6
CZ		 2149 /* The same as above but used for relaxation. */
2150#define UIMM8_8R_S (UIMM8_8_S + 1)
2151 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2152 insert_uimm8_8_s, extract_uimm8_8_s},
2153
886a2506 2154 /* W6 mask = 00000000000000000000111111000000. */
cc07cda6 2155#define W6 (UIMM8_8R_S + 1)
886a2506
NC		 2156 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2157
2158 /* UIMM6_5_S mask = 0000011111100000. */
2159#define UIMM6_5_S (W6 + 1)
2160 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 2161
2162 /* ARC NPS400 Support: See comment near head of file. */
2163#define NPS_R_DST_3B (UIMM6_5_S + 1)
c0c31e91
RZ		 2164 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2165 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2166
2167#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
c0c31e91
RZ		 2168 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2169 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2170
2171#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
c0c31e91
RZ		 2172 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2173 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
e23e8ebe
AB		 2174
2175#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 2176 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 2177
2178#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 2179 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 2180
2181#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2182 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2183
2184#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2185 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2186
2187#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
c0c31e91
RZ		 2188 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2189 insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 2190
820f03ff 2191#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
c0c31e91
RZ		 2192 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2193 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
820f03ff
AB		 2194
2195#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
c0c31e91
RZ		 2196 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2197 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
820f03ff
AB		 2198
2199#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
c0c31e91
RZ		 2200 { 8, 0, 0, ARC_OPERAND_UNSIGNED,
2201 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
820f03ff
AB		 2202
2203#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 2204 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 2205
14053c19
GM		 2206#define NPS_SIMM16 (NPS_UIMM16 + 1)
2207 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2208
2209#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
c0c31e91
RZ		 2210 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2211 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 2212
2213#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
c0c31e91
RZ		 2214 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2215 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 2216
2217#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
c0c31e91
RZ		 2218 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2219 insert_nps_src2_pos, extract_nps_src2_pos },
537aefaf
AB		 2220
2221#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
c0c31e91
RZ		 2222 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2223 insert_nps_src1_pos, extract_nps_src1_pos },
537aefaf
AB		 2224
2225#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
c0c31e91
RZ		 2226 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2227 insert_nps_addb_size, extract_nps_addb_size },
537aefaf
AB		 2228
2229#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
c0c31e91
RZ		 2230 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2231 insert_nps_andb_size, extract_nps_andb_size },
537aefaf
AB		 2232
2233#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
c0c31e91
RZ		 2234 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2235 insert_nps_fxorb_size, extract_nps_fxorb_size },
537aefaf
AB		 2236
2237#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
c0c31e91
RZ		 2238 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2239 insert_nps_wxorb_size, extract_nps_wxorb_size },
537aefaf
AB		 2240
2241#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2242 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2243
2244#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2245 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2246
2247#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
c0c31e91
RZ		 2248 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2249 insert_nps_qcmp_size, extract_nps_qcmp_size },
537aefaf
AB		 2250
2251#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2252 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2253
2254#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2255 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2256
2257#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2258 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2259
2260#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
c0c31e91
RZ		 2261 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2262 insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 2263
2264#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
c0c31e91
RZ		 2265 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2266 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2267
2268#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
c0c31e91
RZ		 2269 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2270 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2271
2272#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
c0c31e91
RZ		 2273 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2274 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
4eb6f892
AB		 2275
2276#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
c0c31e91
RZ		 2277 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2278 insert_nps_bitop2_size, extract_nps_bitop2_size },
4eb6f892
AB		 2279
2280#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
c0c31e91
RZ		 2281 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2282 insert_nps_bitop1_size, extract_nps_bitop1_size },
4eb6f892
AB		 2283
2284#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
c0c31e91
RZ		 2285 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2286 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
4eb6f892
AB		 2287
2288#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
bdfe53e3 2289 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2290
2291#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
bdfe53e3 2292 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2293
2294#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2295 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2296
2297#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2298 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2299
2300#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
bdfe53e3 2301 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2302
2303#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2304 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2305
2306#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2307 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2308
2309#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2310 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2311
bdfe53e3 2312#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
c0c31e91
RZ		 2313 { 2, 0, 0, ARC_OPERAND_UNSIGNED,
2314 insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
4eb6f892 2315
bdfe53e3 2316#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
4eb6f892
AB		 2317 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2318
2319#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2320 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2321
2322#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2323 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2324
2325#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
c0c31e91
RZ		 2326 { 5, 20, 0, ARC_OPERAND_UNSIGNED,
2327 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 2328
2329#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2330 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2331
2332#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
c0c31e91
RZ		 2333 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2334 insert_nps_field_size, extract_nps_field_size },
14053c19
GM		 2335
2336#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
c0c31e91
RZ		 2337 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2338 insert_nps_shift_factor, extract_nps_shift_factor },
14053c19
GM		 2339
2340#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
c0c31e91
RZ		 2341 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2342 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
14053c19
GM		 2343
2344#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2345 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2346
2347#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
c0c31e91
RZ		 2348 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2349 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
14053c19
GM		 2350
2351#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
c0c31e91
RZ		 2352 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2353 insert_nps_min_hofs, extract_nps_min_hofs },
14053c19
GM		 2354
2355#define NPS_PSBC (NPS_MIN_HOFS + 1)
2356 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 2357
2358#define NPS_DPI_DST (NPS_PSBC + 1)
2359 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2360
c0c31e91
RZ		 2361 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
2362 but doesn't duplicate an operand. */
9ba75c88 2363#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
c0c31e91
RZ		 2364 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2365 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
9ba75c88
GM		 2366
2367#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
c0c31e91
RZ		 2368 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2369 insert_nps_hash_width, extract_nps_hash_width },
9ba75c88
GM		 2370
2371#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2372 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2373
2374#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2375 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2376
2377#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2378 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2379
2380#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
c0c31e91
RZ		 2381 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2382 insert_nps_hash_len, extract_nps_hash_len },
9ba75c88
GM		 2383
2384#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2385 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2386
2387#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2388 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2389
2390#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2391 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2392
2393#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2394 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2395
2396#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2397 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2398
2399#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
c0c31e91
RZ		 2400 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2401 insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2402
2403#define COLON (NPS_E4BY_INDEX3 + 1)
2404 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2405
2406#define NPS_BD (COLON + 1)
c0c31e91
RZ		 2407 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2408 insert_nps_bd, extract_nps_bd },
db18dbab
GM		 2409
2410#define NPS_JID (NPS_BD + 1)
c0c31e91
RZ		 2411 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2412 insert_nps_jid, extract_nps_jid },
db18dbab
GM		 2413
2414#define NPS_LBD (NPS_JID + 1)
c0c31e91
RZ		 2415 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2416 insert_nps_lbd, extract_nps_lbd },
db18dbab
GM		 2417
2418#define NPS_MBD (NPS_LBD + 1)
c0c31e91
RZ		 2419 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2420 insert_nps_mbd, extract_nps_mbd },
db18dbab
GM		 2421
2422#define NPS_SD (NPS_MBD + 1)
c0c31e91
RZ		 2423 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2424 insert_nps_sd, extract_nps_sd },
db18dbab
GM		 2425
2426#define NPS_SM (NPS_SD + 1)
c0c31e91
RZ		 2427 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2428 insert_nps_sm, extract_nps_sm },
db18dbab
GM		 2429
2430#define NPS_XA (NPS_SM + 1)
c0c31e91
RZ		 2431 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2432 insert_nps_xa, extract_nps_xa },
db18dbab
GM		 2433
2434#define NPS_XD (NPS_XA + 1)
c0c31e91
RZ		 2435 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2436 insert_nps_xd, extract_nps_xd },
db18dbab
GM		 2437
2438#define NPS_CD (NPS_XD + 1)
c0c31e91
RZ		 2439 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2440 insert_nps_cd, extract_nps_cd },
db18dbab
GM		 2441
2442#define NPS_CBD (NPS_CD + 1)
c0c31e91
RZ		 2443 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2444 insert_nps_cbd, extract_nps_cbd },
db18dbab
GM		 2445
2446#define NPS_CJID (NPS_CBD + 1)
c0c31e91
RZ		 2447 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2448 insert_nps_cjid, extract_nps_cjid },
db18dbab
GM		 2449
2450#define NPS_CLBD (NPS_CJID + 1)
c0c31e91
RZ		 2451 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2452 insert_nps_clbd, extract_nps_clbd },
db18dbab
GM		 2453
2454#define NPS_CM (NPS_CLBD + 1)
c0c31e91
RZ		 2455 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2456 insert_nps_cm, extract_nps_cm },
db18dbab
GM		 2457
2458#define NPS_CSD (NPS_CM + 1)
c0c31e91
RZ		 2459 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2460 insert_nps_csd, extract_nps_csd },
db18dbab
GM		 2461
2462#define NPS_CXA (NPS_CSD + 1)
c0c31e91
RZ		 2463 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2464 insert_nps_cxa, extract_nps_cxa },
db18dbab
GM		 2465
2466#define NPS_CXD (NPS_CXA + 1)
c0c31e91
RZ		 2467 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2468 insert_nps_cxd, extract_nps_cxd },
db18dbab
GM		 2469
2470#define NPS_BD_TYPE (NPS_CXD + 1)
2471 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2472
2473#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
c0c31e91
RZ		 2474 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2475 insert_nps_bd_num_buff, extract_nps_bd_num_buff },
db18dbab
GM		 2476
2477#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2478 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2479
c0c31e91
RZ		 2480#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
2481 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2482 insert_nps_size_16bit, extract_nps_size_16bit },
2483
2484#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
2485 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2486 insert_nps_pmu_num_job, extract_nps_pmu_num_job },
bdfe53e3 2487
645d3342 2488#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
c0c31e91
RZ		 2489 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2490 insert_nps_imm_entry, extract_nps_imm_entry },
645d3342
RZ		 2491
2492#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
c0c31e91
RZ		 2493 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2494 insert_nps_imm_offset, extract_nps_imm_offset },
2495
2496#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
2497 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
2498
2499#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
2500 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2501 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
645d3342 2502
c0c31e91
RZ		 2503#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
2504 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2505 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
bdfe53e3
AB		 2506
2507#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
c0c31e91
RZ		 2508 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2509 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
bdfe53e3
AB		 2510
2511#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
c0c31e91
RZ		 2512 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2513 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
bdfe53e3
AB		 2514
2515#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
c0c31e91
RZ		 2516 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2517 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
bdfe53e3
AB		 2518
2519#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
c0c31e91
RZ		 2520 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2521 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
bdfe53e3
AB		 2522
2523#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
c0c31e91
RZ		 2524 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2525 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
0d2bcfaf 2526
5a736821
GM		 2527#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2528 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2529
2530#define NPS_RB_64 (NPS_RA_64 + 1)
2531 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2532
2533#define NPS_RBdup_64 (NPS_RB_64 + 1)
2534 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2535
2536#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
c0c31e91
RZ		 2537 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2538 insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
5a736821
GM		 2539
2540#define NPS_RC_64 (NPS_RBdouble_64 + 1)
2541 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2542
2543#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2544 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2545
2546#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
c0c31e91
RZ		 2547 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2548 insert_nps_proto_size, extract_nps_proto_size }
5a736821 2549};
886a2506 2550const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2551
886a2506
NC		 2552const unsigned arc_Toperand = FKT_T;
2553const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2554
b99747ae
CZ		 2555const unsigned char arg_none[] = { 0 };
2556const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2557const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2558const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2559const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2560const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2561const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2562const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2563const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2564const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2565const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2566const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2567
2568const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2569const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2570const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2571
2572const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2573const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2574const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2575
2576const unsigned char arg_32bit_rbrc[] = { RB, RC };
2577const unsigned char arg_32bit_zarc[] = { ZA, RC };
2578const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2579const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2580const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2581const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2582
2583const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2584const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2585const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2586const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2587
945e0f82
CZ		 2588const unsigned char arg_32bit_rc[] = { RC };
2589const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2590const unsigned char arg_32bit_limm[] = { LIMM };
2591
886a2506 2592/* The opcode table.
0d2bcfaf 2593
886a2506 2594 The format of the opcode table is:
0d2bcfaf 2595
1328504b
AB		 2596 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2597
2598 The table is organised such that, where possible, all instructions with
2599 the same mnemonic are together in a block. When the assembler searches
2600 for a suitable instruction the entries are checked in table order, so
2601 more specific, or specialised cases should appear earlier in the table.
2602
2603 As an example, consider two instructions 'add a,b,u6' and 'add
2604 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2605 32-bit instruction, while the second takes a 32-bit immediate that is
2606 encoded in a follow-on 32-bit, making the total instruction length
2607 64-bits. In this case the u6 variant must appear first in the table, as
2608 all u6 immediates could also be encoded using the 'limm' extension,
2609 however, we want to use the shorter instruction wherever possible.
2610
2611 It is possible though to split instructions with the same mnemonic into
2612 multiple groups. However, the instructions are still checked in table
2613 order, even across groups. The only time that instructions with the
2614 same mnemonic should be split into different groups is when different
2615 variants of the instruction appear in different architectures, in which
2616 case, grouping all instructions from a particular architecture together
2617 might be preferable to merging the instruction into the main instruction
2618 table.
2619
2620 An example of this split instruction groups can be found with the 'sync'
2621 instruction. The core arc architecture provides a 'sync' instruction,
2622 while the nps instruction set extension provides 'sync.rd' and
2623 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2624 mnemonic, so we end up with two groups for the sync instruction, the
2625 first within the core arc instruction table, and the second within the
2626 nps extension instructions. */
886a2506 2627const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2628{
886a2506 2629#include "arc-tbl.h"
e23e8ebe 2630#include "arc-nps400-tbl.h"
f2dd8838 2631#include "arc-ext-tbl.h"
0d2bcfaf 2632
b99747ae
CZ		 2633 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2634};
252b5132 2635
886a2506
NC		 2636/* List with special cases instructions and the applicable flags. */
2637const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2638{
886a2506
NC		 2639 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2640 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2641 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
c0c31e91
RZ		 2642 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
2643 F_NO_T, F_NULL } },
886a2506
NC		 2644 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2645 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2646 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2647 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2648 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2649 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2650 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2651 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2652 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2653 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2654 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2655 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2656 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2657 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2658 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2659 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2660 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2661 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2662 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2663 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2664 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2665 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2666 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2667 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2668 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2669 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2670};
252b5132 2671
886a2506 2672const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2673
886a2506 2674/* Relocations. */
886a2506
NC		 2675const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2676{
24b368f8
CZ		 2677 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2678 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2679 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2680 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2681 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2682 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2683 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2684 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2685
2686 /* Next two entries will cover the undefined behavior ldb/stb with
2687 address scaling. */
2688 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2689 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2690 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2691 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2692
2693 { "sda", "ld", { F_ASFAKE, F_NULL },
2694 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2695 { "sda", "st", { F_ASFAKE, F_NULL },
2696 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2697 { "sda", "ldd", { F_ASFAKE, F_NULL },
2698 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2699 { "sda", "std", { F_ASFAKE, F_NULL },
2700 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2701
2702 /* Short instructions. */
24b368f8
CZ		 2703 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2704 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2705 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2706 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2707
2708 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2709 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2710
2711 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2712 BFD_RELOC_ARC_S25H_PCREL_PLT },
2713 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2714 BFD_RELOC_ARC_S21H_PCREL_PLT },
2715 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2716 BFD_RELOC_ARC_S25W_PCREL_PLT },
2717 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2718 BFD_RELOC_ARC_S21W_PCREL_PLT },
2719
2720 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2721};
252b5132 2722
886a2506 2723const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2724
886a2506 2725const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2726{
886a2506
NC		 2727 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2728 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2729 { BRAKETdup, 1, 0, 4} } },
2730 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2731 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2732 { BRAKETdup, 1, 0, 4} } },
2733
2734 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2735 { SIMM9_A16_8, 0, 0, 2 } } },
2736 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2737 { SIMM9_A16_8, 0, 0, 2 } } },
2738 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2739 { SIMM9_A16_8, 0, 0, 2 } } },
2740 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2741 { SIMM9_A16_8, 0, 0, 2 } } },
2742 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2743 { SIMM9_A16_8, 0, 0, 2 } } },
2744
2745 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2746 { SIMM9_A16_8, 0, 0, 2 } } },
2747 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2748 { SIMM9_A16_8, 0, 0, 2 } } },
2749 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2750 { SIMM9_A16_8, 0, 0, 2 } } },
2751 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2752 { SIMM9_A16_8, 0, 0, 2 } } },
2753 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2754 { SIMM9_A16_8, 0, 0, 2 } } },
2755
2756 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2757 { SIMM9_A16_8, 0, 0, 2 } } },
2758 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2759 { SIMM9_A16_8, 0, 0, 2 } } },
2760 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2761 { SIMM9_A16_8, 0, 0, 2 } } },
2762 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2763 { SIMM9_A16_8, 0, 0, 2 } } },
2764 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2765 { SIMM9_A16_8, 0, 0, 2 } } },
2766
2767 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2768 { SIMM9_A16_8, 0, 0, 2 } } },
2769 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2770 { SIMM9_A16_8, 0, 0, 2 } } },
2771 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2772 { SIMM9_A16_8, 0, 0, 2 } } },
2773 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2774 { SIMM9_A16_8, 0, 0, 2 } } },
2775 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2776 { SIMM9_A16_8, 0, 0, 2 } } },
2777};
0d2bcfaf 2778
886a2506
NC		 2779const unsigned arc_num_pseudo_insn =
2780 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2781
886a2506 2782const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2783{
886a2506 2784#undef DEF
f36e33da
CZ		 2785#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2786 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2787
886a2506 2788#include "arc-regs.h"
0d2bcfaf 2789
886a2506
NC		 2790#undef DEF
2791};
0d2bcfaf 2792
886a2506 2793const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2794
2795/* NOTE: The order of this array MUST be consistent with 'enum
2796 arc_rlx_types' located in tc-arc.h! */
2797const struct arc_opcode arc_relax_opcodes[] =
2798{
2799 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2800
2801 /* bl_s s13 11111sssssssssss. */
2802 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2803 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2804 { SIMM13_A32_5_S }, { 0 }},
2805
2806 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2807 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2808 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2809 { SIMM25_A32_5 }, { C_D }},
2810
2811 /* b_s s10 1111000sssssssss. */
2812 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2813 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2814 { SIMM10_A16_7_S }, { 0 }},
2815
2816 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2817 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2818 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2819 { SIMM25_A16_5 }, { C_D }},
2820
cc07cda6 2821 /* add_s c,b,u3 01101bbbccc00uuu. */
4670103e
CZ		 2822 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2823 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2824 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2825
cc07cda6 2826 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2827 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2828 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2829 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2830
2831 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2832 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2833 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2834 { RA, RB, LIMM }, { C_F }},
2835
cc07cda6 2836 /* ld_s c,b,u7 10000bbbcccuuuuu. */
4670103e
CZ		 2837 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2838 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2839 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
4670103e
CZ		 2840
2841 /* ld<.di><.aa><.x><zz> a,b,s9
cc07cda6 2842 00010bbbssssssssSBBBDaaZZXAAAAAA. */
4670103e
CZ		 2843 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2844 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2845 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
4670103e
CZ		 2846 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2847
2848 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2849 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2850 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2851 { RA, BRAKET, RB, LIMM, BRAKETdup },
2852 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2853
cc07cda6 2854 /* mov_s b,u8 11011bbbuuuuuuuu. */
4670103e
CZ		 2855 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2856 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2857 { RB_S, UIMM8_8R_S }, { 0 }},
4670103e 2858
cc07cda6 2859 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
4670103e
CZ		 2860 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2861 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2862 { RB, SIMM12_20R }, { C_F }},
4670103e
CZ		 2863
2864 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2865 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2866 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2867 { RB, LIMM }, { C_F }},
2868
cc07cda6 2869 /* sub_s c,b,u3 01101bbbccc01uuu. */
4670103e
CZ		 2870 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2871 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2872 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2873
cc07cda6 2874 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2875 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2876 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2877 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2878
2879 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2880 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2881 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2882 { RA, RB, LIMM }, { C_F }},
2883
cc07cda6 2884 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
4670103e 2885 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
cc07cda6 2886 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2887
2888 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2889 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2890 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2891
cc07cda6 2892 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2893 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2894 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2895 { RB, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2896
2897 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2898 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2899 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2900 { RB, LIMM }, { C_F, C_CC }},
2901
cc07cda6 2902 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2903 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2904 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2905 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2906
2907 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2908 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2909 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2910 { RB, RBdup, LIMM }, { C_F, C_CC }}
2911};
2912
2913const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892 2914
bdfe53e3 2915/* Return length of an opcode in bytes. */
06fe285f
GM		 2916
2917int
2918arc_opcode_len (const struct arc_opcode *opcode)
2919{
2920 if (opcode->mask < 0x10000ull)
2921 return 2;
bdfe53e3
AB		 2922
2923 if (opcode->mask < 0x100000000ull)
2924 return 4;
2925
2926 if (opcode->mask < 0x1000000000000ull)
2927 return 6;
2928
2929 return 8;
06fe285f 2930}
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