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Commit | Line | Data |
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252b5132 | 1 | /* Select disassembly routine for specified architecture. |
fd67aa11 | 2 | Copyright (C) 1994-2024 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
7499d566 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3 of the License, or |
7499d566 | 9 | (at your option) any later version. |
252b5132 | 10 | |
7499d566 NC |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
252b5132 | 15 | |
7499d566 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
88c1242d | 22 | #include "disassemble.h" |
65b48a81 | 23 | #include "safe-ctype.h" |
832a5807 | 24 | #include "opintl.h" |
252b5132 RH |
25 | |
26 | #ifdef ARCH_all | |
0b32f05b | 27 | #ifdef BFD64 |
a06ea964 | 28 | #define ARCH_aarch64 |
252b5132 | 29 | #define ARCH_alpha |
0b32f05b | 30 | #define ARCH_bpf |
0b32f05b AM |
31 | #define ARCH_ia64 |
32 | #define ARCH_loongarch | |
33 | #define ARCH_mips | |
34 | #define ARCH_mmix | |
35 | #define ARCH_nfp | |
36 | #define ARCH_riscv | |
37 | #define ARCH_score | |
38 | #define ARCH_tilegx | |
39 | #endif | |
252b5132 RH |
40 | #define ARCH_arc |
41 | #define ARCH_arm | |
adde6300 | 42 | #define ARCH_avr |
4b7f6baa | 43 | #define ARCH_bfin |
3d3d428f | 44 | #define ARCH_cr16 |
e4e883c0 | 45 | #define ARCH_cris |
1fe1f39c | 46 | #define ARCH_crx |
b8891f8d | 47 | #define ARCH_csky |
252b5132 RH |
48 | #define ARCH_d10v |
49 | #define ARCH_d30v | |
d172d4ba | 50 | #define ARCH_dlx |
56b13185 | 51 | #define ARCH_epiphany |
e729279b NC |
52 | #define ARCH_fr30 |
53 | #define ARCH_frv | |
3f8107ab | 54 | #define ARCH_ft32 |
252b5132 | 55 | #define ARCH_h8300 |
252b5132 RH |
56 | #define ARCH_hppa |
57 | #define ARCH_i386 | |
e729279b NC |
58 | #define ARCH_ip2k |
59 | #define ARCH_iq2000 | |
6e712424 | 60 | #define ARCH_kvx |
84e94c90 | 61 | #define ARCH_lm32 |
e729279b | 62 | #define ARCH_m32c |
252b5132 | 63 | #define ARCH_m32r |
60bcf0fa NC |
64 | #define ARCH_m68hc11 |
65 | #define ARCH_m68hc12 | |
e729279b | 66 | #define ARCH_m68k |
252b5132 | 67 | #define ARCH_mcore |
bd2f2e55 | 68 | #define ARCH_mep |
a3c62988 | 69 | #define ARCH_metag |
7ba29e2a | 70 | #define ARCH_microblaze |
252b5132 RH |
71 | #define ARCH_mn10200 |
72 | #define ARCH_mn10300 | |
59b1530d | 73 | #define ARCH_moxie |
d031aafb | 74 | #define ARCH_mt |
2469cfa2 | 75 | #define ARCH_msp430 |
35c08157 | 76 | #define ARCH_nds32 |
36591ba1 | 77 | #define ARCH_nios2 |
252b5132 | 78 | #define ARCH_ns32k |
73589c9d | 79 | #define ARCH_or1k |
e135f41b | 80 | #define ARCH_pdp11 |
1e608f98 | 81 | #define ARCH_pj |
252b5132 | 82 | #define ARCH_powerpc |
11146849 | 83 | #define ARCH_pru |
252b5132 | 84 | #define ARCH_rs6000 |
99c513f6 | 85 | #define ARCH_rl78 |
c7927a3c | 86 | #define ARCH_rx |
9da4dfd6 | 87 | #define ARCH_s12z |
a85d7ed0 | 88 | #define ARCH_s390 |
252b5132 RH |
89 | #define ARCH_sh |
90 | #define ARCH_sparc | |
e9f53129 | 91 | #define ARCH_spu |
252b5132 | 92 | #define ARCH_tic30 |
026df7c5 | 93 | #define ARCH_tic4x |
5c84d377 | 94 | #define ARCH_tic54x |
40b36596 | 95 | #define ARCH_tic6x |
aa137e4d | 96 | #define ARCH_tilepro |
252b5132 RH |
97 | #define ARCH_v850 |
98 | #define ARCH_vax | |
1945cfa5 | 99 | #define ARCH_visium |
62ecb94c | 100 | #define ARCH_wasm32 |
93fbbb04 | 101 | #define ARCH_xstormy16 |
f6c1a2d5 | 102 | #define ARCH_xgate |
e0001a05 | 103 | #define ARCH_xtensa |
3c9b82ba | 104 | #define ARCH_z80 |
252b5132 RH |
105 | #define ARCH_z8k |
106 | #endif | |
107 | ||
49f58d10 JB |
108 | #ifdef ARCH_m32c |
109 | #include "m32c-desc.h" | |
110 | #endif | |
252b5132 RH |
111 | |
112 | disassembler_ftype | |
b28b8b5e | 113 | disassembler (enum bfd_architecture a, |
78933a4a | 114 | bool big ATTRIBUTE_UNUSED, |
b28b8b5e | 115 | unsigned long mach ATTRIBUTE_UNUSED, |
e347efc3 | 116 | bfd *abfd ATTRIBUTE_UNUSED) |
252b5132 | 117 | { |
252b5132 RH |
118 | disassembler_ftype disassemble; |
119 | ||
120 | switch (a) | |
121 | { | |
122 | /* If you add a case to this table, also add it to the | |
123 | ARCH_all definition right above this function. */ | |
a06ea964 NC |
124 | #ifdef ARCH_aarch64 |
125 | case bfd_arch_aarch64: | |
126 | disassemble = print_insn_aarch64; | |
127 | break; | |
128 | #endif | |
252b5132 RH |
129 | #ifdef ARCH_alpha |
130 | case bfd_arch_alpha: | |
131 | disassemble = print_insn_alpha; | |
132 | break; | |
133 | #endif | |
134 | #ifdef ARCH_arc | |
135 | case bfd_arch_arc: | |
6ca4eb77 AM |
136 | disassemble = arc_get_disassembler (abfd); |
137 | break; | |
252b5132 RH |
138 | #endif |
139 | #ifdef ARCH_arm | |
140 | case bfd_arch_arm: | |
003ca0fd | 141 | if (big) |
252b5132 RH |
142 | disassemble = print_insn_big_arm; |
143 | else | |
144 | disassemble = print_insn_little_arm; | |
145 | break; | |
146 | #endif | |
adde6300 AM |
147 | #ifdef ARCH_avr |
148 | case bfd_arch_avr: | |
149 | disassemble = print_insn_avr; | |
150 | break; | |
151 | #endif | |
4b7f6baa CM |
152 | #ifdef ARCH_bfin |
153 | case bfd_arch_bfin: | |
154 | disassemble = print_insn_bfin; | |
155 | break; | |
156 | #endif | |
3d3d428f NC |
157 | #ifdef ARCH_cr16 |
158 | case bfd_arch_cr16: | |
159 | disassemble = print_insn_cr16; | |
160 | break; | |
161 | #endif | |
6c95a37f HPN |
162 | #ifdef ARCH_cris |
163 | case bfd_arch_cris: | |
78966507 | 164 | disassemble = cris_get_disassembler (abfd); |
6c95a37f | 165 | break; |
1fe1f39c NC |
166 | #endif |
167 | #ifdef ARCH_crx | |
168 | case bfd_arch_crx: | |
169 | disassemble = print_insn_crx; | |
170 | break; | |
6c95a37f | 171 | #endif |
b8891f8d AJ |
172 | #ifdef ARCH_csky |
173 | case bfd_arch_csky: | |
174 | disassemble = csky_get_disassembler (abfd); | |
175 | break; | |
176 | #endif | |
177 | ||
252b5132 RH |
178 | #ifdef ARCH_d10v |
179 | case bfd_arch_d10v: | |
180 | disassemble = print_insn_d10v; | |
181 | break; | |
182 | #endif | |
183 | #ifdef ARCH_d30v | |
184 | case bfd_arch_d30v: | |
185 | disassemble = print_insn_d30v; | |
186 | break; | |
187 | #endif | |
d172d4ba NC |
188 | #ifdef ARCH_dlx |
189 | case bfd_arch_dlx: | |
190 | /* As far as I know we only handle big-endian DLX objects. */ | |
191 | disassemble = print_insn_dlx; | |
192 | break; | |
193 | #endif | |
252b5132 RH |
194 | #ifdef ARCH_h8300 |
195 | case bfd_arch_h8300: | |
003ca0fd | 196 | if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn) |
252b5132 | 197 | disassemble = print_insn_h8300h; |
003ca0fd YQ |
198 | else if (mach == bfd_mach_h8300s |
199 | || mach == bfd_mach_h8300sn | |
200 | || mach == bfd_mach_h8300sx | |
201 | || mach == bfd_mach_h8300sxn) | |
252b5132 | 202 | disassemble = print_insn_h8300s; |
b7ed8fad | 203 | else |
252b5132 RH |
204 | disassemble = print_insn_h8300; |
205 | break; | |
206 | #endif | |
252b5132 RH |
207 | #ifdef ARCH_hppa |
208 | case bfd_arch_hppa: | |
209 | disassemble = print_insn_hppa; | |
210 | break; | |
211 | #endif | |
212 | #ifdef ARCH_i386 | |
213 | case bfd_arch_i386: | |
7b6d09fb | 214 | case bfd_arch_iamcu: |
e396998b | 215 | disassemble = print_insn_i386; |
252b5132 RH |
216 | break; |
217 | #endif | |
800eeca4 JW |
218 | #ifdef ARCH_ia64 |
219 | case bfd_arch_ia64: | |
220 | disassemble = print_insn_ia64; | |
221 | break; | |
222 | #endif | |
a40cbfa3 NC |
223 | #ifdef ARCH_ip2k |
224 | case bfd_arch_ip2k: | |
225 | disassemble = print_insn_ip2k; | |
226 | break; | |
227 | #endif | |
79472b45 JM |
228 | #ifdef ARCH_bpf |
229 | case bfd_arch_bpf: | |
230 | disassemble = print_insn_bpf; | |
231 | break; | |
232 | #endif | |
cfb8c092 NC |
233 | #ifdef ARCH_epiphany |
234 | case bfd_arch_epiphany: | |
235 | disassemble = print_insn_epiphany; | |
236 | break; | |
237 | #endif | |
252b5132 RH |
238 | #ifdef ARCH_fr30 |
239 | case bfd_arch_fr30: | |
240 | disassemble = print_insn_fr30; | |
241 | break; | |
242 | #endif | |
6e712424 PI |
243 | #ifdef ARCH_kvx |
244 | case bfd_arch_kvx: | |
245 | disassemble = print_insn_kvx; | |
246 | break; | |
247 | #endif | |
84e94c90 NC |
248 | #ifdef ARCH_lm32 |
249 | case bfd_arch_lm32: | |
250 | disassemble = print_insn_lm32; | |
251 | break; | |
252 | #endif | |
252b5132 RH |
253 | #ifdef ARCH_m32r |
254 | case bfd_arch_m32r: | |
255 | disassemble = print_insn_m32r; | |
256 | break; | |
257 | #endif | |
6927f982 NC |
258 | #if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \ |
259 | || defined(ARCH_9s12x) || defined(ARCH_m9s12xg) | |
60bcf0fa NC |
260 | case bfd_arch_m68hc11: |
261 | disassemble = print_insn_m68hc11; | |
262 | break; | |
263 | case bfd_arch_m68hc12: | |
264 | disassemble = print_insn_m68hc12; | |
265 | break; | |
6927f982 NC |
266 | case bfd_arch_m9s12x: |
267 | disassemble = print_insn_m9s12x; | |
268 | break; | |
269 | case bfd_arch_m9s12xg: | |
270 | disassemble = print_insn_m9s12xg; | |
271 | break; | |
60bcf0fa | 272 | #endif |
7b4ae824 JD |
273 | #if defined(ARCH_s12z) |
274 | case bfd_arch_s12z: | |
275 | disassemble = print_insn_s12z; | |
276 | break; | |
277 | #endif | |
252b5132 RH |
278 | #ifdef ARCH_m68k |
279 | case bfd_arch_m68k: | |
280 | disassemble = print_insn_m68k; | |
281 | break; | |
282 | #endif | |
d031aafb NS |
283 | #ifdef ARCH_mt |
284 | case bfd_arch_mt: | |
285 | disassemble = print_insn_mt; | |
ac188222 DB |
286 | break; |
287 | #endif | |
7ba29e2a NC |
288 | #ifdef ARCH_microblaze |
289 | case bfd_arch_microblaze: | |
290 | disassemble = print_insn_microblaze; | |
291 | break; | |
292 | #endif | |
2469cfa2 NC |
293 | #ifdef ARCH_msp430 |
294 | case bfd_arch_msp430: | |
295 | disassemble = print_insn_msp430; | |
296 | break; | |
297 | #endif | |
35c08157 KLC |
298 | #ifdef ARCH_nds32 |
299 | case bfd_arch_nds32: | |
300 | disassemble = print_insn_nds32; | |
301 | break; | |
302 | #endif | |
fe944acf FT |
303 | #ifdef ARCH_nfp |
304 | case bfd_arch_nfp: | |
305 | disassemble = print_insn_nfp; | |
306 | break; | |
307 | #endif | |
252b5132 RH |
308 | #ifdef ARCH_ns32k |
309 | case bfd_arch_ns32k: | |
310 | disassemble = print_insn_ns32k; | |
311 | break; | |
312 | #endif | |
313 | #ifdef ARCH_mcore | |
314 | case bfd_arch_mcore: | |
315 | disassemble = print_insn_mcore; | |
316 | break; | |
317 | #endif | |
bd2f2e55 DB |
318 | #ifdef ARCH_mep |
319 | case bfd_arch_mep: | |
320 | disassemble = print_insn_mep; | |
321 | break; | |
322 | #endif | |
a3c62988 NC |
323 | #ifdef ARCH_metag |
324 | case bfd_arch_metag: | |
325 | disassemble = print_insn_metag; | |
326 | break; | |
327 | #endif | |
252b5132 RH |
328 | #ifdef ARCH_mips |
329 | case bfd_arch_mips: | |
003ca0fd | 330 | if (big) |
252b5132 RH |
331 | disassemble = print_insn_big_mips; |
332 | else | |
333 | disassemble = print_insn_little_mips; | |
334 | break; | |
335 | #endif | |
3c3bdf30 NC |
336 | #ifdef ARCH_mmix |
337 | case bfd_arch_mmix: | |
338 | disassemble = print_insn_mmix; | |
339 | break; | |
340 | #endif | |
252b5132 RH |
341 | #ifdef ARCH_mn10200 |
342 | case bfd_arch_mn10200: | |
343 | disassemble = print_insn_mn10200; | |
344 | break; | |
345 | #endif | |
346 | #ifdef ARCH_mn10300 | |
347 | case bfd_arch_mn10300: | |
348 | disassemble = print_insn_mn10300; | |
349 | break; | |
350 | #endif | |
36591ba1 SL |
351 | #ifdef ARCH_nios2 |
352 | case bfd_arch_nios2: | |
003ca0fd | 353 | if (big) |
36591ba1 SL |
354 | disassemble = print_insn_big_nios2; |
355 | else | |
356 | disassemble = print_insn_little_nios2; | |
357 | break; | |
358 | #endif | |
73589c9d CS |
359 | #ifdef ARCH_or1k |
360 | case bfd_arch_or1k: | |
361 | disassemble = print_insn_or1k; | |
3b16e843 NC |
362 | break; |
363 | #endif | |
e135f41b NC |
364 | #ifdef ARCH_pdp11 |
365 | case bfd_arch_pdp11: | |
366 | disassemble = print_insn_pdp11; | |
367 | break; | |
368 | #endif | |
1e608f98 ILT |
369 | #ifdef ARCH_pj |
370 | case bfd_arch_pj: | |
371 | disassemble = print_insn_pj; | |
372 | break; | |
373 | #endif | |
252b5132 RH |
374 | #ifdef ARCH_powerpc |
375 | case bfd_arch_powerpc: | |
52fe4420 AM |
376 | #endif |
377 | #ifdef ARCH_rs6000 | |
378 | case bfd_arch_rs6000: | |
379 | #endif | |
380 | #if defined ARCH_powerpc || defined ARCH_rs6000 | |
003ca0fd | 381 | if (big) |
252b5132 RH |
382 | disassemble = print_insn_big_powerpc; |
383 | else | |
384 | disassemble = print_insn_little_powerpc; | |
385 | break; | |
386 | #endif | |
11146849 DD |
387 | #ifdef ARCH_pru |
388 | case bfd_arch_pru: | |
389 | disassemble = print_insn_pru; | |
390 | break; | |
391 | #endif | |
e23eba97 NC |
392 | #ifdef ARCH_riscv |
393 | case bfd_arch_riscv: | |
8152e040 | 394 | disassemble = riscv_get_disassembler (abfd); |
ae4c0df4 | 395 | break; |
e23eba97 | 396 | #endif |
99c513f6 DD |
397 | #ifdef ARCH_rl78 |
398 | case bfd_arch_rl78: | |
0952813b | 399 | disassemble = rl78_get_disassembler (abfd); |
99c513f6 DD |
400 | break; |
401 | #endif | |
c7927a3c NC |
402 | #ifdef ARCH_rx |
403 | case bfd_arch_rx: | |
404 | disassemble = print_insn_rx; | |
405 | break; | |
406 | #endif | |
a85d7ed0 NC |
407 | #ifdef ARCH_s390 |
408 | case bfd_arch_s390: | |
409 | disassemble = print_insn_s390; | |
410 | break; | |
411 | #endif | |
1c0d3aa6 NC |
412 | #ifdef ARCH_score |
413 | case bfd_arch_score: | |
003ca0fd | 414 | if (big) |
6ca4eb77 | 415 | disassemble = print_insn_big_score; |
1c0d3aa6 | 416 | else |
6ca4eb77 | 417 | disassemble = print_insn_little_score; |
1c0d3aa6 NC |
418 | break; |
419 | #endif | |
252b5132 RH |
420 | #ifdef ARCH_sh |
421 | case bfd_arch_sh: | |
1c509ca8 | 422 | disassemble = print_insn_sh; |
252b5132 RH |
423 | break; |
424 | #endif | |
425 | #ifdef ARCH_sparc | |
426 | case bfd_arch_sparc: | |
427 | disassemble = print_insn_sparc; | |
428 | break; | |
429 | #endif | |
e9f53129 AM |
430 | #ifdef ARCH_spu |
431 | case bfd_arch_spu: | |
432 | disassemble = print_insn_spu; | |
433 | break; | |
434 | #endif | |
252b5132 RH |
435 | #ifdef ARCH_tic30 |
436 | case bfd_arch_tic30: | |
437 | disassemble = print_insn_tic30; | |
438 | break; | |
439 | #endif | |
026df7c5 NC |
440 | #ifdef ARCH_tic4x |
441 | case bfd_arch_tic4x: | |
442 | disassemble = print_insn_tic4x; | |
443 | break; | |
444 | #endif | |
5c84d377 TW |
445 | #ifdef ARCH_tic54x |
446 | case bfd_arch_tic54x: | |
447 | disassemble = print_insn_tic54x; | |
448 | break; | |
449 | #endif | |
40b36596 JM |
450 | #ifdef ARCH_tic6x |
451 | case bfd_arch_tic6x: | |
452 | disassemble = print_insn_tic6x; | |
453 | break; | |
454 | #endif | |
3f8107ab AM |
455 | #ifdef ARCH_ft32 |
456 | case bfd_arch_ft32: | |
457 | disassemble = print_insn_ft32; | |
458 | break; | |
459 | #endif | |
252b5132 RH |
460 | #ifdef ARCH_v850 |
461 | case bfd_arch_v850: | |
de863c74 | 462 | case bfd_arch_v850_rh850: |
252b5132 RH |
463 | disassemble = print_insn_v850; |
464 | break; | |
465 | #endif | |
62ecb94c PC |
466 | #ifdef ARCH_wasm32 |
467 | case bfd_arch_wasm32: | |
468 | disassemble = print_insn_wasm32; | |
469 | break; | |
470 | #endif | |
f6c1a2d5 NC |
471 | #ifdef ARCH_xgate |
472 | case bfd_arch_xgate: | |
473 | disassemble = print_insn_xgate; | |
474 | break; | |
475 | #endif | |
93fbbb04 GK |
476 | #ifdef ARCH_xstormy16 |
477 | case bfd_arch_xstormy16: | |
478 | disassemble = print_insn_xstormy16; | |
479 | break; | |
480 | #endif | |
e0001a05 NC |
481 | #ifdef ARCH_xtensa |
482 | case bfd_arch_xtensa: | |
483 | disassemble = print_insn_xtensa; | |
484 | break; | |
485 | #endif | |
3c9b82ba NC |
486 | #ifdef ARCH_z80 |
487 | case bfd_arch_z80: | |
488 | disassemble = print_insn_z80; | |
489 | break; | |
490 | #endif | |
252b5132 RH |
491 | #ifdef ARCH_z8k |
492 | case bfd_arch_z8k: | |
003ca0fd | 493 | if (mach == bfd_mach_z8001) |
252b5132 | 494 | disassemble = print_insn_z8001; |
b7ed8fad | 495 | else |
252b5132 RH |
496 | disassemble = print_insn_z8002; |
497 | break; | |
498 | #endif | |
499 | #ifdef ARCH_vax | |
500 | case bfd_arch_vax: | |
501 | disassemble = print_insn_vax; | |
502 | break; | |
fd3c93d5 | 503 | #endif |
1945cfa5 EB |
504 | #ifdef ARCH_visium |
505 | case bfd_arch_visium: | |
506 | disassemble = print_insn_visium; | |
507 | break; | |
508 | #endif | |
fd3c93d5 DB |
509 | #ifdef ARCH_frv |
510 | case bfd_arch_frv: | |
511 | disassemble = print_insn_frv; | |
512 | break; | |
47b1a55a | 513 | #endif |
59b1530d AG |
514 | #ifdef ARCH_moxie |
515 | case bfd_arch_moxie: | |
516 | disassemble = print_insn_moxie; | |
517 | break; | |
518 | #endif | |
47b1a55a SC |
519 | #ifdef ARCH_iq2000 |
520 | case bfd_arch_iq2000: | |
521 | disassemble = print_insn_iq2000; | |
522 | break; | |
49f58d10 JB |
523 | #endif |
524 | #ifdef ARCH_m32c | |
525 | case bfd_arch_m32c: | |
526 | disassemble = print_insn_m32c; | |
527 | break; | |
aa137e4d NC |
528 | #endif |
529 | #ifdef ARCH_tilegx | |
530 | case bfd_arch_tilegx: | |
531 | disassemble = print_insn_tilegx; | |
532 | break; | |
533 | #endif | |
534 | #ifdef ARCH_tilepro | |
535 | case bfd_arch_tilepro: | |
536 | disassemble = print_insn_tilepro; | |
537 | break; | |
6cc76c40 | 538 | #endif |
539 | #ifdef ARCH_loongarch | |
540 | case bfd_arch_loongarch: | |
541 | disassemble = print_insn_loongarch; | |
542 | break; | |
252b5132 RH |
543 | #endif |
544 | default: | |
545 | return 0; | |
546 | } | |
547 | return disassemble; | |
548 | } | |
94470b23 NC |
549 | |
550 | void | |
e6c7cdec | 551 | disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) |
94470b23 | 552 | { |
a06ea964 NC |
553 | #ifdef ARCH_aarch64 |
554 | print_aarch64_disassembler_options (stream); | |
555 | #endif | |
37fd5ef3 CZ |
556 | #ifdef ARCH_arc |
557 | print_arc_disassembler_options (stream); | |
558 | #endif | |
58efb6c0 NC |
559 | #ifdef ARCH_arm |
560 | print_arm_disassembler_options (stream); | |
561 | #endif | |
640c0ccd CD |
562 | #ifdef ARCH_mips |
563 | print_mips_disassembler_options (stream); | |
564 | #endif | |
fe944acf FT |
565 | #ifdef ARCH_nfp |
566 | print_nfp_disassembler_options (stream); | |
567 | #endif | |
07dd56a9 NC |
568 | #ifdef ARCH_powerpc |
569 | print_ppc_disassembler_options (stream); | |
570 | #endif | |
e23eba97 NC |
571 | #ifdef ARCH_riscv |
572 | print_riscv_disassembler_options (stream); | |
573 | #endif | |
f59a29b9 L |
574 | #ifdef ARCH_i386 |
575 | print_i386_disassembler_options (stream); | |
576 | #endif | |
6e712424 PI |
577 | #ifdef ARCH_kvx |
578 | print_kvx_disassembler_options (stream); | |
579 | #endif | |
112b7c50 AK |
580 | #ifdef ARCH_s390 |
581 | print_s390_disassembler_options (stream); | |
582 | #endif | |
62ecb94c PC |
583 | #ifdef ARCH_wasm32 |
584 | print_wasm32_disassembler_options (stream); | |
585 | #endif | |
6cc76c40 | 586 | #ifdef ARCH_loongarch |
587 | print_loongarch_disassembler_options (stream); | |
588 | #endif | |
b5c37946 SJ |
589 | #ifdef ARCH_bpf |
590 | print_bpf_disassembler_options (stream); | |
591 | #endif | |
94470b23 NC |
592 | return; |
593 | } | |
22a398e1 NC |
594 | |
595 | void | |
596 | disassemble_init_for_target (struct disassemble_info * info) | |
597 | { | |
598 | if (info == NULL) | |
599 | return; | |
600 | ||
601 | switch (info->arch) | |
602 | { | |
a06ea964 NC |
603 | #ifdef ARCH_aarch64 |
604 | case bfd_arch_aarch64: | |
605 | info->symbol_is_valid = aarch64_symbol_is_valid; | |
78933a4a | 606 | info->disassembler_needs_relocs = true; |
76a4c1e0 | 607 | info->created_styled_output = true; |
a06ea964 NC |
608 | break; |
609 | #endif | |
bbcab336 CZ |
610 | #ifdef ARCH_arc |
611 | case bfd_arch_arc: | |
612 | info->created_styled_output = true; | |
613 | break; | |
614 | #endif | |
22a398e1 NC |
615 | #ifdef ARCH_arm |
616 | case bfd_arch_arm: | |
617 | info->symbol_is_valid = arm_symbol_is_valid; | |
78933a4a | 618 | info->disassembler_needs_relocs = true; |
6576bffe | 619 | info->created_styled_output = true; |
22a398e1 | 620 | break; |
0bcb06d2 | 621 | #endif |
a0f3a4c6 MN |
622 | #ifdef ARCH_avr |
623 | case bfd_arch_avr: | |
624 | info->created_styled_output = true; | |
625 | break; | |
626 | #endif | |
b8891f8d AJ |
627 | #ifdef ARCH_csky |
628 | case bfd_arch_csky: | |
629 | info->symbol_is_valid = csky_symbol_is_valid; | |
78933a4a | 630 | info->disassembler_needs_relocs = true; |
b8891f8d AJ |
631 | break; |
632 | #endif | |
fbbb45ce AB |
633 | #ifdef ARCH_i386 |
634 | case bfd_arch_i386: | |
635 | case bfd_arch_iamcu: | |
636 | info->created_styled_output = true; | |
637 | break; | |
638 | #endif | |
0bcb06d2 AS |
639 | #ifdef ARCH_ia64 |
640 | case bfd_arch_ia64: | |
641 | info->skip_zeroes = 16; | |
642 | break; | |
643 | #endif | |
1b9ea633 WX |
644 | #ifdef ARCH_loongarch |
645 | case bfd_arch_loongarch: | |
646 | info->created_styled_output = true; | |
647 | break; | |
648 | #endif | |
0bcb06d2 AS |
649 | #ifdef ARCH_tic4x |
650 | case bfd_arch_tic4x: | |
651 | info->skip_zeroes = 32; | |
fb53f5a8 | 652 | break; |
49f58d10 | 653 | #endif |
82341e97 AB |
654 | #ifdef ARCH_m68k |
655 | case bfd_arch_m68k: | |
656 | info->created_styled_output = true; | |
657 | break; | |
658 | #endif | |
bd2f2e55 DB |
659 | #ifdef ARCH_mep |
660 | case bfd_arch_mep: | |
661 | info->skip_zeroes = 256; | |
662 | info->skip_zeroes_at_end = 0; | |
663 | break; | |
664 | #endif | |
a3c62988 NC |
665 | #ifdef ARCH_metag |
666 | case bfd_arch_metag: | |
78933a4a | 667 | info->disassembler_needs_relocs = true; |
a3c62988 NC |
668 | break; |
669 | #endif | |
ecfbeec8 AB |
670 | #ifdef ARCH_mips |
671 | case bfd_arch_mips: | |
672 | info->created_styled_output = true; | |
673 | break; | |
674 | #endif | |
49f58d10 JB |
675 | #ifdef ARCH_m32c |
676 | case bfd_arch_m32c: | |
6ca4eb77 AM |
677 | /* This processor in fact is little endian. The value set here |
678 | reflects the way opcodes are written in the cgen description. */ | |
49f58d10 | 679 | info->endian = BFD_ENDIAN_BIG; |
103ebbc3 | 680 | if (!info->private_data) |
fb53f5a8 | 681 | { |
103ebbc3 | 682 | info->private_data = cgen_bitset_create (ISA_MAX); |
fb53f5a8 | 683 | if (info->mach == bfd_mach_m16c) |
103ebbc3 | 684 | cgen_bitset_set (info->private_data, ISA_M16C); |
fb53f5a8 | 685 | else |
103ebbc3 | 686 | cgen_bitset_set (info->private_data, ISA_M32C); |
fb53f5a8 | 687 | } |
49f58d10 | 688 | break; |
b240011a | 689 | #endif |
79472b45 JM |
690 | #ifdef ARCH_bpf |
691 | case bfd_arch_bpf: | |
b5c37946 | 692 | info->created_styled_output = true; |
79472b45 JM |
693 | break; |
694 | #endif | |
024d185c DD |
695 | #ifdef ARCH_pru |
696 | case bfd_arch_pru: | |
78933a4a | 697 | info->disassembler_needs_relocs = true; |
024d185c DD |
698 | break; |
699 | #endif | |
fbc22555 DD |
700 | #ifdef ARCH_powerpc |
701 | case bfd_arch_powerpc: | |
702 | #endif | |
b240011a AM |
703 | #ifdef ARCH_rs6000 |
704 | case bfd_arch_rs6000: | |
705 | #endif | |
706 | #if defined (ARCH_powerpc) || defined (ARCH_rs6000) | |
707 | disassemble_init_powerpc (info); | |
36d94bd4 | 708 | info->created_styled_output = true; |
b240011a | 709 | break; |
65b48a81 | 710 | #endif |
884b49e3 AB |
711 | #ifdef ARCH_riscv |
712 | case bfd_arch_riscv: | |
713 | info->symbol_is_valid = riscv_symbol_is_valid; | |
49d31dc9 | 714 | info->created_styled_output = true; |
884b49e3 AB |
715 | break; |
716 | #endif | |
62ecb94c PC |
717 | #ifdef ARCH_wasm32 |
718 | case bfd_arch_wasm32: | |
719 | disassemble_init_wasm32 (info); | |
720 | break; | |
721 | #endif | |
65b48a81 PB |
722 | #ifdef ARCH_s390 |
723 | case bfd_arch_s390: | |
724 | disassemble_init_s390 (info); | |
ec54dc91 | 725 | info->created_styled_output = true; |
65b48a81 | 726 | break; |
22a398e1 | 727 | #endif |
fbaf61ad NC |
728 | #ifdef ARCH_nds32 |
729 | case bfd_arch_nds32: | |
730 | disassemble_init_nds32 (info); | |
731 | break; | |
732 | #endif | |
22a398e1 NC |
733 | default: |
734 | break; | |
735 | } | |
736 | } | |
65b48a81 | 737 | |
20135676 AM |
738 | void |
739 | disassemble_free_target (struct disassemble_info *info) | |
740 | { | |
741 | if (info == NULL) | |
742 | return; | |
743 | ||
744 | switch (info->arch) | |
745 | { | |
746 | default: | |
747 | return; | |
748 | ||
20135676 AM |
749 | #ifdef ARCH_m32c |
750 | case bfd_arch_m32c: | |
751 | #endif | |
b5c37946 | 752 | #if defined ARCH_m32c |
20135676 AM |
753 | if (info->private_data) |
754 | { | |
755 | CGEN_BITSET *mask = info->private_data; | |
756 | free (mask->bits); | |
757 | } | |
758 | break; | |
759 | #endif | |
760 | ||
761 | #ifdef ARCH_arc | |
762 | case bfd_arch_arc: | |
763 | break; | |
764 | #endif | |
765 | #ifdef ARCH_cris | |
766 | case bfd_arch_cris: | |
767 | break; | |
768 | #endif | |
769 | #ifdef ARCH_mmix | |
770 | case bfd_arch_mmix: | |
771 | break; | |
772 | #endif | |
773 | #ifdef ARCH_nfp | |
774 | case bfd_arch_nfp: | |
775 | break; | |
776 | #endif | |
777 | #ifdef ARCH_powerpc | |
778 | case bfd_arch_powerpc: | |
779 | break; | |
780 | #endif | |
781 | #ifdef ARCH_riscv | |
782 | case bfd_arch_riscv: | |
26e91972 | 783 | disassemble_free_riscv (info); |
20135676 AM |
784 | break; |
785 | #endif | |
786 | #ifdef ARCH_rs6000 | |
787 | case bfd_arch_rs6000: | |
788 | break; | |
789 | #endif | |
790 | } | |
791 | ||
792 | free (info->private_data); | |
793 | } | |
794 | ||
65b48a81 PB |
795 | /* Remove whitespace and consecutive commas from OPTIONS. */ |
796 | ||
797 | char * | |
798 | remove_whitespace_and_extra_commas (char *options) | |
799 | { | |
800 | char *str; | |
801 | size_t i, len; | |
802 | ||
803 | if (options == NULL) | |
804 | return NULL; | |
805 | ||
806 | /* Strip off all trailing whitespace and commas. */ | |
807 | for (len = strlen (options); len > 0; len--) | |
808 | { | |
809 | if (!ISSPACE (options[len - 1]) && options[len - 1] != ',') | |
810 | break; | |
811 | options[len - 1] = '\0'; | |
812 | } | |
813 | ||
814 | /* Convert all remaining whitespace to commas. */ | |
815 | for (i = 0; options[i] != '\0'; i++) | |
816 | if (ISSPACE (options[i])) | |
817 | options[i] = ','; | |
818 | ||
819 | /* Remove consecutive commas. */ | |
820 | for (str = options; *str != '\0'; str++) | |
821 | if (*str == ',' && (*(str + 1) == ',' || str == options)) | |
822 | { | |
823 | char *next = str + 1; | |
824 | while (*next == ',') | |
825 | next++; | |
826 | len = strlen (next); | |
827 | if (str != options) | |
828 | str++; | |
829 | memmove (str, next, len); | |
830 | next[len - (size_t)(next - str)] = '\0'; | |
831 | } | |
832 | return (strlen (options) != 0) ? options : NULL; | |
833 | } | |
834 | ||
835 | /* Like STRCMP, but treat ',' the same as '\0' so that we match | |
836 | strings like "foobar" against "foobar,xxyyzz,...". */ | |
837 | ||
838 | int | |
839 | disassembler_options_cmp (const char *s1, const char *s2) | |
840 | { | |
841 | unsigned char c1, c2; | |
842 | ||
843 | do | |
844 | { | |
845 | c1 = (unsigned char) *s1++; | |
846 | if (c1 == ',') | |
847 | c1 = '\0'; | |
848 | c2 = (unsigned char) *s2++; | |
849 | if (c2 == ',') | |
850 | c2 = '\0'; | |
851 | if (c1 == '\0') | |
852 | return c1 - c2; | |
853 | } | |
854 | while (c1 == c2); | |
855 | ||
856 | return c1 - c2; | |
857 | } | |
832a5807 AM |
858 | |
859 | void | |
860 | opcodes_assert (const char *file, int line) | |
861 | { | |
862 | opcodes_error_handler (_("assertion fail %s:%d"), file, line); | |
863 | opcodes_error_handler (_("Please report this bug")); | |
864 | abort (); | |
865 | } | |
60a3da00 AB |
866 | |
867 | /* Set the stream, and the styled and unstyled printf functions within | |
868 | INFO. */ | |
869 | ||
870 | void | |
871 | disassemble_set_printf (struct disassemble_info *info, void *stream, | |
872 | fprintf_ftype unstyled_printf, | |
873 | fprintf_styled_ftype styled_printf) | |
874 | { | |
875 | info->stream = stream; | |
876 | info->fprintf_func = unstyled_printf; | |
877 | info->fprintf_styled_func = styled_printf; | |
878 | } |