]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/fr30-ibld.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[thirdparty/binutils-gdb.git] / opcodes / fr30-ibld.c
CommitLineData
4162bb66 1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
252b5132
RH		 2/* Instruction building/extraction support for fr30. -*- C -*-
3
47b0e7ad
NC		 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
5 - the resultant file is machine generated, cgen-ibld.in isn't
252b5132 6
b3adc24a 7 Copyright (C) 1996-2020 Free Software Foundation, Inc.
252b5132 8
9b201bb5 9 This file is part of libopcodes.
252b5132 10
9b201bb5 11 This library is free software; you can redistribute it and/or modify
47b0e7ad 12 it under the terms of the GNU General Public License as published by
9b201bb5 13 the Free Software Foundation; either version 3, or (at your option)
47b0e7ad 14 any later version.
252b5132 15
9b201bb5
NC		 16 It is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
252b5132 20
47b0e7ad
NC		 21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
252b5132
RH		 29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "fr30-desc.h"
35#include "fr30-opc.h"
fe8afbc4 36#include "cgen/basic-modes.h"
252b5132 37#include "opintl.h"
37111cc7 38#include "safe-ctype.h"
252b5132 39
47b0e7ad 40#undef min
252b5132 41#define min(a,b) ((a) < (b) ? (a) : (b))
47b0e7ad 42#undef max
252b5132
RH		 43#define max(a,b) ((a) > (b) ? (a) : (b))
44
45/* Used by the ifield rtx function. */
46#define FLD(f) (fields->f)
47
48static const char * insert_normal
ffead7ae
MM		 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
252b5132 51static const char * insert_insn_normal
ffead7ae
MM		 52 (CGEN_CPU_DESC, const CGEN_INSN *,
53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
252b5132 54static int extract_normal
ffead7ae
MM		 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
56 unsigned int, unsigned int, unsigned int, unsigned int,
57 unsigned int, unsigned int, bfd_vma, long *);
252b5132 58static int extract_insn_normal
ffead7ae
MM		 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
d5b2f4d6 61#if CGEN_INT_INSN_P
6bb95a0f 62static void put_insn_int_value
ffead7ae 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
d5b2f4d6 64#endif
0e2ee3ca 65#if ! CGEN_INT_INSN_P
d5b2f4d6 66static CGEN_INLINE void insert_1
ffead7ae 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
0e2ee3ca 68static CGEN_INLINE int fill_cache
ffead7ae 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
0e2ee3ca 70static CGEN_INLINE long extract_1
ffead7ae 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
0e2ee3ca 72#endif
252b5132
RH		 73\f
74/* Operand insertion. */
75
76#if ! CGEN_INT_INSN_P
77
78/* Subroutine of insert_normal. */
79
80static CGEN_INLINE void
ffead7ae
MM		 81insert_1 (CGEN_CPU_DESC cd,
82 unsigned long value,
83 int start,
84 int length,
85 int word_length,
86 unsigned char *bufp)
252b5132
RH		 87{
88 unsigned long x,mask;
89 int shift;
252b5132 90
0e2ee3ca 91 x = cgen_get_insn_value (cd, bufp, word_length);
252b5132
RH		 92
93 /* Written this way to avoid undefined behaviour. */
94 mask = (((1L << (length - 1)) - 1) << 1) | 1;
95 if (CGEN_INSN_LSB0_P)
96 shift = (start + 1) - length;
97 else
98 shift = (word_length - (start + length));
99 x = (x & ~(mask << shift)) | ((value & mask) << shift);
100
0e2ee3ca 101 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
252b5132
RH		 102}
103
104#endif /* ! CGEN_INT_INSN_P */
105
106/* Default insertion routine.
107
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
114
115 The result is an error message or NULL if success. */
116
117/* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119/* ??? This doesn't handle bfd_vma's. Create another function when
120 necessary. */
121
122static const char *
ffead7ae
MM		 123insert_normal (CGEN_CPU_DESC cd,
124 long value,
125 unsigned int attrs,
126 unsigned int word_offset,
127 unsigned int start,
128 unsigned int length,
129 unsigned int word_length,
130 unsigned int total_length,
131 CGEN_INSN_BYTES_PTR buffer)
252b5132
RH		 132{
133 static char errbuf[100];
134 /* Written this way to avoid undefined behaviour. */
135 unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
136
137 /* If LENGTH is zero, this operand doesn't contribute to the value. */
138 if (length == 0)
139 return NULL;
140
b7cd1872 141 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 142 abort ();
143
144 /* For architectures with insns smaller than the base-insn-bitsize,
145 word_length may be too big. */
146 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
147 {
148 if (word_offset == 0
149 && word_length > total_length)
150 word_length = total_length;
151 }
152
153 /* Ensure VALUE will fit. */
fc7bc883
RH		 154 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
155 {
156 long minval = - (1L << (length - 1));
157 unsigned long maxval = mask;
43e65147 158
fc7bc883
RH		 159 if ((value > 0 && (unsigned long) value > maxval)
160 || value < minval)
161 {
162 /* xgettext:c-format */
163 sprintf (errbuf,
164 _("operand out of range (%ld not between %ld and %lu)"),
165 value, minval, maxval);
166 return errbuf;
167 }
168 }
169 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
252b5132
RH		 170 {
171 unsigned long maxval = mask;
ed963e2d
NC		 172 unsigned long val = (unsigned long) value;
173
174 /* For hosts with a word size > 32 check to see if value has been sign
175 extended beyond 32 bits. If so then ignore these higher sign bits
176 as the user is attempting to store a 32-bit signed value into an
177 unsigned 32-bit field which is allowed. */
178 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
179 val &= 0xFFFFFFFF;
180
181 if (val > maxval)
252b5132
RH		 182 {
183 /* xgettext:c-format */
184 sprintf (errbuf,
ed963e2d
NC		 185 _("operand out of range (0x%lx not between 0 and 0x%lx)"),
186 val, maxval);
252b5132
RH		 187 return errbuf;
188 }
189 }
190 else
191 {
6bb95a0f 192 if (! cgen_signed_overflow_ok_p (cd))
252b5132 193 {
6bb95a0f
DB		 194 long minval = - (1L << (length - 1));
195 long maxval = (1L << (length - 1)) - 1;
43e65147 196
6bb95a0f
DB		 197 if (value < minval || value > maxval)
198 {
199 sprintf
200 /* xgettext:c-format */
201 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
202 value, minval, maxval);
203 return errbuf;
204 }
252b5132
RH		 205 }
206 }
207
208#if CGEN_INT_INSN_P
209
210 {
a143b004 211 int shift_within_word, shift_to_word, shift;
252b5132 212
a143b004
AB		 213 /* How to shift the value to BIT0 of the word. */
214 shift_to_word = total_length - (word_offset + word_length);
215
216 /* How to shift the value to the field within the word. */
252b5132 217 if (CGEN_INSN_LSB0_P)
a143b004 218 shift_within_word = start + 1 - length;
252b5132 219 else
a143b004
AB		 220 shift_within_word = word_length - start - length;
221
222 /* The total SHIFT, then mask in the value. */
223 shift = shift_to_word + shift_within_word;
252b5132
RH		 224 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
225 }
226
227#else /* ! CGEN_INT_INSN_P */
228
229 {
230 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
231
232 insert_1 (cd, value, start, length, word_length, bufp);
233 }
234
235#endif /* ! CGEN_INT_INSN_P */
236
237 return NULL;
238}
239
240/* Default insn builder (insert handler).
fc7bc883
RH		 241 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
242 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
243 recorded in host byte order, otherwise BUFFER is an array of bytes
244 and the value is recorded in target byte order).
252b5132
RH		 245 The result is an error message or NULL if success. */
246
247static const char *
ffead7ae
MM		 248insert_insn_normal (CGEN_CPU_DESC cd,
249 const CGEN_INSN * insn,
250 CGEN_FIELDS * fields,
251 CGEN_INSN_BYTES_PTR buffer,
252 bfd_vma pc)
252b5132
RH		 253{
254 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
255 unsigned long value;
b3466c39 256 const CGEN_SYNTAX_CHAR_TYPE * syn;
252b5132
RH		 257
258 CGEN_INIT_INSERT (cd);
259 value = CGEN_INSN_BASE_VALUE (insn);
260
261 /* If we're recording insns as numbers (rather than a string of bytes),
262 target byte order handling is deferred until later. */
263
264#if CGEN_INT_INSN_P
265
6bb95a0f
DB		 266 put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
267 CGEN_FIELDS_BITSIZE (fields), value);
252b5132
RH		 268
269#else
270
0e2ee3ca 271 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
d5b2f4d6 272 (unsigned) CGEN_FIELDS_BITSIZE (fields)),
252b5132
RH		 273 value);
274
275#endif /* ! CGEN_INT_INSN_P */
276
277 /* ??? It would be better to scan the format's fields.
278 Still need to be able to insert a value based on the operand though;
279 e.g. storing a branch displacement that got resolved later.
280 Needs more thought first. */
281
b3466c39 282 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
252b5132
RH		 283 {
284 const char *errmsg;
285
286 if (CGEN_SYNTAX_CHAR_P (* syn))
287 continue;
288
289 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
290 fields, buffer, pc);
291 if (errmsg)
292 return errmsg;
293 }
294
295 return NULL;
296}
6bb95a0f 297
d5b2f4d6 298#if CGEN_INT_INSN_P
6bb95a0f 299/* Cover function to store an insn value into an integral insn. Must go here
47b0e7ad 300 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
6bb95a0f
DB		 301
302static void
ffead7ae
MM		 303put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
304 CGEN_INSN_BYTES_PTR buf,
305 int length,
306 int insn_length,
307 CGEN_INSN_INT value)
6bb95a0f
DB		 308{
309 /* For architectures with insns smaller than the base-insn-bitsize,
310 length may be too big. */
311 if (length > insn_length)
312 *buf = value;
313 else
314 {
315 int shift = insn_length - length;
316 /* Written this way to avoid undefined behaviour. */
317 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
47b0e7ad 318
6bb95a0f
DB		 319 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
320 }
321}
d5b2f4d6 322#endif
252b5132
RH		 323\f
324/* Operand extraction. */
325
326#if ! CGEN_INT_INSN_P
327
328/* Subroutine of extract_normal.
329 Ensure sufficient bytes are cached in EX_INFO.
330 OFFSET is the offset in bytes from the start of the insn of the value.
331 BYTES is the length of the needed value.
332 Returns 1 for success, 0 for failure. */
333
334static CGEN_INLINE int
ffead7ae
MM		 335fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
336 CGEN_EXTRACT_INFO *ex_info,
337 int offset,
338 int bytes,
339 bfd_vma pc)
252b5132
RH		 340{
341 /* It's doubtful that the middle part has already been fetched so
342 we don't optimize that case. kiss. */
d5b2f4d6 343 unsigned int mask;
252b5132
RH		 344 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
345
346 /* First do a quick check. */
347 mask = (1 << bytes) - 1;
348 if (((ex_info->valid >> offset) & mask) == mask)
349 return 1;
350
351 /* Search for the first byte we need to read. */
352 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
353 if (! (mask & ex_info->valid))
354 break;
355
356 if (bytes)
357 {
358 int status;
359
360 pc += offset;
361 status = (*info->read_memory_func)
362 (pc, ex_info->insn_bytes + offset, bytes, info);
363
364 if (status != 0)
365 {
366 (*info->memory_error_func) (status, pc, info);
367 return 0;
368 }
369
370 ex_info->valid |= ((1 << bytes) - 1) << offset;
371 }
372
373 return 1;
374}
375
376/* Subroutine of extract_normal. */
377
378static CGEN_INLINE long
ffead7ae
MM		 379extract_1 (CGEN_CPU_DESC cd,
380 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
381 int start,
382 int length,
383 int word_length,
384 unsigned char *bufp,
385 bfd_vma pc ATTRIBUTE_UNUSED)
252b5132 386{
b3466c39 387 unsigned long x;
252b5132 388 int shift;
47b0e7ad 389
e333d2c4
NC		 390 x = cgen_get_insn_value (cd, bufp, word_length);
391
252b5132
RH		 392 if (CGEN_INSN_LSB0_P)
393 shift = (start + 1) - length;
394 else
395 shift = (word_length - (start + length));
b3466c39 396 return x >> shift;
252b5132
RH		 397}
398
399#endif /* ! CGEN_INT_INSN_P */
400
401/* Default extraction routine.
402
403 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
404 or sometimes less for cases like the m32r where the base insn size is 32
405 but some insns are 16 bits.
406 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
407 but for generality we take a bitmask of all of them.
408 WORD_OFFSET is the offset in bits from the start of the insn of the value.
409 WORD_LENGTH is the length of the word in bits in which the value resides.
410 START is the starting bit number in the word, architecture origin.
411 LENGTH is the length of VALUE in bits.
412 TOTAL_LENGTH is the total length of the insn in bits.
413
414 Returns 1 for success, 0 for failure. */
415
416/* ??? The return code isn't properly used. wip. */
417
418/* ??? This doesn't handle bfd_vma's. Create another function when
419 necessary. */
420
421static int
ffead7ae 422extract_normal (CGEN_CPU_DESC cd,
6bb95a0f 423#if ! CGEN_INT_INSN_P
ffead7ae 424 CGEN_EXTRACT_INFO *ex_info,
6bb95a0f 425#else
ffead7ae 426 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
6bb95a0f 427#endif
ffead7ae
MM		 428 CGEN_INSN_INT insn_value,
429 unsigned int attrs,
430 unsigned int word_offset,
431 unsigned int start,
432 unsigned int length,
433 unsigned int word_length,
434 unsigned int total_length,
6bb95a0f 435#if ! CGEN_INT_INSN_P
ffead7ae 436 bfd_vma pc,
6bb95a0f 437#else
ffead7ae 438 bfd_vma pc ATTRIBUTE_UNUSED,
6bb95a0f 439#endif
ffead7ae 440 long *valuep)
252b5132 441{
fc7bc883 442 long value, mask;
252b5132
RH		 443
444 /* If LENGTH is zero, this operand doesn't contribute to the value
445 so give it a standard value of zero. */
446 if (length == 0)
447 {
448 *valuep = 0;
449 return 1;
450 }
451
b7cd1872 452 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 453 abort ();
454
455 /* For architectures with insns smaller than the insn-base-bitsize,
456 word_length may be too big. */
457 if (cd->min_insn_bitsize < cd->base_insn_bitsize)
458 {
ed963e2d
NC		 459 if (word_offset + word_length > total_length)
460 word_length = total_length - word_offset;
252b5132
RH		 461 }
462
fc7bc883 463 /* Does the value reside in INSN_VALUE, and at the right alignment? */
252b5132 464
fc7bc883 465 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
252b5132 466 {
252b5132 467 if (CGEN_INSN_LSB0_P)
6bb95a0f 468 value = insn_value >> ((word_offset + start + 1) - length);
252b5132 469 else
6bb95a0f 470 value = insn_value >> (total_length - ( word_offset + start + length));
252b5132
RH		 471 }
472
473#if ! CGEN_INT_INSN_P
474
475 else
476 {
477 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
478
b7cd1872 479 if (word_length > 8 * sizeof (CGEN_INSN_INT))
252b5132
RH		 480 abort ();
481
482 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
2f5dd314
AM		 483 {
484 *valuep = 0;
485 return 0;
486 }
252b5132
RH		 487
488 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
489 }
490
491#endif /* ! CGEN_INT_INSN_P */
492
b3466c39
DB		 493 /* Written this way to avoid undefined behaviour. */
494 mask = (((1L << (length - 1)) - 1) << 1) | 1;
495
496 value &= mask;
497 /* sign extend? */
498 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
499 && (value & (1L << (length - 1))))
500 value |= ~mask;
501
252b5132
RH		 502 *valuep = value;
503
504 return 1;
505}
506
507/* Default insn extractor.
508
509 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
510 The extracted fields are stored in FIELDS.
511 EX_INFO is used to handle reading variable length insns.
512 Return the length of the insn in bits, or 0 if no match,
513 or -1 if an error occurs fetching data (memory_error_func will have
514 been called). */
515
516static int
ffead7ae
MM		 517extract_insn_normal (CGEN_CPU_DESC cd,
518 const CGEN_INSN *insn,
519 CGEN_EXTRACT_INFO *ex_info,
520 CGEN_INSN_INT insn_value,
521 CGEN_FIELDS *fields,
522 bfd_vma pc)
252b5132
RH		 523{
524 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
b3466c39 525 const CGEN_SYNTAX_CHAR_TYPE *syn;
252b5132
RH		 526
527 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
528
529 CGEN_INIT_EXTRACT (cd);
530
531 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
532 {
533 int length;
534
535 if (CGEN_SYNTAX_CHAR_P (*syn))
536 continue;
537
538 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
539 ex_info, insn_value, fields, pc);
540 if (length <= 0)
541 return length;
542 }
543
544 /* We recognized and successfully extracted this insn. */
545 return CGEN_INSN_BITSIZE (insn);
546}
547\f
47b0e7ad 548/* Machine generated code added here. */
252b5132 549
0e2ee3ca 550const char * fr30_cgen_insert_operand
47b0e7ad 551 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
0e2ee3ca 552
252b5132
RH		 553/* Main entry point for operand insertion.
554
555 This function is basically just a big switch statement. Earlier versions
556 used tables to look up the function to use, but
557 - if the table contains both assembler and disassembler functions then
558 the disassembler contains much of the assembler and vice-versa,
559 - there's a lot of inlining possibilities as things grow,
560 - using a switch statement avoids the function call overhead.
561
562 This function could be moved into `parse_insn_normal', but keeping it
563 separate makes clear the interface between `parse_insn_normal' and each of
564 the handlers. It's also needed by GAS to insert operands that couldn't be
9a2e995d 565 resolved during parsing. */
252b5132
RH		 566
567const char *
47b0e7ad
NC		 568fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
569 int opindex,
570 CGEN_FIELDS * fields,
571 CGEN_INSN_BYTES_PTR buffer,
572 bfd_vma pc ATTRIBUTE_UNUSED)
252b5132 573{
eb1b03df 574 const char * errmsg = NULL;
252b5132
RH		 575 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
576
577 switch (opindex)
578 {
579 case FR30_OPERAND_CRI :
580 errmsg = insert_normal (cd, fields->f_CRi, 0, 16, 12, 4, 16, total_length, buffer);
581 break;
582 case FR30_OPERAND_CRJ :
583 errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer);
584 break;
585 case FR30_OPERAND_R13 :
252b5132
RH		 586 break;
587 case FR30_OPERAND_R14 :
252b5132
RH		 588 break;
589 case FR30_OPERAND_R15 :
252b5132
RH		 590 break;
591 case FR30_OPERAND_RI :
592 errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer);
593 break;
594 case FR30_OPERAND_RIC :
595 errmsg = insert_normal (cd, fields->f_Ric, 0, 16, 12, 4, 16, total_length, buffer);
596 break;
597 case FR30_OPERAND_RJ :
598 errmsg = insert_normal (cd, fields->f_Rj, 0, 0, 8, 4, 16, total_length, buffer);
599 break;
600 case FR30_OPERAND_RJC :
601 errmsg = insert_normal (cd, fields->f_Rjc, 0, 16, 8, 4, 16, total_length, buffer);
602 break;
603 case FR30_OPERAND_RS1 :
604 errmsg = insert_normal (cd, fields->f_Rs1, 0, 0, 8, 4, 16, total_length, buffer);
605 break;
606 case FR30_OPERAND_RS2 :
607 errmsg = insert_normal (cd, fields->f_Rs2, 0, 0, 12, 4, 16, total_length, buffer);
608 break;
609 case FR30_OPERAND_CC :
610 errmsg = insert_normal (cd, fields->f_cc, 0, 0, 4, 4, 16, total_length, buffer);
611 break;
612 case FR30_OPERAND_CCC :
613 errmsg = insert_normal (cd, fields->f_ccc, 0, 16, 0, 8, 16, total_length, buffer);
614 break;
615 case FR30_OPERAND_DIR10 :
616 {
617 long value = fields->f_dir10;
fe8afbc4 618 value = ((USI) (value) >> (2));
252b5132
RH		 619 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
620 }
621 break;
622 case FR30_OPERAND_DIR8 :
623 errmsg = insert_normal (cd, fields->f_dir8, 0, 0, 8, 8, 16, total_length, buffer);
624 break;
625 case FR30_OPERAND_DIR9 :
626 {
627 long value = fields->f_dir9;
fe8afbc4 628 value = ((USI) (value) >> (1));
252b5132
RH		 629 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
630 }
631 break;
632 case FR30_OPERAND_DISP10 :
633 {
634 long value = fields->f_disp10;
fe8afbc4 635 value = ((SI) (value) >> (2));
252b5132
RH		 636 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
637 }
638 break;
639 case FR30_OPERAND_DISP8 :
640 errmsg = insert_normal (cd, fields->f_disp8, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
641 break;
642 case FR30_OPERAND_DISP9 :
643 {
644 long value = fields->f_disp9;
fe8afbc4 645 value = ((SI) (value) >> (1));
252b5132
RH		 646 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
647 }
648 break;
649 case FR30_OPERAND_I20 :
650 {
651{
fe8afbc4 652 FLD (f_i20_4) = ((UINT) (FLD (f_i20)) >> (16));
252b5132
RH		 653 FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
654}
655 errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
656 if (errmsg)
657 break;
658 errmsg = insert_normal (cd, fields->f_i20_16, 0, 16, 0, 16, 16, total_length, buffer);
659 if (errmsg)
660 break;
661 }
662 break;
663 case FR30_OPERAND_I32 :
664 errmsg = insert_normal (cd, fields->f_i32, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, buffer);
665 break;
666 case FR30_OPERAND_I8 :
667 errmsg = insert_normal (cd, fields->f_i8, 0, 0, 4, 8, 16, total_length, buffer);
668 break;
669 case FR30_OPERAND_LABEL12 :
670 {
671 long value = fields->f_rel12;
fe8afbc4 672 value = ((SI) (((value) - (((pc) + (2))))) >> (1));
252b5132
RH		 673 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
674 }
675 break;
676 case FR30_OPERAND_LABEL9 :
677 {
678 long value = fields->f_rel9;
fe8afbc4 679 value = ((SI) (((value) - (((pc) + (2))))) >> (1));
252b5132
RH		 680 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
681 }
682 break;
683 case FR30_OPERAND_M4 :
684 {
685 long value = fields->f_m4;
686 value = ((value) & (15));
687 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
688 }
689 break;
690 case FR30_OPERAND_PS :
252b5132
RH		 691 break;
692 case FR30_OPERAND_REGLIST_HI_LD :
693 errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer);
694 break;
695 case FR30_OPERAND_REGLIST_HI_ST :
696 errmsg = insert_normal (cd, fields->f_reglist_hi_st, 0, 0, 8, 8, 16, total_length, buffer);
697 break;
698 case FR30_OPERAND_REGLIST_LOW_LD :
699 errmsg = insert_normal (cd, fields->f_reglist_low_ld, 0, 0, 8, 8, 16, total_length, buffer);
700 break;
701 case FR30_OPERAND_REGLIST_LOW_ST :
702 errmsg = insert_normal (cd, fields->f_reglist_low_st, 0, 0, 8, 8, 16, total_length, buffer);
703 break;
704 case FR30_OPERAND_S10 :
705 {
706 long value = fields->f_s10;
fe8afbc4 707 value = ((SI) (value) >> (2));
252b5132
RH		 708 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
709 }
710 break;
711 case FR30_OPERAND_U10 :
712 {
713 long value = fields->f_u10;
fe8afbc4 714 value = ((USI) (value) >> (2));
252b5132
RH		 715 errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
716 }
717 break;
718 case FR30_OPERAND_U4 :
719 errmsg = insert_normal (cd, fields->f_u4, 0, 0, 8, 4, 16, total_length, buffer);
720 break;
721 case FR30_OPERAND_U4C :
722 errmsg = insert_normal (cd, fields->f_u4c, 0, 0, 12, 4, 16, total_length, buffer);
723 break;
724 case FR30_OPERAND_U8 :
725 errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 16, total_length, buffer);
726 break;
727 case FR30_OPERAND_UDISP6 :
728 {
729 long value = fields->f_udisp6;
fe8afbc4 730 value = ((USI) (value) >> (2));
252b5132
RH		 731 errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
732 }
733 break;
734
735 default :
736 /* xgettext:c-format */
a6743a54
AM		 737 opcodes_error_handler
738 (_("internal error: unrecognized field %d while building insn"),
739 opindex);
252b5132
RH		 740 abort ();
741 }
742
743 return errmsg;
744}
745
0e2ee3ca 746int fr30_cgen_extract_operand
47b0e7ad 747 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 748
252b5132 749/* Main entry point for operand extraction.
eb1b03df
DE		 750 The result is <= 0 for error, >0 for success.
751 ??? Actual values aren't well defined right now.
252b5132
RH		 752
753 This function is basically just a big switch statement. Earlier versions
754 used tables to look up the function to use, but
755 - if the table contains both assembler and disassembler functions then
756 the disassembler contains much of the assembler and vice-versa,
757 - there's a lot of inlining possibilities as things grow,
758 - using a switch statement avoids the function call overhead.
759
760 This function could be moved into `print_insn_normal', but keeping it
761 separate makes clear the interface between `print_insn_normal' and each of
9a2e995d 762 the handlers. */
252b5132
RH		 763
764int
47b0e7ad
NC		 765fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
766 int opindex,
767 CGEN_EXTRACT_INFO *ex_info,
768 CGEN_INSN_INT insn_value,
769 CGEN_FIELDS * fields,
770 bfd_vma pc)
252b5132 771{
eb1b03df
DE		 772 /* Assume success (for those operands that are nops). */
773 int length = 1;
252b5132
RH		 774 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
775
776 switch (opindex)
777 {
778 case FR30_OPERAND_CRI :
779 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_CRi);
780 break;
781 case FR30_OPERAND_CRJ :
782 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj);
783 break;
784 case FR30_OPERAND_R13 :
252b5132
RH		 785 break;
786 case FR30_OPERAND_R14 :
252b5132
RH		 787 break;
788 case FR30_OPERAND_R15 :
252b5132
RH		 789 break;
790 case FR30_OPERAND_RI :
791 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri);
792 break;
793 case FR30_OPERAND_RIC :
794 length = extract_normal (cd, ex_info, insn_value, 0, 16, 12, 4, 16, total_length, pc, & fields->f_Ric);
795 break;
796 case FR30_OPERAND_RJ :
797 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rj);
798 break;
799 case FR30_OPERAND_RJC :
800 length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_Rjc);
801 break;
802 case FR30_OPERAND_RS1 :
803 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_Rs1);
804 break;
805 case FR30_OPERAND_RS2 :
806 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Rs2);
807 break;
808 case FR30_OPERAND_CC :
809 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 16, total_length, pc, & fields->f_cc);
810 break;
811 case FR30_OPERAND_CCC :
812 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 8, 16, total_length, pc, & fields->f_ccc);
813 break;
814 case FR30_OPERAND_DIR10 :
815 {
816 long value;
817 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
818 value = ((value) << (2));
819 fields->f_dir10 = value;
820 }
821 break;
822 case FR30_OPERAND_DIR8 :
823 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_dir8);
824 break;
825 case FR30_OPERAND_DIR9 :
826 {
827 long value;
828 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
829 value = ((value) << (1));
830 fields->f_dir9 = value;
831 }
832 break;
833 case FR30_OPERAND_DISP10 :
834 {
835 long value;
836 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
202e762b 837 value = ((value) * (4));
252b5132
RH		 838 fields->f_disp10 = value;
839 }
840 break;
841 case FR30_OPERAND_DISP8 :
842 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
843 break;
844 case FR30_OPERAND_DISP9 :
845 {
846 long value;
847 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
202e762b 848 value = ((value) * (2));
252b5132
RH		 849 fields->f_disp9 = value;
850 }
851 break;
852 case FR30_OPERAND_I20 :
853 {
854 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
6bb95a0f 855 if (length <= 0) break;
252b5132 856 length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16);
6bb95a0f 857 if (length <= 0) break;
252b5132
RH		 858{
859 FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16)));
860}
861 }
862 break;
863 case FR30_OPERAND_I32 :
864 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 16, 0, 32, 32, total_length, pc, & fields->f_i32);
865 break;
866 case FR30_OPERAND_I8 :
867 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 16, total_length, pc, & fields->f_i8);
868 break;
869 case FR30_OPERAND_LABEL12 :
870 {
871 long value;
872 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value);
202e762b 873 value = ((((value) * (2))) + (((pc) + (2))));
252b5132
RH		 874 fields->f_rel12 = value;
875 }
876 break;
877 case FR30_OPERAND_LABEL9 :
878 {
879 long value;
880 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value);
202e762b 881 value = ((((value) * (2))) + (((pc) + (2))));
252b5132
RH		 882 fields->f_rel9 = value;
883 }
884 break;
885 case FR30_OPERAND_M4 :
886 {
887 long value;
888 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
62de1c63 889 value = ((value) | (-16));
252b5132
RH		 890 fields->f_m4 = value;
891 }
892 break;
893 case FR30_OPERAND_PS :
252b5132
RH		 894 break;
895 case FR30_OPERAND_REGLIST_HI_LD :
896 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld);
897 break;
898 case FR30_OPERAND_REGLIST_HI_ST :
899 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st);
900 break;
901 case FR30_OPERAND_REGLIST_LOW_LD :
902 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld);
903 break;
904 case FR30_OPERAND_REGLIST_LOW_ST :
905 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st);
906 break;
907 case FR30_OPERAND_S10 :
908 {
909 long value;
910 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
202e762b 911 value = ((value) * (4));
252b5132
RH		 912 fields->f_s10 = value;
913 }
914 break;
915 case FR30_OPERAND_U10 :
916 {
917 long value;
918 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & value);
919 value = ((value) << (2));
920 fields->f_u10 = value;
921 }
922 break;
923 case FR30_OPERAND_U4 :
924 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_u4);
925 break;
926 case FR30_OPERAND_U4C :
927 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_u4c);
928 break;
929 case FR30_OPERAND_U8 :
930 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_u8);
931 break;
932 case FR30_OPERAND_UDISP6 :
933 {
934 long value;
935 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
936 value = ((value) << (2));
937 fields->f_udisp6 = value;
938 }
939 break;
940
941 default :
942 /* xgettext:c-format */
a6743a54
AM		 943 opcodes_error_handler
944 (_("internal error: unrecognized field %d while decoding insn"),
945 opindex);
252b5132
RH		 946 abort ();
947 }
948
949 return length;
950}
951
43e65147 952cgen_insert_fn * const fr30_cgen_insert_handlers[] =
252b5132
RH		 953{
954 insert_insn_normal,
955};
956
43e65147 957cgen_extract_fn * const fr30_cgen_extract_handlers[] =
252b5132
RH		 958{
959 extract_insn_normal,
960};
961
47b0e7ad
NC		 962int fr30_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
963bfd_vma fr30_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
0e2ee3ca 964
252b5132
RH		 965/* Getting values from cgen_fields is handled by a collection of functions.
966 They are distinguished by the type of the VALUE argument they return.
967 TODO: floating point, inlining support, remove cases where result type
968 not appropriate. */
969
970int
47b0e7ad
NC		 971fr30_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
972 int opindex,
973 const CGEN_FIELDS * fields)
252b5132
RH		 974{
975 int value;
976
977 switch (opindex)
978 {
979 case FR30_OPERAND_CRI :
980 value = fields->f_CRi;
981 break;
982 case FR30_OPERAND_CRJ :
983 value = fields->f_CRj;
984 break;
985 case FR30_OPERAND_R13 :
eb1b03df 986 value = 0;
252b5132
RH		 987 break;
988 case FR30_OPERAND_R14 :
eb1b03df 989 value = 0;
252b5132
RH		 990 break;
991 case FR30_OPERAND_R15 :
eb1b03df 992 value = 0;
252b5132
RH		 993 break;
994 case FR30_OPERAND_RI :
995 value = fields->f_Ri;
996 break;
997 case FR30_OPERAND_RIC :
998 value = fields->f_Ric;
999 break;
1000 case FR30_OPERAND_RJ :
1001 value = fields->f_Rj;
1002 break;
1003 case FR30_OPERAND_RJC :
1004 value = fields->f_Rjc;
1005 break;
1006 case FR30_OPERAND_RS1 :
1007 value = fields->f_Rs1;
1008 break;
1009 case FR30_OPERAND_RS2 :
1010 value = fields->f_Rs2;
1011 break;
1012 case FR30_OPERAND_CC :
1013 value = fields->f_cc;
1014 break;
1015 case FR30_OPERAND_CCC :
1016 value = fields->f_ccc;
1017 break;
1018 case FR30_OPERAND_DIR10 :
1019 value = fields->f_dir10;
1020 break;
1021 case FR30_OPERAND_DIR8 :
1022 value = fields->f_dir8;
1023 break;
1024 case FR30_OPERAND_DIR9 :
1025 value = fields->f_dir9;
1026 break;
1027 case FR30_OPERAND_DISP10 :
1028 value = fields->f_disp10;
1029 break;
1030 case FR30_OPERAND_DISP8 :
1031 value = fields->f_disp8;
1032 break;
1033 case FR30_OPERAND_DISP9 :
1034 value = fields->f_disp9;
1035 break;
1036 case FR30_OPERAND_I20 :
1037 value = fields->f_i20;
1038 break;
1039 case FR30_OPERAND_I32 :
1040 value = fields->f_i32;
1041 break;
1042 case FR30_OPERAND_I8 :
1043 value = fields->f_i8;
1044 break;
1045 case FR30_OPERAND_LABEL12 :
1046 value = fields->f_rel12;
1047 break;
1048 case FR30_OPERAND_LABEL9 :
1049 value = fields->f_rel9;
1050 break;
1051 case FR30_OPERAND_M4 :
1052 value = fields->f_m4;
1053 break;
1054 case FR30_OPERAND_PS :
eb1b03df 1055 value = 0;
252b5132
RH		 1056 break;
1057 case FR30_OPERAND_REGLIST_HI_LD :
1058 value = fields->f_reglist_hi_ld;
1059 break;
1060 case FR30_OPERAND_REGLIST_HI_ST :
1061 value = fields->f_reglist_hi_st;
1062 break;
1063 case FR30_OPERAND_REGLIST_LOW_LD :
1064 value = fields->f_reglist_low_ld;
1065 break;
1066 case FR30_OPERAND_REGLIST_LOW_ST :
1067 value = fields->f_reglist_low_st;
1068 break;
1069 case FR30_OPERAND_S10 :
1070 value = fields->f_s10;
1071 break;
1072 case FR30_OPERAND_U10 :
1073 value = fields->f_u10;
1074 break;
1075 case FR30_OPERAND_U4 :
1076 value = fields->f_u4;
1077 break;
1078 case FR30_OPERAND_U4C :
1079 value = fields->f_u4c;
1080 break;
1081 case FR30_OPERAND_U8 :
1082 value = fields->f_u8;
1083 break;
1084 case FR30_OPERAND_UDISP6 :
1085 value = fields->f_udisp6;
1086 break;
1087
1088 default :
1089 /* xgettext:c-format */
a6743a54
AM		 1090 opcodes_error_handler
1091 (_("internal error: unrecognized field %d while getting int operand"),
1092 opindex);
252b5132
RH		 1093 abort ();
1094 }
1095
1096 return value;
1097}
1098
1099bfd_vma
47b0e7ad
NC		 1100fr30_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1101 int opindex,
1102 const CGEN_FIELDS * fields)
252b5132
RH		 1103{
1104 bfd_vma value;
1105
1106 switch (opindex)
1107 {
1108 case FR30_OPERAND_CRI :
1109 value = fields->f_CRi;
1110 break;
1111 case FR30_OPERAND_CRJ :
1112 value = fields->f_CRj;
1113 break;
1114 case FR30_OPERAND_R13 :
eb1b03df 1115 value = 0;
252b5132
RH		 1116 break;
1117 case FR30_OPERAND_R14 :
eb1b03df 1118 value = 0;
252b5132
RH		 1119 break;
1120 case FR30_OPERAND_R15 :
eb1b03df 1121 value = 0;
252b5132
RH		 1122 break;
1123 case FR30_OPERAND_RI :
1124 value = fields->f_Ri;
1125 break;
1126 case FR30_OPERAND_RIC :
1127 value = fields->f_Ric;
1128 break;
1129 case FR30_OPERAND_RJ :
1130 value = fields->f_Rj;
1131 break;
1132 case FR30_OPERAND_RJC :
1133 value = fields->f_Rjc;
1134 break;
1135 case FR30_OPERAND_RS1 :
1136 value = fields->f_Rs1;
1137 break;
1138 case FR30_OPERAND_RS2 :
1139 value = fields->f_Rs2;
1140 break;
1141 case FR30_OPERAND_CC :
1142 value = fields->f_cc;
1143 break;
1144 case FR30_OPERAND_CCC :
1145 value = fields->f_ccc;
1146 break;
1147 case FR30_OPERAND_DIR10 :
1148 value = fields->f_dir10;
1149 break;
1150 case FR30_OPERAND_DIR8 :
1151 value = fields->f_dir8;
1152 break;
1153 case FR30_OPERAND_DIR9 :
1154 value = fields->f_dir9;
1155 break;
1156 case FR30_OPERAND_DISP10 :
1157 value = fields->f_disp10;
1158 break;
1159 case FR30_OPERAND_DISP8 :
1160 value = fields->f_disp8;
1161 break;
1162 case FR30_OPERAND_DISP9 :
1163 value = fields->f_disp9;
1164 break;
1165 case FR30_OPERAND_I20 :
1166 value = fields->f_i20;
1167 break;
1168 case FR30_OPERAND_I32 :
1169 value = fields->f_i32;
1170 break;
1171 case FR30_OPERAND_I8 :
1172 value = fields->f_i8;
1173 break;
1174 case FR30_OPERAND_LABEL12 :
1175 value = fields->f_rel12;
1176 break;
1177 case FR30_OPERAND_LABEL9 :
1178 value = fields->f_rel9;
1179 break;
1180 case FR30_OPERAND_M4 :
1181 value = fields->f_m4;
1182 break;
1183 case FR30_OPERAND_PS :
eb1b03df 1184 value = 0;
252b5132
RH		 1185 break;
1186 case FR30_OPERAND_REGLIST_HI_LD :
1187 value = fields->f_reglist_hi_ld;
1188 break;
1189 case FR30_OPERAND_REGLIST_HI_ST :
1190 value = fields->f_reglist_hi_st;
1191 break;
1192 case FR30_OPERAND_REGLIST_LOW_LD :
1193 value = fields->f_reglist_low_ld;
1194 break;
1195 case FR30_OPERAND_REGLIST_LOW_ST :
1196 value = fields->f_reglist_low_st;
1197 break;
1198 case FR30_OPERAND_S10 :
1199 value = fields->f_s10;
1200 break;
1201 case FR30_OPERAND_U10 :
1202 value = fields->f_u10;
1203 break;
1204 case FR30_OPERAND_U4 :
1205 value = fields->f_u4;
1206 break;
1207 case FR30_OPERAND_U4C :
1208 value = fields->f_u4c;
1209 break;
1210 case FR30_OPERAND_U8 :
1211 value = fields->f_u8;
1212 break;
1213 case FR30_OPERAND_UDISP6 :
1214 value = fields->f_udisp6;
1215 break;
1216
1217 default :
1218 /* xgettext:c-format */
a6743a54
AM		 1219 opcodes_error_handler
1220 (_("internal error: unrecognized field %d while getting vma operand"),
1221 opindex);
252b5132
RH		 1222 abort ();
1223 }
1224
1225 return value;
1226}
1227
47b0e7ad
NC		 1228void fr30_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1229void fr30_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
0e2ee3ca 1230
252b5132
RH		 1231/* Stuffing values in cgen_fields is handled by a collection of functions.
1232 They are distinguished by the type of the VALUE argument they accept.
1233 TODO: floating point, inlining support, remove cases where argument type
1234 not appropriate. */
1235
1236void
47b0e7ad
NC		 1237fr30_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1238 int opindex,
1239 CGEN_FIELDS * fields,
1240 int value)
252b5132
RH		 1241{
1242 switch (opindex)
1243 {
1244 case FR30_OPERAND_CRI :
1245 fields->f_CRi = value;
1246 break;
1247 case FR30_OPERAND_CRJ :
1248 fields->f_CRj = value;
1249 break;
1250 case FR30_OPERAND_R13 :
252b5132
RH		 1251 break;
1252 case FR30_OPERAND_R14 :
252b5132
RH		 1253 break;
1254 case FR30_OPERAND_R15 :
252b5132
RH		 1255 break;
1256 case FR30_OPERAND_RI :
1257 fields->f_Ri = value;
1258 break;
1259 case FR30_OPERAND_RIC :
1260 fields->f_Ric = value;
1261 break;
1262 case FR30_OPERAND_RJ :
1263 fields->f_Rj = value;
1264 break;
1265 case FR30_OPERAND_RJC :
1266 fields->f_Rjc = value;
1267 break;
1268 case FR30_OPERAND_RS1 :
1269 fields->f_Rs1 = value;
1270 break;
1271 case FR30_OPERAND_RS2 :
1272 fields->f_Rs2 = value;
1273 break;
1274 case FR30_OPERAND_CC :
1275 fields->f_cc = value;
1276 break;
1277 case FR30_OPERAND_CCC :
1278 fields->f_ccc = value;
1279 break;
1280 case FR30_OPERAND_DIR10 :
1281 fields->f_dir10 = value;
1282 break;
1283 case FR30_OPERAND_DIR8 :
1284 fields->f_dir8 = value;
1285 break;
1286 case FR30_OPERAND_DIR9 :
1287 fields->f_dir9 = value;
1288 break;
1289 case FR30_OPERAND_DISP10 :
1290 fields->f_disp10 = value;
1291 break;
1292 case FR30_OPERAND_DISP8 :
1293 fields->f_disp8 = value;
1294 break;
1295 case FR30_OPERAND_DISP9 :
1296 fields->f_disp9 = value;
1297 break;
1298 case FR30_OPERAND_I20 :
1299 fields->f_i20 = value;
1300 break;
1301 case FR30_OPERAND_I32 :
1302 fields->f_i32 = value;
1303 break;
1304 case FR30_OPERAND_I8 :
1305 fields->f_i8 = value;
1306 break;
1307 case FR30_OPERAND_LABEL12 :
1308 fields->f_rel12 = value;
1309 break;
1310 case FR30_OPERAND_LABEL9 :
1311 fields->f_rel9 = value;
1312 break;
1313 case FR30_OPERAND_M4 :
1314 fields->f_m4 = value;
1315 break;
1316 case FR30_OPERAND_PS :
252b5132
RH		 1317 break;
1318 case FR30_OPERAND_REGLIST_HI_LD :
1319 fields->f_reglist_hi_ld = value;
1320 break;
1321 case FR30_OPERAND_REGLIST_HI_ST :
1322 fields->f_reglist_hi_st = value;
1323 break;
1324 case FR30_OPERAND_REGLIST_LOW_LD :
1325 fields->f_reglist_low_ld = value;
1326 break;
1327 case FR30_OPERAND_REGLIST_LOW_ST :
1328 fields->f_reglist_low_st = value;
1329 break;
1330 case FR30_OPERAND_S10 :
1331 fields->f_s10 = value;
1332 break;
1333 case FR30_OPERAND_U10 :
1334 fields->f_u10 = value;
1335 break;
1336 case FR30_OPERAND_U4 :
1337 fields->f_u4 = value;
1338 break;
1339 case FR30_OPERAND_U4C :
1340 fields->f_u4c = value;
1341 break;
1342 case FR30_OPERAND_U8 :
1343 fields->f_u8 = value;
1344 break;
1345 case FR30_OPERAND_UDISP6 :
1346 fields->f_udisp6 = value;
1347 break;
1348
1349 default :
1350 /* xgettext:c-format */
a6743a54
AM		 1351 opcodes_error_handler
1352 (_("internal error: unrecognized field %d while setting int operand"),
1353 opindex);
252b5132
RH		 1354 abort ();
1355 }
1356}
1357
1358void
47b0e7ad
NC		 1359fr30_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1360 int opindex,
1361 CGEN_FIELDS * fields,
1362 bfd_vma value)
252b5132
RH		 1363{
1364 switch (opindex)
1365 {
1366 case FR30_OPERAND_CRI :
1367 fields->f_CRi = value;
1368 break;
1369 case FR30_OPERAND_CRJ :
1370 fields->f_CRj = value;
1371 break;
1372 case FR30_OPERAND_R13 :
252b5132
RH		 1373 break;
1374 case FR30_OPERAND_R14 :
252b5132
RH		 1375 break;
1376 case FR30_OPERAND_R15 :
252b5132
RH		 1377 break;
1378 case FR30_OPERAND_RI :
1379 fields->f_Ri = value;
1380 break;
1381 case FR30_OPERAND_RIC :
1382 fields->f_Ric = value;
1383 break;
1384 case FR30_OPERAND_RJ :
1385 fields->f_Rj = value;
1386 break;
1387 case FR30_OPERAND_RJC :
1388 fields->f_Rjc = value;
1389 break;
1390 case FR30_OPERAND_RS1 :
1391 fields->f_Rs1 = value;
1392 break;
1393 case FR30_OPERAND_RS2 :
1394 fields->f_Rs2 = value;
1395 break;
1396 case FR30_OPERAND_CC :
1397 fields->f_cc = value;
1398 break;
1399 case FR30_OPERAND_CCC :
1400 fields->f_ccc = value;
1401 break;
1402 case FR30_OPERAND_DIR10 :
1403 fields->f_dir10 = value;
1404 break;
1405 case FR30_OPERAND_DIR8 :
1406 fields->f_dir8 = value;
1407 break;
1408 case FR30_OPERAND_DIR9 :
1409 fields->f_dir9 = value;
1410 break;
1411 case FR30_OPERAND_DISP10 :
1412 fields->f_disp10 = value;
1413 break;
1414 case FR30_OPERAND_DISP8 :
1415 fields->f_disp8 = value;
1416 break;
1417 case FR30_OPERAND_DISP9 :
1418 fields->f_disp9 = value;
1419 break;
1420 case FR30_OPERAND_I20 :
1421 fields->f_i20 = value;
1422 break;
1423 case FR30_OPERAND_I32 :
1424 fields->f_i32 = value;
1425 break;
1426 case FR30_OPERAND_I8 :
1427 fields->f_i8 = value;
1428 break;
1429 case FR30_OPERAND_LABEL12 :
1430 fields->f_rel12 = value;
1431 break;
1432 case FR30_OPERAND_LABEL9 :
1433 fields->f_rel9 = value;
1434 break;
1435 case FR30_OPERAND_M4 :
1436 fields->f_m4 = value;
1437 break;
1438 case FR30_OPERAND_PS :
252b5132
RH		 1439 break;
1440 case FR30_OPERAND_REGLIST_HI_LD :
1441 fields->f_reglist_hi_ld = value;
1442 break;
1443 case FR30_OPERAND_REGLIST_HI_ST :
1444 fields->f_reglist_hi_st = value;
1445 break;
1446 case FR30_OPERAND_REGLIST_LOW_LD :
1447 fields->f_reglist_low_ld = value;
1448 break;
1449 case FR30_OPERAND_REGLIST_LOW_ST :
1450 fields->f_reglist_low_st = value;
1451 break;
1452 case FR30_OPERAND_S10 :
1453 fields->f_s10 = value;
1454 break;
1455 case FR30_OPERAND_U10 :
1456 fields->f_u10 = value;
1457 break;
1458 case FR30_OPERAND_U4 :
1459 fields->f_u4 = value;
1460 break;
1461 case FR30_OPERAND_U4C :
1462 fields->f_u4c = value;
1463 break;
1464 case FR30_OPERAND_U8 :
1465 fields->f_u8 = value;
1466 break;
1467 case FR30_OPERAND_UDISP6 :
1468 fields->f_udisp6 = value;
1469 break;
1470
1471 default :
1472 /* xgettext:c-format */
a6743a54
AM		 1473 opcodes_error_handler
1474 (_("internal error: unrecognized field %d while setting vma operand"),
1475 opindex);
252b5132
RH		 1476 abort ();
1477 }
1478}
1479
1480/* Function to call before using the instruction builder tables. */
1481
1482void
47b0e7ad 1483fr30_cgen_init_ibld_table (CGEN_CPU_DESC cd)
252b5132
RH		 1484{
1485 cd->insert_handlers = & fr30_cgen_insert_handlers[0];
1486 cd->extract_handlers = & fr30_cgen_extract_handlers[0];
1487
1488 cd->insert_operand = fr30_cgen_insert_operand;
1489 cd->extract_operand = fr30_cgen_extract_operand;
1490
1491 cd->get_int_operand = fr30_cgen_get_int_operand;
1492 cd->set_int_operand = fr30_cgen_set_int_operand;
1493 cd->get_vma_operand = fr30_cgen_get_vma_operand;
1494 cd->set_vma_operand = fr30_cgen_set_vma_operand;
1495}
A mirror of the official binutils-gdb repository