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40b8e679 | 1 | // i386 opcode table. |
a2c58332 | 2 | // Copyright (C) 2007-2022 Free Software Foundation, Inc. |
9b201bb5 NC |
3 | // |
4 | // This file is part of the GNU opcodes library. | |
5 | // | |
6 | // This library is free software; you can redistribute it and/or modify | |
7 | // it under the terms of the GNU General Public License as published by | |
8 | // the Free Software Foundation; either version 3, or (at your option) | |
9 | // any later version. | |
10 | // | |
11 | // It is distributed in the hope that it will be useful, but WITHOUT | |
12 | // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | // License for more details. | |
15 | // | |
16 | // You should have received a copy of the GNU General Public License | |
17 | // along with GAS; see the file COPYING. If not, write to the Free | |
18 | // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | // 02110-1301, USA. | |
40b8e679 | 20 | |
c30be56e JB |
21 | #define OPCODE_I386_H |
22 | #include "i386-opc.h" | |
23 | #undef None | |
24 | ||
33b6a20a JB |
25 | // When necessary lines can be split in a non-standard way, by placing a |
26 | // trailing + on a to-be-continued line. This is intended mainly for non-insn | |
27 | // templates. Insn templates are better kept all on one line to make grep and | |
28 | // alike produce useful results. | |
29 | ||
4b5aaf5f L |
30 | #define Amd64 ISA64=AMD64 |
31 | #define Intel64 ISA64=INTEL64 | |
32 | #define Intel64Only ISA64=INTEL64ONLY | |
33 | ||
bab6aec1 JB |
34 | #define Reg8 Class=Reg|Byte |
35 | #define Reg16 Class=Reg|Word | |
36 | #define Reg32 Class=Reg|Dword | |
37 | #define Reg64 Class=Reg|Qword | |
3cc17af5 | 38 | |
474da251 JB |
39 | #define Acc Instance=Accum |
40 | #define RegC Instance=RegC | |
41 | #define RegD Instance=RegD | |
42 | #define RegB Instance=RegB | |
43 | ||
44 | #define ShiftCount RegC|Byte | |
45 | #define InOutPortReg RegD|Word | |
75e5731b | 46 | |
3cc17af5 | 47 | #define FloatAcc Acc|Tbyte |
bab6aec1 | 48 | #define FloatReg Class=Reg|Tbyte |
3cc17af5 | 49 | |
00cee14f JB |
50 | #define SReg Class=SReg |
51 | ||
4a5c67ed JB |
52 | #define Control Class=RegCR |
53 | #define Debug Class=RegDR | |
54 | #define Test Class=RegTR | |
55 | ||
3528c362 JB |
56 | #define RegMMX Class=RegMMX |
57 | #define RegXMM Class=RegSIMD|Xmmword | |
58 | #define RegYMM Class=RegSIMD|Ymmword | |
59 | #define RegZMM Class=RegSIMD|Zmmword | |
260cd341 | 60 | #define RegTMM Class=RegSIMD|Tmmword |
3cc17af5 | 61 | |
f74a6307 JB |
62 | #define RegMask Class=RegMask |
63 | ||
64 | #define RegBND Class=RegBND | |
65 | ||
b818b220 JB |
66 | #define Mmword Qword |
67 | #define Oword Xmmword | |
68 | ||
0cfa3eb3 JB |
69 | #define JumpByte Jump=JUMP_BYTE |
70 | #define JumpDword Jump=JUMP_DWORD | |
71 | #define JumpAbsolute Jump=JUMP_ABSOLUTE | |
72 | #define JumpInterSegment Jump=JUMP_INTERSEGMENT | |
73 | ||
673fe0f0 JB |
74 | #define Size16 Size=SIZE16 |
75 | #define Size32 Size=SIZE32 | |
76 | #define Size64 Size=SIZE64 | |
77 | ||
2368c6bf L |
78 | #define NoSuf No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf |
79 | ||
80 | #define AddrPrefixOpReg OperandConstraint=ADDR_PREFIX_OP_REG | |
255571cd JB |
81 | #define Anysize OperandConstraint=ANY_SIZE |
82 | #define DistinctDest OperandConstraint=DISTINCT_DEST | |
83 | #define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 | |
84 | #define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP | |
85 | #define NoDefMask OperandConstraint=NO_DEFAULT_MASK | |
86 | #define RegKludge OperandConstraint=REG_KLUDGE | |
87 | #define SwapSources OperandConstraint=SWAP_SOURCES | |
88 | #define Ugh OperandConstraint=UGH | |
89 | ||
3cd7f3e3 L |
90 | #define IgnoreSize MnemonicSize=IGNORESIZE |
91 | #define DefaultSize MnemonicSize=DEFAULTSIZE | |
92 | ||
dfd69174 JB |
93 | // RegMem implies a ModR/M byte |
94 | #define RegMem Modrm|RegMem | |
95 | ||
51c8edf6 JB |
96 | #define IsStringEsOp0 IsString=IS_STRING_ES_OP0 |
97 | #define IsStringEsOp1 IsString=IS_STRING_ES_OP1 | |
98 | ||
742732c7 JB |
99 | #define RepPrefixOk PrefixOk=PrefixRep |
100 | #define LockPrefixOk PrefixOk=PrefixLock | |
101 | #define HLEPrefixAny PrefixOk=PrefixHLEAny | |
102 | #define HLEPrefixLock PrefixOk=PrefixHLELock | |
103 | #define HLEPrefixRelease PrefixOk=PrefixHLERelease | |
104 | #define NoTrackPrefixOk PrefixOk=PrefixNoTrack | |
105 | ||
441f6aca JB |
106 | #define Space0F OpcodeSpace=SPACE_0F |
107 | #define Space0F38 OpcodeSpace=SPACE_0F38 | |
108 | #define Space0F3A OpcodeSpace=SPACE_0F3A | |
109 | #define SpaceXOP08 OpcodeSpace=SPACE_XOP08 | |
110 | #define SpaceXOP09 OpcodeSpace=SPACE_XOP09 | |
111 | #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A | |
112 | ||
0cc78721 CL |
113 | #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 |
114 | #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 | |
115 | ||
bbae6b11 JB |
116 | #define VexW0 VexW=VEXW0 |
117 | #define VexW1 VexW=VEXW1 | |
6fa52824 L |
118 | #define VexWIG VexW=VEXWIG |
119 | ||
fd71a375 JB |
120 | #define Vex128 Vex=VEX128 |
121 | #define Vex256 Vex=VEX256 | |
122 | #define VexLIG Vex=VEXScalar | |
e978ad62 | 123 | |
79b32e73 | 124 | #define VecSIB128 SIB=VECSIB128 |
63112cd6 L |
125 | #define VecSIB256 SIB=VECSIB256 |
126 | #define VecSIB512 SIB=VECSIB512 | |
260cd341 | 127 | #define Sibmem SIB=SIBMEM|Modrm |
fd71a375 JB |
128 | |
129 | #define EVex128 EVex=EVEX128 | |
130 | #define EVex256 EVex=EVEX256 | |
131 | #define EVex512 EVex=EVEX512 | |
132 | #define EVexLIG EVex=EVEXLIG | |
133 | #define EVexDYN EVex=EVEXDYN | |
134 | ||
79dec6b7 JB |
135 | // The EVEX purpose of StaticRounding appears only together with SAE. Re-use |
136 | // the bit to mark commutative VEX encodings where swapping the source | |
137 | // operands may allow to switch from 3-byte to 2-byte VEX encoding. | |
138 | #define C StaticRounding | |
139 | ||
b818b220 JB |
140 | #define CpuFP Cpu387|Cpu287|Cpu8087 |
141 | ||
bbae6b11 JB |
142 | ### MARKER ### |
143 | ||
40b8e679 | 144 | // Move instructions. |
8ee52bcf JB |
145 | mov, 0xa0, None, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword } |
146 | mov, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } | |
147 | movabs, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword } | |
2368c6bf | 148 | movq, 0xa1, None, Cpu64, D|Size64|NoSuf, { Disp64|Unspecified|Qword, Acc|Qword } |
9a182d04 | 149 | mov, 0x88, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } |
2368c6bf | 150 | movq, 0x89, None, Cpu64, D|Modrm|Size64|NoSuf|HLEPrefixRelease, { Reg64, Reg64|Unspecified|Qword|BaseIndex } |
40b8e679 L |
151 | // In the 64bit mode the short form mov immediate is redefined to have |
152 | // 64bit value. | |
9a182d04 JB |
153 | mov, 0xb0, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } |
154 | mov, 0xc6, 0, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
2368c6bf | 155 | movq, 0xc7, 0, Cpu64, Modrm|Size64|NoSuf|HLEPrefixRelease|Optimize, { Imm32S, Reg64|Qword|Unspecified|BaseIndex } |
9a182d04 | 156 | mov, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Optimize, { Imm64, Reg64 } |
bbe1eca6 | 157 | movabs, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 } |
2368c6bf | 158 | movq, 0xb8, None, Cpu64, Size64|NoSuf|Optimize, { Imm64, Reg64 } |
40b8e679 L |
159 | // The segment register moves accept WordReg so that a segment register |
160 | // can be copied to a 32 bit register, and vice versa, without using a | |
161 | // size prefix. When moving to a 32 bit register, the upper 16 bits | |
162 | // are set to an implementation defined value (on the Pentium Pro, the | |
163 | // implementation defined value is zero). | |
9a182d04 JB |
164 | mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 } |
165 | mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex } | |
2368c6bf | 166 | movq, 0x8c, None, Cpu64, D|RegMem|NoSuf|NoRex64, { SReg, Reg64 } |
9a182d04 | 167 | mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg } |
40b8e679 L |
168 | // Move to/from control debug registers. In the 16 or 32bit modes |
169 | // they are 32bit. In the 64bit mode they are 64bit. | |
9a182d04 JB |
170 | mov, 0xf20, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Control, Reg32 } |
171 | mov, 0xf20, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Control, Reg64 } | |
2368c6bf | 172 | movq, 0xf20, None, Cpu64, D|RegMem|Size64|NoSuf|NoRex64, { Control, Reg64 } |
9a182d04 JB |
173 | mov, 0xf21, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Debug, Reg32 } |
174 | mov, 0xf21, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Debug, Reg64 } | |
2368c6bf | 175 | movq, 0xf21, None, Cpu64, D|RegMem|Size64|NoSuf|NoRex64, { Debug, Reg64 } |
9a182d04 | 176 | mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 } |
40b8e679 | 177 | |
f1f8f695 | 178 | // Move after swapping the bytes |
8ee52bcf | 179 | movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
f1f8f695 | 180 | |
40b8e679 L |
181 | // Move with sign extend. |
182 | // "movsbl" & "movsbw" must not be unified into "movsb" to avoid | |
183 | // conflict with the "movs" string move instruction. | |
2368c6bf L |
184 | movsbl, 0xfbe, None, Cpu386, Modrm|NoSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg32 } |
185 | movsbw, 0xfbe, None, Cpu386, Modrm|NoSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16 } | |
186 | movswl, 0xfbf, None, Cpu386, Modrm|NoSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32 } | |
187 | movsbq, 0xfbe, None, Cpu64, Modrm|NoSuf|Size64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 } | |
188 | movswq, 0xfbf, None, Cpu64, Modrm|NoSuf|Size64, { Reg16|Word|Unspecified|BaseIndex, Reg64 } | |
189 | movslq, 0x63, None, Cpu64, Modrm|NoSuf|Size64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 } | |
9a182d04 JB |
190 | movsx, 0xfbe, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
191 | movsx, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
2368c6bf L |
192 | movsxd, 0x63, None, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 } |
193 | movsxd, 0x63, None, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 } | |
194 | movsxd, 0x63, None, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 } | |
40b8e679 | 195 | |
c07315e0 | 196 | // Move with zero extend. |
9a182d04 JB |
197 | movzb, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
198 | movzw, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 } | |
6867aac0 L |
199 | // The 64-bit variant is not particularly useful since the zero extend |
200 | // 32->64 is implicit, but we can encode them. | |
9a182d04 | 201 | movzx, 0xfb6, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 L |
202 | |
203 | // Push instructions. | |
9a182d04 JB |
204 | push, 0x50, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } |
205 | push, 0xff, 6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } | |
206 | push, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S } | |
207 | push, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 } | |
208 | push, 0x6, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg } | |
40b8e679 | 209 | // In 64bit mode, the operand size is implicitly 64bit. |
9a182d04 JB |
210 | push, 0x50, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } |
211 | push, 0xff, 6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } | |
212 | push, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S } | |
213 | push, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S } | |
214 | push, 0xfa0, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg } | |
40b8e679 | 215 | |
9a182d04 | 216 | pusha, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {} |
40b8e679 L |
217 | |
218 | // Pop instructions. | |
9a182d04 JB |
219 | pop, 0x58, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } |
220 | pop, 0x8f, 0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } | |
221 | pop, 0x7, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg } | |
40b8e679 | 222 | // In 64bit mode, the operand size is implicitly 64bit. |
9a182d04 JB |
223 | pop, 0x58, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } |
224 | pop, 0x8f, 0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } | |
225 | pop, 0xfa1, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg } | |
40b8e679 | 226 | |
9a182d04 | 227 | popa, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {} |
40b8e679 L |
228 | |
229 | // Exchange instructions. | |
230 | // xchg commutes: we allow both operand orders. | |
231 | ||
232 | // In the 64bit code, xchg rax, rax is reused for new nop instruction. | |
9a182d04 JB |
233 | xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword } |
234 | xchg, 0x90, None, 0, CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 } | |
235 | xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
236 | xchg, 0x86, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } | |
40b8e679 L |
237 | |
238 | // In/out from ports. | |
9a182d04 JB |
239 | in, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Acc|Byte|Word|Dword } |
240 | in, 0xec, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg, Acc|Byte|Word|Dword } | |
241 | in, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } | |
242 | in, 0xec, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg } | |
243 | out, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, Imm8 } | |
244 | out, 0xee, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, InOutPortReg } | |
245 | out, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } | |
246 | out, 0xee, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg } | |
40b8e679 L |
247 | |
248 | // Load effective address. | |
fe134c65 | 249 | lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 L |
250 | |
251 | // Load segment registers from memory. | |
9a182d04 JB |
252 | lds, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } |
253 | les, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
254 | lfs, 0xfb4, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
255 | lfs, 0xfb4, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
256 | lgs, 0xfb5, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
257 | lgs, 0xfb5, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
258 | lss, 0xfb2, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 } | |
259 | lss, 0xfb2, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
40b8e679 L |
260 | |
261 | // Flags register instructions. | |
2368c6bf L |
262 | clc, 0xf8, None, 0, NoSuf, {} |
263 | cld, 0xfc, None, 0, NoSuf, {} | |
264 | cli, 0xfa, None, 0, NoSuf, {} | |
265 | clts, 0xf06, None, Cpu286, NoSuf, {} | |
266 | cmc, 0xf5, None, 0, NoSuf, {} | |
267 | lahf, 0x9f, None, 0, NoSuf, {} | |
268 | sahf, 0x9e, None, 0, NoSuf, {} | |
9a182d04 JB |
269 | pushf, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {} |
270 | pushf, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {} | |
271 | popf, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {} | |
272 | popf, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {} | |
2368c6bf L |
273 | stc, 0xf9, None, 0, NoSuf, {} |
274 | std, 0xfd, None, 0, NoSuf, {} | |
275 | sti, 0xfb, None, 0, NoSuf, {} | |
40b8e679 L |
276 | |
277 | // Arithmetic. | |
9a182d04 JB |
278 | add, 0x0, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } |
279 | add, 0x83, 0, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
280 | add, 0x4, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
281 | add, 0x80, 0, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
282 | ||
283 | inc, 0x40, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } | |
284 | inc, 0xfe, 0, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
285 | ||
286 | sub, 0x28, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
287 | sub, 0x83, 5, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
288 | sub, 0x2c, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
289 | sub, 0x80, 5, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
290 | ||
291 | dec, 0x48, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } | |
292 | dec, 0xfe, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
293 | ||
294 | sbb, 0x18, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
295 | sbb, 0x83, 3, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
296 | sbb, 0x1c, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
297 | sbb, 0x80, 3, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
298 | ||
299 | cmp, 0x38, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
300 | cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
301 | cmp, 0x3c, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
302 | cmp, 0x80, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
303 | ||
304 | test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex } | |
8ee52bcf | 305 | test, 0x84, None, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } |
9a182d04 JB |
306 | test, 0xa8, None, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } |
307 | test, 0xf6, 0, 0, W|Modrm|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
308 | ||
309 | and, 0x20, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
310 | and, 0x83, 4, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
311 | and, 0x24, None, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
312 | and, 0x80, 4, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
313 | ||
314 | or, 0x8, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
315 | or, 0x83, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
316 | or, 0xc, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
317 | or, 0x80, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
318 | ||
319 | xor, 0x30, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
320 | xor, 0x83, 6, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
321 | xor, 0x34, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
322 | xor, 0x80, 6, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
40b8e679 L |
323 | |
324 | // clr with 1 operand is really xor with 2 operands. | |
9a182d04 | 325 | clr, 0x30, None, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 } |
40b8e679 | 326 | |
9a182d04 JB |
327 | adc, 0x10, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } |
328 | adc, 0x83, 2, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
329 | adc, 0x14, None, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } | |
330 | adc, 0x80, 2, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
40b8e679 | 331 | |
9a182d04 JB |
332 | neg, 0xf6, 3, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } |
333 | not, 0xf6, 2, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
40b8e679 | 334 | |
2368c6bf L |
335 | aaa, 0x37, None, CpuNo64, NoSuf, {} |
336 | aas, 0x3f, None, CpuNo64, NoSuf, {} | |
337 | daa, 0x27, None, CpuNo64, NoSuf, {} | |
338 | das, 0x2f, None, CpuNo64, NoSuf, {} | |
339 | aad, 0xd50a, None, CpuNo64, NoSuf, {} | |
340 | aad, 0xd5, None, CpuNo64, NoSuf, { Imm8 } | |
341 | aam, 0xd40a, None, CpuNo64, NoSuf, {} | |
342 | aam, 0xd4, None, CpuNo64, NoSuf, { Imm8 } | |
40b8e679 L |
343 | |
344 | // Conversion insns. | |
345 | // Intel naming | |
2368c6bf L |
346 | cbw, 0x98, None, 0, Size16|NoSuf, {} |
347 | cwde, 0x98, None, Cpu386, Size32|NoSuf, {} | |
348 | cdqe, 0x98, None, Cpu64, Size64|NoSuf, {} | |
349 | cwd, 0x99, None, 0, Size16|NoSuf, {} | |
350 | cdq, 0x99, None, Cpu386, Size32|NoSuf, {} | |
351 | cqo, 0x99, None, Cpu64, Size64|NoSuf, {} | |
40b8e679 | 352 | // AT&T naming |
2368c6bf L |
353 | cbtw, 0x98, None, 0, Size16|NoSuf, {} |
354 | cwtl, 0x98, None, Cpu386, Size32|NoSuf, {} | |
355 | cltq, 0x98, None, Cpu64, Size64|NoSuf, {} | |
356 | cwtd, 0x99, None, 0, Size16|NoSuf, {} | |
357 | cltd, 0x99, None, Cpu386, Size32|NoSuf, {} | |
358 | cqto, 0x99, None, Cpu64, Size64|NoSuf, {} | |
40b8e679 L |
359 | |
360 | // Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are | |
361 | // expanding 64-bit multiplies, and *cannot* be selected to accomplish | |
362 | // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) | |
363 | // These multiplies can only be selected with single operand forms. | |
9a182d04 JB |
364 | mul, 0xf6, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } |
365 | imul, 0xf6, 5, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
366 | imul, 0xfaf, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 } | |
367 | imul, 0x6b, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
368 | imul, 0x69, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
40b8e679 L |
369 | // imul with 2 operands mimics imul with 3 by putting the register in |
370 | // both i.rm.reg & i.rm.regmem fields. RegKludge enables this | |
371 | // transformation. | |
9a182d04 JB |
372 | imul, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } |
373 | imul, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } | |
374 | ||
375 | div, 0xf6, 6, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
376 | div, 0xf6, 6, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
377 | idiv, 0xf6, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
378 | idiv, 0xf6, 7, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
379 | ||
380 | rol, 0xd0, 0, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
381 | rol, 0xc0, 0, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
382 | rol, 0xd2, 0, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
383 | rol, 0xd0, 0, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
384 | ||
385 | ror, 0xd0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
386 | ror, 0xc0, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
387 | ror, 0xd2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
388 | ror, 0xd0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
389 | ||
390 | rcl, 0xd0, 2, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
391 | rcl, 0xc0, 2, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
392 | rcl, 0xd2, 2, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
393 | rcl, 0xd0, 2, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
394 | ||
395 | rcr, 0xd0, 3, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
396 | rcr, 0xc0, 3, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
397 | rcr, 0xd2, 3, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
398 | rcr, 0xd0, 3, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
399 | ||
400 | sal, 0xd0, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
401 | sal, 0xc0, 4, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
402 | sal, 0xd2, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
403 | sal, 0xd0, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
404 | ||
405 | shl, 0xd0, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
406 | shl, 0xc0, 4, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
407 | shl, 0xd2, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
408 | shl, 0xd0, 4, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
409 | ||
410 | shr, 0xd0, 5, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
411 | shr, 0xc0, 5, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
412 | shr, 0xd2, 5, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
413 | shr, 0xd0, 5, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
414 | ||
415 | sar, 0xd0, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
416 | sar, 0xc0, 7, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
417 | sar, 0xd2, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
418 | sar, 0xd0, 7, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
419 | ||
420 | shld, 0xfa4, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
421 | shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
422 | shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
423 | ||
424 | shrd, 0xfac, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
425 | shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
426 | shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
40b8e679 L |
427 | |
428 | // Control transfer instructions. | |
9a182d04 | 429 | call, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 } |
a775efc8 JB |
430 | call, 0xe8, None, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 } |
431 | call, 0xe8, None, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32 } | |
9a182d04 JB |
432 | call, 0xff, 2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } |
433 | call, 0xff, 2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } | |
434 | call, 0xff, 2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } | |
5990e377 | 435 | // Intel Syntax remaining call instances. |
9a182d04 JB |
436 | call, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } |
437 | call, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex } | |
2368c6bf | 438 | call, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } |
9a182d04 JB |
439 | lcall, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } |
440 | lcall, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } | |
441 | lcall, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } | |
442 | ||
2368c6bf L |
443 | jmp, 0xeb, None, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } |
444 | jmp, 0xeb, None, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 } | |
9a182d04 JB |
445 | jmp, 0xff, 4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex } |
446 | jmp, 0xff, 4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex } | |
447 | jmp, 0xff, 4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex } | |
5990e377 | 448 | // Intel Syntax remaining jmp instances. |
9a182d04 JB |
449 | jmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } |
450 | jmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex } | |
2368c6bf | 451 | jmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex } |
9a182d04 JB |
452 | ljmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 } |
453 | ljmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } | |
454 | ljmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } | |
455 | ||
456 | ret, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, {} | |
457 | ret, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
458 | ret, 0xc3, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} | |
459 | ret, 0xc2, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
460 | ret, 0xc3, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {} | |
461 | ret, 0xc2, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 } | |
462 | lret, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {} | |
463 | lret, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 } | |
ddab3d59 | 464 | // Intel Syntax. |
9a182d04 JB |
465 | retf, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {} |
466 | retf, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 } | |
ddab3d59 | 467 | |
9a182d04 JB |
468 | enter, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 } |
469 | enter, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 } | |
470 | leave, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {} | |
471 | leave, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {} | |
40b8e679 | 472 | |
33b6a20a | 473 | <cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, + |
4c4898e8 JB |
474 | s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f> |
475 | ||
40b8e679 | 476 | // Conditional jumps. |
2368c6bf | 477 | j<cc>, 0x7<cc:opc>, None, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 } |
40b8e679 L |
478 | |
479 | // jcxz vs. jecxz is chosen on the basis of the address size prefix. | |
2368c6bf L |
480 | jcxz, 0xe3, None, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 } |
481 | jecxz, 0xe3, None, Cpu386, JumpByte|Size32|NoSuf, { Disp8 } | |
482 | jrcxz, 0xe3, None, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 } | |
40b8e679 L |
483 | |
484 | // The loop instructions also use the address size prefix to select | |
485 | // %cx rather than %ecx for the loop count, so the `w' form of these | |
486 | // instructions emit an address size prefix rather than a data size | |
487 | // prefix. | |
9a182d04 JB |
488 | loop, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 } |
489 | loop, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 } | |
490 | loopz, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 } | |
491 | loopz, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 } | |
492 | loope, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 } | |
493 | loope, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 } | |
494 | loopnz, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 } | |
495 | loopnz, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 } | |
496 | loopne, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 } | |
497 | loopne, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 } | |
40b8e679 L |
498 | |
499 | // Set byte on flag instructions. | |
9a182d04 | 500 | set<cc>, 0xf9<cc:opc>, 0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex } |
40b8e679 L |
501 | |
502 | // String manipulation. | |
9a182d04 JB |
503 | cmps, 0xa6, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} |
504 | cmps, 0xa6, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
bbe1eca6 | 505 | // Intel mode string compare. |
2368c6bf L |
506 | cmpsd, 0xa7, None, Cpu386, Size32|NoSuf|IsString|RepPrefixOk, {} |
507 | cmpsd, 0xa7, None, Cpu386, Size32|NoSuf|IsStringEsOp0|RepPrefixOk, { Dword|Unspecified|BaseIndex, Dword|Unspecified|BaseIndex } | |
9a182d04 JB |
508 | scmp, 0xa6, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} |
509 | scmp, 0xa6, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
510 | ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
511 | ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex } | |
512 | outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
513 | outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg } | |
514 | lods, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
515 | lods, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
516 | lods, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
517 | slod, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
518 | slod, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
519 | slod, 0xac, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
520 | movs, 0xa4, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
521 | movs, 0xa4, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
bbe1eca6 | 522 | // Intel mode string move. |
2368c6bf L |
523 | movsd, 0xa5, None, Cpu386, Size32|NoSuf|IsString|RepPrefixOk, {} |
524 | movsd, 0xa5, None, Cpu386, Size32|NoSuf|IsStringEsOp1|RepPrefixOk, { Dword|Unspecified|BaseIndex, Dword|Unspecified|BaseIndex } | |
9a182d04 JB |
525 | smov, 0xa4, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} |
526 | smov, 0xa4, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
527 | scas, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
528 | scas, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
529 | scas, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
530 | ssca, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
531 | ssca, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
532 | ssca, 0xae, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } | |
533 | stos, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
534 | stos, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
535 | stos, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
536 | ssto, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {} | |
537 | ssto, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
538 | ssto, 0xaa, None, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
539 | xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, {} | |
540 | xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex } | |
40b8e679 L |
541 | |
542 | // Bit manipulation. | |
9a182d04 JB |
543 | bsf, 0xfbc, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
544 | bsr, 0xfbd, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
545 | bt, 0xfa3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
546 | bt, 0xfba, 4, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
547 | btc, 0xfbb, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
548 | btc, 0xfba, 7, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
549 | btr, 0xfb3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
550 | btr, 0xfba, 6, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
551 | bts, 0xfab, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
552 | bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } | |
40b8e679 L |
553 | |
554 | // Interrupts & op. sys insns. | |
555 | // See gas/config/tc-i386.c for conversion of 'int $3' into the special | |
556 | // int 3 insn. | |
2368c6bf L |
557 | int, 0xcd, None, 0, NoSuf, { Imm8 } |
558 | int1, 0xf1, None, 0, NoSuf, {} | |
559 | int3, 0xcc, None, 0, NoSuf, {} | |
560 | into, 0xce, None, CpuNo64, NoSuf, {} | |
9a182d04 | 561 | iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {} |
40b8e679 | 562 | // i386sl, i486sl, later 486, and Pentium. |
2368c6bf | 563 | rsm, 0xfaa, None, Cpu386, NoSuf, {} |
40b8e679 | 564 | |
9a182d04 | 565 | bound, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex } |
40b8e679 | 566 | |
2368c6bf | 567 | hlt, 0xf4, None, 0, NoSuf, {} |
40b8e679 | 568 | |
9a182d04 | 569 | nop, 0xf1f, 0, CpuNop, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } |
40b8e679 L |
570 | |
571 | // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in | |
572 | // 32bit mode and "xchg %rax,%rax" in 64bit mode. | |
2368c6bf | 573 | nop, 0x90, None, 0, NoSuf|RepPrefixOk, {} |
40b8e679 L |
574 | |
575 | // Protection control. | |
9a182d04 | 576 | arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex } |
c9f5b96b JB |
577 | lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
578 | lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
9a182d04 JB |
579 | lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex } |
580 | lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } | |
581 | lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex } | |
582 | lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } | |
583 | lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex } | |
584 | lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex } | |
c9f5b96b JB |
585 | lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 } |
586 | lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
9a182d04 JB |
587 | ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex } |
588 | ||
589 | sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex } | |
590 | sgdt, 0xf01, 0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } | |
591 | sidt, 0xf01, 1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex } | |
592 | sidt, 0xf01, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex } | |
593 | sldt, 0xf00, 0, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 } | |
594 | sldt, 0xf00, 0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } | |
595 | smsw, 0xf01, 4, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 } | |
596 | smsw, 0xf01, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } | |
597 | str, 0xf00, 1, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 } | |
598 | str, 0xf00, 1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } | |
599 | ||
600 | verr, 0xf00, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex } | |
601 | verw, 0xf00, 5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex } | |
40b8e679 L |
602 | |
603 | // Floating point instructions. | |
604 | ||
605 | // load | |
2368c6bf | 606 | fld, 0xd9c0, None, CpuFP, NoSuf, { FloatReg } |
9a182d04 JB |
607 | fld, 0xd9, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
608 | fld, 0xd9c0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } | |
40b8e679 | 609 | // Intel Syntax |
9a182d04 JB |
610 | fld, 0xdb, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex } |
611 | fild, 0xdf, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
612 | fild, 0xdf, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
2368c6bf L |
613 | fildll, 0xdf, 5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } |
614 | fldt, 0xdb, 5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } | |
9a182d04 | 615 | fbld, 0xdf, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex } |
40b8e679 L |
616 | |
617 | // store (no pop) | |
2368c6bf | 618 | fst, 0xddd0, None, CpuFP, NoSuf, { FloatReg } |
9a182d04 JB |
619 | fst, 0xd9, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
620 | fst, 0xddd0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } | |
621 | fist, 0xdf, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 L |
622 | |
623 | // store (with pop) | |
2368c6bf | 624 | fstp, 0xddd8, None, CpuFP, NoSuf, { FloatReg } |
9a182d04 JB |
625 | fstp, 0xd9, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
626 | fstp, 0xddd8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } | |
40b8e679 | 627 | // Intel Syntax |
9a182d04 JB |
628 | fstp, 0xdb, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex } |
629 | fistp, 0xdf, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
630 | fistp, 0xdf, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
2368c6bf L |
631 | fistpll, 0xdf, 7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } |
632 | fstpt, 0xdb, 7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } | |
9a182d04 | 633 | fbstp, 0xdf, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex } |
40b8e679 L |
634 | |
635 | // exchange %st<n> with %st0 | |
2368c6bf | 636 | fxch, 0xd9c8, None, CpuFP, NoSuf, { FloatReg } |
40b8e679 | 637 | // alias for fxch %st(1) |
2368c6bf | 638 | fxch, 0xd9c9, None, CpuFP, NoSuf, {} |
40b8e679 L |
639 | |
640 | // comparison (without pop) | |
2368c6bf | 641 | fcom, 0xd8d0, None, CpuFP, NoSuf, { FloatReg } |
40b8e679 | 642 | // alias for fcom %st(1) |
2368c6bf | 643 | fcom, 0xd8d1, None, CpuFP, NoSuf, {} |
9a182d04 JB |
644 | fcom, 0xd8, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
645 | fcom, 0xd8d0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } | |
646 | ficom, 0xde, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 L |
647 | |
648 | // comparison (with pop) | |
2368c6bf | 649 | fcomp, 0xd8d8, None, CpuFP, NoSuf, { FloatReg } |
40b8e679 | 650 | // alias for fcomp %st(1) |
2368c6bf | 651 | fcomp, 0xd8d9, None, CpuFP, NoSuf, {} |
9a182d04 JB |
652 | fcomp, 0xd8, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
653 | fcomp, 0xd8d8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg } | |
654 | ficomp, 0xde, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
2368c6bf | 655 | fcompp, 0xded9, None, CpuFP, NoSuf, {} |
40b8e679 L |
656 | |
657 | // unordered comparison (with pop) | |
2368c6bf | 658 | fucom, 0xdde0, None, Cpu387, NoSuf, { FloatReg } |
40b8e679 | 659 | // alias for fucom %st(1) |
2368c6bf L |
660 | fucom, 0xdde1, None, Cpu387, NoSuf, {} |
661 | fucomp, 0xdde8, None, Cpu387, NoSuf, { FloatReg } | |
40b8e679 | 662 | // alias for fucomp %st(1) |
2368c6bf L |
663 | fucomp, 0xdde9, None, Cpu387, NoSuf, {} |
664 | fucompp, 0xdae9, None, Cpu387, NoSuf, {} | |
40b8e679 | 665 | |
2368c6bf L |
666 | ftst, 0xd9e4, None, CpuFP, NoSuf, {} |
667 | fxam, 0xd9e5, None, CpuFP, NoSuf, {} | |
40b8e679 L |
668 | |
669 | // load constants into %st0 | |
2368c6bf L |
670 | fld1, 0xd9e8, None, CpuFP, NoSuf, {} |
671 | fldl2t, 0xd9e9, None, CpuFP, NoSuf, {} | |
672 | fldl2e, 0xd9ea, None, CpuFP, NoSuf, {} | |
673 | fldpi, 0xd9eb, None, CpuFP, NoSuf, {} | |
674 | fldlg2, 0xd9ec, None, CpuFP, NoSuf, {} | |
675 | fldln2, 0xd9ed, None, CpuFP, NoSuf, {} | |
676 | fldz, 0xd9ee, None, CpuFP, NoSuf, {} | |
40b8e679 L |
677 | |
678 | // Arithmetic. | |
679 | ||
680 | // add | |
2368c6bf | 681 | fadd, 0xd8c0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 682 | // alias for fadd %st(i), %st |
2368c6bf | 683 | fadd, 0xd8c0, None, CpuFP, NoSuf, { FloatReg } |
40b8e679 | 684 | // alias for faddp |
2368c6bf | 685 | fadd, 0xdec1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} |
9a182d04 JB |
686 | fadd, 0xd8, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
687 | fiadd, 0xde, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 | 688 | |
2368c6bf L |
689 | faddp, 0xdec0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } |
690 | faddp, 0xdec0, None, CpuFP, NoSuf, { FloatReg } | |
40b8e679 | 691 | // alias for faddp %st, %st(1) |
2368c6bf L |
692 | faddp, 0xdec1, None, CpuFP, NoSuf, {} |
693 | faddp, 0xdec0, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } | |
40b8e679 L |
694 | |
695 | // subtract | |
2368c6bf | 696 | fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg } |
ac9226cf | 697 | fsub, 0xd8e0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 698 | // alias for fsubp |
2368c6bf L |
699 | fsub, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} |
700 | fsub, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} | |
9a182d04 JB |
701 | fsub, 0xd8, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
702 | fisub, 0xde, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
703 | ||
2368c6bf L |
704 | fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } |
705 | fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } | |
706 | fsubp, 0xdee1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} | |
707 | fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } | |
708 | fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatReg } | |
709 | fsubp, 0xdee9, None, CpuFP, NoSuf, {} | |
40b8e679 L |
710 | |
711 | // subtract reverse | |
2368c6bf | 712 | fsubr, 0xd8e8, None, CpuFP, NoSuf, { FloatReg } |
ac9226cf | 713 | fsubr, 0xd8e8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 714 | // alias for fsubrp |
2368c6bf L |
715 | fsubr, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} |
716 | fsubr, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} | |
9a182d04 JB |
717 | fsubr, 0xd8, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
718 | fisubr, 0xde, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
719 | ||
2368c6bf L |
720 | fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } |
721 | fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } | |
722 | fsubrp, 0xdee9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} | |
723 | fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } | |
724 | fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatReg } | |
725 | fsubrp, 0xdee1, None, CpuFP, NoSuf, {} | |
40b8e679 L |
726 | |
727 | // multiply | |
2368c6bf L |
728 | fmul, 0xd8c8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
729 | fmul, 0xd8c8, None, CpuFP, NoSuf, { FloatReg } | |
40b8e679 | 730 | // alias for fmulp |
2368c6bf | 731 | fmul, 0xdec9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} |
9a182d04 JB |
732 | fmul, 0xd8, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
733 | fimul, 0xde, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
40b8e679 | 734 | |
2368c6bf L |
735 | fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } |
736 | fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatReg } | |
737 | fmulp, 0xdec9, None, CpuFP, NoSuf, {} | |
738 | fmulp, 0xdec8, None, CpuFP, NoSuf|Ugh, { FloatReg, FloatAcc } | |
40b8e679 L |
739 | |
740 | // divide | |
2368c6bf | 741 | fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg } |
ac9226cf | 742 | fdiv, 0xd8f0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 743 | // alias for fdivp |
2368c6bf L |
744 | fdiv, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} |
745 | fdiv, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} | |
9a182d04 JB |
746 | fdiv, 0xd8, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
747 | fidiv, 0xde, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
748 | ||
2368c6bf L |
749 | fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } |
750 | fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } | |
751 | fdivp, 0xdef1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} | |
752 | fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatAcc, FloatReg } | |
753 | fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatReg } | |
754 | fdivp, 0xdef9, None, CpuFP, NoSuf, {} | |
40b8e679 L |
755 | |
756 | // divide reverse | |
2368c6bf | 757 | fdivr, 0xd8f8, None, CpuFP, NoSuf, { FloatReg } |
ac9226cf | 758 | fdivr, 0xd8f8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc } |
40b8e679 | 759 | // alias for fdivrp |
2368c6bf L |
760 | fdivr, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {} |
761 | fdivr, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {} | |
9a182d04 JB |
762 | fdivr, 0xd8, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex } |
763 | fidivr, 0xde, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
764 | ||
2368c6bf L |
765 | fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } |
766 | fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg } | |
767 | fdivrp, 0xdef9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {} | |
768 | fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatAcc, FloatReg } | |
769 | fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatReg } | |
770 | fdivrp, 0xdef1, None, CpuFP, NoSuf, {} | |
771 | ||
772 | f2xm1, 0xd9f0, None, CpuFP, NoSuf, {} | |
773 | fyl2x, 0xd9f1, None, CpuFP, NoSuf, {} | |
774 | fptan, 0xd9f2, None, CpuFP, NoSuf, {} | |
775 | fpatan, 0xd9f3, None, CpuFP, NoSuf, {} | |
776 | fxtract, 0xd9f4, None, CpuFP, NoSuf, {} | |
777 | fprem1, 0xd9f5, None, Cpu387, NoSuf, {} | |
778 | fdecstp, 0xd9f6, None, CpuFP, NoSuf, {} | |
779 | fincstp, 0xd9f7, None, CpuFP, NoSuf, {} | |
780 | fprem, 0xd9f8, None, CpuFP, NoSuf, {} | |
781 | fyl2xp1, 0xd9f9, None, CpuFP, NoSuf, {} | |
782 | fsqrt, 0xd9fa, None, CpuFP, NoSuf, {} | |
783 | fsincos, 0xd9fb, None, Cpu387, NoSuf, {} | |
784 | frndint, 0xd9fc, None, CpuFP, NoSuf, {} | |
785 | fscale, 0xd9fd, None, CpuFP, NoSuf, {} | |
786 | fsin, 0xd9fe, None, Cpu387, NoSuf, {} | |
787 | fcos, 0xd9ff, None, Cpu387, NoSuf, {} | |
788 | fchs, 0xd9e0, None, CpuFP, NoSuf, {} | |
789 | fabs, 0xd9e1, None, CpuFP, NoSuf, {} | |
40b8e679 L |
790 | |
791 | // processor control | |
2368c6bf L |
792 | fninit, 0xdbe3, None, CpuFP, NoSuf, {} |
793 | finit, 0xdbe3, None, CpuFP, NoSuf|FWait, {} | |
9a182d04 JB |
794 | fldcw, 0xd9, 5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } |
795 | fnstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } | |
796 | fstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Word|Unspecified|BaseIndex } | |
2368c6bf | 797 | fnstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word } |
9a182d04 | 798 | fnstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex } |
2368c6bf L |
799 | fnstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf, {} |
800 | fstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word } | |
9a182d04 | 801 | fstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Word|Unspecified|BaseIndex } |
2368c6bf L |
802 | fstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf|FWait, {} |
803 | fnclex, 0xdbe2, None, CpuFP, NoSuf, {} | |
804 | fclex, 0xdbe2, None, CpuFP, NoSuf|FWait, {} | |
62b3f548 | 805 | // Short forms of fldenv, fstenv, fsave, and frstor use data size prefix. |
9a182d04 JB |
806 | fnstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } |
807 | fstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex } | |
808 | fldenv, 0xd9, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } | |
809 | fnsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } | |
810 | fsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex } | |
811 | frstor, 0xdd, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex } | |
309d3373 | 812 | // 8087 only |
2368c6bf L |
813 | fneni, 0xdbe0, None, Cpu8087, NoSuf, {} |
814 | feni, 0xdbe0, None, Cpu8087, NoSuf|FWait, {} | |
815 | fndisi, 0xdbe1, None, Cpu8087, NoSuf, {} | |
816 | fdisi, 0xdbe1, None, Cpu8087, NoSuf|FWait, {} | |
309d3373 | 817 | // 287 only |
2368c6bf L |
818 | fnsetpm, 0xdbe4, None, Cpu287, NoSuf, {} |
819 | fsetpm, 0xdbe4, None, Cpu287, NoSuf|FWait, {} | |
820 | frstpm, 0xdbe5, None, Cpu287, NoSuf, {} | |
309d3373 | 821 | |
2368c6bf | 822 | ffree, 0xddc0, None, CpuFP, NoSuf, { FloatReg } |
40b8e679 | 823 | // P6:free st(i), pop st |
2368c6bf L |
824 | ffreep, 0xdfc0, None, Cpu687, NoSuf, { FloatReg } |
825 | fnop, 0xd9d0, None, CpuFP, NoSuf, {} | |
826 | fwait, 0x9b, None, CpuFP, NoSuf, {} | |
40b8e679 L |
827 | |
828 | // Opcode prefixes; we allow them as separate insns too. | |
829 | ||
2368c6bf L |
830 | addr16, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} |
831 | addr32, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} | |
832 | aword, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {} | |
833 | adword, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {} | |
834 | data16, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} | |
835 | data32, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} | |
836 | word, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {} | |
837 | dword, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {} | |
838 | lock, 0xf0, None, 0, NoSuf|IsPrefix, {} | |
839 | wait, 0x9b, None, 0, NoSuf|IsPrefix, {} | |
840 | cs, 0x2e, None, 0, NoSuf|IsPrefix, {} | |
841 | ds, 0x3e, None, 0, NoSuf|IsPrefix, {} | |
842 | es, 0x26, None, CpuNo64, NoSuf|IsPrefix, {} | |
843 | fs, 0x64, None, Cpu386, NoSuf|IsPrefix, {} | |
844 | gs, 0x65, None, Cpu386, NoSuf|IsPrefix, {} | |
845 | ss, 0x36, None, CpuNo64, NoSuf|IsPrefix, {} | |
846 | rep, 0xf3, None, 0, NoSuf|IsPrefix, {} | |
847 | repe, 0xf3, None, 0, NoSuf|IsPrefix, {} | |
848 | repz, 0xf3, None, 0, NoSuf|IsPrefix, {} | |
849 | repne, 0xf2, None, 0, NoSuf|IsPrefix, {} | |
850 | repnz, 0xf2, None, 0, NoSuf|IsPrefix, {} | |
851 | ht, 0x3e, None, 0, NoSuf|IsPrefix, {} | |
852 | hnt, 0x2e, None, 0, NoSuf|IsPrefix, {} | |
853 | rex, 0x40, None, Cpu64, NoSuf|IsPrefix, {} | |
854 | rexz, 0x41, None, Cpu64, NoSuf|IsPrefix, {} | |
855 | rexy, 0x42, None, Cpu64, NoSuf|IsPrefix, {} | |
856 | rexyz, 0x43, None, Cpu64, NoSuf|IsPrefix, {} | |
857 | rexx, 0x44, None, Cpu64, NoSuf|IsPrefix, {} | |
858 | rexxz, 0x45, None, Cpu64, NoSuf|IsPrefix, {} | |
859 | rexxy, 0x46, None, Cpu64, NoSuf|IsPrefix, {} | |
860 | rexxyz, 0x47, None, Cpu64, NoSuf|IsPrefix, {} | |
861 | rex64, 0x48, None, Cpu64, NoSuf|IsPrefix, {} | |
862 | rex64z, 0x49, None, Cpu64, NoSuf|IsPrefix, {} | |
863 | rex64y, 0x4a, None, Cpu64, NoSuf|IsPrefix, {} | |
864 | rex64yz, 0x4b, None, Cpu64, NoSuf|IsPrefix, {} | |
865 | rex64x, 0x4c, None, Cpu64, NoSuf|IsPrefix, {} | |
866 | rex64xz, 0x4d, None, Cpu64, NoSuf|IsPrefix, {} | |
867 | rex64xy, 0x4e, None, Cpu64, NoSuf|IsPrefix, {} | |
868 | rex64xyz, 0x4f, None, Cpu64, NoSuf|IsPrefix, {} | |
869 | rex.b, 0x41, None, Cpu64, NoSuf|IsPrefix, {} | |
870 | rex.x, 0x42, None, Cpu64, NoSuf|IsPrefix, {} | |
871 | rex.xb, 0x43, None, Cpu64, NoSuf|IsPrefix, {} | |
872 | rex.r, 0x44, None, Cpu64, NoSuf|IsPrefix, {} | |
873 | rex.rb, 0x45, None, Cpu64, NoSuf|IsPrefix, {} | |
874 | rex.rx, 0x46, None, Cpu64, NoSuf|IsPrefix, {} | |
875 | rex.rxb, 0x47, None, Cpu64, NoSuf|IsPrefix, {} | |
876 | rex.w, 0x48, None, Cpu64, NoSuf|IsPrefix, {} | |
877 | rex.wb, 0x49, None, Cpu64, NoSuf|IsPrefix, {} | |
878 | rex.wx, 0x4a, None, Cpu64, NoSuf|IsPrefix, {} | |
879 | rex.wxb, 0x4b, None, Cpu64, NoSuf|IsPrefix, {} | |
880 | rex.wr, 0x4c, None, Cpu64, NoSuf|IsPrefix, {} | |
881 | rex.wrb, 0x4d, None, Cpu64, NoSuf|IsPrefix, {} | |
882 | rex.wrx, 0x4e, None, Cpu64, NoSuf|IsPrefix, {} | |
883 | rex.wrxb, 0x4f, None, Cpu64, NoSuf|IsPrefix, {} | |
40b8e679 | 884 | |
31184569 JB |
885 | // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) |
886 | ||
33b6a20a JB |
887 | <pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, + |
888 | load:Load:0, store:Store:0, + | |
889 | vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, + | |
31184569 JB |
890 | rex:REX:Cpu64, nooptimize:NoOptimize:0> |
891 | ||
2368c6bf | 892 | {<pseudopfx>}, PSEUDO_PREFIX, Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {} |
86fa6981 | 893 | |
40b8e679 L |
894 | // 486 extensions. |
895 | ||
9a182d04 JB |
896 | bswap, 0xfc8, None, Cpu486, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64 } |
897 | xadd, 0xfc0, None, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
898 | cmpxchg, 0xfb0, None, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } | |
2368c6bf L |
899 | invd, 0xf08, None, Cpu486, NoSuf, {} |
900 | wbinvd, 0xf09, None, Cpu486, NoSuf, {} | |
901 | invlpg, 0xf01, 7, Cpu486, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
40b8e679 L |
902 | |
903 | // 586 and late 486 extensions. | |
2368c6bf | 904 | cpuid, 0xfa2, None, Cpu486, NoSuf, {} |
40b8e679 L |
905 | |
906 | // Pentium extensions. | |
2368c6bf L |
907 | wrmsr, 0xf30, None, Cpu586, NoSuf, {} |
908 | rdtsc, 0xf31, None, Cpu586, NoSuf, {} | |
909 | rdmsr, 0xf32, None, Cpu586, NoSuf, {} | |
9a182d04 | 910 | cmpxchg8b, 0xfc7, 1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex } |
40b8e679 L |
911 | |
912 | // Pentium II/Pentium Pro extensions. | |
2368c6bf L |
913 | sysenter, 0xf34, None, Cpu64, Intel64Only|NoSuf, {} |
914 | sysenter, 0xf34, None, Cpu686|CpuNo64, NoSuf, {} | |
9a182d04 | 915 | sysexit, 0xf35, None, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, {} |
2368c6bf | 916 | sysexit, 0xf35, None, Cpu686|CpuNo64, NoSuf, {} |
9a182d04 | 917 | fxsave, 0xfae, 0, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } |
2368c6bf | 918 | fxsave64, 0xfae, 0, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
9a182d04 | 919 | fxrstor, 0xfae, 1, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } |
2368c6bf L |
920 | fxrstor64, 0xfae, 1, CpuFXSR|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
921 | rdpmc, 0xf33, None, Cpu686, NoSuf, {} | |
40b8e679 | 922 | // official undefined instr. |
2368c6bf | 923 | ud2, 0xf0b, None, Cpu186, NoSuf, {} |
40b8e679 | 924 | // alias for ud2 |
2368c6bf | 925 | ud2a, 0xf0b, None, Cpu186, NoSuf, {} |
40b8e679 | 926 | // 2nd. official undefined instr. |
a122baf5 | 927 | ud1, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
b414985b | 928 | // alias for ud1 |
a122baf5 | 929 | ud2b, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
66f1eba0 | 930 | // 3rd official undefined instr (older CPUs don't take a ModR/M byte) |
a122baf5 | 931 | ud0, 0xfff, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
9a182d04 JB |
932 | |
933 | cmov<cc>, 0xf4<cc:opc>, None, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
934 | ||
2368c6bf L |
935 | fcmovb, 0xdac0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } |
936 | fcmovnae, 0xdac0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
937 | fcmove, 0xdac8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
938 | fcmovbe, 0xdad0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
939 | fcmovna, 0xdad0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
940 | fcmovu, 0xdad8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
941 | fcmovae, 0xdbc0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
942 | fcmovnb, 0xdbc0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
943 | fcmovne, 0xdbc8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
944 | fcmova, 0xdbd0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
945 | fcmovnbe, 0xdbd0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
946 | fcmovnu, 0xdbd8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
947 | ||
948 | fcomi, 0xdbf0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
949 | fcomi, 0xdbf1, None, Cpu687, NoSuf, {} | |
950 | fcomi, 0xdbf0, None, Cpu687, NoSuf, { FloatReg } | |
951 | fucomi, 0xdbe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
952 | fucomi, 0xdbe9, None, Cpu687, NoSuf, {} | |
953 | fucomi, 0xdbe8, None, Cpu687, NoSuf, { FloatReg } | |
954 | fcomip, 0xdff0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
955 | fcomip, 0xdff1, None, Cpu687, NoSuf, {} | |
956 | fcomip, 0xdff0, None, Cpu687, NoSuf, { FloatReg } | |
957 | fcompi, 0xdff0, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
958 | fcompi, 0xdff1, None, Cpu687, NoSuf, {} | |
959 | fcompi, 0xdff0, None, Cpu687, NoSuf, { FloatReg } | |
960 | fucomip, 0xdfe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
961 | fucomip, 0xdfe9, None, Cpu687, NoSuf, {} | |
962 | fucomip, 0xdfe8, None, Cpu687, NoSuf, { FloatReg } | |
963 | fucompi, 0xdfe8, None, Cpu687, NoSuf, { FloatReg, FloatAcc } | |
964 | fucompi, 0xdfe9, None, Cpu687, NoSuf, {} | |
965 | fucompi, 0xdfe8, None, Cpu687, NoSuf, { FloatReg } | |
40b8e679 L |
966 | |
967 | // Pentium4 extensions. | |
968 | ||
8ee52bcf | 969 | movnti, 0xfc3, None, CpuSSE2, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
2368c6bf L |
970 | clflush, 0xfae, 7, CpuClflush, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
971 | lfence, 0xfaee8, None, CpuSSE2, NoSuf, {} | |
972 | mfence, 0xfaef0, None, CpuSSE2, NoSuf, {} | |
bd5295b2 | 973 | // Processors that do not support PAUSE treat this opcode as a NOP instruction. |
2368c6bf | 974 | pause, 0xf390, None, Cpu186, NoSuf, {} |
40b8e679 L |
975 | |
976 | // MMX/SSE2 instructions. | |
977 | ||
33b6a20a JB |
978 | <mmx:cpu:pfx:attr:shimm:reg:mem, + |
979 | $avx:CpuAVX:66:Vex128|VexVVVV|VexW0|SSE2AVX:Vex128|VexVVVV=2|VexW0|SSE2AVX:RegXMM:Xmmword, + | |
980 | $sse:CpuSSE2:66:::RegXMM:Xmmword, + | |
1cb0ab18 | 981 | $mmx:CpuMMX::::RegMMX:Qword> |
5cdaf100 | 982 | |
33b6a20a JB |
983 | <sse2:cpu:attr:scal:vvvv:shimm, + |
984 | $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|VexVVVV=2|VexW0|SSE2AVX, + | |
1cb0ab18 | 985 | $sse:CpuSSE2::::> |
5cdaf100 | 986 | |
b9df5afb JB |
987 | <bw:opc:vexw:elem:kcpu:kpfx:cpubmi, + |
988 | b:0:VexW0:Byte:CpuAVX512DQ:66:CpuAVX512VBMI, + | |
989 | w:1:VexW1:Word:CpuAVX512F::CpuAVX512BW> | |
990 | ||
6473a592 | 991 | <dq:opc:vexw:vexw64:elem:cpu64:gpr:kpfx, + |
1cb0ab18 | 992 | d:0:VexW0::Dword::Reg32:66, + |
6473a592 JB |
993 | q:1:VexW1:VexW1:Qword:Cpu64:Reg64:> |
994 | ||
2368c6bf | 995 | emms, 0xf77, None, CpuMMX, NoSuf, {} |
40b8e679 L |
996 | // These really shouldn't allow for Reg64 (movq is the right mnemonic for |
997 | // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's | |
998 | // spec). AMD's spec, having been in existence for much longer, failed to | |
999 | // recognize that and specified movd for 32- and 64-bit operations. | |
2368c6bf L |
1000 | movd, 0x666e, None, CpuAVX, D|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM } |
1001 | movd, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM } | |
1002 | movd, 0x660f6e, None, CpuSSE2, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } | |
1003 | movd, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM } | |
1004 | movd, 0xf6e, None, CpuMMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX } | |
1005 | movd, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX } | |
1006 | movq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1007 | movq, 0x66d6, None, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
1008 | movq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM } | |
1009 | movq, 0xf30f7e, None, CpuSSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM } | |
1010 | movq, 0x660fd6, None, CpuSSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM } | |
1011 | movq, 0x660f6e, None, CpuSSE2|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } | |
1012 | movq, 0xf6f, None, CpuMMX, D|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX } | |
1013 | movq, 0xf6e, None, CpuMMX|Cpu64, D|Modrm|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX } | |
1014 | packssdw<mmx>, 0x<mmx:pfx>0f6b, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1015 | packsswb<mmx>, 0x<mmx:pfx>0f63, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1016 | packuswb<mmx>, 0x<mmx:pfx>0f67, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1017 | padd<bw><mmx>, 0x<mmx:pfx>0ffc | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1018 | paddd<mmx>, 0x<mmx:pfx>0ffe, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1019 | paddq<sse2>, 0x660fd4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1020 | paddq, 0xfd4, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1021 | padds<bw><mmx>, 0x<mmx:pfx>0fec | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1022 | paddus<bw><mmx>, 0x<mmx:pfx>0fdc | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1023 | pand<mmx>, 0x<mmx:pfx>0fdb, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1024 | pandn<mmx>, 0x<mmx:pfx>0fdf, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1025 | pcmpeq<bw><mmx>, 0x<mmx:pfx>0f74 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1026 | pcmpeqd<mmx>, 0x<mmx:pfx>0f76, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1027 | pcmpgt<bw><mmx>, 0x<mmx:pfx>0f64 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1028 | pcmpgtd<mmx>, 0x<mmx:pfx>0f66, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1029 | pmaddwd<mmx>, 0x<mmx:pfx>0ff5, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1030 | pmulhw<mmx>, 0x<mmx:pfx>0fe5, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1031 | pmullw<mmx>, 0x<mmx:pfx>0fd5, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1032 | por<mmx>, 0x<mmx:pfx>0feb, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1033 | psllw<mmx>, 0x<mmx:pfx>0ff1, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1034 | psllw<mmx>, 0x<mmx:pfx>0f71, 6, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1035 | psll<dq><mmx>, 0x<mmx:pfx>0ff2 | <dq:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1036 | psll<dq><mmx>, 0x<mmx:pfx>0f72 | <dq:opc>, 6, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1037 | psraw<mmx>, 0x<mmx:pfx>0fe1, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1038 | psraw<mmx>, 0x<mmx:pfx>0f71, 4, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1039 | psrad<mmx>, 0x<mmx:pfx>0fe2, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1040 | psrad<mmx>, 0x<mmx:pfx>0f72, 4, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1041 | psrlw<mmx>, 0x<mmx:pfx>0fd1, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1042 | psrlw<mmx>, 0x<mmx:pfx>0f71, 2, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1043 | psrl<dq><mmx>, 0x<mmx:pfx>0fd2 | <dq:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1044 | psrl<dq><mmx>, 0x<mmx:pfx>0f72 | <dq:opc>, 2, <mmx:cpu>, Modrm|<mmx:shimm>|NoSuf, { Imm8, <mmx:reg> } | |
1045 | psub<bw><mmx>, 0x<mmx:pfx>0ff8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1046 | psubd<mmx>, 0x<mmx:pfx>0ffa, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1047 | psubq<sse2>, 0x660ffb, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1048 | psubq, 0xffb, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1049 | psubs<bw><mmx>, 0x<mmx:pfx>0fe8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1050 | psubus<bw><mmx>, 0x<mmx:pfx>0fd8 | <bw:opc>, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1051 | punpckhbw<mmx>, 0x<mmx:pfx>0f68, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1052 | punpckhwd<mmx>, 0x<mmx:pfx>0f69, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1053 | punpckhdq<mmx>, 0x<mmx:pfx>0f6a, None, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
1054 | punpcklbw<sse2>, 0x660f60, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1055 | punpcklbw, 0xf60, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1056 | punpcklwd<sse2>, 0x660f61, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1057 | punpcklwd, 0xf61, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1058 | punpckldq<sse2>, 0x660f62, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1059 | punpckldq, 0xf62, None, CpuMMX, Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1060 | pxor<mmx>, 0x<mmx:pfx>0fef, None, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> } | |
40b8e679 | 1061 | |
458fa392 | 1062 | // SSE instructions. |
40b8e679 | 1063 | |
33b6a20a JB |
1064 | <sse:cpu:attr:scal:vvvv, + |
1065 | $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, + | |
1cb0ab18 | 1066 | $sse:CpuSSE:::> |
390ddd6f | 1067 | <frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, ord:7:C> |
3677e4c1 | 1068 | |
2368c6bf L |
1069 | addps<sse>, 0x0f58, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1070 | addss<sse>, 0xf30f58, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1071 | andnps<sse>, 0x0f55, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1072 | andps<sse>, 0x0f54, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1073 | cmp<frel>ps<sse>, 0x0fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1074 | cmp<frel>ss<sse>, 0xf30fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
1075 | cmpps<sse>, 0x0fc2, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1076 | cmpss<sse>, 0xf30fc2, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1077 | comiss<sse>, 0x0f2f, None, <sse:cpu>, Modrm|<sse:scal>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1078 | cvtpi2ps, 0xf2a, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM } | |
1079 | cvtps2pi, 0xf2d, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } | |
5cdaf100 | 1080 | cvtsi2ss<sse>, 0xf30f2a, None, <sse:cpu>|CpuNo64, Modrm|<sse:scal>|<sse:vvvv>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
9a182d04 JB |
1081 | cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
1082 | cvtsi2ss, 0xf32a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
73e45eb2 JB |
1083 | cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
1084 | cvtsi2ss, 0xf30f2a, None, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
1cb0ab18 JB |
1085 | cvtss2si, 0xf32d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
1086 | cvtss2si, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
2368c6bf | 1087 | cvttps2pi, 0xf2c, None, CpuSSE, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX } |
1cb0ab18 JB |
1088 | cvttss2si, 0xf32c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
1089 | cvttss2si, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
2368c6bf L |
1090 | divps<sse>, 0x0f5e, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1091 | divss<sse>, 0xf30f5e, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1092 | ldmxcsr<sse>, 0x0fae, 2, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { Dword|Unspecified|BaseIndex } | |
1093 | maskmovq, 0xff7, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, RegMMX } | |
1094 | maxps<sse>, 0x0f5f, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1095 | maxss<sse>, 0xf30f5f, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1096 | minps<sse>, 0x0f5d, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1097 | minss<sse>, 0xf30f5d, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1098 | movaps<sse>, 0x0f28, None, <sse:cpu>, D|Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1099 | movhlps<sse>, 0x0f12, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } | |
1100 | movhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1101 | movhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } | |
1102 | movhps, 0xf16, None, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } | |
1103 | movlhps<sse>, 0x0f16, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } | |
1104 | movlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1105 | movlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } | |
1106 | movlps, 0xf12, None, CpuSSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } | |
5cdaf100 | 1107 | movmskps<sse>, 0x0f50, None, <sse:cpu>, Modrm|<sse:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
2368c6bf L |
1108 | movntps<sse>, 0x0f2b, None, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } |
1109 | movntq, 0xfe7, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } | |
1110 | movntdq<sse2>, 0x660fe7, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } | |
1111 | movss, 0xf310, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } | |
1112 | movss, 0xf310, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } | |
1113 | movss, 0xf30f10, None, CpuSSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1114 | movups<sse>, 0x0f10, None, <sse:cpu>, D|Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1115 | mulps<sse>, 0x0f59, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1116 | mulss<sse>, 0xf30f59, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1117 | orps<sse>, 0x0f56, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1118 | pavg<bw>, 0xfe0 | (3 * <bw:opc>), None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1119 | pavg<bw><sse2>, 0x660fe0 | (3 * <bw:opc>), None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
5cdaf100 | 1120 | pextrw<sse2>, 0x660fc5, None, <sse2:cpu>, Load|Modrm|<sse2:attr>|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } |
ffb86450 | 1121 | pextrw, 0xfc5, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegMMX, Reg32|Reg64 } |
5cdaf100 | 1122 | pinsrw<sse2>, 0x660fc4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } |
2368c6bf | 1123 | pinsrw<sse2>, 0x660fc4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM } |
ffb86450 | 1124 | pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegMMX } |
2368c6bf L |
1125 | pinsrw, 0xfc4, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegMMX } |
1126 | pmaxsw<sse2>, 0x660fee, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1127 | pmaxsw, 0xfee, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1128 | pmaxub<sse2>, 0x660fde, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1129 | pmaxub, 0xfde, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1130 | pminsw<sse2>, 0x660fea, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1131 | pminsw, 0xfea, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1132 | pminub<sse2>, 0x660fda, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1133 | pminub, 0xfda, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
5cdaf100 | 1134 | pmovmskb<sse2>, 0x660fd7, None, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
ffb86450 | 1135 | pmovmskb, 0xfd7, None, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegMMX, Reg32|Reg64 } |
2368c6bf L |
1136 | pmulhuw<sse2>, 0x660fe4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1137 | pmulhuw, 0xfe4, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1138 | prefetchnta, 0xf18, 0, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1139 | prefetcht0, 0xf18, 1, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1140 | prefetcht1, 0xf18, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1141 | prefetcht2, 0xf18, 3, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1142 | psadbw, 0xff6, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1143 | psadbw<sse2>, 0x660ff6, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1144 | pshufw, 0xf70, None, CpuSSE|Cpu3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1145 | rcpps<sse>, 0x0f53, None, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1146 | rcpss<sse>, 0xf30f53, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1147 | rsqrtps<sse>, 0x0f52, None, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1148 | rsqrtss<sse>, 0xf30f52, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1149 | sfence, 0xfaef8, None, CpuSSE|Cpu3dnowA, NoSuf, {} | |
1150 | shufps<sse>, 0x0fc6, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1151 | sqrtps<sse>, 0x0f51, None, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1152 | sqrtss<sse>, 0xf30f51, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1153 | stmxcsr<sse>, 0x0fae, 3, <sse:cpu>, Modrm|<sse:attr>|NoSuf, { Dword|Unspecified|BaseIndex } | |
1154 | subps<sse>, 0x0f5c, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1155 | subss<sse>, 0xf30f5c, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1156 | ucomiss<sse>, 0x0f2e, None, <sse:cpu>, Modrm|<sse:scal>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1157 | unpckhps<sse>, 0x0f15, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1158 | unpcklps<sse>, 0x0f14, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1159 | xorps<sse>, 0x0f57, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
40b8e679 | 1160 | |
458fa392 | 1161 | // SSE2 instructions. |
40b8e679 | 1162 | |
2368c6bf L |
1163 | addpd<sse2>, 0x660f58, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1164 | addsd<sse2>, 0xf20f58, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1165 | andnpd<sse2>, 0x660f55, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1166 | andpd<sse2>, 0x660f54, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1167 | cmp<frel>pd<sse2>, 0x660fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1168 | cmp<frel>sd<sse2>, 0xf20fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|<frel:comm>|NoSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
1169 | cmppd<sse2>, 0x660fc2, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1170 | cmpsd<sse2>, 0xf20fc2, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1171 | comisd<sse2>, 0x660f2f, None, <sse2:cpu>, Modrm|<sse2:scal>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1172 | cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } | |
1173 | cvtpi2pd, 0xf3e6, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1174 | cvtpi2pd, 0x660f2a, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } | |
5cdaf100 | 1175 | cvtsi2sd<sse2>, 0xf20f2a, None, <sse2:cpu>|CpuNo64, Modrm|IgnoreSize|<sse2:scal>|<sse2:vvvv>|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
9a182d04 JB |
1176 | cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
1177 | cvtsi2sd, 0xf22a, None, CpuAVX|Cpu64, Modrm|Vex=3|Space0F|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
73e45eb2 JB |
1178 | cvtsi2sd, 0xf20f2a, None, CpuSSE2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } |
1179 | cvtsi2sd, 0xf20f2a, None, CpuSSE2|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2368c6bf L |
1180 | divpd<sse2>, 0x660f5e, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1181 | divsd<sse2>, 0xf20f5e, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1182 | maxpd<sse2>, 0x660f5f, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1183 | maxsd<sse2>, 0xf20f5f, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1184 | minpd<sse2>, 0x660f5d, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1185 | minsd<sse2>, 0xf20f5d, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1186 | movapd<sse2>, 0x660f28, None, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1187 | movhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1188 | movhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } | |
1189 | movhpd, 0x660f16, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } | |
1190 | movlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1191 | movlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } | |
1192 | movlpd, 0x660f12, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } | |
5cdaf100 | 1193 | movmskpd<sse2>, 0x660f50, None, <sse2:cpu>, Modrm|<sse2:attr>|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 } |
2368c6bf L |
1194 | movntpd<sse2>, 0x660f2b, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } |
1195 | movsd, 0xf210, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } | |
1196 | movsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3|Space0F|VexVVVV=1|VexW=1|NoSuf|SSE2AVX, { RegXMM, RegXMM } | |
1197 | movsd, 0xf20f10, None, CpuSSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1198 | movupd<sse2>, 0x660f10, None, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1199 | mulpd<sse2>, 0x660f59, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1200 | mulsd<sse2>, 0xf20f59, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1201 | orpd<sse2>, 0x660f56, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1202 | shufpd<sse2>, 0x660fc6, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1203 | sqrtpd<sse2>, 0x660f51, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1204 | sqrtsd<sse2>, 0xf20f51, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1205 | subpd<sse2>, 0x660f5c, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1206 | subsd<sse2>, 0xf20f5c, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1207 | ucomisd<sse2>, 0x660f2e, None, <sse2:cpu>, Modrm|<sse2:scal>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1208 | unpckhpd<sse2>, 0x660f15, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1209 | unpcklpd<sse2>, 0x660f14, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1210 | xorpd<sse2>, 0x660f57, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1211 | cvtdq2pd<sse2>, 0xf30fe6, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1212 | cvtpd2dq<sse2>, 0xf20fe6, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1213 | cvtdq2ps<sse2>, 0x0f5b, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1214 | cvtpd2pi, 0x660f2d, None, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } | |
1215 | cvtpd2ps<sse2>, 0x660f5a, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1216 | cvtps2pd<sse2>, 0x0f5a, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1217 | cvtps2dq<sse2>, 0x660f5b, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1cb0ab18 JB |
1218 | cvtsd2si, 0xf22d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
1219 | cvtsd2si, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
2368c6bf L |
1220 | cvtsd2ss<sse2>, 0xf20f5a, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1221 | cvtss2sd<sse2>, 0xf30f5a, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
5cdaf100 | 1222 | |
2368c6bf | 1223 | cvttpd2pi, 0x660f2c, None, CpuSSE2, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegMMX } |
1cb0ab18 JB |
1224 | cvttsd2si, 0xf22c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
1225 | cvttsd2si, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } | |
2368c6bf L |
1226 | cvttpd2dq<sse2>, 0x660fe6, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1227 | cvttps2dq<sse2>, 0xf30f5b, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1228 | maskmovdqu<sse2>, 0x660ff7, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { RegXMM, RegXMM } | |
1229 | movdqa<sse2>, 0x660f6f, None, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1230 | movdqu<sse2>, 0xf30f6f, None, <sse2:cpu>, D|Modrm|<sse2:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1231 | movdq2q, 0xf20fd6, None, CpuSSE2, Modrm|NoSuf, { RegXMM, RegMMX } | |
1232 | movq2dq, 0xf30fd6, None, CpuSSE2, Modrm|NoSuf, { RegMMX, RegXMM } | |
1233 | pmuludq<sse2>, 0x660ff4, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1234 | pmuludq, 0xff4, None, CpuSSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1235 | pshufd<sse2>, 0x660f70, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1236 | pshufhw<sse2>, 0xf30f70, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1237 | pshuflw<sse2>, 0xf20f70, None, <sse2:cpu>, Modrm|<sse2:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1238 | pslldq<sse2>, 0x660f73, 7, <sse2:cpu>, Modrm|<sse2:shimm>|NoSuf, { Imm8, RegXMM } | |
1239 | psrldq<sse2>, 0x660f73, 3, <sse2:cpu>, Modrm|<sse2:shimm>|NoSuf, { Imm8, RegXMM } | |
1240 | punpckhqdq<sse2>, 0x660f6d, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1241 | punpcklqdq<sse2>, 0x660f6c, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
40b8e679 | 1242 | |
390ddd6f JB |
1243 | <frel> |
1244 | ||
458fa392 | 1245 | // SSE3 instructions. |
40b8e679 | 1246 | |
5cdaf100 JB |
1247 | <sse3:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE3::> |
1248 | ||
2368c6bf L |
1249 | addsubpd<sse3>, 0x660fd0, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1250 | addsubps<sse3>, 0xf20fd0, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1251 | haddpd<sse3>, 0x660f7c, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1252 | haddps<sse3>, 0xf20f7c, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1253 | hsubpd<sse3>, 0x660f7d, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1254 | hsubps<sse3>, 0xf20f7d, None, <sse3:cpu>, Modrm|<sse3:attr>|<sse3:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1255 | lddqu<sse3>, 0xf20ff0, None, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } | |
1256 | movddup<sse3>, 0xf20f12, None, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1257 | movshdup<sse3>, 0xf30f16, None, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1258 | movsldup<sse3>, 0xf30f12, None, <sse3:cpu>, Modrm|<sse3:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
bbe1eca6 JB |
1259 | |
1260 | // FPU instructions also covered by SSE3 CPUID flag. | |
1261 | ||
1262 | fisttp, 0xdf, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex } | |
1263 | fisttp, 0xdd, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex } | |
2368c6bf | 1264 | fisttpll, 0xdd, 1, CpuFISTTP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } |
bbe1eca6 JB |
1265 | |
1266 | // CMPXCHG16B instruction. | |
1267 | ||
2368c6bf | 1268 | cmpxchg16b, 0xfc7, 1, CpuCX16|Cpu64, Modrm|NoSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex } |
bbe1eca6 JB |
1269 | |
1270 | // MONITOR instructions. | |
1271 | ||
2368c6bf | 1272 | monitor, 0xf01c8, None, CpuSSE3, NoSuf, {} |
a79eaed6 | 1273 | // monitor is very special. CX and DX are always 32 bits. The |
40b8e679 L |
1274 | // address size override prefix can be used to overrride the AX size in |
1275 | // all modes. | |
2368c6bf | 1276 | monitor, 0xf01c8, None, CpuSSE3, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } |
a79eaed6 | 1277 | // The 64-bit form exists only for compatibility with older gas. |
2368c6bf L |
1278 | monitor, 0xf01c8, None, CpuSSE3|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } |
1279 | mwait, 0xf01c9, None, CpuSSE3, NoSuf, {} | |
a79eaed6 | 1280 | // mwait is very special. AX and CX are always 32 bits. |
a79eaed6 | 1281 | // The 64-bit form exists only for compatibility with older gas. |
2368c6bf | 1282 | mwait, 0xf01c9, None, CpuSSE3, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword } |
40b8e679 L |
1283 | |
1284 | // VMX instructions. | |
47dd174c | 1285 | |
2368c6bf L |
1286 | vmcall, 0xf01c1, None, CpuVMX, NoSuf, {} |
1287 | vmclear, 0x660fc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
1288 | vmlaunch, 0xf01c2, None, CpuVMX, NoSuf, {} | |
1289 | vmresume, 0xf01c3, None, CpuVMX, NoSuf, {} | |
1290 | vmptrld, 0xfc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
1291 | vmptrst, 0xfc7, 7, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
9a182d04 JB |
1292 | vmread, 0xf78, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Unspecified|BaseIndex } |
1293 | vmread, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex } | |
1294 | vmwrite, 0xf79, None, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32 } | |
1295 | vmwrite, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } | |
2368c6bf L |
1296 | vmxoff, 0xf01c4, None, CpuVMX, NoSuf, {} |
1297 | vmxon, 0xf30fc7, 6, CpuVMX, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
40b8e679 | 1298 | |
8729a6f6 L |
1299 | // VMFUNC instruction |
1300 | ||
2368c6bf | 1301 | vmfunc, 0xf01d4, None, CpuVMFUNC, NoSuf, {} |
8729a6f6 | 1302 | |
47dd174c L |
1303 | // SMX instructions. |
1304 | ||
2368c6bf | 1305 | getsec, 0xf37, None, CpuSMX, NoSuf, {} |
47dd174c | 1306 | |
f1f8f695 L |
1307 | // EPT instructions. |
1308 | ||
2368c6bf L |
1309 | invept, 0x660f3880, None, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } |
1310 | invept, 0x660f3880, None, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
1311 | invvpid, 0x660f3881, None, CpuEPT|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } | |
1312 | invvpid, 0x660f3881, None, CpuEPT|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
f1f8f695 | 1313 | |
6c30d220 L |
1314 | // INVPCID instruction |
1315 | ||
2368c6bf L |
1316 | invpcid, 0x660f3882, None, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } |
1317 | invpcid, 0x660f3882, None, CpuINVPCID|Cpu64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } | |
6c30d220 | 1318 | |
458fa392 | 1319 | // SSSE3 instructions. |
40b8e679 | 1320 | |
33b6a20a JB |
1321 | <ssse3:cpu:pfx:attr:vvvv:reg:mem, + |
1322 | $avx:CpuAVX:66:Vex128|VexW0|SSE2AVX:VexVVVV:RegXMM:Xmmword, + | |
1323 | $sse:CpuSSSE3:66:::RegXMM:Xmmword, + | |
1cb0ab18 | 1324 | $mmx:CpuSSSE3::::RegMMX:Qword> |
5cdaf100 | 1325 | |
2368c6bf L |
1326 | phaddw<ssse3>, 0x<ssse3:pfx>0f3801, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } |
1327 | phaddd<ssse3>, 0x<ssse3:pfx>0f3802, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1328 | phaddsw<ssse3>, 0x<ssse3:pfx>0f3803, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1329 | phsubw<ssse3>, 0x<ssse3:pfx>0f3805, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1330 | phsubd<ssse3>, 0x<ssse3:pfx>0f3806, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1331 | phsubsw<ssse3>, 0x<ssse3:pfx>0f3807, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1332 | pmaddubsw<ssse3>, 0x<ssse3:pfx>0f3804, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1333 | pmulhrsw<ssse3>, 0x<ssse3:pfx>0f380b, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1334 | pshufb<ssse3>, 0x<ssse3:pfx>0f3800, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1335 | psign<bw><ssse3>, 0x<ssse3:pfx>0f3808 | <bw:opc>, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1336 | psignd<ssse3>, 0x<ssse3:pfx>0f380a, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1337 | palignr<ssse3>, 0x<ssse3:pfx>0f3a0f, None, <ssse3:cpu>, Modrm|<ssse3:attr>|<ssse3:vvvv>|NoSuf, { Imm8, <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1338 | pabs<bw><ssse3>, 0x<ssse3:pfx>0f381c | <bw:opc>, None, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
1339 | pabsd<ssse3>, 0x<ssse3:pfx>0f381e, None, <ssse3:cpu>, Modrm|<ssse3:attr>|NoSuf, { <ssse3:reg>|<ssse3:mem>|Unspecified|BaseIndex, <ssse3:reg> } | |
40b8e679 | 1340 | |
458fa392 | 1341 | // SSE4.1 instructions. |
40b8e679 | 1342 | |
5cdaf100 | 1343 | <sse41:cpu:attr:scal:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE4_1:::> |
1cb0ab18 | 1344 | <sd:ppfx:spfx:opc:vexw:elem, s::f3:0:VexW0:Dword, d:66:f2:1:VexW1:Qword> |
73d214b2 | 1345 | |
2368c6bf L |
1346 | blendp<sd><sse41>, 0x660f3a0c | <sd:opc>, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1347 | blendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1348 | blendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1349 | blendvp<sd>, 0x660f3814 | <sd:opc>, None, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1350 | blendvp<sd>, 0x660f3814 | <sd:opc>, None, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1351 | dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1352 | extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } | |
1353 | extractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } | |
1354 | extractps, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } | |
1355 | extractps, 0x660f3a17, None, CpuSSE4_1|Cpu64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } | |
1356 | insertps<sse41>, 0x660f3a21, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1357 | movntdqa<sse41>, 0x660f382a, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } | |
1358 | mpsadbw<sse41>, 0x660f3a42, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1359 | packusdw<sse41>, 0x660f382b, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1360 | pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1361 | pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1362 | pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1363 | pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1364 | pblendw<sse41>, 0x660f3a0e, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1365 | pcmpeqq<sse41>, 0x660f3829, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1366 | pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, None, <sse41:cpu>, RegMem|<sse41:attr>|NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } | |
1367 | pextr<bw><sse41>, 0x660f3a14 | <bw:opc>, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
1368 | pextrd<sse41>, 0x660f3a16, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf|IgnoreSize, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex } | |
1369 | pextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } | |
1370 | pextrq, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex } | |
1371 | phminposuw<sse41>, 0x660f3841, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1372 | pinsrb<sse41>, 0x660f3a20, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf|IgnoreSize|NoRex64, { Imm8, Reg32|Reg64, RegXMM } | |
1373 | pinsrb<sse41>, 0x660f3a20, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM } | |
1374 | pinsrd<sse41>, 0x660f3a22, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf|IgnoreSize, { Imm8, Reg32|Unspecified|BaseIndex, RegXMM } | |
1375 | pinsrq, 0x6622, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=1|VexW1|NoSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } | |
1376 | pinsrq, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|NoSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM } | |
1377 | pmaxsb<sse41>, 0x660f383c, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1378 | pmaxsd<sse41>, 0x660f383d, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1379 | pmaxud<sse41>, 0x660f383f, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1380 | pmaxuw<sse41>, 0x660f383e, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1381 | pminsb<sse41>, 0x660f3838, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1382 | pminsd<sse41>, 0x660f3839, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1383 | pminud<sse41>, 0x660f383b, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1384 | pminuw<sse41>, 0x660f383a, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1385 | pmovsxbw<sse41>, 0x660f3820, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1386 | pmovsxbd<sse41>, 0x660f3821, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1387 | pmovsxbq<sse41>, 0x660f3822, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1388 | pmovsxwd<sse41>, 0x660f3823, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1389 | pmovsxwq<sse41>, 0x660f3824, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1390 | pmovsxdq<sse41>, 0x660f3825, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1391 | pmovzxbw<sse41>, 0x660f3830, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1392 | pmovzxbd<sse41>, 0x660f3831, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1393 | pmovzxbq<sse41>, 0x660f3832, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1394 | pmovzxwd<sse41>, 0x660f3833, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1395 | pmovzxwq<sse41>, 0x660f3834, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1396 | pmovzxdq<sse41>, 0x660f3835, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1397 | pmuldq<sse41>, 0x660f3828, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1398 | pmulld<sse41>, 0x660f3840, None, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1399 | ptest<sse41>, 0x660f3817, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1400 | roundp<sd><sse41>, 0x660f3a08 | <sd:opc>, None, <sse41:cpu>, Modrm|<sse41:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1401 | rounds<sd><sse41>, 0x660f3a0a | <sd:opc>, None, <sse41:cpu>, Modrm|<sse41:scal>|<sse41:vvvv>|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } | |
40b8e679 | 1402 | |
458fa392 | 1403 | // SSE4.2 instructions. |
40b8e679 | 1404 | |
5cdaf100 JB |
1405 | <sse42:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE4_2::> |
1406 | ||
2368c6bf L |
1407 | pcmpgtq<sse42>, 0x660f3837, None, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1408 | pcmpestri<sse42>, 0x660f3a61, None, <sse42:cpu>|CpuNo64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
9a182d04 | 1409 | pcmpestri, 0x6661, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
73e45eb2 | 1410 | pcmpestri, 0x660f3a61, None, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
2368c6bf | 1411 | pcmpestrm<sse42>, 0x660f3a60, None, <sse42:cpu>|CpuNo64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
9a182d04 | 1412 | pcmpestrm, 0x6660, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
73e45eb2 | 1413 | pcmpestrm, 0x660f3a60, None, CpuSSE4_2|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
2368c6bf L |
1414 | pcmpistri<sse42>, 0x660f3a63, None, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1415 | pcmpistrm<sse42>, 0x660f3a62, None, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
ffb86450 JB |
1416 | crc32, 0xf20f38f0, None, CpuSSE4_2, W|Modrm|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } |
1417 | crc32, 0xf20f38f0, None, CpuSSE4_2|Cpu64, W|Modrm|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } | |
40b8e679 | 1418 | |
475a2301 L |
1419 | // xsave/xrstor New Instructions. |
1420 | ||
9a182d04 | 1421 | xsave, 0xfae, 4, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } |
2368c6bf | 1422 | xsave64, 0xfae, 4, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
9a182d04 | 1423 | xrstor, 0xfae, 5, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } |
2368c6bf L |
1424 | xrstor64, 0xfae, 5, CpuXsave|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
1425 | xgetbv, 0xf01d0, None, CpuXsave, NoSuf, {} | |
1426 | xsetbv, 0xf01d1, None, CpuXsave, NoSuf, {} | |
475a2301 | 1427 | |
29c048b6 | 1428 | // xsaveopt |
9a182d04 | 1429 | xsaveopt, 0xfae, 6, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex } |
2368c6bf | 1430 | xsaveopt64, 0xfae, 6, CpuXsaveopt|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } |
c7b8aa3a | 1431 | |
c0f3af97 L |
1432 | // AES instructions. |
1433 | ||
5cdaf100 JB |
1434 | <aes:cpu:attr:vvvv, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:::> |
1435 | ||
2368c6bf L |
1436 | aesdec<aes>, 0x660f38de, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } |
1437 | aesdeclast<aes>, 0x660f38df, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1438 | aesenc<aes>, 0x660f38dc, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1439 | aesenclast<aes>, 0x660f38dd, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|<aes:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1440 | aesimc<aes>, 0x660f38db, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1441 | aeskeygenassist<aes>, 0x660f3adf, None, <aes:cpu>CpuAES, Modrm|<aes:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
c0f3af97 | 1442 | |
8dcf1fad IT |
1443 | // VAES |
1444 | ||
2368c6bf L |
1445 | vaesdec, 0x66de, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } |
1446 | vaesdeclast, 0x66df, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } | |
1447 | vaesenc, 0x66dc, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } | |
1448 | vaesenclast, 0x66dd, None, CpuVAES, Modrm|Vex=2|Space0F38|VexVVVV=1|VexWIG|NoSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM } | |
8dcf1fad | 1449 | |
594ab6a3 | 1450 | // PCLMUL |
c0f3af97 | 1451 | |
5cdaf100 JB |
1452 | <pclmul:cpu:attr, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX|VexVVVV, $sse::> |
1453 | ||
2368c6bf L |
1454 | pclmulqdq<pclmul>, 0x660f3a44, None, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1455 | pclmullqlqdq<pclmul>, 0x660f3a44, 0x00, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1456 | pclmulhqlqdq<pclmul>, 0x660f3a44, 0x01, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1457 | pclmullqhqdq<pclmul>, 0x660f3a44, 0x10, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1458 | pclmulhqhqdq<pclmul>, 0x660f3a44, 0x11, <pclmul:cpu>CpuPCLMUL, Modrm|<pclmul:attr>|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
c0f3af97 | 1459 | |
48521003 IT |
1460 | // GFNI |
1461 | ||
5cdaf100 JB |
1462 | <gfni:cpu:w0:w1, $avx:CpuAVX|:Vex128|VexW0|SSE2AVX|VexVVVV:Vex128|VexW1|SSE2AVX|VexVVVV, $sse:::> |
1463 | ||
2368c6bf L |
1464 | gf2p8affineqb<gfni>, 0x660f3ace, None, <gfni:cpu>CpuGFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
1465 | gf2p8affineinvqb<gfni>, 0x660f3acf, None, <gfni:cpu>CpuGFNI, Modrm|<gfni:w1>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1466 | gf2p8mulb<gfni>, 0x660f38cf, None, <gfni:cpu>CpuGFNI, Modrm|<gfni:w0>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
48521003 | 1467 | |
c0f3af97 L |
1468 | // AVX instructions. |
1469 | ||
390ddd6f | 1470 | <frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, + |
33b6a20a JB |
1471 | unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, + |
1472 | nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, + | |
1473 | nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, + | |
1474 | neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, + | |
1475 | true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, + | |
1476 | unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, + | |
1477 | nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, + | |
3fabc179 JB |
1478 | true_us:1f:C> |
1479 | ||
4e0dd3ab | 1480 | // <Vxy> is used for VEX instructions with x/y suffixes. |
1481 | <Vxy:vex:syntax:dst, + | |
e07ae9a3 JB |
1482 | $i:Vex:IntelSyntax:RegXMM|RegYMM|Unspecified|BaseIndex, + |
1483 | $a:Vex:ATTSyntax:RegXMM|RegYMM, + | |
1484 | x:Vex128:ATTSyntax:RegXMM|Unspecified|BaseIndex, + | |
1485 | y:Vex256:ATTSyntax:RegYMM|Unspecified|BaseIndex> | |
1486 | ||
2368c6bf L |
1487 | vaddp<sd>, 0x<sd:ppfx>58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1488 | vadds<sd>, 0x<sd:spfx>58, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1489 | vaddsubpd, 0x66d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1490 | vaddsubps, 0xf2d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1491 | vandnp<sd>, 0x<sd:ppfx>55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1492 | vandp<sd>, 0x<sd:ppfx>54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1493 | vblendp<sd>, 0x660c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1494 | vblendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1495 | vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } | |
1496 | vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } | |
1497 | vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1498 | vcmp<frel>p<sd>, 0x<sd:ppfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
1499 | vcmp<frel>s<sd>, 0x<sd:spfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1500 | vcmpp<sd>, 0x<sd:ppfx>c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1501 | vcmps<sd>, 0x<sd:spfx>c2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1502 | vcomis<sd>, 0x<sd:ppfx>2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1503 | vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
1504 | vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
1505 | vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1506 | vcvtpd2dq<Vxy>, 0xf2e6, None, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } | |
1507 | vcvtpd2ps<Vxy>, 0x665a, None, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } | |
1508 | vcvtps2dq, 0x665b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1509 | vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
1510 | vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
1cb0ab18 | 1511 | vcvts<sd>2si, 0x<sd:spfx>2d, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
2368c6bf | 1512 | vcvtsd2ss, 0xf25a, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
73d214b2 JB |
1513 | vcvtsi2s<sd>, 0x<sd:spfx>2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
1514 | vcvtsi2s<sd>, 0x<sd:spfx>2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2368c6bf L |
1515 | vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1516 | vcvttpd2dq<Vxy>, 0x66e6, None, CpuAVX, Modrm|<Vxy:vex>|Space0F|VexWIG|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } | |
1517 | vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1cb0ab18 | 1518 | vcvtts<sd>2si, 0x<sd:spfx>2c, None, CpuAVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } |
2368c6bf L |
1519 | vdivp<sd>, 0x<sd:ppfx>5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1520 | vdivs<sd>, 0x<sd:spfx>5e, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1521 | vdppd, 0x6641, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1522 | vdpps, 0x6640, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1523 | vextractf128, 0x6619, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } | |
1524 | vextractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } | |
1525 | vextractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } | |
1526 | vhaddpd, 0x667c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1527 | vhaddps, 0xf27c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1528 | vhsubpd, 0x667d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1529 | vhsubps, 0xf27d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1530 | vinsertf128, 0x6618, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } | |
1531 | vinsertps, 0x6621, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1532 | vlddqu, 0xf2f0, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1533 | vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } | |
1534 | vmaskmovdqu, 0x66f7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, RegXMM } | |
1535 | vmaskmovp<sd>, 0x662e | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } | |
1536 | vmaskmovp<sd>, 0x662c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
1537 | vmaxp<sd>, 0x<sd:ppfx>5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1538 | vmaxs<sd>, 0x<sd:spfx>5f, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1539 | vminp<sd>, 0x<sd:ppfx>5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1540 | vmins<sd>, 0x<sd:spfx>5d, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1541 | vmovap<sd>, 0x<sd:ppfx>28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
a5dabbb0 L |
1542 | // vmovd really shouldn't allow for 64bit operand (vmovq is the right |
1543 | // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated | |
1544 | // by Intel AVX spec). To avoid extra template in gcc x86 backend and | |
1545 | // support assembler for AMD64, we accept 64bit operand on vmovd so | |
1546 | // that we can use one template for both SSE and AVX instructions. | |
2368c6bf L |
1547 | vmovd, 0x666e, None, CpuAVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
1548 | vmovd, 0x667e, None, CpuAVX|Cpu64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 } | |
1549 | vmovddup, 0xf212, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1550 | vmovddup, 0xf212, None, CpuAVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM } | |
1551 | vmovdqa, 0x666f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1552 | vmovdqu, 0xf36f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1553 | vmovhlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } | |
1554 | vmovhp<sd>, 0x<sd:ppfx>16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1555 | vmovhp<sd>, 0x<sd:ppfx>17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } | |
1556 | vmovlhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } | |
1557 | vmovlp<sd>, 0x<sd:ppfx>12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1558 | vmovlp<sd>, 0x<sd:ppfx>13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } | |
73d214b2 | 1559 | vmovmskp<sd>, 0x<sd:ppfx>50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } |
2368c6bf L |
1560 | vmovntdq, 0x66e7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } |
1561 | vmovntdqa, 0x662a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1562 | vmovntp<sd>, 0x<sd:ppfx>2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } | |
1563 | vmovq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1564 | vmovq, 0x66d6, None, CpuAVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
1565 | vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM } | |
1566 | vmovs<sd>, 0x<sd:spfx>10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } | |
1567 | vmovs<sd>, 0x<sd:spfx>10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM } | |
1568 | vmovshdup, 0xf316, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1569 | vmovsldup, 0xf312, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1570 | vmovup<sd>, 0x<sd:ppfx>10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1571 | vmpsadbw, 0x6642, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1572 | vmulp<sd>, 0x<sd:ppfx>59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1573 | vmuls<sd>, 0x<sd:spfx>59, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1574 | vorp<sd>, 0x<sd:ppfx>56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1575 | vpabs<bw>, 0x661c | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1576 | vpabsd, 0x661e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1577 | vpackssdw, 0x666b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1578 | vpacksswb, 0x6663, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1579 | vpackusdw, 0x662b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1580 | vpackuswb, 0x6667, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1581 | vpadds<bw>, 0x66ec | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1582 | vpadd<bw>, 0x66fc | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1583 | vpaddd, 0x66fe, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1584 | vpaddq, 0x66d4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1585 | vpaddus<bw>, 0x66dc | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1586 | vpalignr, 0x660f, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1587 | vpand, 0x66db, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1588 | vpandn, 0x66df, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1589 | vpavg<bw>, 0x66e0 | (3 * <bw:opc>), None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1590 | vpblendvb, 0x664c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1591 | vpblendw, 0x660e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1592 | vpcmpeq<bw>, 0x6674 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1593 | vpcmpeqd, 0x6676, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1594 | vpcmpeqq, 0x6629, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1595 | vpcmpestri, 0x6661, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
9a182d04 | 1596 | vpcmpestri, 0x6661, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
2368c6bf | 1597 | vpcmpestrm, 0x6660, None, CpuAVX|CpuNo64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } |
9a182d04 | 1598 | vpcmpestrm, 0x6660, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM } |
2368c6bf L |
1599 | vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1600 | vpcmpgtd, 0x6666, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1601 | vpcmpgtq, 0x6637, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1602 | vpcmpistri, 0x6663, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
1603 | vpcmpistrm, 0x6662, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
1604 | vperm2f128, 0x6606, None, CpuAVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
1605 | vpermilp<sd>, 0x660c | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1606 | vpermilp<sd>, 0x6604 | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexW0|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1607 | vpextr<dq>, 0x6616, None, CpuAVX|<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vexw64>|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } | |
9a182d04 | 1608 | vpextrw, 0x66c5, None, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } |
2368c6bf L |
1609 | vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } |
1610 | vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
1611 | vphaddd, 0x6602, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1612 | vphaddsw, 0x6603, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1613 | vphaddw, 0x6601, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1614 | vphminposuw, 0x6641, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } | |
1615 | vphsubd, 0x6606, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1616 | vphsubsw, 0x6607, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1617 | vphsubw, 0x6605, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1618 | vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
1619 | vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1620 | vpinsr<dq>, 0x6622, None, CpuAVX|<dq:cpu64>, Modrm|Vex|Space0F3A|VexVVVV|<dq:vexw64>|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 1621 | vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } |
2368c6bf L |
1622 | vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
1623 | vpmaddubsw, 0x6604, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1624 | vpmaddwd, 0x66f5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1625 | vpmaxsb, 0x663c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1626 | vpmaxsd, 0x663d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1627 | vpmaxsw, 0x66ee, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1628 | vpmaxub, 0x66de, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1629 | vpmaxud, 0x663f, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1630 | vpmaxuw, 0x663e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1631 | vpminsb, 0x6638, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1632 | vpminsd, 0x6639, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1633 | vpminsw, 0x66ea, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1634 | vpminub, 0x66da, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1635 | vpminud, 0x663b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1636 | vpminuw, 0x663a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
22c36940 | 1637 | vpmovmskb, 0x66d7, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } |
2368c6bf L |
1638 | vpmovsxbd, 0x6621, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } |
1639 | vpmovsxbq, 0x6622, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1640 | vpmovsxbw, 0x6620, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1641 | vpmovsxdq, 0x6625, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1642 | vpmovsxwd, 0x6623, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1643 | vpmovsxwq, 0x6624, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1644 | vpmovzxbd, 0x6631, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1645 | vpmovzxbq, 0x6632, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1646 | vpmovzxbw, 0x6630, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1647 | vpmovzxdq, 0x6635, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1648 | vpmovzxwd, 0x6633, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1649 | vpmovzxwq, 0x6634, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1650 | vpmuldq, 0x6628, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1651 | vpmulhrsw, 0x660b, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1652 | vpmulhuw, 0x66e4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1653 | vpmulhw, 0x66e5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1654 | vpmulld, 0x6640, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1655 | vpmullw, 0x66d5, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1656 | vpmuludq, 0x66f4, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1657 | vpor, 0x66eb, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1658 | vpsadbw, 0x66f6, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1659 | vpshufb, 0x6600, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1660 | vpshufd, 0x6670, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1661 | vpshufhw, 0xf370, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1662 | vpshuflw, 0xf270, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1663 | vpsign<bw>, 0x6608 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1664 | vpsignd, 0x660a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1665 | vpsll<dq>, 0x6672 | <dq:opc>, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1666 | vpsll<dq>, 0x66f2 | <dq:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1667 | vpslldq, 0x6673, 7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1668 | vpsllw, 0x6671, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1669 | vpsllw, 0x66f1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1670 | vpsrad, 0x6672, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1671 | vpsrad, 0x66e2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1672 | vpsraw, 0x6671, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1673 | vpsraw, 0x66e1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1674 | vpsrl<dq>, 0x6672 | <dq:opc>, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1675 | vpsrl<dq>, 0x66d2 | <dq:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1676 | vpsrldq, 0x6673, 3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1677 | vpsrlw, 0x6671, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } | |
1678 | vpsrlw, 0x66d1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1679 | vpsub<bw>, 0x66f8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1680 | vpsub<dq>, 0x66fa | <dq:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1681 | vpsubs<bw>, 0x66e8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1682 | vpsubus<bw>, 0x66d8 | <bw:opc>, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1683 | vptest, 0x6617, None, CpuAVX, Modrm|Vex|Space0F38|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1684 | vpunpckhbw, 0x6668, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1685 | vpunpckhdq, 0x666a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1686 | vpunpckhqdq, 0x666d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1687 | vpunpckhwd, 0x6669, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1688 | vpunpcklbw, 0x6660, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1689 | vpunpckldq, 0x6662, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1690 | vpunpcklqdq, 0x666c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1691 | vpunpcklwd, 0x6661, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1692 | vpxor, 0x66ef, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1693 | vrcpps, 0x53, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1694 | vrcpss, 0xf353, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1695 | vroundp<sd>, 0x6608 | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1696 | vrounds<sd>, 0x660a | <sd:opc>, None, CpuAVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1697 | vrsqrtps, 0x52, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1698 | vrsqrtss, 0xf352, None, CpuAVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1699 | vshufp<sd>, 0x<sd:ppfx>c6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1700 | vsqrtp<sd>, 0x<sd:ppfx>51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1701 | vsqrts<sd>, 0x<sd:spfx>51, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1702 | vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } | |
1703 | vsubp<sd>, 0x<sd:ppfx>5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1704 | vsubs<sd>, 0x<sd:spfx>5c, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1705 | vtestp<sd>, 0x660e | <sd:opc>, None, CpuAVX, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } | |
1706 | vucomis<sd>, 0x<sd:ppfx>2e, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1707 | vunpckhp<sd>, 0x<sd:ppfx>15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1708 | vunpcklp<sd>, 0x<sd:ppfx>14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1709 | vxorp<sd>, 0x<sd:ppfx>57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1710 | vzeroall, 0x77, None, CpuAVX, Vex=2|Space0F|VexWIG|NoSuf, {} | |
1711 | vzeroupper, 0x77, None, CpuAVX, Vex|Space0F|VexWIG|NoSuf, {} | |
c0f3af97 | 1712 | |
e07ae9a3 | 1713 | |
6c30d220 L |
1714 | // 256bit integer AVX2 instructions. |
1715 | ||
2368c6bf L |
1716 | vpmovsxbd, 0x6621, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } |
1717 | vpmovsxbq, 0x6622, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } | |
1718 | vpmovsxbw, 0x6620, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1719 | vpmovsxdq, 0x6625, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1720 | vpmovsxwd, 0x6623, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1721 | vpmovsxwq, 0x6624, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } | |
1722 | vpmovzxbd, 0x6631, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } | |
1723 | vpmovzxbq, 0x6632, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM } | |
1724 | vpmovzxbw, 0x6630, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1725 | vpmovzxdq, 0x6635, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1726 | vpmovzxwd, 0x6633, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1727 | vpmovzxwq, 0x6634, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM } | |
6c30d220 L |
1728 | |
1729 | // New AVX2 instructions. | |
1730 | ||
2368c6bf L |
1731 | vbroadcasti128, 0x665A, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } |
1732 | vbroadcastsd, 0x6619, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } | |
1733 | vbroadcastss, 0x6618, None, CpuAVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } | |
1734 | vpblendd, 0x6602, None, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1735 | vpbroadcast<bw>, 0x6678 | <bw:opc>, None, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <bw:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } | |
1736 | vpbroadcast<dq>, 0x6658 | <dq:opc>, None, CpuAVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <dq:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } | |
1737 | vperm2i128, 0x6646, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
1738 | vpermd, 0x6636, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
1739 | vpermpd, 0x6601, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } | |
1740 | vpermps, 0x6616, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
1741 | vpermq, 0x6600, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } | |
1742 | vextracti128, 0x6639, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } | |
1743 | vinserti128, 0x6638, None, CpuAVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } | |
1744 | vpmaskmov<dq>, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } | |
1745 | vpmaskmov<dq>, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
1746 | vpsllv<dq>, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1747 | vpsravd, 0x6646, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1748 | vpsrlv<dq>, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
6c30d220 L |
1749 | |
1750 | // AVX gather instructions | |
2368c6bf L |
1751 | vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } |
1752 | vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1753 | vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } | |
1754 | vgatherqp<sd>, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM } | |
1755 | vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } | |
1756 | vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1757 | vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1758 | vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } | |
1759 | vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
1760 | vpgatherq<dq>, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM } | |
1761 | vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } | |
1762 | vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } | |
6c30d220 | 1763 | |
a5ff0eb2 L |
1764 | // AES + AVX |
1765 | ||
2368c6bf L |
1766 | vaesdec, 0x66de, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1767 | vaesdeclast, 0x66df, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1768 | vaesenc, 0x66dc, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1769 | vaesenclast, 0x66dd, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexVVVV=1|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1770 | vaesimc, 0x66db, None, CpuAVX|CpuAES, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegXMM } | |
1771 | vaeskeygenassist, 0x66df, None, CpuAVX|CpuAES, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } | |
a5ff0eb2 | 1772 | |
ce2f5b3c L |
1773 | // PCLMUL + AVX |
1774 | ||
2368c6bf L |
1775 | vpclmulqdq, 0x6644, None, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } |
1776 | vpclmullqlqdq, 0x6644, 0x00, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1777 | vpclmulhqlqdq, 0x6644, 0x01, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1778 | vpclmullqhqdq, 0x6644, 0x10, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1779 | vpclmulhqhqdq, 0x6644, 0x11, CpuAVX|CpuPCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
ce2f5b3c | 1780 | |
48521003 IT |
1781 | // GFNI + AVX |
1782 | ||
2368c6bf L |
1783 | vgf2p8affineinvqb, 0x66cf, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1784 | vgf2p8affineqb, 0x66ce, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1785 | vgf2p8mulb, 0x66cf, None, CpuAVX|CpuGFNI, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
48521003 | 1786 | |
c7b8aa3a L |
1787 | // FSGSBASE, RDRND and F16C |
1788 | ||
2368c6bf L |
1789 | rdfsbase, 0xf30fae, 0, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } |
1790 | rdgsbase, 0xf30fae, 1, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1791 | rdrand, 0xfc7, 6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } | |
1792 | wrfsbase, 0xf30fae, 2, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1793 | wrgsbase, 0xf30fae, 3, CpuFSGSBase, Modrm|IgnoreSize|NoSuf, { Reg32|Reg64 } | |
1794 | vcvtph2ps, 0x6613, None, CpuF16C, Modrm|Vex|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
1795 | vcvtph2ps, 0x6613, None, CpuF16C, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM } | |
1796 | vcvtps2ph, 0x661d, None, CpuF16C, Modrm|Vex|Space0F3A|VexW0|NoSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
1797 | vcvtps2ph, 0x661d, None, CpuF16C, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } | |
c7b8aa3a | 1798 | |
c0f3af97 L |
1799 | // FMA instructions |
1800 | ||
edb7c8ec JB |
1801 | <fma:opc, 132:10, 213:20, 231:30> |
1802 | ||
2368c6bf L |
1803 | vfmadd<fma>p<sd>, 0x6688 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1804 | vfmadd<fma>s<sd>, 0x6689 | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1805 | vfmaddsub<fma>p<sd>, 0x6686 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1806 | vfmsub<fma>p<sd>, 0x668a | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1807 | vfmsub<fma>s<sd>, 0x668b | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1808 | vfmsubadd<fma>p<sd>, 0x6687 | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1809 | vfnmadd<fma>p<sd>, 0x668c | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1810 | vfnmadd<fma>s<sd>, 0x668d | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
1811 | vfnmsub<fma>p<sd>, 0x668e | 0x<fma:opc>, None, CpuFMA, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1812 | vfnmsub<fma>s<sd>, 0x668f | 0x<fma:opc>, None, CpuFMA, Modrm|VexLIG|Space0F38|VexVVVV|<sd:vexw>|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } | |
c0f3af97 | 1813 | |
42164a71 L |
1814 | // HLE prefixes |
1815 | ||
2368c6bf L |
1816 | xacquire, 0xf2, None, CpuHLE, NoSuf|IsPrefix, {} |
1817 | xrelease, 0xf3, None, CpuHLE, NoSuf|IsPrefix, {} | |
42164a71 L |
1818 | |
1819 | // RTM instructions | |
2368c6bf L |
1820 | xabort, 0xc6f8, None, CpuRTM, NoSuf, { Imm8 } |
1821 | xbegin, 0xc7f8, None, CpuRTM, JumpDword|NoSuf, { Disp16|Disp32 } | |
1822 | xend, 0xf01d5, None, CpuRTM, NoSuf, {} | |
1823 | xtest, 0xf01d6, None, CpuHLE|CpuRTM, NoSuf, {} | |
42164a71 | 1824 | |
6c30d220 | 1825 | // BMI2 instructions. |
9a182d04 JB |
1826 | bzhi, 0xf5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } |
1827 | mulx, 0xf2f6, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
1828 | pdep, 0xf2f5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
1829 | pext, 0xf3f5, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } | |
1830 | rorx, 0xf2f0, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1831 | sarx, 0xf3f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1832 | shlx, 0x66f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1833 | shrx, 0xf2f7, None, CpuBMI2, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
6c30d220 | 1834 | |
922d8de8 DR |
1835 | // FMA4 instructions |
1836 | ||
2368c6bf L |
1837 | vfmaddp<sd>, 0x6668 | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
1838 | vfmadds<sd>, 0x666a | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
1839 | vfmaddsubp<sd>, 0x665c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1840 | vfmsubaddp<sd>, 0x665e | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1841 | vfmsubp<sd>, 0x666c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1842 | vfmsubs<sd>, 0x666e | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
1843 | vfnmaddp<sd>, 0x6678 | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1844 | vfnmadds<sd>, 0x667a | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
1845 | vfnmsubp<sd>, 0x667c | <sd:opc>, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1846 | vfnmsubs<sd>, 0x667e | <sd:opc>, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|NoSuf, { <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } | |
922d8de8 | 1847 | |
5dd85c99 SP |
1848 | // XOP instructions |
1849 | ||
390ddd6f JB |
1850 | <xop:opc, b:0, w:1, d:2, q:3> |
1851 | <irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7> | |
1852 | <sign:opc, :00, u:20> | |
2f13234b | 1853 | |
2368c6bf L |
1854 | vfrczp<sd>, 0x80 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|NoSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } |
1855 | vfrczs<sd>, 0x82 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { <sd:elem>|RegXMM|Unspecified|BaseIndex, RegXMM } | |
1856 | vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|NoSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1857 | vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1858 | vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, <irel:imm>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1859 | vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1860 | vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
1861 | vphaddb<dq>, 0xc2 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1862 | vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1863 | vphadddq, 0xcb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1864 | vphaddub<dq>, 0xd2 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1865 | vphaddubw, 0xd1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1866 | vphaddudq, 0xdb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1867 | vphadduw<dq>, 0xd6 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1868 | vphaddw<dq>, 0xc6 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1869 | vphsubbw, 0xe1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1870 | vphsubdq, 0xe3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1871 | vphsubwd, 0xe2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|NoSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
1872 | vpmacsdd, 0x9e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1873 | vpmacsdqh, 0x9f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1874 | vpmacsdql, 0x97, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1875 | vpmacssdd, 0x8e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1876 | vpmacssdqh, 0x8f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1877 | vpmacssdql, 0x87, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1878 | vpmacsswd, 0x86, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1879 | vpmacssww, 0x85, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1880 | vpmacswd, 0x96, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1881 | vpmacsww, 0x95, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1882 | vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1883 | vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1884 | vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } | |
1885 | vprot<xop>, 0x90 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1886 | vprot<xop>, 0xc0 | <xop:opc>, None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1887 | vpsha<xop>, 0x98 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } | |
1888 | vpshl<xop>, 0x94 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } | |
390ddd6f JB |
1889 | |
1890 | <xop> | |
1891 | <irel> | |
1892 | <sign> | |
5dd85c99 | 1893 | |
f88c9eb0 SP |
1894 | // LWP instructions |
1895 | ||
2368c6bf L |
1896 | llwpcb, 0x12, 0, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } |
1897 | slwpcb, 0x12, 1, CpuLWP, Modrm|SpaceXOP09|NoSuf|Vex, { Reg32|Reg64 } | |
1898 | lwpval, 0x12, 1, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
1899 | lwpins, 0x12, 0, CpuLWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 } | |
f88c9eb0 | 1900 | |
f12dc422 L |
1901 | // BMI instructions |
1902 | ||
9a182d04 JB |
1903 | andn, 0xf2, None, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } |
1904 | bextr, 0xf7, None, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1905 | blsi, 0xf3, 3, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1906 | blsmsk, 0xf3, 2, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1907 | blsr, 0xf3, 1, CpuBMI, Modrm|CheckRegSize|Vex128|Space0F38|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
73e45eb2 | 1908 | tzcnt, 0xf30fbc, None, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
f12dc422 | 1909 | |
2a2a0f38 | 1910 | // TBM instructions |
9a182d04 JB |
1911 | bextr, 0x10, None, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP0A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } |
1912 | blcfill, 0x01, 1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1913 | blci, 0x02, 6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1914 | blcic, 0x01, 5, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1915 | blcmsk, 0x02, 1, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1916 | blcs, 0x01, 3, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1917 | blsfill, 0x01, 2, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1918 | blsic, 0x01, 6, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1919 | t1mskc, 0x01, 7, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
1920 | tzmsk, 0x01, 4, CpuTBM, Modrm|CheckRegSize|Vex128|SpaceXOP09|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } | |
2a2a0f38 | 1921 | |
40b8e679 L |
1922 | // AMD 3DNow! instructions. |
1923 | ||
2368c6bf L |
1924 | prefetch, 0xf0d, 0, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
1925 | prefetchw, 0xf0d, 1, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
1926 | femms, 0xf0e, None, Cpu3dnow, NoSuf, {} | |
1927 | pavgusb, 0xf0f, 0xbf, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1928 | pf2id, 0xf0f, 0x1d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1929 | pf2iw, 0xf0f, 0x1c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1930 | pfacc, 0xf0f, 0xae, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1931 | pfadd, 0xf0f, 0x9e, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1932 | pfcmpeq, 0xf0f, 0xb0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1933 | pfcmpge, 0xf0f, 0x90, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1934 | pfcmpgt, 0xf0f, 0xa0, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1935 | pfmax, 0xf0f, 0xa4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1936 | pfmin, 0xf0f, 0x94, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1937 | pfmul, 0xf0f, 0xb4, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1938 | pfnacc, 0xf0f, 0x8a, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1939 | pfpnacc, 0xf0f, 0x8e, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1940 | pfrcp, 0xf0f, 0x96, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1941 | pfrcpit1, 0xf0f, 0xa6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1942 | pfrcpit2, 0xf0f, 0xb6, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1943 | pfrsqit1, 0xf0f, 0xa7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1944 | pfrsqrt, 0xf0f, 0x97, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1945 | pfsub, 0xf0f, 0x9a, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1946 | pfsubr, 0xf0f, 0xaa, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1947 | pi2fd, 0xf0f, 0x0d, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1948 | pi2fw, 0xf0f, 0x0c, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1949 | pmulhrw, 0xf0f, 0xb7, Cpu3dnow, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
1950 | pswapd, 0xf0f, 0xbb, Cpu3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } | |
40b8e679 L |
1951 | |
1952 | // AMD extensions. | |
2368c6bf | 1953 | syscall, 0xf05, None, CpuSYSCALL, NoSuf, {} |
9a182d04 | 1954 | sysret, 0xf07, None, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, {} |
2368c6bf L |
1955 | swapgs, 0xf01f8, None, Cpu64, NoSuf, {} |
1956 | rdtscp, 0xf01f9, None, CpuRdtscp, NoSuf, {} | |
40b8e679 L |
1957 | |
1958 | // AMD Pacifica additions. | |
2368c6bf L |
1959 | clgi, 0xf01dd, None, CpuSVME, NoSuf, {} |
1960 | invlpga, 0xf01df, None, CpuSVME, NoSuf, {} | |
1961 | invlpga, 0xf01df, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword } | |
1962 | skinit, 0xf01de, None, CpuSVME, NoSuf, {} | |
1963 | skinit, 0xf01de, None, CpuSVME, IgnoreSize|NoSuf, { Acc|Dword } | |
1964 | stgi, 0xf01dc, None, CpuSVME, NoSuf, {} | |
1965 | vmgexit, 0xf30f01d9, None, CpuSEV_ES, NoSuf, {} | |
1966 | vmload, 0xf01da, None, CpuSVME, NoSuf, {} | |
1967 | vmload, 0xf01da, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
1968 | vmmcall, 0xf01d9, None, CpuSVME, NoSuf, {} | |
1969 | vmrun, 0xf01d8, None, CpuSVME, NoSuf, {} | |
1970 | vmrun, 0xf01d8, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
1971 | vmsave, 0xf01db, None, CpuSVME, NoSuf, {} | |
1972 | vmsave, 0xf01db, None, CpuSVME, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
40b8e679 L |
1973 | |
1974 | ||
1975 | // SSE4a instructions | |
2368c6bf L |
1976 | movntsd, 0xf20f2b, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } |
1977 | movntss, 0xf30f2b, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
1978 | extrq, 0x660f78, 0, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM } | |
1979 | extrq, 0x660f79, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } | |
1980 | insertq, 0xf20f79, None, CpuSSE4a, Modrm|NoSuf, { RegXMM, RegXMM } | |
1981 | insertq, 0xf20f78, None, CpuSSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM } | |
40b8e679 | 1982 | |
272a84b1 | 1983 | // LZCNT instruction |
73e45eb2 | 1984 | lzcnt, 0xf30fbd, None, CpuLZCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
272a84b1 L |
1985 | |
1986 | // POPCNT instruction | |
f0db6fb6 | 1987 | popcnt, 0xf30fb8, None, CpuPOPCNT, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
40b8e679 | 1988 | |
40b8e679 | 1989 | // VIA PadLock extensions. |
2368c6bf L |
1990 | xstore-rng, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} |
1991 | xcrypt-ecb, 0xf30fa7c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1992 | xcrypt-cbc, 0xf30fa7d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1993 | xcrypt-ctr, 0xf30fa7d8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1994 | xcrypt-cfb, 0xf30fa7e0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1995 | xcrypt-ofb, 0xf30fa7e8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1996 | montmul, 0xf30fa6c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1997 | xsha1, 0xf30fa6c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
1998 | xsha256, 0xf30fa6d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
40b8e679 | 1999 | // Aliases without hyphens. |
2368c6bf L |
2000 | xstorerng, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} |
2001 | xcryptecb, 0xf30fa7c8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
2002 | xcryptcbc, 0xf30fa7d0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
2003 | xcryptctr, 0xf30fa7d8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
2004 | xcryptcfb, 0xf30fa7e0, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
2005 | xcryptofb, 0xf30fa7e8, None, CpuPadLock, NoSuf|RepPrefixOk, {} | |
40b8e679 | 2006 | // Alias for xstore-rng. |
2368c6bf | 2007 | xstore, 0xfa7c0, None, CpuPadLock, NoSuf|RepPrefixOk, {} |
e2e1fcde L |
2008 | |
2009 | // Multy-precision Add Carry, rdseed instructions. | |
73e45eb2 JB |
2010 | adcx, 0x660f38f6, None, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } |
2011 | adox, 0xf30f38f6, None, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } | |
2368c6bf | 2012 | rdseed, 0xfc7, 7, CpuRdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } |
5c111e37 L |
2013 | |
2014 | // SMAP instructions. | |
2368c6bf L |
2015 | clac, 0xf01ca, None, CpuSMAP, NoSuf, {} |
2016 | stac, 0xf01cb, None, CpuSMAP, NoSuf, {} | |
7e8b059b L |
2017 | |
2018 | // BND prefix | |
2368c6bf | 2019 | bnd, 0xf2, None, CpuMPX, NoSuf|IsPrefix, {} |
7e8b059b L |
2020 | |
2021 | // MPX instructions. | |
2368c6bf L |
2022 | bndmk, 0xf30f1b, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } |
2023 | bndmov, 0x660f1a, None, CpuMPX, D|Modrm|NoSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND } | |
2024 | bndcl, 0xf30f1a, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } | |
2025 | bndcl, 0xf30f1a, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
2026 | bndcu, 0xf20f1a, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } | |
2027 | bndcu, 0xf20f1a, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
2028 | bndcn, 0xf20f1b, None, CpuMPX|CpuNo64, Modrm|Anysize|IgnoreSize|NoSuf, { Reg32|BaseIndex, RegBND } | |
2029 | bndcn, 0xf20f1b, None, CpuMPX|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf|NoRex64, { Reg64|BaseIndex, RegBND } | |
2030 | bndstx, 0x0f1b, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { RegBND, BaseIndex } | |
2031 | bndldx, 0x0f1a, None, CpuMPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } | |
a0046408 L |
2032 | |
2033 | // SHA instructions. | |
2368c6bf L |
2034 | sha1rnds4, 0xf3acc, None, CpuSHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } |
2035 | sha1nexte, 0xf38c8, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2036 | sha1msg1, 0xf38c9, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2037 | sha1msg2, 0xf38ca, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2038 | sha256rnds2, 0xf38cb, None, CpuSHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } | |
2039 | sha256rnds2, 0xf38cb, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2040 | sha256msg1, 0xf38cc, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
2041 | sha256msg2, 0xf38cd, None, CpuSHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } | |
43234a1e | 2042 | |
ff1982d5 IT |
2043 | // VPCLMULQDQ instructions |
2044 | ||
2368c6bf L |
2045 | vpclmulqdq, 0x6644, None, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } |
2046 | vpclmullqlqdq, 0x6644, 0x00, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
2047 | vpclmulhqlqdq, 0x6644, 0x01, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
2048 | vpclmullqhqdq, 0x6644, 0x10, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
2049 | vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } | |
ff1982d5 IT |
2050 | |
2051 | // VPCLMULQDQ instructions end | |
2052 | ||
43234a1e L |
2053 | // AVX512F instructions. |
2054 | ||
7091c612 | 2055 | #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL |
ae2387fe | 2056 | #define MaskingMorZ Masking=DYNAMIC_MASKING |
7091c612 | 2057 | |
73d214b2 JB |
2058 | <sdh:cpu:cpudq:ppfx:spfx:pfx:spc1:spc2:opc:vexw:elem, + |
2059 | s:CpuAVX512F:CpuAVX512DQ::f3:66:Space0F:Space0F38:0:VexW0:Dword, + | |
2060 | d:CpuAVX512F:CpuAVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, + | |
2061 | h:CpuAVX512_FP16:CpuAVX512_FP16::f3::EVexMap5:EVexMap6:0:VexW0:Word> | |
2062 | ||
4e0dd3ab | 2063 | // <Exy> is used for EVEX instructions with x/y suffixes. |
2064 | <Exy:vl:attr:sr:sae:src:dst, + | |
e07ae9a3 JB |
2065 | $z::EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, + |
2066 | $i:CpuAVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, + | |
2067 | $a:CpuAVX512VL:Disp8ShiftVL|ATTSyntax:::RegXMM|RegYMM|BaseIndex:RegXMM, + | |
2068 | x:CpuAVX512VL:EVex128|Disp8MemShift=4|ATTSyntax:::RegXMM|Unspecified|BaseIndex:RegXMM, + | |
2069 | y:CpuAVX512VL:EVex256|Disp8MemShift=5|ATTSyntax:::RegYMM|Unspecified|BaseIndex:RegXMM> | |
2070 | ||
2368c6bf L |
2071 | kand<bw>, 0x<bw:kpfx>41, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } |
2072 | kandn<bw>, 0x<bw:kpfx>42, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2073 | kor<bw>, 0x<bw:kpfx>45, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2074 | kxnor<bw>, 0x<bw:kpfx>46, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
2075 | kxor<bw>, 0x<bw:kpfx>47, None, <bw:kcpu>, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } | |
9a182d04 | 2076 | |
2368c6bf L |
2077 | kmov<bw>, 0x<bw:kpfx>90, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask|<bw:elem>|Unspecified|BaseIndex, RegMask } |
2078 | kmov<bw>, 0x<bw:kpfx>91, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, <bw:elem>|Unspecified|BaseIndex } | |
2079 | kmov<bw>, 0x<bw:kpfx>92, None, <bw:kcpu>, D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } | |
9a182d04 | 2080 | |
2368c6bf L |
2081 | knot<bw>, 0x<bw:kpfx>44, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } |
2082 | kortest<bw>, 0x<bw:kpfx>98, None, <bw:kcpu>, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } | |
9a182d04 | 2083 | |
2368c6bf L |
2084 | kshiftl<bw>, 0x6632, None, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } |
2085 | kshiftr<bw>, 0x6630, None, <bw:kcpu>, Modrm|Vex128|Space0F3A|<bw:vexw>|NoSuf, { Imm8, RegMask, RegMask } | |
9a182d04 | 2086 | |
2368c6bf | 2087 | kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } |
9a182d04 | 2088 | |
2368c6bf L |
2089 | vaddp<sdh>, 0x<sdh:ppfx>58, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2090 | vdivp<sdh>, 0x<sdh:ppfx>5e, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2091 | vmulp<sdh>, 0x<sdh:ppfx>59, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2092 | vsqrtp<sdh>, 0x<sdh:ppfx>51, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2093 | vsubp<sdh>, 0x<sdh:ppfx>5c, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
cf665fee | 2094 | |
2368c6bf L |
2095 | vadds<sdh>, 0x<sdh:spfx>58, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } |
2096 | vdivs<sdh>, 0x<sdh:spfx>5e, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2097 | vmuls<sdh>, 0x<sdh:spfx>59, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2098 | vsqrts<sdh>, 0x<sdh:spfx>51, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2099 | vsubs<sdh>, 0x<sdh:spfx>5C, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2100 | |
2368c6bf L |
2101 | valign<dq>, 0x6603, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2102 | vblendmp<sd>, 0x6665, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2103 | vpblendm<dq>, 0x6664, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2104 | vpermi2<dq>, 0x6676, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2105 | vpermi2p<sd>, 0x6677, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2106 | vpermt2<dq>, 0x667E, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2107 | vpermt2p<sd>, 0x667F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2108 | vpmaxs<dq>, 0x663D, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2109 | vpmaxu<dq>, 0x663F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2110 | vpmins<dq>, 0x6639, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2111 | vpminu<dq>, 0x663B, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2112 | vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2113 | vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2114 | vprolv<dq>, 0x6615, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2115 | vprorv<dq>, 0x6614, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2116 | vpsllv<dq>, 0x6647, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2117 | vpsrav<dq>, 0x6646, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2118 | vpsrlv<dq>, 0x6645, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2119 | vpternlog<dq>, 0x6625, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2120 | |
2368c6bf L |
2121 | vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2122 | vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
9a182d04 | 2123 | |
2368c6bf L |
2124 | vbroadcastf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } |
2125 | vbroadcasti64x4, 0x665B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2126 | |
2368c6bf L |
2127 | vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2128 | vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
9a182d04 | 2129 | |
2368c6bf L |
2130 | vpbroadcast<dq>, 0x6658 | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Disp8MemShift|NoSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2131 | vpbroadcast<dq>, 0x667c, None, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2132 | |
2368c6bf L |
2133 | vcmp<frel>p<sd>, 0x<sd:ppfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2134 | vcmpp<sd>, 0x<sd:ppfx>C2, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
9a182d04 | 2135 | |
2368c6bf L |
2136 | vcmp<frel>s<sd>, 0x<sd:spfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } |
2137 | vcmps<sd>, 0x<sd:spfx>C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegMask } | |
9a182d04 | 2138 | |
2368c6bf L |
2139 | vcomis<sdh>, 0x<sdh:ppfx>2f, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } |
2140 | vucomis<sdh>, 0x<sdh:ppfx>2e, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM } | |
9a182d04 | 2141 | |
2368c6bf L |
2142 | vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } |
2143 | vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
2144 | vpcompressq, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
2145 | vpcompressd, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
9a182d04 | 2146 | |
2368c6bf L |
2147 | vpscatterdd, 0x66A0, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } |
2148 | vpscatterdq, 0x66A0, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2149 | vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2150 | vpscatterqq, 0x66A1, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2151 | vscatterdpd, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2152 | vscatterdps, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseIndex } | |
2153 | vscatterqpd, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseIndex } | |
2154 | vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
9a182d04 | 2155 | |
2368c6bf L |
2156 | vcvtdq2pd, 0xF3E6, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
2157 | vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2158 | |
2368c6bf L |
2159 | vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2160 | vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 2161 | |
2368c6bf | 2162 | vcvtpd2dq<Exy>, 0xf2e6, None, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2163 | |
2368c6bf | 2164 | vcvtpd2ps<Exy>, 0x665a, None, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2165 | |
2368c6bf | 2166 | vcvtpd2udq<Exy>, 0x79, None, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
cf665fee | 2167 | |
2368c6bf | 2168 | vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } |
cf665fee | 2169 | |
2368c6bf | 2170 | vcvtps2dq, 0x665B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
cf665fee | 2171 | |
2368c6bf | 2172 | vcvtps2pd, 0x5A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
cf665fee | 2173 | |
2368c6bf | 2174 | vcvtps2ph, 0x661D, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
cf665fee | 2175 | |
1cb0ab18 | 2176 | vcvts<sd>2si, 0x<sd:spfx>2d, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
2368c6bf | 2177 | vcvts<sdh>2usi, 0x<sdh:spfx>79, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 2178 | |
2368c6bf | 2179 | vcvtsd2ss, 0xF25A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
cf665fee JB |
2180 | |
2181 | vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2182 | vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2183 | vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2184 | vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2185 | vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2186 | vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2187 | vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2188 | vcvtusi2sd, 0xF27B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2189 | ||
2190 | vcvtsi2ss, 0xF32A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2191 | vcvtsi2ss, 0xF32A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2192 | vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2193 | vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2194 | ||
2368c6bf | 2195 | vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } |
cf665fee | 2196 | |
2368c6bf L |
2197 | vcvttpd2dq<Exy>, 0x66e6, None, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } |
2198 | vcvttpd2udq<Exy>, 0x78, None, CpuAVX512F|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sae>, { <Exy:src>|Qword, <Exy:dst> } | |
cf665fee | 2199 | |
2368c6bf L |
2200 | vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2201 | vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 2202 | |
1cb0ab18 | 2203 | vcvtts<sd>2si, 0x<sd:spfx>2c, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
2368c6bf | 2204 | vcvtts<sdh>2usi, 0x<sdh:spfx>78, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 2205 | |
2368c6bf | 2206 | vcvtudq2ps, 0xF27A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2207 | |
2368c6bf L |
2208 | vexpandpd, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2209 | vpexpandq, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2210 | |
2368c6bf L |
2211 | vexpandps, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2212 | vpexpandd, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2213 | |
2368c6bf L |
2214 | vextractf32x4, 0x6619, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } |
2215 | vextracti32x4, 0x6639, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } | |
9a182d04 | 2216 | |
2368c6bf L |
2217 | vextractf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
2218 | vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } | |
9a182d04 | 2219 | |
2368c6bf L |
2220 | vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } |
2221 | vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } | |
9a182d04 | 2222 | |
2368c6bf L |
2223 | vfixupimmp<sd>, 0x6654, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2224 | vfixupimms<sd>, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
73d214b2 | 2225 | |
2368c6bf L |
2226 | vgetmantp<sdh>, 0x<sdh:pfx>26, None, <sdh:cpu>, Modrm|Masking=3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2227 | vgetmants<sdh>, 0x<sdh:pfx>27, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
73d214b2 | 2228 | |
2368c6bf L |
2229 | vrndscalep<sdh>, 0x<sdh:pfx>08 | <sdh:opc>, None, <sdh:cpu>, Modrm|Masking=3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2230 | vrndscales<sdh>, 0x<sdh:pfx>0a | <sdh:opc>, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
73d214b2 | 2231 | |
2368c6bf L |
2232 | vfmadd<fma>p<sdh>, 0x6688 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2233 | vfmadd<fma>s<sdh>, 0x6689 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2234 | vfmaddsub<fma>p<sdh>, 0x6686 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2235 | vfmsub<fma>p<sdh>, 0x668a | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2236 | vfmsub<fma>s<sdh>, 0x668b | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2237 | vfmsubadd<fma>p<sdh>, 0x6687 | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2238 | vfnmadd<fma>p<sdh>, 0x668c | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2239 | vfnmadd<fma>s<sdh>, 0x668d | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2240 | vfnmsub<fma>p<sdh>, 0x668e | 0x<fma:opc>, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2241 | vfnmsub<fma>s<sdh>, 0x668f | 0x<fma:opc>, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
73d214b2 | 2242 | |
2368c6bf L |
2243 | vscalefp<sdh>, 0x662c, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2244 | vscalefs<sdh>, 0x662d, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2245 | |
2368c6bf L |
2246 | vgatherdpd, 0x6692, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } |
2247 | vgatherdps, 0x6692, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } | |
2248 | vgatherqpd, 0x6693, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
2249 | vgatherqps, 0x6693, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2250 | vpgatherdd, 0x6690, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM } | |
2251 | vpgatherdq, 0x6690, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
2252 | vpgatherqd, 0x6691, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2253 | vpgatherqq, 0x6691, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2254 | |
2368c6bf | 2255 | vmovntdqa, 0x662A, None, CpuAVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2256 | |
2368c6bf L |
2257 | vgetexpp<sdh>, 0x6642, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc2>|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2258 | vgetexps<sdh>, 0x6643, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc2>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2259 | |
2368c6bf L |
2260 | vinsertf32x4, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2261 | vinserti32x4, 0x6638, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
9a182d04 | 2262 | |
2368c6bf L |
2263 | vinsertf64x4, 0x661A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } |
2264 | vinserti64x4, 0x663A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } | |
9a182d04 | 2265 | |
2368c6bf | 2266 | vinsertps, 0x6621, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } |
9a182d04 | 2267 | |
2368c6bf L |
2268 | vmaxp<sdh>, 0x<sdh:ppfx>5f, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2269 | vmaxs<sdh>, 0x<sdh:spfx>5f, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2270 | |
2368c6bf L |
2271 | vminp<sdh>, 0x<sdh:ppfx>5d, None, <sdh:cpu>, Modrm|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2272 | vmins<sdh>, 0x<sdh:spfx>5d, None, <sdh:cpu>, Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2273 | |
2368c6bf L |
2274 | vmovap<sd>, 0x<sd:ppfx>28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2275 | vmovntp<sd>, 0x<sd:ppfx>2B, None, CpuAVX512F, Modrm|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } | |
2276 | vmovup<sd>, 0x<sd:ppfx>10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|<sd:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2277 | |
2368c6bf | 2278 | vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM } |
9a182d04 | 2279 | |
2368c6bf | 2280 | vmovddup, 0xF212, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } |
9a182d04 | 2281 | |
2368c6bf L |
2282 | vmovdqa64, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2283 | vmovdqa32, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2284 | vmovntdq, 0x66E7, None, CpuAVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } | |
2285 | vmovdqu32, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2286 | vmovdqu64, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2287 | |
2368c6bf L |
2288 | vmovhlps, 0x12, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } |
2289 | vmovlhps, 0x16, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegXMM, RegXMM, RegXMM } | |
9a182d04 | 2290 | |
2368c6bf L |
2291 | vmovhp<sd>, 0x<sd:ppfx>16, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
2292 | vmovhp<sd>, 0x<sd:ppfx>17, None, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } | |
2293 | vmovlp<sd>, 0x<sd:ppfx>12, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2294 | vmovlp<sd>, 0x<sd:ppfx>13, None, CpuAVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex } | |
9a182d04 | 2295 | |
2368c6bf L |
2296 | vmovq, 0x666E, None, CpuAVX512F|Cpu64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM } |
2297 | vmovq, 0xF37E, None, CpuAVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } | |
2298 | vmovq, 0x66D6, None, CpuAVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } | |
9a182d04 | 2299 | |
2368c6bf L |
2300 | vmovs<sdh>, 0x<sdh:spfx>10, None, <sdh:cpu>, D|Modrm|EVexLIG|MaskingMorZ|<sdh:spc1>|<sdh:vexw>|Disp8MemShift|NoSuf, { <sdh:elem>|Unspecified|BaseIndex, RegXMM } |
2301 | vmovs<sdh>, 0x<sdh:spfx>10, None, <sdh:cpu>, D|Modrm|EVexLIG|Masking=3|<sdh:spc1>|VexVVVV|<sdh:vexw>|NoSuf, { RegXMM, RegXMM, RegXMM } | |
43234a1e | 2302 | |
2368c6bf L |
2303 | vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2304 | vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2305 | |
2368c6bf L |
2306 | vpabs<dq>, 0x661e | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2307 | vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2308 | vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2309 | vpand<dq>, 0x66db, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2310 | vpandn<dq>, 0x66df, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2311 | vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2312 | vpor<dq>, 0x66eb, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2313 | vpsub<dq>, 0x66fa | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2314 | vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2315 | vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2316 | vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2317 | vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2318 | vpxor<dq>, 0x66ef, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2319 | |
390ddd6f | 2320 | <irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6> |
865e2027 | 2321 | |
2368c6bf L |
2322 | vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2323 | vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2324 | vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2325 | vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2326 | vpcmp<dq>, 0x661f, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2327 | vpcmpu<dq>, 0x661e, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2328 | vpcmp<irel><dq>, 0x661f, <irel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2329 | vpcmp<irel>u<dq>, 0x661e, <irel:imm>, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
7091c612 | 2330 | |
2368c6bf L |
2331 | vptestm<dq>, 0x6627, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
2332 | vptestnm<dq>, 0xf327, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
7091c612 | 2333 | |
2368c6bf L |
2334 | vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2335 | vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
7091c612 | 2336 | |
2368c6bf L |
2337 | vpermilp<sd>, 0x6604 | <sd:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2338 | vpermilp<sd>, 0x660C | <sd:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
7091c612 | 2339 | |
2368c6bf L |
2340 | vpermpd, 0x6601, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2341 | vpermpd, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
2342 | vpermq, 0x6600, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
2343 | vpermq, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2344 | |
2368c6bf L |
2345 | vpmovdb, 0xF331, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } |
2346 | vpmovsdb, 0xF321, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
2347 | vpmovusdb, 0xF311, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
ae2387fe | 2348 | |
2368c6bf L |
2349 | vpmovdw, 0xF333, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
2350 | vpmovsdw, 0xF323, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2351 | vpmovusdw, 0xF313, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
ae2387fe | 2352 | |
2368c6bf L |
2353 | vpmovqb, 0xF332, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } |
2354 | vpmovsqb, 0xF322, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2355 | vpmovusqb, 0xF312, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } | |
ae2387fe | 2356 | |
2368c6bf L |
2357 | vpmovqd, 0xF335, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } |
2358 | vpmovsqd, 0xF325, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2359 | vpmovusqd, 0xF315, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
ae2387fe | 2360 | |
2368c6bf L |
2361 | vpmovqw, 0xF334, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } |
2362 | vpmovsqw, 0xF324, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
2363 | vpmovusqw, 0xF314, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } | |
43234a1e | 2364 | |
2368c6bf L |
2365 | vpmovsxbd, 0x6621, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } |
2366 | vpmovzxbd, 0x6631, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2367 | |
2368c6bf L |
2368 | vpmovsxbq, 0x6622, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } |
2369 | vpmovzxbq, 0x6632, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2370 | |
2368c6bf L |
2371 | vpmovsxdq, 0x6625, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
2372 | vpmovzxdq, 0x6635, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2373 | |
2368c6bf L |
2374 | vpmovsxwd, 0x6623, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } |
2375 | vpmovzxwd, 0x6633, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2376 | |
2368c6bf L |
2377 | vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } |
2378 | vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } | |
43234a1e | 2379 | |
2368c6bf L |
2380 | vprol<dq>, 0x6672, 1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2381 | vpror<dq>, 0x6672, 0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2382 | |
2368c6bf | 2383 | vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2384 | |
2368c6bf L |
2385 | vpsll<dq>, 0x66f2 | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2386 | vpsll<dq>, 0x6672 | <dq:opc>, 6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2387 | vpsra<dq>, 0x66e2, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2388 | vpsra<dq>, 0x6672, 4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2389 | vpsrl<dq>, 0x66d2 | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<dq:vexw>|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2390 | vpsrl<dq>, 0x6672 | <dq:opc>, 2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2391 | |
2368c6bf L |
2392 | vrcp14p<sd>, 0x664C, None, CpuAVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2393 | vrcp14s<sd>, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
43234a1e | 2394 | |
2368c6bf L |
2395 | vrsqrt14p<sd>, 0x664E, None, CpuAVX512F, Modrm|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2396 | vrsqrt14s<sd>, 0x664F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
43234a1e | 2397 | |
2368c6bf L |
2398 | vshuff32x4, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2399 | vshufi32x4, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2400 | |
2368c6bf L |
2401 | vshuff64x2, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } |
2402 | vshufi64x2, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
43234a1e | 2403 | |
2368c6bf | 2404 | vshufp<sd>, 0x<sd:ppfx>C6, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
43234a1e | 2405 | |
2368c6bf L |
2406 | vunpckhp<sd>, 0x<sd:ppfx>15, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2407 | vunpcklp<sd>, 0x<sd:ppfx>14, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
957d0955 | 2408 | |
43234a1e L |
2409 | // AVX512F instructions end. |
2410 | ||
2411 | // AVX512CD instructions. | |
2412 | ||
2368c6bf L |
2413 | vpbroadcastmb2q, 0xF32A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=2|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } |
2414 | vpbroadcastmw2d, 0xF33A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=1|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
43234a1e | 2415 | |
2368c6bf | 2416 | vpconflict<dq>, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2417 | |
2368c6bf | 2418 | vplzcnt<dq>, 0x6644, None, CpuAVX512CD, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
43234a1e | 2419 | |
43234a1e L |
2420 | // AVX512CD instructions end. |
2421 | ||
2422 | // AVX512ER instructions. | |
2423 | ||
2368c6bf | 2424 | vexp2p<sd>, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
43234a1e | 2425 | |
2368c6bf L |
2426 | vrcp28p<sd>, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
2427 | vrcp28s<sd>, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
43234a1e | 2428 | |
2368c6bf L |
2429 | vrsqrt28p<sd>, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf|SAE, { RegZMM|<sd:elem>|Unspecified|BaseIndex, RegZMM } |
2430 | vrsqrt28s<sd>, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
43234a1e L |
2431 | |
2432 | // AVX512ER instructions end. | |
2433 | ||
2434 | // AVX512PF instructions. | |
2435 | ||
2368c6bf L |
2436 | vgatherpf0dpd, 0x66C6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } |
2437 | vgatherpf0dps, 0x66C6, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2438 | vgatherpf0qp<sd>, 0x66C7, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
2439 | vgatherpf1dpd, 0x66C6, 2, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } | |
2440 | vgatherpf1dps, 0x66C6, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2441 | vgatherpf1qp<sd>, 0x66C7, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
d580ae46 | 2442 | |
2368c6bf L |
2443 | vscatterpf0dpd, 0x66C6, 5, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } |
2444 | vscatterpf0dps, 0x66C6, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2445 | vscatterpf0qp<sd>, 0x66C7, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
2446 | vscatterpf1dpd, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } | |
2447 | vscatterpf1dps, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } | |
2448 | vscatterpf1qp<sd>, 0x66C7, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB512|NoSuf, { <sd:elem>|Unspecified|BaseIndex } | |
43234a1e | 2449 | |
43234a1e | 2450 | // AVX512PF instructions end. |
963f3586 | 2451 | |
dcf893b5 IT |
2452 | // CpuPREFETCHWT1 instructions. |
2453 | ||
2368c6bf | 2454 | prefetchwt1, 0x0F0D, 2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
dcf893b5 IT |
2455 | |
2456 | // CpuPREFETCHWT1 instructions end. | |
2457 | ||
963f3586 IT |
2458 | // CLFLUSHOPT instructions. |
2459 | ||
2368c6bf | 2460 | clflushopt, 0x660fae, 7, CpuClflushOpt, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
963f3586 IT |
2461 | |
2462 | // CLFLUSHOPT instructions end. | |
2463 | ||
2464 | // XSAVES/XRSTORS instructions. | |
2465 | ||
2368c6bf L |
2466 | xrstors, 0xfc7, 3, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } |
2467 | xrstors64, 0xfc7, 3, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } | |
2468 | xsaves, 0xfc7, 5, CpuXSAVES, Modrm|NoSuf, { Unspecified|BaseIndex } | |
2469 | xsaves64, 0xfc7, 5, CpuXSAVES|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } | |
963f3586 IT |
2470 | |
2471 | // XSAVES instructions end. | |
2472 | ||
2473 | // XSAVEC instructions. | |
2474 | ||
2368c6bf L |
2475 | xsavec, 0xfc7, 4, CpuXSAVEC, Modrm|NoSuf, { Unspecified|BaseIndex } |
2476 | xsavec64, 0xfc7, 4, CpuXSAVEC|Cpu64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex } | |
963f3586 IT |
2477 | |
2478 | // XSAVEC instructions end. | |
2cf200a4 IT |
2479 | |
2480 | // SGX instructions. | |
2481 | ||
2368c6bf L |
2482 | encls, 0xf01cf, None, CpuSE1, NoSuf, {} |
2483 | enclu, 0xf01d7, None, CpuSE1, NoSuf, {} | |
2484 | enclv, 0xf01c0, None, CpuSE1, NoSuf, {} | |
2cf200a4 IT |
2485 | |
2486 | // SGX instructions end. | |
b28d1bda IT |
2487 | |
2488 | // AVX512VL instructions. | |
2489 | ||
2368c6bf L |
2490 | vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } |
2491 | vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2492 | vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2493 | vgatherqp<sd>, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM } | |
2494 | vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } | |
2495 | vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2496 | vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2497 | vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM } | |
2498 | vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
2499 | vpgatherq<dq>, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { <dq:elem>|Unspecified|BaseIndex, RegXMM } | |
2500 | vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { Dword|Unspecified|BaseIndex, RegXMM } | |
2501 | vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } | |
2502 | ||
2503 | vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2504 | vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2505 | vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } | |
2506 | vpscatterq<dq>, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<dq:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <dq:elem>|Unspecified|BaseIndex } | |
2507 | vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2508 | vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } | |
2509 | vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } | |
2510 | vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2511 | vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegYMM, Dword|Unspecified|BaseIndex } | |
2512 | vscatterqp<sd>, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|<sd:vexw>|Disp8MemShift|VecSIB128|NoSuf, { RegXMM, <sd:elem>|Unspecified|BaseIndex } | |
2513 | vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|NoSuf, { RegYMM, Qword|Unspecified|BaseIndex } | |
2514 | vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|NoSuf, { RegXMM, Dword|Unspecified|BaseIndex } | |
2515 | ||
2516 | vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2517 | vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2518 | vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2519 | vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2520 | ||
2521 | vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2522 | vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2523 | ||
2524 | vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2525 | vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2526 | ||
2527 | vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2528 | vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } | |
2529 | ||
2530 | vmovddup, 0xF212, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2531 | ||
2532 | vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2533 | vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2534 | vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2535 | vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2536 | vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2537 | vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2538 | ||
2539 | vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2540 | vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2541 | vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2542 | vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2543 | vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2544 | vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2545 | ||
2546 | vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2547 | vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2548 | vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2549 | vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2550 | vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } | |
2551 | vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2552 | ||
2553 | vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2554 | vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2555 | vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2556 | vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2557 | vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2558 | vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2559 | ||
2560 | vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2561 | vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2562 | vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2563 | vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2564 | vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } | |
2565 | vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2566 | ||
2567 | vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
2568 | vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
2569 | vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
2570 | vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
2571 | ||
2572 | vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } | |
2573 | vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2574 | vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } | |
2575 | vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2576 | ||
2577 | vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2578 | vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2579 | vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2580 | vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2581 | ||
2582 | vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2583 | vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2584 | vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2585 | vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2586 | ||
2587 | vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
2588 | vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
2589 | vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } | |
2590 | vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } | |
7ac20022 | 2591 | |
b28d1bda | 2592 | // AVX512VL instructions end. |
99282af6 | 2593 | |
e771e7c9 | 2594 | // AVX512BW instructions. |
1ba585e8 | 2595 | |
2368c6bf L |
2596 | kadd<dq>, 0x<dq:kpfx>4a, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } |
2597 | kand<dq>, 0x<dq:kpfx>41, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } | |
2598 | kandn<dq>, 0x<dq:kpfx>42, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } | |
2599 | kmov<dq>, 0x<dq:kpfx>90, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask|<dq:elem>|Unspecified|BaseIndex, RegMask } | |
2600 | kmov<dq>, 0x<dq:kpfx>91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, <dq:elem>|Unspecified|BaseIndex } | |
2601 | kmov<dq>, 0xf292, None, CpuAVX512BW, D|Modrm|Vex128|Space0F|<dq:vexw64>|NoSuf, { <dq:gpr>, RegMask } | |
2602 | knot<dq>, 0x<dq:kpfx>44, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } | |
2603 | kor<dq>, 0x<dq:kpfx>45, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } | |
2604 | kortest<dq>, 0x<dq:kpfx>98, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } | |
2605 | ktest<dq>, 0x<dq:kpfx>99, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|NoSuf, { RegMask, RegMask } | |
2606 | kxnor<dq>, 0x<dq:kpfx>46, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf, { RegMask, RegMask, RegMask } | |
2607 | kxor<dq>, 0x<dq:kpfx>47, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|NoSuf|Optimize, { RegMask, RegMask, RegMask } | |
2608 | kunpckdq, 0x4B, None, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=2|NoSuf, { RegMask, RegMask, RegMask } | |
2609 | kunpckwd, 0x4B, None, CpuAVX512BW, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|NoSuf, { RegMask, RegMask, RegMask } | |
2610 | kshiftl<dq>, 0x6633, None, CpuAVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } | |
2611 | kshiftr<dq>, 0x6631, None, CpuAVX512BW, Modrm|Vex128|Space0F3A|<dq:vexw>|NoSuf, { Imm8, RegMask, RegMask } | |
2612 | ||
2613 | vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2614 | ||
2615 | vmovdqu8, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2616 | vmovdqu16, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2617 | ||
2618 | vpabs<bw>, 0x661c | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2619 | vpmaxsb, 0x663C, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2620 | vpminsb, 0x6638, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2621 | vpshufb, 0x6600, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2622 | ||
2623 | vpmaddubsw, 0x6604, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2624 | vpmaxuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2625 | vpminuw, 0x663A, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2626 | vpmulhrsw, 0x660B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2627 | ||
2628 | vpackssdw, 0x666B, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2629 | vpacksswb, 0x6663, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2630 | vpackuswb, 0x6667, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2631 | vpackusdw, 0x662B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2632 | ||
2633 | vpadd<bw>, 0x66fc | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2634 | vpadds<bw>, 0x66ec | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2635 | vpaddus<bw>, 0x66dc | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2636 | vpavg<bw>, 0x66e0 | (3 * <bw:opc>), None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2637 | vpmaxub, 0x66DE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2638 | vpminub, 0x66DA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2639 | vpsub<bw>, 0x66f8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2640 | vpsubs<bw>, 0x66e8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2641 | vpsubus<bw>, 0x66d8 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2642 | vpunpckhbw, 0x6668, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2643 | vpunpcklbw, 0x6660, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2644 | ||
2645 | vpmaxsw, 0x66EE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2646 | vpminsw, 0x66EA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2647 | vpmulhuw, 0x66E4, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2648 | vpmulhw, 0x66E5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2649 | vpmullw, 0x66D5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2650 | vpsllw, 0x6671, 6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2651 | vpsllw, 0x66F1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2652 | vpsraw, 0x6671, 4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2653 | vpsraw, 0x66E1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2654 | vpsrlw, 0x6671, 2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2655 | vpsrlw, 0x66D1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2656 | vpunpckhwd, 0x6669, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2657 | vpunpcklwd, 0x6661, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2658 | ||
2659 | vpalignr, 0x660F, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2660 | ||
2661 | vpblendm<bw>, 0x6666, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2662 | vpbroadcast<bw>, 0x6678 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|<bw:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2663 | vpbroadcast<bw>, 0x667a | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|NoSuf, { Reg32, RegXMM|RegYMM|RegZMM } | |
2664 | ||
2665 | vpermi2<bw>, 0x6675, None, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2666 | vpermt2<bw>, 0x667d, None, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2667 | vperm<bw>, 0x668d, None, <bw:cpubmi>, Modrm|Masking=3|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2668 | vpsllvw, 0x6612, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2669 | vpsravw, 0x6611, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2670 | vpsrlvw, 0x6610, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2671 | ||
2672 | vpcmpeq<bw>, 0x6674 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2673 | vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2674 | vpcmp<bw>, 0x663f, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2675 | vpcmpu<bw>, 0x663e, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2676 | vpcmp<irel><bw>, 0x663f, <irel:imm>, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2677 | vpcmp<irel>u<bw>, 0x663e, <irel:imm>, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2678 | ||
2679 | vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2680 | vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2681 | ||
2682 | vpextrw, 0x66C5, None, CpuAVX512BW, Load|Modrm|EVex128|Space0F|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } | |
2683 | vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX512BW, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } | |
2684 | vpextr<bw>, 0x6614 | <bw:opc>, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift|NoSuf, { Imm8, RegXMM, <bw:elem>|Unspecified|BaseIndex } | |
2685 | ||
2686 | vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
2687 | vpinsrw, 0x66C4, None, CpuAVX512BW, Modrm|EVex128|Space0F|VexWIG|VexVVVV|Disp8MemShift=1|NoSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2688 | vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } | |
2689 | vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2690 | ||
2691 | vpmaddwd, 0x66F5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2692 | ||
2693 | vpmov<bw>2m, 0xf329, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } | |
2694 | vpmovm2<bw>, 0xf328, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38|<bw:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
2695 | ||
2696 | vpmovswb, 0xF320, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2697 | vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2698 | vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2699 | ||
2700 | vpmovuswb, 0xF310, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2701 | vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2702 | vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2703 | ||
2704 | vpmovwb, 0xF330, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } | |
2705 | vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } | |
2706 | vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } | |
2707 | ||
2708 | vpmovsxbw, 0x6620, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
2709 | vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2710 | vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2711 | vpmovzxbw, 0x6630, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } | |
2712 | vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } | |
2713 | vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } | |
2714 | ||
2715 | vpsadbw, 0x66F6, None, CpuAVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2716 | ||
2717 | vpshufhw, 0xF370, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2718 | vpshuflw, 0xF270, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2719 | ||
2720 | vptestm<bw>, 0x6626, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
2721 | vptestnm<bw>, 0xf326, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
1ba585e8 IT |
2722 | |
2723 | // AVX512BW instructions end. | |
90a915bf IT |
2724 | |
2725 | // AVX512DQ instructions. | |
2726 | ||
e07ae9a3 JB |
2727 | <xyz:vl:attr:sr:att:src, + |
2728 | $i::Disp8ShiftVL|IntelSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, + | |
2729 | $a::Disp8ShiftVL|ATTSyntax:StaticRounding|SAE::RegXMM|RegYMM|RegZMM|BaseIndex, + | |
2730 | z::EVex512|Disp8MemShift=6:StaticRounding|SAE:ATTSyntax:RegZMM|Unspecified|BaseIndex, + | |
2731 | x:CpuAVX512VL:EVex128|Disp8MemShift=4::ATTSyntax:RegXMM|Unspecified|BaseIndex, + | |
2732 | y:CpuAVX512VL:EVex256|Disp8MemShift=5::ATTSyntax:RegYMM|Unspecified|BaseIndex> | |
2733 | ||
2368c6bf L |
2734 | kadd<bw>, 0x<bw:kpfx>4A, None, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } |
2735 | ktest<bw>, 0x<bw:kpfx>99, None, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } | |
9a182d04 | 2736 | |
2368c6bf L |
2737 | vandnp<sd>, 0x<sd:ppfx>55, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2738 | vandp<sd>, 0x<sd:ppfx>54, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2739 | vorp<sd>, 0x<sd:ppfx>56, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2740 | vxorp<sd>, 0x<sd:ppfx>57, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2741 | |
2368c6bf L |
2742 | vbroadcastf32x2, 0x6619, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2743 | vbroadcastf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
2744 | vbroadcasti32x2, 0x6659, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
2745 | vbroadcasti32x8, 0x665B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } | |
9a182d04 | 2746 | |
2368c6bf L |
2747 | vbroadcastf64x2, 0x661A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } |
2748 | vbroadcasti64x2, 0x665A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } | |
9a182d04 | 2749 | |
2368c6bf L |
2750 | vcvtpd2qq, 0x667B, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2751 | vcvtpd2uqq, 0x6679, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2752 | |
2368c6bf L |
2753 | vcvtps2qq, 0x667B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
2754 | vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2755 | vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2756 | vcvtps2uqq, 0x6679, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } | |
2757 | vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2758 | vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
9a182d04 | 2759 | |
2368c6bf L |
2760 | vcvtqq2pd, 0xF3E6, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2761 | vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2762 | |
2368c6bf | 2763 | vcvtqq2ps<Exy>, 0x5b, None, CpuAVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
9a182d04 | 2764 | |
2368c6bf L |
2765 | vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2766 | vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2767 | |
2368c6bf L |
2768 | vcvttps2qq, 0x667A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } |
2769 | vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2770 | vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
2771 | vcvttps2uqq, 0x6678, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } | |
2772 | vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } | |
2773 | vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } | |
9a182d04 | 2774 | |
2368c6bf | 2775 | vcvtuqq2ps<Exy>, 0xf27a, None, CpuAVX512DQ|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|Space0F|VexW1|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Qword, <Exy:dst> } |
9a182d04 | 2776 | |
2368c6bf L |
2777 | vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } |
2778 | vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } | |
2779 | vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } | |
2780 | vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } | |
9a182d04 | 2781 | |
2368c6bf L |
2782 | vpextr<dq>, 0x6616, None, CpuAVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex } |
2783 | vpinsr<dq>, 0x6622, None, CpuAVX512DQ|<dq:cpu64>, Modrm|EVex128|Space0F3A|VexVVVV|<dq:vexw64>|Disp8MemShift|NoSuf, { Imm8, <dq:gpr>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2784 | |
2368c6bf L |
2785 | vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } |
2786 | vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } | |
2787 | vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
2788 | vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } | |
9a182d04 | 2789 | |
2368c6bf L |
2790 | vfpclassp<sd>, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } |
2791 | vfpclassp<sd>, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask } | |
2792 | vfpclassp<sd>z, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } | |
2793 | vfpclassp<sd>x, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegMask } | |
2794 | vfpclassp<sd>y, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM|<sd:elem>|Unspecified|BaseIndex, RegMask } | |
2795 | vfpclasss<sdh>, 0x<sdh:pfx>67, None, <sdh:cpudq>, Modrm|EVexLIG|Masking=2|Space0F3A|<sdh:vexw>|Disp8MemShift|NoSuf, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegMask } | |
9a182d04 | 2796 | |
2368c6bf L |
2797 | vpmov<dq>2m, 0xf339, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } |
2798 | vpmovm2<dq>, 0xf338, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } | |
9a182d04 | 2799 | |
2368c6bf | 2800 | vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
9a182d04 | 2801 | |
2368c6bf L |
2802 | vrangep<sd>, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2803 | vranges<sd>, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
9a182d04 | 2804 | |
2368c6bf L |
2805 | vreducep<sdh>, 0x<sdh:pfx>56, None, <sdh:cpudq>, Modrm|Masking=3|Space0F3A|<sdh:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2806 | vreduces<sdh>, 0x<sdh:pfx>57, None, <sdh:cpudq>, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV|<sdh:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM, RegXMM } | |
90a915bf IT |
2807 | |
2808 | // AVX512DQ instructions end. | |
c5e7287a IT |
2809 | |
2810 | // CLWB instructions. | |
2811 | ||
2368c6bf | 2812 | clwb, 0x660fae, 6, CpuCLWB, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
c5e7287a IT |
2813 | |
2814 | // CLWB instructions end. | |
9d8596f0 | 2815 | |
2cc1b5aa IT |
2816 | // AVX512IFMA instructions |
2817 | ||
2368c6bf L |
2818 | vpmadd52huq, 0x66B5, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2819 | vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2cc1b5aa IT |
2820 | |
2821 | // AVX512IFMA instructions end | |
14f195c9 | 2822 | |
4321af3e HW |
2823 | // AVX-IFMA instructions. |
2824 | ||
2368c6bf L |
2825 | vpmadd52huq, 0x66B5, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
2826 | vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
4321af3e HW |
2827 | |
2828 | // AVX-IFMA instructions end. | |
2829 | ||
14f195c9 IT |
2830 | // AVX512VBMI instructions |
2831 | ||
2368c6bf | 2832 | vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
14f195c9 IT |
2833 | |
2834 | // AVX512VBMI instructions end | |
920d2ddc IT |
2835 | |
2836 | // AVX512_4FMAPS instructions | |
2837 | ||
2368c6bf L |
2838 | v4fmaddps, 0xf29a, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } |
2839 | v4fnmaddps, 0xf2aa, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } | |
2840 | v4fmaddss, 0xf29b, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
2841 | v4fnmaddss, 0xf2ab, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
920d2ddc IT |
2842 | |
2843 | // AVX512_4FMAPS instructions end | |
029f3522 | 2844 | |
47acf0bd IT |
2845 | // AVX512_4VNNIW instructions |
2846 | ||
2368c6bf L |
2847 | vp4dpwssd, 0xf252, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } |
2848 | vp4dpwssds, 0xf253, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } | |
47acf0bd | 2849 | |
620214f7 IT |
2850 | // AVX512_4VNNIW instructions end |
2851 | ||
2852 | // AVX512_VPOPCNTDQ instructions | |
2853 | ||
2368c6bf | 2854 | vpopcnt<dq>, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
620214f7 IT |
2855 | |
2856 | // AVX512_VPOPCNTDQ instructions end | |
47acf0bd | 2857 | |
53467f57 IT |
2858 | // AVX512_VBMI2 instructions |
2859 | ||
2368c6bf L |
2860 | vpcompressb, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } |
2861 | vpcompressw, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } | |
53467f57 | 2862 | |
2368c6bf L |
2863 | vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
2864 | vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
53467f57 | 2865 | |
2368c6bf L |
2866 | vpshldv<dq>, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2867 | vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 2868 | |
2368c6bf L |
2869 | vpshrdv<dq>, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2870 | vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 2871 | |
2368c6bf L |
2872 | vpshld<dq>, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2873 | vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 | 2874 | |
2368c6bf L |
2875 | vpshrd<dq>, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2876 | vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
53467f57 IT |
2877 | |
2878 | // AVX512_VBMI2 instructions end | |
2879 | ||
8cfcb765 IT |
2880 | // AVX512_VNNI instructions |
2881 | ||
2368c6bf L |
2882 | vpdpbusd, 0x6650, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2883 | vpdpwssd, 0x6652, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
8cfcb765 | 2884 | |
2368c6bf L |
2885 | vpdpbusds, 0x6651, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2886 | vpdpwssds, 0x6653, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
8cfcb765 IT |
2887 | |
2888 | // AVX512_VNNI instructions end | |
2889 | ||
837e225b JB |
2890 | // AVX_VNNI instructions |
2891 | ||
2368c6bf L |
2892 | vpdpbusd, 0x6650, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
2893 | vpdpwssd, 0x6652, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
837e225b | 2894 | |
2368c6bf L |
2895 | vpdpbusds, 0x6651, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } |
2896 | vpdpwssds, 0x6653, None, CpuAVX_VNNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } | |
837e225b JB |
2897 | |
2898 | // AVX_VNNI instructions end | |
2899 | ||
23ae61ad CL |
2900 | // AVX-VNNI-INT8 instructions. |
2901 | ||
2368c6bf L |
2902 | vpdpbuud, 0x50, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } |
2903 | vpdpbuuds, 0x51, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
2904 | vpdpbssd, 0xf250, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
2905 | vpdpbssds, 0xf251, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
2906 | vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
2907 | vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } | |
23ae61ad CL |
2908 | |
2909 | // AVX-VNNI-INT8 instructions end. | |
2910 | ||
ee6872be IT |
2911 | // AVX512_BITALG instructions |
2912 | ||
2368c6bf | 2913 | vpopcnt<bw>, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
ee6872be | 2914 | |
2368c6bf | 2915 | vpshufbitqmb, 0x668f, None, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
ee6872be IT |
2916 | |
2917 | // AVX512_BITALG instructions end | |
2918 | ||
48521003 IT |
2919 | // AVX512 + GFNI instructions |
2920 | ||
2368c6bf L |
2921 | vgf2p8affineinvqb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2922 | vgf2p8affineqb, 0x66ce, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2923 | vgf2p8mulb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
48521003 IT |
2924 | |
2925 | // AVX512 + GFNI instructions end | |
2926 | ||
8dcf1fad IT |
2927 | // AVX512 + VAES instructions |
2928 | ||
2368c6bf L |
2929 | vaesdec, 0x66de, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2930 | vaesdeclast, 0x66df, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2931 | vaesenc, 0x66dc, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2932 | vaesenclast, 0x66dd, None, CpuVAES|CpuAVX512F, Modrm|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
8dcf1fad IT |
2933 | |
2934 | // AVX512 + VAES instructions end | |
2935 | ||
ff1982d5 IT |
2936 | // AVX512 + VPCLMULQDQ instructions |
2937 | ||
2368c6bf L |
2938 | vpclmulqdq, 0x6644, None, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
2939 | vpclmullqlqdq, 0x6644, 0x00, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2940 | vpclmulhqlqdq, 0x6644, 0x01, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2941 | vpclmullqhqdq, 0x6644, 0x10, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
2942 | vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ|CpuAVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } | |
ff1982d5 IT |
2943 | |
2944 | // AVX512 + VPCLMULQDQ instructions end | |
2945 | ||
646cc3e0 GG |
2946 | // INVLPGB instructions |
2947 | ||
2368c6bf L |
2948 | invlpgb, 0xf01fe, None, CpuINVLPGB, NoSuf, {} |
2949 | invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
646cc3e0 GG |
2950 | |
2951 | // INVLPGB instructions end | |
2952 | ||
2953 | // TLBSYNC instructions | |
2954 | ||
2368c6bf | 2955 | tlbsync, 0xf01ff, None, CpuTLBSYNC, NoSuf, {} |
646cc3e0 GG |
2956 | |
2957 | // TLBSYNC instructions end | |
2958 | ||
029f3522 GG |
2959 | // CLZERO instructions |
2960 | ||
2368c6bf L |
2961 | clzero, 0xf01fc, None, CpuCLZERO, NoSuf, {} |
2962 | clzero, 0xf01fc, None, CpuCLZERO, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } | |
029f3522 GG |
2963 | |
2964 | // CLZERO instructions end | |
2965 | ||
9916071f | 2966 | // MONITORX/MWAITX instructions |
474da251 | 2967 | |
2368c6bf L |
2968 | monitorx, 0xf01fa, None, CpuMWAITX, NoSuf, {} |
2969 | monitorx, 0xf01fa, None, CpuMWAITX, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
a79eaed6 | 2970 | // The 64-bit form exists only for compatibility with older gas. |
2368c6bf | 2971 | monitorx, 0xf01fa, None, CpuMWAITX|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } |
9916071f | 2972 | |
2368c6bf | 2973 | mwaitx, 0xf01fb, None, CpuMWAITX, NoSuf, {} |
a79eaed6 | 2974 | // The 64-bit form exists only for compatibility with older gas. |
2368c6bf | 2975 | mwaitx, 0xf01fb, None, CpuMWAITX, CheckRegSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword } |
474da251 | 2976 | |
9916071f | 2977 | // MONITORX/MWAITX instructions end |
8eab4136 L |
2978 | |
2979 | // OSPKE instructions. | |
2980 | ||
2368c6bf L |
2981 | rdpkru, 0xf01ee, None, CpuOSPKE, NoSuf, {} |
2982 | wrpkru, 0xf01ef, None, CpuOSPKE, NoSuf, {} | |
8eab4136 L |
2983 | |
2984 | // OSPKE instructions end. | |
8bc52696 AF |
2985 | |
2986 | // RDPID instructions. | |
2987 | ||
2368c6bf L |
2988 | rdpid, 0xf30fc7, 7, CpuRDPID|CpuNo64, Modrm|IgnoreSize|NoSuf, { Reg32 } |
2989 | rdpid, 0xf30fc7, 7, CpuRDPID|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } | |
8bc52696 AF |
2990 | |
2991 | // RDPID instructions end. | |
6b40c462 L |
2992 | |
2993 | // PTWRITE instructions. | |
2994 | ||
73e45eb2 JB |
2995 | ptwrite, 0xf30fae, 4, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex } |
2996 | ptwrite, 0xf30fae, 4, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex } | |
6b40c462 L |
2997 | |
2998 | // PTWRITE instructions end. | |
603555e5 L |
2999 | |
3000 | // CET instructions. | |
3001 | ||
2368c6bf L |
3002 | incsspd, 0xf30fae, 5, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } |
3003 | incsspq, 0xf30fae, 5, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } | |
3004 | rdsspd, 0xf30f1e, 1, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32 } | |
3005 | rdsspq, 0xf30f1e, 1, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64 } | |
3006 | saveprevssp, 0xf30f01ea, None, CpuSHSTK, NoSuf, {} | |
3007 | rstorssp, 0xf30f01, 5, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
3008 | wrssd, 0x0f38f6, None, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } | |
3009 | wrssq, 0x0f38f6, None, CpuSHSTK|Cpu64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } | |
3010 | wrussd, 0x660f38f5, None, CpuSHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } | |
3011 | wrussq, 0x660f38f5, None, CpuSHSTK|Cpu64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } | |
3012 | setssbsy, 0xf30f01e8, None, CpuSHSTK, NoSuf, {} | |
3013 | clrssbsy, 0xf30fae, 6, CpuSHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } | |
3014 | endbr64, 0xf30f1efa, None, CpuIBT, NoSuf, {} | |
3015 | endbr32, 0xf30f1efb, None, CpuIBT, NoSuf, {} | |
603555e5 | 3016 | |
04ef582a | 3017 | // notrack prefix |
2368c6bf | 3018 | notrack, 0x3e, None, CpuIBT, NoSuf|IsPrefix, {} |
04ef582a | 3019 | |
603555e5 | 3020 | // CET instructions end. |
3233d7d0 IT |
3021 | |
3022 | // WBNOINVD instruction. | |
3023 | ||
2368c6bf | 3024 | wbnoinvd, 0xf30f09, None, CpuWBNOINVD, NoSuf, {} |
3233d7d0 IT |
3025 | |
3026 | // WBNOINVD instruction end. | |
be3a8dca IT |
3027 | |
3028 | // PCONFIG instruction. | |
3029 | ||
2368c6bf | 3030 | pconfig, 0x0f01c5, None, CpuPCONFIG, NoSuf, {} |
be3a8dca IT |
3031 | |
3032 | // PCONFIG instruction end. | |
de89d0a3 IT |
3033 | |
3034 | // WAITPKG instructions. | |
3035 | ||
2368c6bf L |
3036 | umonitor, 0xf30fae, 6, CpuWAITPKG, Modrm|AddrPrefixOpReg|NoSuf, { Reg16|Reg32|Reg64 } |
3037 | tpause, 0x660fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } | |
3038 | tpause, 0x660fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } | |
3039 | umwait, 0xf20fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32 } | |
3040 | umwait, 0xf20fae, 6, CpuWAITPKG, Modrm|IgnoreSize|NoSuf, { Reg32, RegD|Dword, Acc|Dword } | |
de89d0a3 IT |
3041 | |
3042 | // WAITPKG instructions end. | |
c48935d7 IT |
3043 | |
3044 | // CLDEMOTE instructions. | |
3045 | ||
2368c6bf | 3046 | cldemote, 0x0f1c, 0, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
c48935d7 IT |
3047 | |
3048 | // CLDEMOTE instructions end. | |
c0a30a9f L |
3049 | |
3050 | // MOVDIR[I,64B] instructions. | |
3051 | ||
8ee52bcf | 3052 | movdiri, 0xf38f9, None, CpuMOVDIRI, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
2368c6bf | 3053 | movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
c0a30a9f L |
3054 | |
3055 | // MOVEDIR instructions end. | |
d6aab7a1 XG |
3056 | |
3057 | // AVX512_BF16 instructions. | |
3058 | ||
2368c6bf | 3059 | vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
d6aab7a1 | 3060 | |
2368c6bf | 3061 | vcvtneps2bf16<Exy>, 0xf372, None, CpuAVX512_BF16|<Exy:vl>, Modrm|Space0F38|<Exy:attr>|Masking=3|VexW0|Broadcast|NoSuf, { <Exy:src>|Dword, <Exy:dst> } |
d6aab7a1 | 3062 | |
2368c6bf | 3063 | vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
d6aab7a1 | 3064 | |
d6aab7a1 | 3065 | // AVX512_BF16 instructions end. |
5d79adc4 | 3066 | |
01d8ce74 | 3067 | // AVX-NE-CONVERT instructions. |
3068 | ||
2368c6bf L |
3069 | vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } |
3070 | vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|NoSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3071 | vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3072 | vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3073 | vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3074 | vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM } | |
3075 | vcvtneps2bf16<Vxy>, 0xf372, None, CpuAVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSuf|<Vxy:syntax>, { <Vxy:dst>, RegXMM } | |
01d8ce74 | 3076 | |
3077 | // AVX-NE-CONVERT instructions end. | |
3078 | ||
5d79adc4 L |
3079 | // ENQCMD instructions. |
3080 | ||
2368c6bf L |
3081 | enqcmd, 0xf20f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } |
3082 | enqcmds, 0xf30f38f8, None, CpuENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } | |
5d79adc4 L |
3083 | |
3084 | // ENQCMD instructions end. | |
9186c494 L |
3085 | |
3086 | // VP2INTERSECT instructions. | |
3087 | ||
2368c6bf | 3088 | vp2intersect<dq>, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
9186c494 L |
3089 | |
3090 | // VP2INTERSECT instructions end. | |
142861df JB |
3091 | |
3092 | // MCOMMIT instruction | |
3093 | ||
2368c6bf | 3094 | mcommit, 0xf30f01fa, None, CpuMCOMMIT, NoSuf, {} |
142861df JB |
3095 | |
3096 | // MCOMMIT instruction end | |
3097 | ||
646cc3e0 GG |
3098 | // SNP instructions |
3099 | ||
2368c6bf L |
3100 | psmash, 0xf30f01ff, None, CpuSNP|Cpu64, NoSuf, {} |
3101 | psmash, 0xf30f01ff, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } | |
3102 | pvalidate, 0xf20f01ff, None, CpuSNP, NoSuf, {} | |
3103 | pvalidate, 0xf20f01ff, None, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword } | |
3104 | rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, NoSuf, {} | |
3105 | rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword } | |
3106 | rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, NoSuf, {} | |
3107 | rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } | |
c0e54661 | 3108 | // The single-operand forms exist only for compatibility with older gas. |
2368c6bf L |
3109 | pvalidate, 0xf20f01ff, None, CpuSNP, AddrPrefixOpReg|NoSuf, { Acc|Word|Dword|Qword } |
3110 | rmpupdate, 0xf20f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } | |
3111 | rmpadjust, 0xf30f01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword } | |
646cc3e0 GG |
3112 | |
3113 | // SNP instructions end | |
3114 | ||
b0e8fa7f TJ |
3115 | // RMPQUERY instruction |
3116 | ||
2368c6bf L |
3117 | rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, NoSuf, {} |
3118 | rmpquery, 0xf30f01fd, None, CpuRMPQUERY|Cpu64, AddrPrefixOpReg|NoSuf, { Acc|Dword|Qword, RegC|Qword, RegD|Qword } | |
b0e8fa7f TJ |
3119 | |
3120 | // RMPQUERY instruction end | |
3121 | ||
142861df JB |
3122 | // RDPRU instruction |
3123 | ||
2368c6bf | 3124 | rdpru, 0x0f01fd, None, CpuRDPRU, NoSuf, {} |
142861df JB |
3125 | |
3126 | // RDPRU instruction end | |
4b27d27c L |
3127 | |
3128 | // SERIALIZE instruction. | |
3129 | ||
2368c6bf | 3130 | serialize, 0x0f01e8, None, CpuSERIALIZE, NoSuf, {} |
4b27d27c L |
3131 | |
3132 | // SERIALIZE instruction end. | |
bb651e8b CL |
3133 | |
3134 | // TSXLDTRK instructions. | |
3135 | ||
2368c6bf L |
3136 | xsusldtrk, 0xf20f01e8, None, CpuTSXLDTRK, NoSuf, {} |
3137 | xresldtrk, 0xf20f01e9, None, CpuTSXLDTRK, NoSuf, {} | |
bb651e8b CL |
3138 | |
3139 | // TSXLDTRK instructions end. | |
260cd341 LC |
3140 | |
3141 | // AMX instructions. | |
3142 | ||
2368c6bf L |
3143 | ldtilecfg, 0x49, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } |
3144 | sttilecfg, 0x6649, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } | |
260cd341 | 3145 | |
2368c6bf L |
3146 | tdpbf16ps, 0xf35c, None, CpuAMX_BF16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } |
3147 | tdpfp16ps, 0xf25c, None, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3148 | tdpbssd, 0xf25e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3149 | tdpbuud, 0x5e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3150 | tdpbusd, 0x665e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } | |
3151 | tdpbsud, 0xf35e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } | |
260cd341 | 3152 | |
2368c6bf L |
3153 | tileloadd, 0xf24b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } |
3154 | tileloaddt1, 0x664b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } | |
3155 | tilestored, 0xf34b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } | |
260cd341 | 3156 | |
2368c6bf | 3157 | tilerelease, 0x49c0, None, CpuAMX_TILE|Cpu64, Vex128|Space0F38|VexW0|NoSuf, {} |
260cd341 | 3158 | |
2368c6bf | 3159 | tilezero, 0xf249, None, CpuAMX_TILE|Cpu64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } |
260cd341 LC |
3160 | |
3161 | // AMX instructions end. | |
c4694f17 TG |
3162 | |
3163 | // KEYLOCKER instructions. | |
3164 | ||
2368c6bf L |
3165 | loadiwkey, 0xf30f38dc, None, CpuKL, Load|Modrm|NoSuf, { RegXMM, RegXMM } |
3166 | encodekey128, 0xf30f38fa, None, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } | |
3167 | encodekey256, 0xf30f38fb, None, CpuKL, Modrm|NoSuf, { Reg32, Reg32 } | |
3168 | aesenc128kl, 0xf30f38dc, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3169 | aesdec128kl, 0xf30f38dd, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3170 | aesenc256kl, 0xf30f38de, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3171 | aesdec256kl, 0xf30f38df, None, CpuKL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } | |
3172 | aesencwide128kl, 0xf30f38d8, 0, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3173 | aesdecwide128kl, 0xf30f38d8, 1, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3174 | aesencwide256kl, 0xf30f38d8, 2, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
3175 | aesdecwide256kl, 0xf30f38d8, 3, CpuWideKL, Modrm|NoSuf, { Unspecified|BaseIndex } | |
c4694f17 TG |
3176 | |
3177 | // KEYLOCKER instructions end. | |
81d54bb7 CL |
3178 | |
3179 | // TDX instructions. | |
3180 | ||
2368c6bf L |
3181 | tdcall, 0x660f01cc, None, CpuTDX, NoSuf, {} |
3182 | seamret, 0x660f01cd, None, CpuTDX|Cpu64, NoSuf, {} | |
3183 | seamops, 0x660f01ce, None, CpuTDX|Cpu64, NoSuf, {} | |
3184 | seamcall, 0x660f01cf, None, CpuTDX|Cpu64, NoSuf, {} | |
81d54bb7 CL |
3185 | |
3186 | // TDX instructions end. | |
f64c42a9 LC |
3187 | |
3188 | // UINTR instructions. | |
3189 | ||
2368c6bf L |
3190 | uiret, 0xf30f01ec, None, CpuUINTR|Cpu64, NoSuf, {} |
3191 | clui, 0xf30f01ee, None, CpuUINTR|Cpu64, NoSuf, {} | |
3192 | stui, 0xf30f01ef, None, CpuUINTR|Cpu64, NoSuf, {} | |
3193 | testui, 0xf30f01ed, None, CpuUINTR|Cpu64, NoSuf, {} | |
3194 | senduipi, 0xf30fc7, 6, CpuUINTR|Cpu64, Modrm|NoSuf|NoRex64, { Reg64 } | |
f64c42a9 LC |
3195 | |
3196 | // UINTR instructions end. | |
c1fa250a LC |
3197 | |
3198 | // HRESET instructions. | |
3199 | ||
2368c6bf | 3200 | hreset, 0xf30f3af0c0, None, CpuHRESET, NoSuf, { Imm8 } |
c1fa250a LC |
3201 | |
3202 | // HRESET instructions end. | |
0cc78721 CL |
3203 | |
3204 | // FP16 (HFNI) instructions. | |
3205 | ||
2368c6bf L |
3206 | vfcmaddcph, 0xf256, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3207 | vfcmaddcsh, 0xf257, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3208 | |
2368c6bf L |
3209 | vfmaddcph, 0xf356, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3210 | vfmaddcsh, 0xf357, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3211 | |
2368c6bf L |
3212 | vfcmulcph, 0xf2d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3213 | vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3214 | |
2368c6bf L |
3215 | vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } |
3216 | vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3217 | |
2368c6bf L |
3218 | vcmp<frel>ph, 0xc2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } |
3219 | vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } | |
0cc78721 | 3220 | |
2368c6bf L |
3221 | vcmp<frel>sh, 0xf3c2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } |
3222 | vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } | |
0cc78721 | 3223 | |
2368c6bf L |
3224 | vcvtdq2ph<Exy>, 0x5b, None, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } |
3225 | vcvtudq2ph<Exy>, 0xf27a, None, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } | |
e07ae9a3 | 3226 | |
2368c6bf L |
3227 | vcvtqq2ph<xyz>, 0x5b, None, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } |
3228 | vcvtuqq2ph<xyz>, 0xf27a, None, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } | |
e07ae9a3 | 3229 | |
2368c6bf | 3230 | vcvtpd2ph<xyz>, 0x665a, None, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=3|EVexMap5|VexW1|Broadcast|NoSuf|<xyz:sr>|<xyz:att>, { <xyz:src>|Qword, RegXMM } |
e07ae9a3 | 3231 | |
2368c6bf | 3232 | vcvtps2phx<Exy>, 0x661d, None, CpuAVX512_FP16|<Exy:vl>, Modrm|<Exy:attr>|Masking=3|EVexMap5|VexW0|Broadcast|NoSuf|<Exy:sr>, { <Exy:src>|Dword, <Exy:dst> } |
0cc78721 | 3233 | |
2368c6bf L |
3234 | vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3235 | vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
0cc78721 | 3236 | |
2368c6bf L |
3237 | vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3238 | vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
3239 | vcvtph2dq, 0x665b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3240 | |
2368c6bf L |
3241 | vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3242 | vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
3243 | vcvtph2udq, 0x79, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3244 | |
2368c6bf L |
3245 | vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3246 | vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
3247 | vcvtph2qq, 0x667b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3248 | |
2368c6bf L |
3249 | vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3250 | vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
3251 | vcvtph2uqq, 0x6679, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3252 | |
2368c6bf L |
3253 | vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3254 | vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
3255 | vcvtph2pd, 0x5a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3256 | |
2368c6bf L |
3257 | vcvtph2w, 0x667d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3258 | vcvtph2uw, 0x7d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
0cc78721 | 3259 | |
2368c6bf L |
3260 | vcvtsd2sh, 0xf25a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } |
3261 | vcvtss2sh, 0x1d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|NoSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3262 | |
cf665fee JB |
3263 | vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
3264 | vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3265 | |
cf665fee JB |
3266 | vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } |
3267 | vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3268 | |
2368c6bf L |
3269 | vcvtsh2sd, 0xf35a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
3270 | vcvtsh2ss, 0x13, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } | |
0cc78721 | 3271 | |
2368c6bf | 3272 | vcvtsh2si, 0xf32d, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } |
0cc78721 | 3273 | |
2368c6bf L |
3274 | vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3275 | vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
3276 | vcvttph2dq, 0xf35b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3277 | |
2368c6bf L |
3278 | vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3279 | vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
3280 | vcvttph2udq, 0x78, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3281 | |
2368c6bf L |
3282 | vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3283 | vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
3284 | vcvttph2qq, 0x667a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3285 | |
2368c6bf L |
3286 | vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|NoSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } |
3287 | vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } | |
3288 | vcvttph2uqq, 0x6678, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } | |
0cc78721 | 3289 | |
2368c6bf L |
3290 | vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|NoSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } |
3291 | vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } | |
3292 | vcvtph2psx, 0x6613, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|NoSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } | |
cf665fee | 3293 | |
2368c6bf L |
3294 | vcvttph2w, 0x667c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
3295 | vcvttph2uw, 0x7c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } | |
cf665fee | 3296 | |
2368c6bf | 3297 | vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } |
cf665fee | 3298 | |
2368c6bf | 3299 | vfpclassph<xyz>, 0x66, None, CpuAVX512_FP16|<xyz:vl>, Modrm|<xyz:attr>|Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|<xyz:att>, { Imm8, <xyz:src>|Word, RegMask } |
0cc78721 | 3300 | |
2368c6bf L |
3301 | vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } |
3302 | vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 } | |
0cc78721 | 3303 | |
2368c6bf | 3304 | vrcpph, 0x664c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
0cc78721 | 3305 | |
2368c6bf | 3306 | vrcpsh, 0x664d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
0cc78721 | 3307 | |
2368c6bf | 3308 | vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } |
0cc78721 | 3309 | |
2368c6bf | 3310 | vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } |
0cc78721 | 3311 | |
0cc78721 | 3312 | // FP16 (HFNI) instructions end. |
ef07be45 CL |
3313 | |
3314 | // PREFETCHI instructions. | |
3315 | ||
2368c6bf L |
3316 | prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } |
3317 | prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } | |
ef07be45 CL |
3318 | |
3319 | // PREFETCHI instructions end. | |
a93e3234 HJ |
3320 | |
3321 | // CMPCCXADD instructions. | |
3322 | ||
2368c6bf | 3323 | cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
a93e3234 HJ |
3324 | |
3325 | // CMPCCXADD instructions end. | |
941f0833 HL |
3326 | |
3327 | // WRMSRNS instruction. | |
3328 | ||
2368c6bf | 3329 | wrmsrns, 0x0f01c6, None, CpuWRMSRNS, NoSuf, {} |
941f0833 HL |
3330 | |
3331 | // WRMSRNS instruction end. | |
2188d6ea HL |
3332 | |
3333 | // MSRLIST instructions. | |
3334 | ||
2368c6bf L |
3335 | rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, NoSuf, {} |
3336 | wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, NoSuf, {} | |
2188d6ea HL |
3337 | |
3338 | // MSRLIST instructions end. | |
b06311ad KL |
3339 | |
3340 | // RAO-INT instructions. | |
3341 | ||
2368c6bf L |
3342 | aadd, 0xf38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } |
3343 | aand, 0x660f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } | |
3344 | aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } | |
3345 | axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|CheckRegSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } | |
b06311ad KL |
3346 | |
3347 | // RAO-INT instructions end. |