]>
Commit | Line | Data |
---|---|---|
4162bb66 | 1 | /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ |
47b1a55a SC |
2 | /* CPU data for iq2000. |
3 | ||
4 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
5 | ||
fd67aa11 | 6 | Copyright (C) 1996-2024 Free Software Foundation, Inc. |
47b1a55a SC |
7 | |
8 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
9 | ||
9b201bb5 NC |
10 | This file is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3, or (at your option) | |
13 | any later version. | |
47b1a55a | 14 | |
9b201bb5 NC |
15 | It is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
47b1a55a | 19 | |
9b201bb5 NC |
20 | You should have received a copy of the GNU General Public License along |
21 | with this program; if not, write to the Free Software Foundation, Inc., | |
22 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
47b1a55a SC |
23 | |
24 | */ | |
25 | ||
26 | #include "sysdep.h" | |
47b1a55a SC |
27 | #include <stdio.h> |
28 | #include <stdarg.h> | |
a2c58332 | 29 | #include <stdlib.h> |
47b1a55a SC |
30 | #include "ansidecl.h" |
31 | #include "bfd.h" | |
32 | #include "symcat.h" | |
33 | #include "iq2000-desc.h" | |
34 | #include "iq2000-opc.h" | |
35 | #include "opintl.h" | |
36 | #include "libiberty.h" | |
75798298 | 37 | #include "xregex.h" |
47b1a55a SC |
38 | |
39 | /* Attributes. */ | |
40 | ||
41 | static const CGEN_ATTR_ENTRY bool_attr[] = | |
42 | { | |
43 | { "#f", 0 }, | |
44 | { "#t", 1 }, | |
45 | { 0, 0 } | |
46 | }; | |
47 | ||
bf143b25 | 48 | static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = |
47b1a55a SC |
49 | { |
50 | { "base", MACH_BASE }, | |
51 | { "iq2000", MACH_IQ2000 }, | |
52 | { "iq10", MACH_IQ10 }, | |
53 | { "max", MACH_MAX }, | |
54 | { 0, 0 } | |
55 | }; | |
56 | ||
bf143b25 | 57 | static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = |
47b1a55a SC |
58 | { |
59 | { "iq2000", ISA_IQ2000 }, | |
60 | { "max", ISA_MAX }, | |
61 | { 0, 0 } | |
62 | }; | |
63 | ||
64 | const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] = | |
65 | { | |
66 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
67 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
68 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
69 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
70 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, | |
71 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
72 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
73 | { 0, 0, 0 } | |
74 | }; | |
75 | ||
76 | const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] = | |
77 | { | |
78 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
79 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
80 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, | |
81 | { "PC", &bool_attr[0], &bool_attr[0] }, | |
82 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, | |
83 | { 0, 0, 0 } | |
84 | }; | |
85 | ||
86 | const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] = | |
87 | { | |
88 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
89 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
90 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
91 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
92 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
93 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
94 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, | |
95 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
96 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, | |
97 | { 0, 0, 0 } | |
98 | }; | |
99 | ||
100 | const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = | |
101 | { | |
102 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
103 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, | |
104 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
105 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, | |
106 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, | |
107 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, | |
108 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, | |
109 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, | |
b11dcf4e | 110 | { "RELAXED", &bool_attr[0], &bool_attr[0] }, |
47b1a55a SC |
111 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, |
112 | { "PBB", &bool_attr[0], &bool_attr[0] }, | |
113 | { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, | |
114 | { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, | |
115 | { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] }, | |
116 | { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] }, | |
117 | { "USES-RD", &bool_attr[0], &bool_attr[0] }, | |
118 | { "USES-RS", &bool_attr[0], &bool_attr[0] }, | |
119 | { "USES-RT", &bool_attr[0], &bool_attr[0] }, | |
120 | { "USES-R31", &bool_attr[0], &bool_attr[0] }, | |
121 | { 0, 0, 0 } | |
122 | }; | |
123 | ||
124 | /* Instruction set variants. */ | |
125 | ||
126 | static const CGEN_ISA iq2000_cgen_isa_table[] = { | |
4030fa5a | 127 | { "iq2000", 32, 32, 32, 32 }, |
47b1a55a SC |
128 | { 0, 0, 0, 0, 0 } |
129 | }; | |
130 | ||
131 | /* Machine variants. */ | |
132 | ||
133 | static const CGEN_MACH iq2000_cgen_mach_table[] = { | |
134 | { "iq2000", "iq2000", MACH_IQ2000, 0 }, | |
135 | { "iq10", "iq10", MACH_IQ10, 0 }, | |
136 | { 0, 0, 0, 0 } | |
137 | }; | |
138 | ||
139 | static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] = | |
140 | { | |
a92e0d0a L |
141 | { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, |
142 | { "%0", 0, {0, {{{0, 0}}}}, 0, 0 }, | |
143 | { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, | |
144 | { "%1", 1, {0, {{{0, 0}}}}, 0, 0 }, | |
145 | { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, | |
146 | { "%2", 2, {0, {{{0, 0}}}}, 0, 0 }, | |
147 | { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, | |
148 | { "%3", 3, {0, {{{0, 0}}}}, 0, 0 }, | |
149 | { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, | |
150 | { "%4", 4, {0, {{{0, 0}}}}, 0, 0 }, | |
151 | { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, | |
152 | { "%5", 5, {0, {{{0, 0}}}}, 0, 0 }, | |
153 | { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, | |
154 | { "%6", 6, {0, {{{0, 0}}}}, 0, 0 }, | |
155 | { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, | |
156 | { "%7", 7, {0, {{{0, 0}}}}, 0, 0 }, | |
157 | { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, | |
158 | { "%8", 8, {0, {{{0, 0}}}}, 0, 0 }, | |
159 | { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, | |
160 | { "%9", 9, {0, {{{0, 0}}}}, 0, 0 }, | |
161 | { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, | |
162 | { "%10", 10, {0, {{{0, 0}}}}, 0, 0 }, | |
163 | { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, | |
164 | { "%11", 11, {0, {{{0, 0}}}}, 0, 0 }, | |
165 | { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, | |
166 | { "%12", 12, {0, {{{0, 0}}}}, 0, 0 }, | |
167 | { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, | |
168 | { "%13", 13, {0, {{{0, 0}}}}, 0, 0 }, | |
169 | { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, | |
170 | { "%14", 14, {0, {{{0, 0}}}}, 0, 0 }, | |
171 | { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, | |
172 | { "%15", 15, {0, {{{0, 0}}}}, 0, 0 }, | |
173 | { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, | |
174 | { "%16", 16, {0, {{{0, 0}}}}, 0, 0 }, | |
175 | { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, | |
176 | { "%17", 17, {0, {{{0, 0}}}}, 0, 0 }, | |
177 | { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, | |
178 | { "%18", 18, {0, {{{0, 0}}}}, 0, 0 }, | |
179 | { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, | |
180 | { "%19", 19, {0, {{{0, 0}}}}, 0, 0 }, | |
181 | { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, | |
182 | { "%20", 20, {0, {{{0, 0}}}}, 0, 0 }, | |
183 | { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, | |
184 | { "%21", 21, {0, {{{0, 0}}}}, 0, 0 }, | |
185 | { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, | |
186 | { "%22", 22, {0, {{{0, 0}}}}, 0, 0 }, | |
187 | { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, | |
188 | { "%23", 23, {0, {{{0, 0}}}}, 0, 0 }, | |
189 | { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, | |
190 | { "%24", 24, {0, {{{0, 0}}}}, 0, 0 }, | |
191 | { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, | |
192 | { "%25", 25, {0, {{{0, 0}}}}, 0, 0 }, | |
193 | { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, | |
194 | { "%26", 26, {0, {{{0, 0}}}}, 0, 0 }, | |
195 | { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, | |
196 | { "%27", 27, {0, {{{0, 0}}}}, 0, 0 }, | |
197 | { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, | |
198 | { "%28", 28, {0, {{{0, 0}}}}, 0, 0 }, | |
199 | { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, | |
200 | { "%29", 29, {0, {{{0, 0}}}}, 0, 0 }, | |
201 | { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, | |
202 | { "%30", 30, {0, {{{0, 0}}}}, 0, 0 }, | |
203 | { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, | |
204 | { "%31", 31, {0, {{{0, 0}}}}, 0, 0 } | |
47b1a55a SC |
205 | }; |
206 | ||
207 | CGEN_KEYWORD iq2000_cgen_opval_gr_names = | |
208 | { | |
209 | & iq2000_cgen_opval_gr_names_entries[0], | |
210 | 64, | |
211 | 0, 0, 0, 0, "" | |
212 | }; | |
213 | ||
214 | ||
215 | /* The hardware table. */ | |
216 | ||
47b1a55a | 217 | #define A(a) (1 << CGEN_HW_##a) |
47b1a55a SC |
218 | |
219 | const CGEN_HW_ENTRY iq2000_cgen_hw_table[] = | |
220 | { | |
a92e0d0a L |
221 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
222 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
223 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
224 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
225 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
226 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, | |
0dfdb523 | 227 | { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
a92e0d0a | 228 | { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } |
47b1a55a SC |
229 | }; |
230 | ||
231 | #undef A | |
232 | ||
233 | ||
234 | /* The instruction field table. */ | |
235 | ||
47b1a55a | 236 | #define A(a) (1 << CGEN_IFLD_##a) |
47b1a55a SC |
237 | |
238 | const CGEN_IFLD iq2000_cgen_ifld_table[] = | |
239 | { | |
a92e0d0a L |
240 | { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
241 | { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
242 | { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
243 | { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
244 | { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
245 | { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
246 | { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
247 | { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
248 | { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
249 | { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
250 | { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
251 | { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
252 | { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, | |
253 | { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, | |
254 | { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, | |
255 | { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, | |
256 | { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, | |
257 | { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, | |
258 | { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
259 | { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
260 | { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
261 | { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
262 | { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
263 | { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
264 | { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
265 | { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
266 | { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
267 | { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
268 | { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
269 | { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
270 | { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
271 | { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
272 | { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
273 | { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
274 | { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
275 | { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
276 | { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, | |
277 | { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } | |
47b1a55a SC |
278 | }; |
279 | ||
280 | #undef A | |
281 | ||
282 | ||
283 | ||
284 | /* multi ifield declarations */ | |
285 | ||
286 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD []; | |
287 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD []; | |
288 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD []; | |
289 | ||
290 | ||
291 | /* multi ifield definitions */ | |
292 | ||
293 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] = | |
294 | { | |
0dfdb523 AM |
295 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, |
296 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, | |
297 | { 0, { 0 } } | |
47b1a55a SC |
298 | }; |
299 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] = | |
300 | { | |
0dfdb523 AM |
301 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, |
302 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, | |
303 | { 0, { 0 } } | |
47b1a55a SC |
304 | }; |
305 | const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] = | |
306 | { | |
0dfdb523 AM |
307 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, |
308 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, | |
309 | { 0, { 0 } } | |
47b1a55a SC |
310 | }; |
311 | ||
312 | /* The operand table. */ | |
313 | ||
47b1a55a | 314 | #define A(a) (1 << CGEN_OPERAND_##a) |
47b1a55a | 315 | #define OPERAND(op) IQ2000_OPERAND_##op |
47b1a55a SC |
316 | |
317 | const CGEN_OPERAND iq2000_cgen_operand_table[] = | |
318 | { | |
319 | /* pc: program counter */ | |
320 | { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0, | |
0dfdb523 | 321 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_NIL] } }, |
a92e0d0a | 322 | { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
323 | /* rs: register Rs */ |
324 | { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5, | |
0dfdb523 | 325 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, |
a92e0d0a | 326 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
327 | /* rt: register Rt */ |
328 | { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5, | |
0dfdb523 | 329 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, |
a92e0d0a | 330 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
331 | /* rd: register Rd */ |
332 | { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5, | |
0dfdb523 | 333 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, |
a92e0d0a | 334 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
335 | /* rd-rs: register Rd from Rs */ |
336 | { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10, | |
0dfdb523 | 337 | { 2, { &IQ2000_F_RD_RS_MULTI_IFIELD[0] } }, |
a92e0d0a | 338 | { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
339 | /* rd-rt: register Rd from Rt */ |
340 | { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10, | |
0dfdb523 | 341 | { 2, { &IQ2000_F_RD_RT_MULTI_IFIELD[0] } }, |
a92e0d0a | 342 | { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
343 | /* rt-rs: register Rt from Rs */ |
344 | { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10, | |
0dfdb523 | 345 | { 2, { &IQ2000_F_RT_RS_MULTI_IFIELD[0] } }, |
a92e0d0a | 346 | { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
347 | /* shamt: shift amount */ |
348 | { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5, | |
0dfdb523 | 349 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } }, |
a92e0d0a | 350 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
351 | /* imm: immediate */ |
352 | { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16, | |
0dfdb523 | 353 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, |
a92e0d0a | 354 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
355 | /* offset: pc-relative offset */ |
356 | { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16, | |
0dfdb523 | 357 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } }, |
a92e0d0a | 358 | { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
359 | /* baseoff: base register offset */ |
360 | { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16, | |
0dfdb523 | 361 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, |
a92e0d0a | 362 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
363 | /* jmptarg: jump target */ |
364 | { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16, | |
0dfdb523 | 365 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } }, |
a92e0d0a | 366 | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
367 | /* mask: mask */ |
368 | { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4, | |
0dfdb523 | 369 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASK] } }, |
a92e0d0a | 370 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
371 | /* maskq10: iq10 mask */ |
372 | { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5, | |
0dfdb523 | 373 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } }, |
a92e0d0a | 374 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
375 | /* maskl: mask left */ |
376 | { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5, | |
0dfdb523 | 377 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } }, |
a92e0d0a | 378 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
379 | /* count: count */ |
380 | { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7, | |
0dfdb523 | 381 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } }, |
a92e0d0a | 382 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
4030fa5a NC |
383 | /* _index: index */ |
384 | { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9, | |
0dfdb523 | 385 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } }, |
a92e0d0a | 386 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
387 | /* execode: execcode */ |
388 | { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20, | |
0dfdb523 | 389 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } }, |
a92e0d0a | 390 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
391 | /* bytecount: byte count */ |
392 | { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8, | |
0dfdb523 | 393 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } }, |
a92e0d0a | 394 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
395 | /* cam-y: cam global opn y */ |
396 | { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3, | |
0dfdb523 | 397 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } }, |
a92e0d0a | 398 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
399 | /* cam-z: cam global mask z */ |
400 | { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3, | |
0dfdb523 | 401 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } }, |
a92e0d0a | 402 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
403 | /* cm-3func: CM 3 bit fn field */ |
404 | { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3, | |
0dfdb523 | 405 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } }, |
a92e0d0a | 406 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
407 | /* cm-4func: CM 4 bit fn field */ |
408 | { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4, | |
0dfdb523 | 409 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } }, |
a92e0d0a | 410 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
411 | /* cm-3z: CM 3 bit Z field */ |
412 | { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2, | |
0dfdb523 | 413 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } }, |
a92e0d0a | 414 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
415 | /* cm-4z: CM 4 bit Z field */ |
416 | { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3, | |
0dfdb523 | 417 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } }, |
a92e0d0a | 418 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
419 | /* base: base register */ |
420 | { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5, | |
0dfdb523 | 421 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, |
a92e0d0a | 422 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
423 | /* maskr: mask right */ |
424 | { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5, | |
0dfdb523 | 425 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, |
a92e0d0a | 426 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
427 | /* bitnum: bit number */ |
428 | { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5, | |
0dfdb523 | 429 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, |
a92e0d0a | 430 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
431 | /* hi16: high 16 bit immediate */ |
432 | { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16, | |
0dfdb523 | 433 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, |
a92e0d0a | 434 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
435 | /* lo16: 16 bit signed immediate, for low */ |
436 | { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16, | |
0dfdb523 | 437 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, |
a92e0d0a | 438 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
439 | /* mlo16: negated 16 bit signed immediate */ |
440 | { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16, | |
0dfdb523 | 441 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, |
a92e0d0a | 442 | { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
443 | /* jmptargq10: iq10 21-bit jump offset */ |
444 | { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21, | |
0dfdb523 | 445 | { 0, { &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } }, |
a92e0d0a | 446 | { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, |
75798298 NC |
447 | /* sentinel */ |
448 | { 0, 0, 0, 0, 0, | |
0dfdb523 | 449 | { 0, { 0 } }, |
a92e0d0a | 450 | { 0, { { { (1<<MACH_BASE), 0 } } } } } |
47b1a55a SC |
451 | }; |
452 | ||
453 | #undef A | |
454 | ||
455 | ||
456 | /* The instruction table. */ | |
457 | ||
458 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
47b1a55a | 459 | #define A(a) (1 << CGEN_INSN_##a) |
47b1a55a SC |
460 | |
461 | static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = | |
462 | { | |
463 | /* Special null first entry. | |
464 | A `num' value of zero is thus invalid. | |
465 | Also, the special `invalid' insn resides here. */ | |
a92e0d0a | 466 | { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, |
47b1a55a SC |
467 | /* add ${rd-rs},$rt */ |
468 | { | |
469 | -1, "add2", "add", 32, | |
a92e0d0a | 470 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
471 | }, |
472 | /* add $rd,$rs,$rt */ | |
473 | { | |
474 | IQ2000_INSN_ADD, "add", "add", 32, | |
a92e0d0a | 475 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
476 | }, |
477 | /* addi ${rt-rs},$lo16 */ | |
478 | { | |
479 | -1, "addi2", "addi", 32, | |
a92e0d0a | 480 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
481 | }, |
482 | /* addi $rt,$rs,$lo16 */ | |
483 | { | |
484 | IQ2000_INSN_ADDI, "addi", "addi", 32, | |
a92e0d0a | 485 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
486 | }, |
487 | /* addiu ${rt-rs},$lo16 */ | |
488 | { | |
489 | -1, "addiu2", "addiu", 32, | |
a92e0d0a | 490 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
491 | }, |
492 | /* addiu $rt,$rs,$lo16 */ | |
493 | { | |
494 | IQ2000_INSN_ADDIU, "addiu", "addiu", 32, | |
a92e0d0a | 495 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
496 | }, |
497 | /* addu ${rd-rs},$rt */ | |
498 | { | |
499 | -1, "addu2", "addu", 32, | |
a92e0d0a | 500 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
501 | }, |
502 | /* addu $rd,$rs,$rt */ | |
503 | { | |
504 | IQ2000_INSN_ADDU, "addu", "addu", 32, | |
a92e0d0a | 505 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
506 | }, |
507 | /* ado16 ${rd-rs},$rt */ | |
508 | { | |
509 | -1, "ado162", "ado16", 32, | |
a92e0d0a | 510 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
511 | }, |
512 | /* ado16 $rd,$rs,$rt */ | |
513 | { | |
514 | IQ2000_INSN_ADO16, "ado16", "ado16", 32, | |
a92e0d0a | 515 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
516 | }, |
517 | /* and ${rd-rs},$rt */ | |
518 | { | |
519 | -1, "and2", "and", 32, | |
a92e0d0a | 520 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
521 | }, |
522 | /* and $rd,$rs,$rt */ | |
523 | { | |
524 | IQ2000_INSN_AND, "and", "and", 32, | |
a92e0d0a | 525 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
526 | }, |
527 | /* andi ${rt-rs},$lo16 */ | |
528 | { | |
529 | -1, "andi2", "andi", 32, | |
a92e0d0a | 530 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
531 | }, |
532 | /* andi $rt,$rs,$lo16 */ | |
533 | { | |
534 | IQ2000_INSN_ANDI, "andi", "andi", 32, | |
a92e0d0a | 535 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
536 | }, |
537 | /* andoi ${rt-rs},$lo16 */ | |
538 | { | |
539 | -1, "andoi2", "andoi", 32, | |
a92e0d0a | 540 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
541 | }, |
542 | /* andoi $rt,$rs,$lo16 */ | |
543 | { | |
544 | IQ2000_INSN_ANDOI, "andoi", "andoi", 32, | |
a92e0d0a | 545 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
546 | }, |
547 | /* nor ${rd-rs},$rt */ | |
548 | { | |
549 | -1, "nor2", "nor", 32, | |
a92e0d0a | 550 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
551 | }, |
552 | /* nor $rd,$rs,$rt */ | |
553 | { | |
554 | IQ2000_INSN_NOR, "nor", "nor", 32, | |
a92e0d0a | 555 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
556 | }, |
557 | /* or ${rd-rs},$rt */ | |
558 | { | |
559 | -1, "or2", "or", 32, | |
a92e0d0a | 560 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
561 | }, |
562 | /* or $rd,$rs,$rt */ | |
563 | { | |
564 | IQ2000_INSN_OR, "or", "or", 32, | |
a92e0d0a | 565 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
566 | }, |
567 | /* ori ${rt-rs},$lo16 */ | |
568 | { | |
569 | -1, "ori2", "ori", 32, | |
a92e0d0a | 570 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
571 | }, |
572 | /* ori $rt,$rs,$lo16 */ | |
573 | { | |
574 | IQ2000_INSN_ORI, "ori", "ori", 32, | |
a92e0d0a | 575 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
576 | }, |
577 | /* ram $rd,$rt,$shamt,$maskl,$maskr */ | |
578 | { | |
579 | IQ2000_INSN_RAM, "ram", "ram", 32, | |
a92e0d0a | 580 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
581 | }, |
582 | /* sll $rd,$rt,$shamt */ | |
583 | { | |
584 | IQ2000_INSN_SLL, "sll", "sll", 32, | |
a92e0d0a | 585 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
586 | }, |
587 | /* sllv ${rd-rt},$rs */ | |
588 | { | |
589 | -1, "sllv2", "sllv", 32, | |
a92e0d0a | 590 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
591 | }, |
592 | /* sllv $rd,$rt,$rs */ | |
593 | { | |
594 | IQ2000_INSN_SLLV, "sllv", "sllv", 32, | |
a92e0d0a | 595 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
596 | }, |
597 | /* slmv ${rd-rt},$rs,$shamt */ | |
598 | { | |
599 | -1, "slmv2", "slmv", 32, | |
a92e0d0a | 600 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
601 | }, |
602 | /* slmv $rd,$rt,$rs,$shamt */ | |
603 | { | |
604 | IQ2000_INSN_SLMV, "slmv", "slmv", 32, | |
a92e0d0a | 605 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
606 | }, |
607 | /* slt ${rd-rs},$rt */ | |
608 | { | |
609 | -1, "slt2", "slt", 32, | |
a92e0d0a | 610 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
611 | }, |
612 | /* slt $rd,$rs,$rt */ | |
613 | { | |
614 | IQ2000_INSN_SLT, "slt", "slt", 32, | |
a92e0d0a | 615 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
616 | }, |
617 | /* slti ${rt-rs},$imm */ | |
618 | { | |
619 | -1, "slti2", "slti", 32, | |
a92e0d0a | 620 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
621 | }, |
622 | /* slti $rt,$rs,$imm */ | |
623 | { | |
624 | IQ2000_INSN_SLTI, "slti", "slti", 32, | |
a92e0d0a | 625 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
626 | }, |
627 | /* sltiu ${rt-rs},$imm */ | |
628 | { | |
629 | -1, "sltiu2", "sltiu", 32, | |
a92e0d0a | 630 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
631 | }, |
632 | /* sltiu $rt,$rs,$imm */ | |
633 | { | |
634 | IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32, | |
a92e0d0a | 635 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
636 | }, |
637 | /* sltu ${rd-rs},$rt */ | |
638 | { | |
639 | -1, "sltu2", "sltu", 32, | |
a92e0d0a | 640 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
641 | }, |
642 | /* sltu $rd,$rs,$rt */ | |
643 | { | |
644 | IQ2000_INSN_SLTU, "sltu", "sltu", 32, | |
a92e0d0a | 645 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
646 | }, |
647 | /* sra ${rd-rt},$shamt */ | |
648 | { | |
649 | -1, "sra2", "sra", 32, | |
a92e0d0a | 650 | { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
651 | }, |
652 | /* sra $rd,$rt,$shamt */ | |
653 | { | |
654 | IQ2000_INSN_SRA, "sra", "sra", 32, | |
a92e0d0a | 655 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
656 | }, |
657 | /* srav ${rd-rt},$rs */ | |
658 | { | |
659 | -1, "srav2", "srav", 32, | |
a92e0d0a | 660 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
661 | }, |
662 | /* srav $rd,$rt,$rs */ | |
663 | { | |
664 | IQ2000_INSN_SRAV, "srav", "srav", 32, | |
a92e0d0a | 665 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
666 | }, |
667 | /* srl $rd,$rt,$shamt */ | |
668 | { | |
669 | IQ2000_INSN_SRL, "srl", "srl", 32, | |
a92e0d0a | 670 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
671 | }, |
672 | /* srlv ${rd-rt},$rs */ | |
673 | { | |
674 | -1, "srlv2", "srlv", 32, | |
a92e0d0a | 675 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
676 | }, |
677 | /* srlv $rd,$rt,$rs */ | |
678 | { | |
679 | IQ2000_INSN_SRLV, "srlv", "srlv", 32, | |
a92e0d0a | 680 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
681 | }, |
682 | /* srmv ${rd-rt},$rs,$shamt */ | |
683 | { | |
684 | -1, "srmv2", "srmv", 32, | |
a92e0d0a | 685 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
686 | }, |
687 | /* srmv $rd,$rt,$rs,$shamt */ | |
688 | { | |
689 | IQ2000_INSN_SRMV, "srmv", "srmv", 32, | |
a92e0d0a | 690 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
691 | }, |
692 | /* sub ${rd-rs},$rt */ | |
693 | { | |
694 | -1, "sub2", "sub", 32, | |
a92e0d0a | 695 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
696 | }, |
697 | /* sub $rd,$rs,$rt */ | |
698 | { | |
699 | IQ2000_INSN_SUB, "sub", "sub", 32, | |
a92e0d0a | 700 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
701 | }, |
702 | /* subu ${rd-rs},$rt */ | |
703 | { | |
704 | -1, "subu2", "subu", 32, | |
a92e0d0a | 705 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
706 | }, |
707 | /* subu $rd,$rs,$rt */ | |
708 | { | |
709 | IQ2000_INSN_SUBU, "subu", "subu", 32, | |
a92e0d0a | 710 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
711 | }, |
712 | /* xor ${rd-rs},$rt */ | |
713 | { | |
714 | -1, "xor2", "xor", 32, | |
a92e0d0a | 715 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
716 | }, |
717 | /* xor $rd,$rs,$rt */ | |
718 | { | |
719 | IQ2000_INSN_XOR, "xor", "xor", 32, | |
a92e0d0a | 720 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
721 | }, |
722 | /* xori ${rt-rs},$lo16 */ | |
723 | { | |
724 | -1, "xori2", "xori", 32, | |
a92e0d0a | 725 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
726 | }, |
727 | /* xori $rt,$rs,$lo16 */ | |
728 | { | |
729 | IQ2000_INSN_XORI, "xori", "xori", 32, | |
a92e0d0a | 730 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
731 | }, |
732 | /* bbi $rs($bitnum),$offset */ | |
733 | { | |
734 | IQ2000_INSN_BBI, "bbi", "bbi", 32, | |
a92e0d0a | 735 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
736 | }, |
737 | /* bbin $rs($bitnum),$offset */ | |
738 | { | |
739 | IQ2000_INSN_BBIN, "bbin", "bbin", 32, | |
a92e0d0a | 740 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
741 | }, |
742 | /* bbv $rs,$rt,$offset */ | |
743 | { | |
744 | IQ2000_INSN_BBV, "bbv", "bbv", 32, | |
a92e0d0a | 745 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
746 | }, |
747 | /* bbvn $rs,$rt,$offset */ | |
748 | { | |
749 | IQ2000_INSN_BBVN, "bbvn", "bbvn", 32, | |
a92e0d0a | 750 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
751 | }, |
752 | /* beq $rs,$rt,$offset */ | |
753 | { | |
754 | IQ2000_INSN_BEQ, "beq", "beq", 32, | |
a92e0d0a | 755 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
756 | }, |
757 | /* beql $rs,$rt,$offset */ | |
758 | { | |
759 | IQ2000_INSN_BEQL, "beql", "beql", 32, | |
a92e0d0a | 760 | { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
761 | }, |
762 | /* bgez $rs,$offset */ | |
763 | { | |
764 | IQ2000_INSN_BGEZ, "bgez", "bgez", 32, | |
a92e0d0a | 765 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
766 | }, |
767 | /* bgezal $rs,$offset */ | |
768 | { | |
769 | IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32, | |
a92e0d0a | 770 | { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
771 | }, |
772 | /* bgezall $rs,$offset */ | |
773 | { | |
774 | IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32, | |
a92e0d0a | 775 | { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
776 | }, |
777 | /* bgezl $rs,$offset */ | |
778 | { | |
779 | IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32, | |
a92e0d0a | 780 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
781 | }, |
782 | /* bltz $rs,$offset */ | |
783 | { | |
784 | IQ2000_INSN_BLTZ, "bltz", "bltz", 32, | |
a92e0d0a | 785 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
786 | }, |
787 | /* bltzl $rs,$offset */ | |
788 | { | |
789 | IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32, | |
a92e0d0a | 790 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
791 | }, |
792 | /* bltzal $rs,$offset */ | |
793 | { | |
794 | IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32, | |
a92e0d0a | 795 | { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
796 | }, |
797 | /* bltzall $rs,$offset */ | |
798 | { | |
799 | IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32, | |
a92e0d0a | 800 | { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
801 | }, |
802 | /* bmb0 $rs,$rt,$offset */ | |
803 | { | |
804 | IQ2000_INSN_BMB0, "bmb0", "bmb0", 32, | |
a92e0d0a | 805 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
806 | }, |
807 | /* bmb1 $rs,$rt,$offset */ | |
808 | { | |
809 | IQ2000_INSN_BMB1, "bmb1", "bmb1", 32, | |
a92e0d0a | 810 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
811 | }, |
812 | /* bmb2 $rs,$rt,$offset */ | |
813 | { | |
814 | IQ2000_INSN_BMB2, "bmb2", "bmb2", 32, | |
a92e0d0a | 815 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
816 | }, |
817 | /* bmb3 $rs,$rt,$offset */ | |
818 | { | |
819 | IQ2000_INSN_BMB3, "bmb3", "bmb3", 32, | |
a92e0d0a | 820 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
821 | }, |
822 | /* bne $rs,$rt,$offset */ | |
823 | { | |
824 | IQ2000_INSN_BNE, "bne", "bne", 32, | |
a92e0d0a | 825 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
826 | }, |
827 | /* bnel $rs,$rt,$offset */ | |
828 | { | |
829 | IQ2000_INSN_BNEL, "bnel", "bnel", 32, | |
a92e0d0a | 830 | { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
831 | }, |
832 | /* jalr $rd,$rs */ | |
833 | { | |
834 | IQ2000_INSN_JALR, "jalr", "jalr", 32, | |
a92e0d0a | 835 | { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
836 | }, |
837 | /* jr $rs */ | |
838 | { | |
839 | IQ2000_INSN_JR, "jr", "jr", 32, | |
a92e0d0a | 840 | { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
841 | }, |
842 | /* lb $rt,$lo16($base) */ | |
843 | { | |
844 | IQ2000_INSN_LB, "lb", "lb", 32, | |
a92e0d0a | 845 | { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
846 | }, |
847 | /* lbu $rt,$lo16($base) */ | |
848 | { | |
849 | IQ2000_INSN_LBU, "lbu", "lbu", 32, | |
a92e0d0a | 850 | { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
851 | }, |
852 | /* lh $rt,$lo16($base) */ | |
853 | { | |
854 | IQ2000_INSN_LH, "lh", "lh", 32, | |
a92e0d0a | 855 | { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
856 | }, |
857 | /* lhu $rt,$lo16($base) */ | |
858 | { | |
859 | IQ2000_INSN_LHU, "lhu", "lhu", 32, | |
a92e0d0a | 860 | { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
861 | }, |
862 | /* lui $rt,$hi16 */ | |
863 | { | |
864 | IQ2000_INSN_LUI, "lui", "lui", 32, | |
a92e0d0a | 865 | { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
866 | }, |
867 | /* lw $rt,$lo16($base) */ | |
868 | { | |
869 | IQ2000_INSN_LW, "lw", "lw", 32, | |
a92e0d0a | 870 | { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
871 | }, |
872 | /* sb $rt,$lo16($base) */ | |
873 | { | |
874 | IQ2000_INSN_SB, "sb", "sb", 32, | |
a92e0d0a | 875 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
876 | }, |
877 | /* sh $rt,$lo16($base) */ | |
878 | { | |
879 | IQ2000_INSN_SH, "sh", "sh", 32, | |
a92e0d0a | 880 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
881 | }, |
882 | /* sw $rt,$lo16($base) */ | |
883 | { | |
884 | IQ2000_INSN_SW, "sw", "sw", 32, | |
a92e0d0a | 885 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
886 | }, |
887 | /* break */ | |
888 | { | |
889 | IQ2000_INSN_BREAK, "break", "break", 32, | |
a92e0d0a | 890 | { 0, { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
891 | }, |
892 | /* syscall */ | |
893 | { | |
894 | IQ2000_INSN_SYSCALL, "syscall", "syscall", 32, | |
a92e0d0a | 895 | { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } } |
47b1a55a SC |
896 | }, |
897 | /* andoui $rt,$rs,$hi16 */ | |
898 | { | |
899 | IQ2000_INSN_ANDOUI, "andoui", "andoui", 32, | |
a92e0d0a | 900 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
901 | }, |
902 | /* andoui ${rt-rs},$hi16 */ | |
903 | { | |
904 | -1, "andoui2", "andoui", 32, | |
a92e0d0a | 905 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
906 | }, |
907 | /* orui ${rt-rs},$hi16 */ | |
908 | { | |
909 | -1, "orui2", "orui", 32, | |
a92e0d0a | 910 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
911 | }, |
912 | /* orui $rt,$rs,$hi16 */ | |
913 | { | |
914 | IQ2000_INSN_ORUI, "orui", "orui", 32, | |
a92e0d0a | 915 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
916 | }, |
917 | /* bgtz $rs,$offset */ | |
918 | { | |
919 | IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32, | |
a92e0d0a | 920 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
921 | }, |
922 | /* bgtzl $rs,$offset */ | |
923 | { | |
924 | IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32, | |
a92e0d0a | 925 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
926 | }, |
927 | /* blez $rs,$offset */ | |
928 | { | |
929 | IQ2000_INSN_BLEZ, "blez", "blez", 32, | |
a92e0d0a | 930 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
931 | }, |
932 | /* blezl $rs,$offset */ | |
933 | { | |
934 | IQ2000_INSN_BLEZL, "blezl", "blezl", 32, | |
a92e0d0a | 935 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
936 | }, |
937 | /* mrgb $rd,$rs,$rt,$mask */ | |
938 | { | |
939 | IQ2000_INSN_MRGB, "mrgb", "mrgb", 32, | |
a92e0d0a | 940 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
941 | }, |
942 | /* mrgb ${rd-rs},$rt,$mask */ | |
943 | { | |
944 | -1, "mrgb2", "mrgb", 32, | |
a92e0d0a | 945 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
946 | }, |
947 | /* bctxt $rs,$offset */ | |
948 | { | |
949 | IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32, | |
a92e0d0a | 950 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
951 | }, |
952 | /* bc0f $offset */ | |
953 | { | |
954 | IQ2000_INSN_BC0F, "bc0f", "bc0f", 32, | |
a92e0d0a | 955 | { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
956 | }, |
957 | /* bc0fl $offset */ | |
958 | { | |
959 | IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32, | |
a92e0d0a | 960 | { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
961 | }, |
962 | /* bc3f $offset */ | |
963 | { | |
964 | IQ2000_INSN_BC3F, "bc3f", "bc3f", 32, | |
a92e0d0a | 965 | { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
966 | }, |
967 | /* bc3fl $offset */ | |
968 | { | |
969 | IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32, | |
a92e0d0a | 970 | { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
971 | }, |
972 | /* bc0t $offset */ | |
973 | { | |
974 | IQ2000_INSN_BC0T, "bc0t", "bc0t", 32, | |
a92e0d0a | 975 | { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
976 | }, |
977 | /* bc0tl $offset */ | |
978 | { | |
979 | IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32, | |
a92e0d0a | 980 | { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
981 | }, |
982 | /* bc3t $offset */ | |
983 | { | |
984 | IQ2000_INSN_BC3T, "bc3t", "bc3t", 32, | |
a92e0d0a | 985 | { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
986 | }, |
987 | /* bc3tl $offset */ | |
988 | { | |
989 | IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32, | |
a92e0d0a | 990 | { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
991 | }, |
992 | /* cfc0 $rt,$rd */ | |
993 | { | |
994 | IQ2000_INSN_CFC0, "cfc0", "cfc0", 32, | |
a92e0d0a | 995 | { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
996 | }, |
997 | /* cfc1 $rt,$rd */ | |
998 | { | |
999 | IQ2000_INSN_CFC1, "cfc1", "cfc1", 32, | |
a92e0d0a | 1000 | { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1001 | }, |
1002 | /* cfc2 $rt,$rd */ | |
1003 | { | |
1004 | IQ2000_INSN_CFC2, "cfc2", "cfc2", 32, | |
a92e0d0a | 1005 | { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1006 | }, |
1007 | /* cfc3 $rt,$rd */ | |
1008 | { | |
1009 | IQ2000_INSN_CFC3, "cfc3", "cfc3", 32, | |
a92e0d0a | 1010 | { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1011 | }, |
1012 | /* chkhdr $rd,$rt */ | |
1013 | { | |
1014 | IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32, | |
a92e0d0a | 1015 | { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1016 | }, |
1017 | /* ctc0 $rt,$rd */ | |
1018 | { | |
1019 | IQ2000_INSN_CTC0, "ctc0", "ctc0", 32, | |
a92e0d0a | 1020 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1021 | }, |
1022 | /* ctc1 $rt,$rd */ | |
1023 | { | |
1024 | IQ2000_INSN_CTC1, "ctc1", "ctc1", 32, | |
a92e0d0a | 1025 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1026 | }, |
1027 | /* ctc2 $rt,$rd */ | |
1028 | { | |
1029 | IQ2000_INSN_CTC2, "ctc2", "ctc2", 32, | |
a92e0d0a | 1030 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1031 | }, |
1032 | /* ctc3 $rt,$rd */ | |
1033 | { | |
1034 | IQ2000_INSN_CTC3, "ctc3", "ctc3", 32, | |
a92e0d0a | 1035 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1036 | }, |
1037 | /* jcr $rs */ | |
1038 | { | |
1039 | IQ2000_INSN_JCR, "jcr", "jcr", 32, | |
a92e0d0a | 1040 | { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1041 | }, |
1042 | /* luc32 $rt,$rd */ | |
1043 | { | |
1044 | IQ2000_INSN_LUC32, "luc32", "luc32", 32, | |
a92e0d0a | 1045 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1046 | }, |
1047 | /* luc32l $rt,$rd */ | |
1048 | { | |
1049 | IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32, | |
a92e0d0a | 1050 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1051 | }, |
1052 | /* luc64 $rt,$rd */ | |
1053 | { | |
1054 | IQ2000_INSN_LUC64, "luc64", "luc64", 32, | |
a92e0d0a | 1055 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1056 | }, |
1057 | /* luc64l $rt,$rd */ | |
1058 | { | |
1059 | IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32, | |
a92e0d0a | 1060 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1061 | }, |
1062 | /* luk $rt,$rd */ | |
1063 | { | |
1064 | IQ2000_INSN_LUK, "luk", "luk", 32, | |
a92e0d0a | 1065 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1066 | }, |
1067 | /* lulck $rt */ | |
1068 | { | |
1069 | IQ2000_INSN_LULCK, "lulck", "lulck", 32, | |
a92e0d0a | 1070 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1071 | }, |
1072 | /* lum32 $rt,$rd */ | |
1073 | { | |
1074 | IQ2000_INSN_LUM32, "lum32", "lum32", 32, | |
a92e0d0a | 1075 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1076 | }, |
1077 | /* lum32l $rt,$rd */ | |
1078 | { | |
1079 | IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32, | |
a92e0d0a | 1080 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1081 | }, |
1082 | /* lum64 $rt,$rd */ | |
1083 | { | |
1084 | IQ2000_INSN_LUM64, "lum64", "lum64", 32, | |
a92e0d0a | 1085 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1086 | }, |
1087 | /* lum64l $rt,$rd */ | |
1088 | { | |
1089 | IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32, | |
a92e0d0a | 1090 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1091 | }, |
1092 | /* lur $rt,$rd */ | |
1093 | { | |
1094 | IQ2000_INSN_LUR, "lur", "lur", 32, | |
a92e0d0a | 1095 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1096 | }, |
1097 | /* lurl $rt,$rd */ | |
1098 | { | |
1099 | IQ2000_INSN_LURL, "lurl", "lurl", 32, | |
a92e0d0a | 1100 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1101 | }, |
1102 | /* luulck $rt */ | |
1103 | { | |
1104 | IQ2000_INSN_LUULCK, "luulck", "luulck", 32, | |
a92e0d0a | 1105 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1106 | }, |
1107 | /* mfc0 $rt,$rd */ | |
1108 | { | |
1109 | IQ2000_INSN_MFC0, "mfc0", "mfc0", 32, | |
a92e0d0a | 1110 | { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1111 | }, |
1112 | /* mfc1 $rt,$rd */ | |
1113 | { | |
1114 | IQ2000_INSN_MFC1, "mfc1", "mfc1", 32, | |
a92e0d0a | 1115 | { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1116 | }, |
1117 | /* mfc2 $rt,$rd */ | |
1118 | { | |
1119 | IQ2000_INSN_MFC2, "mfc2", "mfc2", 32, | |
a92e0d0a | 1120 | { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1121 | }, |
1122 | /* mfc3 $rt,$rd */ | |
1123 | { | |
1124 | IQ2000_INSN_MFC3, "mfc3", "mfc3", 32, | |
a92e0d0a | 1125 | { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1126 | }, |
1127 | /* mtc0 $rt,$rd */ | |
1128 | { | |
1129 | IQ2000_INSN_MTC0, "mtc0", "mtc0", 32, | |
a92e0d0a | 1130 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1131 | }, |
1132 | /* mtc1 $rt,$rd */ | |
1133 | { | |
1134 | IQ2000_INSN_MTC1, "mtc1", "mtc1", 32, | |
a92e0d0a | 1135 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1136 | }, |
1137 | /* mtc2 $rt,$rd */ | |
1138 | { | |
1139 | IQ2000_INSN_MTC2, "mtc2", "mtc2", 32, | |
a92e0d0a | 1140 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1141 | }, |
1142 | /* mtc3 $rt,$rd */ | |
1143 | { | |
1144 | IQ2000_INSN_MTC3, "mtc3", "mtc3", 32, | |
a92e0d0a | 1145 | { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1146 | }, |
1147 | /* pkrl $rd,$rt */ | |
1148 | { | |
1149 | IQ2000_INSN_PKRL, "pkrl", "pkrl", 32, | |
a92e0d0a | 1150 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1151 | }, |
4030fa5a | 1152 | /* pkrlr1 $rt,$_index,$count */ |
47b1a55a | 1153 | { |
4030fa5a | 1154 | IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32, |
a92e0d0a | 1155 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1156 | }, |
4030fa5a | 1157 | /* pkrlr30 $rt,$_index,$count */ |
47b1a55a | 1158 | { |
4030fa5a | 1159 | IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32, |
a92e0d0a | 1160 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1161 | }, |
1162 | /* rb $rd,$rt */ | |
1163 | { | |
1164 | IQ2000_INSN_RB, "rb", "rb", 32, | |
a92e0d0a | 1165 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1166 | }, |
4030fa5a | 1167 | /* rbr1 $rt,$_index,$count */ |
47b1a55a | 1168 | { |
4030fa5a | 1169 | IQ2000_INSN_RBR1, "rbr1", "rbr1", 32, |
a92e0d0a | 1170 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1171 | }, |
4030fa5a | 1172 | /* rbr30 $rt,$_index,$count */ |
47b1a55a | 1173 | { |
4030fa5a | 1174 | IQ2000_INSN_RBR30, "rbr30", "rbr30", 32, |
a92e0d0a | 1175 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1176 | }, |
1177 | /* rfe */ | |
1178 | { | |
1179 | IQ2000_INSN_RFE, "rfe", "rfe", 32, | |
a92e0d0a | 1180 | { 0, { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1181 | }, |
1182 | /* rx $rd,$rt */ | |
1183 | { | |
1184 | IQ2000_INSN_RX, "rx", "rx", 32, | |
a92e0d0a | 1185 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1186 | }, |
4030fa5a | 1187 | /* rxr1 $rt,$_index,$count */ |
47b1a55a | 1188 | { |
4030fa5a | 1189 | IQ2000_INSN_RXR1, "rxr1", "rxr1", 32, |
a92e0d0a | 1190 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1191 | }, |
4030fa5a | 1192 | /* rxr30 $rt,$_index,$count */ |
47b1a55a | 1193 | { |
4030fa5a | 1194 | IQ2000_INSN_RXR30, "rxr30", "rxr30", 32, |
a92e0d0a | 1195 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1196 | }, |
1197 | /* sleep */ | |
1198 | { | |
1199 | IQ2000_INSN_SLEEP, "sleep", "sleep", 32, | |
a92e0d0a | 1200 | { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1201 | }, |
1202 | /* srrd $rt */ | |
1203 | { | |
1204 | IQ2000_INSN_SRRD, "srrd", "srrd", 32, | |
a92e0d0a | 1205 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1206 | }, |
1207 | /* srrdl $rt */ | |
1208 | { | |
1209 | IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32, | |
a92e0d0a | 1210 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1211 | }, |
1212 | /* srulck $rt */ | |
1213 | { | |
1214 | IQ2000_INSN_SRULCK, "srulck", "srulck", 32, | |
a92e0d0a | 1215 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1216 | }, |
1217 | /* srwr $rt,$rd */ | |
1218 | { | |
1219 | IQ2000_INSN_SRWR, "srwr", "srwr", 32, | |
a92e0d0a | 1220 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1221 | }, |
1222 | /* srwru $rt,$rd */ | |
1223 | { | |
1224 | IQ2000_INSN_SRWRU, "srwru", "srwru", 32, | |
a92e0d0a | 1225 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1226 | }, |
1227 | /* trapqfl */ | |
1228 | { | |
1229 | IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32, | |
a92e0d0a | 1230 | { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1231 | }, |
1232 | /* trapqne */ | |
1233 | { | |
1234 | IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32, | |
a92e0d0a | 1235 | { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1236 | }, |
1237 | /* traprel $rt */ | |
1238 | { | |
1239 | IQ2000_INSN_TRAPREL, "traprel", "traprel", 32, | |
a92e0d0a | 1240 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1241 | }, |
1242 | /* wb $rd,$rt */ | |
1243 | { | |
1244 | IQ2000_INSN_WB, "wb", "wb", 32, | |
a92e0d0a | 1245 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1246 | }, |
1247 | /* wbu $rd,$rt */ | |
1248 | { | |
1249 | IQ2000_INSN_WBU, "wbu", "wbu", 32, | |
a92e0d0a | 1250 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1251 | }, |
4030fa5a | 1252 | /* wbr1 $rt,$_index,$count */ |
47b1a55a | 1253 | { |
4030fa5a | 1254 | IQ2000_INSN_WBR1, "wbr1", "wbr1", 32, |
a92e0d0a | 1255 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1256 | }, |
4030fa5a | 1257 | /* wbr1u $rt,$_index,$count */ |
47b1a55a | 1258 | { |
4030fa5a | 1259 | IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32, |
a92e0d0a | 1260 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1261 | }, |
4030fa5a | 1262 | /* wbr30 $rt,$_index,$count */ |
47b1a55a | 1263 | { |
4030fa5a | 1264 | IQ2000_INSN_WBR30, "wbr30", "wbr30", 32, |
a92e0d0a | 1265 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1266 | }, |
4030fa5a | 1267 | /* wbr30u $rt,$_index,$count */ |
47b1a55a | 1268 | { |
4030fa5a | 1269 | IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32, |
a92e0d0a | 1270 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1271 | }, |
1272 | /* wx $rd,$rt */ | |
1273 | { | |
1274 | IQ2000_INSN_WX, "wx", "wx", 32, | |
a92e0d0a | 1275 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1276 | }, |
1277 | /* wxu $rd,$rt */ | |
1278 | { | |
1279 | IQ2000_INSN_WXU, "wxu", "wxu", 32, | |
a92e0d0a | 1280 | { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1281 | }, |
4030fa5a | 1282 | /* wxr1 $rt,$_index,$count */ |
47b1a55a | 1283 | { |
4030fa5a | 1284 | IQ2000_INSN_WXR1, "wxr1", "wxr1", 32, |
a92e0d0a | 1285 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1286 | }, |
4030fa5a | 1287 | /* wxr1u $rt,$_index,$count */ |
47b1a55a | 1288 | { |
4030fa5a | 1289 | IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32, |
a92e0d0a | 1290 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1291 | }, |
4030fa5a | 1292 | /* wxr30 $rt,$_index,$count */ |
47b1a55a | 1293 | { |
4030fa5a | 1294 | IQ2000_INSN_WXR30, "wxr30", "wxr30", 32, |
a92e0d0a | 1295 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a | 1296 | }, |
4030fa5a | 1297 | /* wxr30u $rt,$_index,$count */ |
47b1a55a | 1298 | { |
4030fa5a | 1299 | IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32, |
a92e0d0a | 1300 | { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1301 | }, |
1302 | /* ldw $rt,$lo16($base) */ | |
1303 | { | |
1304 | IQ2000_INSN_LDW, "ldw", "ldw", 32, | |
a92e0d0a | 1305 | { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1306 | }, |
1307 | /* sdw $rt,$lo16($base) */ | |
1308 | { | |
1309 | IQ2000_INSN_SDW, "sdw", "sdw", 32, | |
a92e0d0a | 1310 | { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1311 | }, |
1312 | /* j $jmptarg */ | |
1313 | { | |
1314 | IQ2000_INSN_J, "j", "j", 32, | |
a92e0d0a | 1315 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1316 | }, |
1317 | /* jal $jmptarg */ | |
1318 | { | |
1319 | IQ2000_INSN_JAL, "jal", "jal", 32, | |
a92e0d0a | 1320 | { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1321 | }, |
1322 | /* bmb $rs,$rt,$offset */ | |
1323 | { | |
1324 | IQ2000_INSN_BMB, "bmb", "bmb", 32, | |
a92e0d0a | 1325 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } |
47b1a55a SC |
1326 | }, |
1327 | /* andoui $rt,$rs,$hi16 */ | |
1328 | { | |
1329 | IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32, | |
a92e0d0a | 1330 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1331 | }, |
1332 | /* andoui ${rt-rs},$hi16 */ | |
1333 | { | |
1334 | -1, "andoui2-q10", "andoui", 32, | |
a92e0d0a | 1335 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1336 | }, |
1337 | /* orui $rt,$rs,$hi16 */ | |
1338 | { | |
1339 | IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32, | |
a92e0d0a | 1340 | { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1341 | }, |
1342 | /* orui ${rt-rs},$hi16 */ | |
1343 | { | |
1344 | -1, "orui2-q10", "orui", 32, | |
a92e0d0a | 1345 | { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1346 | }, |
1347 | /* mrgb $rd,$rs,$rt,$maskq10 */ | |
1348 | { | |
1349 | IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32, | |
a92e0d0a | 1350 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1351 | }, |
1352 | /* mrgb ${rd-rs},$rt,$maskq10 */ | |
1353 | { | |
1354 | -1, "mrgbq102", "mrgb", 32, | |
a92e0d0a | 1355 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1356 | }, |
1357 | /* j $jmptarg */ | |
1358 | { | |
1359 | IQ2000_INSN_JQ10, "jq10", "j", 32, | |
a92e0d0a | 1360 | { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1361 | }, |
1362 | /* jal $rt,$jmptarg */ | |
1363 | { | |
1364 | IQ2000_INSN_JALQ10, "jalq10", "jal", 32, | |
a92e0d0a | 1365 | { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1366 | }, |
1367 | /* jal $jmptarg */ | |
1368 | { | |
1369 | IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32, | |
a92e0d0a | 1370 | { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1371 | }, |
1372 | /* bbil $rs($bitnum),$offset */ | |
1373 | { | |
1374 | IQ2000_INSN_BBIL, "bbil", "bbil", 32, | |
a92e0d0a | 1375 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1376 | }, |
1377 | /* bbinl $rs($bitnum),$offset */ | |
1378 | { | |
1379 | IQ2000_INSN_BBINL, "bbinl", "bbinl", 32, | |
a92e0d0a | 1380 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1381 | }, |
1382 | /* bbvl $rs,$rt,$offset */ | |
1383 | { | |
1384 | IQ2000_INSN_BBVL, "bbvl", "bbvl", 32, | |
a92e0d0a | 1385 | { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1386 | }, |
1387 | /* bbvnl $rs,$rt,$offset */ | |
1388 | { | |
1389 | IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32, | |
a92e0d0a | 1390 | { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1391 | }, |
1392 | /* bgtzal $rs,$offset */ | |
1393 | { | |
1394 | IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32, | |
a92e0d0a | 1395 | { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1396 | }, |
1397 | /* bgtzall $rs,$offset */ | |
1398 | { | |
1399 | IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32, | |
a92e0d0a | 1400 | { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1401 | }, |
1402 | /* blezal $rs,$offset */ | |
1403 | { | |
1404 | IQ2000_INSN_BLEZAL, "blezal", "blezal", 32, | |
a92e0d0a | 1405 | { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1406 | }, |
1407 | /* blezall $rs,$offset */ | |
1408 | { | |
1409 | IQ2000_INSN_BLEZALL, "blezall", "blezall", 32, | |
a92e0d0a | 1410 | { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1411 | }, |
1412 | /* bgtz $rs,$offset */ | |
1413 | { | |
1414 | IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32, | |
a92e0d0a | 1415 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1416 | }, |
1417 | /* bgtzl $rs,$offset */ | |
1418 | { | |
1419 | IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32, | |
a92e0d0a | 1420 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1421 | }, |
1422 | /* blez $rs,$offset */ | |
1423 | { | |
1424 | IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32, | |
a92e0d0a | 1425 | { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1426 | }, |
1427 | /* blezl $rs,$offset */ | |
1428 | { | |
1429 | IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32, | |
a92e0d0a | 1430 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1431 | }, |
1432 | /* bmb $rs,$rt,$offset */ | |
1433 | { | |
1434 | IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32, | |
a92e0d0a | 1435 | { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1436 | }, |
1437 | /* bmbl $rs,$rt,$offset */ | |
1438 | { | |
1439 | IQ2000_INSN_BMBL, "bmbl", "bmbl", 32, | |
a92e0d0a | 1440 | { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1441 | }, |
1442 | /* bri $rs,$offset */ | |
1443 | { | |
1444 | IQ2000_INSN_BRI, "bri", "bri", 32, | |
a92e0d0a | 1445 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1446 | }, |
1447 | /* brv $rs,$offset */ | |
1448 | { | |
1449 | IQ2000_INSN_BRV, "brv", "brv", 32, | |
a92e0d0a | 1450 | { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1451 | }, |
1452 | /* bctx $rs,$offset */ | |
1453 | { | |
1454 | IQ2000_INSN_BCTX, "bctx", "bctx", 32, | |
a92e0d0a | 1455 | { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1456 | }, |
1457 | /* yield */ | |
1458 | { | |
1459 | IQ2000_INSN_YIELD, "yield", "yield", 32, | |
a92e0d0a | 1460 | { 0, { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1461 | }, |
1462 | /* crc32 $rd,$rs,$rt */ | |
1463 | { | |
1464 | IQ2000_INSN_CRC32, "crc32", "crc32", 32, | |
a92e0d0a | 1465 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1466 | }, |
1467 | /* crc32b $rd,$rs,$rt */ | |
1468 | { | |
1469 | IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32, | |
a92e0d0a | 1470 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1471 | }, |
1472 | /* cnt1s $rd,$rs */ | |
1473 | { | |
1474 | IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32, | |
a92e0d0a | 1475 | { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1476 | }, |
1477 | /* avail $rd */ | |
1478 | { | |
1479 | IQ2000_INSN_AVAIL, "avail", "avail", 32, | |
a92e0d0a | 1480 | { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1481 | }, |
1482 | /* free $rd,$rs */ | |
1483 | { | |
1484 | IQ2000_INSN_FREE, "free", "free", 32, | |
a92e0d0a | 1485 | { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1486 | }, |
1487 | /* tstod $rd,$rs */ | |
1488 | { | |
1489 | IQ2000_INSN_TSTOD, "tstod", "tstod", 32, | |
a92e0d0a | 1490 | { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1491 | }, |
1492 | /* cmphdr $rd */ | |
1493 | { | |
1494 | IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32, | |
a92e0d0a | 1495 | { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1496 | }, |
1497 | /* mcid $rd,$rt */ | |
1498 | { | |
1499 | IQ2000_INSN_MCID, "mcid", "mcid", 32, | |
a92e0d0a | 1500 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1501 | }, |
1502 | /* dba $rd */ | |
1503 | { | |
1504 | IQ2000_INSN_DBA, "dba", "dba", 32, | |
a92e0d0a | 1505 | { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1506 | }, |
1507 | /* dbd $rd,$rs,$rt */ | |
1508 | { | |
1509 | IQ2000_INSN_DBD, "dbd", "dbd", 32, | |
a92e0d0a | 1510 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1511 | }, |
1512 | /* dpwt $rd,$rs */ | |
1513 | { | |
1514 | IQ2000_INSN_DPWT, "dpwt", "dpwt", 32, | |
a92e0d0a | 1515 | { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1516 | }, |
1517 | /* chkhdr $rd,$rs */ | |
1518 | { | |
1519 | IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32, | |
a92e0d0a | 1520 | { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1521 | }, |
1522 | /* rba $rd,$rs,$rt */ | |
1523 | { | |
1524 | IQ2000_INSN_RBA, "rba", "rba", 32, | |
a92e0d0a | 1525 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1526 | }, |
1527 | /* rbal $rd,$rs,$rt */ | |
1528 | { | |
1529 | IQ2000_INSN_RBAL, "rbal", "rbal", 32, | |
a92e0d0a | 1530 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1531 | }, |
1532 | /* rbar $rd,$rs,$rt */ | |
1533 | { | |
1534 | IQ2000_INSN_RBAR, "rbar", "rbar", 32, | |
a92e0d0a | 1535 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1536 | }, |
1537 | /* wba $rd,$rs,$rt */ | |
1538 | { | |
1539 | IQ2000_INSN_WBA, "wba", "wba", 32, | |
a92e0d0a | 1540 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1541 | }, |
1542 | /* wbau $rd,$rs,$rt */ | |
1543 | { | |
1544 | IQ2000_INSN_WBAU, "wbau", "wbau", 32, | |
a92e0d0a | 1545 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1546 | }, |
1547 | /* wbac $rd,$rs,$rt */ | |
1548 | { | |
1549 | IQ2000_INSN_WBAC, "wbac", "wbac", 32, | |
a92e0d0a | 1550 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1551 | }, |
1552 | /* rbi $rd,$rs,$rt,$bytecount */ | |
1553 | { | |
1554 | IQ2000_INSN_RBI, "rbi", "rbi", 32, | |
a92e0d0a | 1555 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1556 | }, |
1557 | /* rbil $rd,$rs,$rt,$bytecount */ | |
1558 | { | |
1559 | IQ2000_INSN_RBIL, "rbil", "rbil", 32, | |
a92e0d0a | 1560 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1561 | }, |
1562 | /* rbir $rd,$rs,$rt,$bytecount */ | |
1563 | { | |
1564 | IQ2000_INSN_RBIR, "rbir", "rbir", 32, | |
a92e0d0a | 1565 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1566 | }, |
1567 | /* wbi $rd,$rs,$rt,$bytecount */ | |
1568 | { | |
1569 | IQ2000_INSN_WBI, "wbi", "wbi", 32, | |
a92e0d0a | 1570 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1571 | }, |
1572 | /* wbic $rd,$rs,$rt,$bytecount */ | |
1573 | { | |
1574 | IQ2000_INSN_WBIC, "wbic", "wbic", 32, | |
a92e0d0a | 1575 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1576 | }, |
1577 | /* wbiu $rd,$rs,$rt,$bytecount */ | |
1578 | { | |
1579 | IQ2000_INSN_WBIU, "wbiu", "wbiu", 32, | |
a92e0d0a | 1580 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1581 | }, |
1582 | /* pkrli $rd,$rs,$rt,$bytecount */ | |
1583 | { | |
1584 | IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32, | |
a92e0d0a | 1585 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1586 | }, |
1587 | /* pkrlih $rd,$rs,$rt,$bytecount */ | |
1588 | { | |
1589 | IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32, | |
a92e0d0a | 1590 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1591 | }, |
1592 | /* pkrliu $rd,$rs,$rt,$bytecount */ | |
1593 | { | |
1594 | IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32, | |
a92e0d0a | 1595 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1596 | }, |
1597 | /* pkrlic $rd,$rs,$rt,$bytecount */ | |
1598 | { | |
1599 | IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32, | |
a92e0d0a | 1600 | { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1601 | }, |
1602 | /* pkrla $rd,$rs,$rt */ | |
1603 | { | |
1604 | IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32, | |
a92e0d0a | 1605 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1606 | }, |
1607 | /* pkrlau $rd,$rs,$rt */ | |
1608 | { | |
1609 | IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32, | |
a92e0d0a | 1610 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1611 | }, |
1612 | /* pkrlah $rd,$rs,$rt */ | |
1613 | { | |
1614 | IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32, | |
a92e0d0a | 1615 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1616 | }, |
1617 | /* pkrlac $rd,$rs,$rt */ | |
1618 | { | |
1619 | IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32, | |
a92e0d0a | 1620 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1621 | }, |
1622 | /* lock $rd,$rt */ | |
1623 | { | |
1624 | IQ2000_INSN_LOCK, "lock", "lock", 32, | |
a92e0d0a | 1625 | { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1626 | }, |
1627 | /* unlk $rd,$rt */ | |
1628 | { | |
1629 | IQ2000_INSN_UNLK, "unlk", "unlk", 32, | |
a92e0d0a | 1630 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1631 | }, |
1632 | /* swrd $rd,$rt */ | |
1633 | { | |
1634 | IQ2000_INSN_SWRD, "swrd", "swrd", 32, | |
a92e0d0a | 1635 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1636 | }, |
1637 | /* swrdl $rd,$rt */ | |
1638 | { | |
1639 | IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32, | |
a92e0d0a | 1640 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1641 | }, |
1642 | /* swwr $rd,$rs,$rt */ | |
1643 | { | |
1644 | IQ2000_INSN_SWWR, "swwr", "swwr", 32, | |
a92e0d0a | 1645 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1646 | }, |
1647 | /* swwru $rd,$rs,$rt */ | |
1648 | { | |
1649 | IQ2000_INSN_SWWRU, "swwru", "swwru", 32, | |
a92e0d0a | 1650 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1651 | }, |
1652 | /* dwrd $rd,$rt */ | |
1653 | { | |
1654 | IQ2000_INSN_DWRD, "dwrd", "dwrd", 32, | |
a92e0d0a | 1655 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1656 | }, |
1657 | /* dwrdl $rd,$rt */ | |
1658 | { | |
1659 | IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32, | |
a92e0d0a | 1660 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1661 | }, |
1662 | /* cam36 $rd,$rt,${cam-z},${cam-y} */ | |
1663 | { | |
1664 | IQ2000_INSN_CAM36, "cam36", "cam36", 32, | |
a92e0d0a | 1665 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1666 | }, |
1667 | /* cam72 $rd,$rt,${cam-y},${cam-z} */ | |
1668 | { | |
1669 | IQ2000_INSN_CAM72, "cam72", "cam72", 32, | |
a92e0d0a | 1670 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1671 | }, |
1672 | /* cam144 $rd,$rt,${cam-y},${cam-z} */ | |
1673 | { | |
1674 | IQ2000_INSN_CAM144, "cam144", "cam144", 32, | |
a92e0d0a | 1675 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1676 | }, |
1677 | /* cam288 $rd,$rt,${cam-y},${cam-z} */ | |
1678 | { | |
1679 | IQ2000_INSN_CAM288, "cam288", "cam288", 32, | |
a92e0d0a | 1680 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1681 | }, |
1682 | /* cm32and $rd,$rs,$rt */ | |
1683 | { | |
1684 | IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32, | |
a92e0d0a | 1685 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1686 | }, |
1687 | /* cm32andn $rd,$rs,$rt */ | |
1688 | { | |
1689 | IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32, | |
a92e0d0a | 1690 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1691 | }, |
1692 | /* cm32or $rd,$rs,$rt */ | |
1693 | { | |
1694 | IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32, | |
a92e0d0a | 1695 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1696 | }, |
1697 | /* cm32ra $rd,$rs,$rt */ | |
1698 | { | |
1699 | IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32, | |
a92e0d0a | 1700 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1701 | }, |
1702 | /* cm32rd $rd,$rt */ | |
1703 | { | |
1704 | IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32, | |
a92e0d0a | 1705 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1706 | }, |
1707 | /* cm32ri $rd,$rt */ | |
1708 | { | |
1709 | IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32, | |
a92e0d0a | 1710 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1711 | }, |
1712 | /* cm32rs $rd,$rs,$rt */ | |
1713 | { | |
1714 | IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32, | |
a92e0d0a | 1715 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1716 | }, |
1717 | /* cm32sa $rd,$rs,$rt */ | |
1718 | { | |
1719 | IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32, | |
a92e0d0a | 1720 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1721 | }, |
1722 | /* cm32sd $rd,$rt */ | |
1723 | { | |
1724 | IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32, | |
a92e0d0a | 1725 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1726 | }, |
1727 | /* cm32si $rd,$rt */ | |
1728 | { | |
1729 | IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32, | |
a92e0d0a | 1730 | { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1731 | }, |
1732 | /* cm32ss $rd,$rs,$rt */ | |
1733 | { | |
1734 | IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32, | |
a92e0d0a | 1735 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1736 | }, |
1737 | /* cm32xor $rd,$rs,$rt */ | |
1738 | { | |
1739 | IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32, | |
a92e0d0a | 1740 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1741 | }, |
1742 | /* cm64clr $rd,$rt */ | |
1743 | { | |
1744 | IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32, | |
a92e0d0a | 1745 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1746 | }, |
1747 | /* cm64ra $rd,$rs,$rt */ | |
1748 | { | |
1749 | IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32, | |
a92e0d0a | 1750 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1751 | }, |
1752 | /* cm64rd $rd,$rt */ | |
1753 | { | |
1754 | IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32, | |
a92e0d0a | 1755 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1756 | }, |
1757 | /* cm64ri $rd,$rt */ | |
1758 | { | |
1759 | IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32, | |
a92e0d0a | 1760 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1761 | }, |
1762 | /* cm64ria2 $rd,$rs,$rt */ | |
1763 | { | |
1764 | IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32, | |
a92e0d0a | 1765 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1766 | }, |
1767 | /* cm64rs $rd,$rs,$rt */ | |
1768 | { | |
1769 | IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32, | |
a92e0d0a | 1770 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1771 | }, |
1772 | /* cm64sa $rd,$rs,$rt */ | |
1773 | { | |
1774 | IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32, | |
a92e0d0a | 1775 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1776 | }, |
1777 | /* cm64sd $rd,$rt */ | |
1778 | { | |
1779 | IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32, | |
a92e0d0a | 1780 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1781 | }, |
1782 | /* cm64si $rd,$rt */ | |
1783 | { | |
1784 | IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32, | |
a92e0d0a | 1785 | { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1786 | }, |
1787 | /* cm64sia2 $rd,$rs,$rt */ | |
1788 | { | |
1789 | IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32, | |
a92e0d0a | 1790 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1791 | }, |
1792 | /* cm64ss $rd,$rs,$rt */ | |
1793 | { | |
1794 | IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32, | |
a92e0d0a | 1795 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1796 | }, |
1797 | /* cm128ria2 $rd,$rs,$rt */ | |
1798 | { | |
1799 | IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32, | |
a92e0d0a | 1800 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1801 | }, |
1802 | /* cm128ria3 $rd,$rs,$rt,${cm-3z} */ | |
1803 | { | |
1804 | IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32, | |
a92e0d0a | 1805 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1806 | }, |
1807 | /* cm128ria4 $rd,$rs,$rt,${cm-4z} */ | |
1808 | { | |
1809 | IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32, | |
a92e0d0a | 1810 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1811 | }, |
1812 | /* cm128sia2 $rd,$rs,$rt */ | |
1813 | { | |
1814 | IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32, | |
a92e0d0a | 1815 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1816 | }, |
1817 | /* cm128sia3 $rd,$rs,$rt,${cm-3z} */ | |
1818 | { | |
1819 | IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32, | |
a92e0d0a | 1820 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1821 | }, |
1822 | /* cm128sia4 $rd,$rs,$rt,${cm-4z} */ | |
1823 | { | |
1824 | IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32, | |
a92e0d0a | 1825 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1826 | }, |
1827 | /* cm128vsa $rd,$rs,$rt */ | |
1828 | { | |
1829 | IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32, | |
a92e0d0a | 1830 | { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1831 | }, |
1832 | /* cfc $rd,$rt */ | |
1833 | { | |
1834 | IQ2000_INSN_CFC, "cfc", "cfc", 32, | |
a92e0d0a | 1835 | { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1836 | }, |
1837 | /* ctc $rs,$rt */ | |
1838 | { | |
1839 | IQ2000_INSN_CTC, "ctc", "ctc", 32, | |
a92e0d0a | 1840 | { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } |
47b1a55a SC |
1841 | }, |
1842 | }; | |
1843 | ||
1844 | #undef OP | |
1845 | #undef A | |
1846 | ||
1847 | /* Initialize anything needed to be done once, before any cpu_open call. */ | |
47b1a55a SC |
1848 | |
1849 | static void | |
47b0e7ad | 1850 | init_tables (void) |
47b1a55a SC |
1851 | { |
1852 | } | |
1853 | ||
a6743a54 AM |
1854 | #ifndef opcodes_error_handler |
1855 | #define opcodes_error_handler(...) \ | |
1856 | fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) | |
1857 | #endif | |
1858 | ||
47b0e7ad NC |
1859 | static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); |
1860 | static void build_hw_table (CGEN_CPU_TABLE *); | |
1861 | static void build_ifield_table (CGEN_CPU_TABLE *); | |
1862 | static void build_operand_table (CGEN_CPU_TABLE *); | |
1863 | static void build_insn_table (CGEN_CPU_TABLE *); | |
1864 | static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *); | |
47b1a55a SC |
1865 | |
1866 | /* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name. */ | |
1867 | ||
1868 | static const CGEN_MACH * | |
47b0e7ad | 1869 | lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) |
47b1a55a SC |
1870 | { |
1871 | while (table->name) | |
1872 | { | |
1873 | if (strcmp (name, table->bfd_name) == 0) | |
1874 | return table; | |
1875 | ++table; | |
1876 | } | |
42742084 | 1877 | return NULL; |
47b1a55a SC |
1878 | } |
1879 | ||
1880 | /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ | |
1881 | ||
1882 | static void | |
47b0e7ad | 1883 | build_hw_table (CGEN_CPU_TABLE *cd) |
47b1a55a SC |
1884 | { |
1885 | int i; | |
1886 | int machs = cd->machs; | |
1887 | const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0]; | |
1888 | /* MAX_HW is only an upper bound on the number of selected entries. | |
1889 | However each entry is indexed by it's enum so there can be holes in | |
1890 | the table. */ | |
1891 | const CGEN_HW_ENTRY **selected = | |
1892 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1893 | ||
1894 | cd->hw_table.init_entries = init; | |
1895 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); | |
1896 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1897 | /* ??? For now we just use machs to determine which ones we want. */ | |
1898 | for (i = 0; init[i].name != NULL; ++i) | |
1899 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) | |
1900 | & machs) | |
1901 | selected[init[i].type] = &init[i]; | |
1902 | cd->hw_table.entries = selected; | |
1903 | cd->hw_table.num_entries = MAX_HW; | |
1904 | } | |
1905 | ||
1906 | /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ | |
1907 | ||
1908 | static void | |
47b0e7ad | 1909 | build_ifield_table (CGEN_CPU_TABLE *cd) |
47b1a55a SC |
1910 | { |
1911 | cd->ifld_table = & iq2000_cgen_ifld_table[0]; | |
1912 | } | |
1913 | ||
1914 | /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ | |
1915 | ||
1916 | static void | |
47b0e7ad | 1917 | build_operand_table (CGEN_CPU_TABLE *cd) |
47b1a55a SC |
1918 | { |
1919 | int i; | |
1920 | int machs = cd->machs; | |
1921 | const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0]; | |
1922 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. | |
1923 | However each entry is indexed by it's enum so there can be holes in | |
1924 | the table. */ | |
47b0e7ad | 1925 | const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); |
47b1a55a SC |
1926 | |
1927 | cd->operand_table.init_entries = init; | |
1928 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); | |
1929 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
1930 | /* ??? For now we just use mach to determine which ones we want. */ | |
1931 | for (i = 0; init[i].name != NULL; ++i) | |
1932 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) | |
1933 | & machs) | |
1934 | selected[init[i].type] = &init[i]; | |
1935 | cd->operand_table.entries = selected; | |
1936 | cd->operand_table.num_entries = MAX_OPERANDS; | |
1937 | } | |
1938 | ||
1939 | /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. | |
1940 | ??? This could leave out insns not supported by the specified mach/isa, | |
1941 | but that would cause errors like "foo only supported by bar" to become | |
1942 | "unknown insn", so for now we include all insns and require the app to | |
1943 | do the checking later. | |
1944 | ??? On the other hand, parsing of such insns may require their hardware or | |
1945 | operand elements to be in the table [which they mightn't be]. */ | |
1946 | ||
1947 | static void | |
47b0e7ad | 1948 | build_insn_table (CGEN_CPU_TABLE *cd) |
47b1a55a SC |
1949 | { |
1950 | int i; | |
1951 | const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; | |
47b0e7ad | 1952 | CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); |
47b1a55a SC |
1953 | |
1954 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); | |
1955 | for (i = 0; i < MAX_INSNS; ++i) | |
1956 | insns[i].base = &ib[i]; | |
1957 | cd->insn_table.init_entries = insns; | |
1958 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); | |
1959 | cd->insn_table.num_init_entries = MAX_INSNS; | |
1960 | } | |
1961 | ||
1962 | /* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ | |
1963 | ||
1964 | static void | |
47b0e7ad | 1965 | iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) |
47b1a55a SC |
1966 | { |
1967 | int i; | |
a92e0d0a | 1968 | CGEN_BITSET *isas = cd->isas; |
47b1a55a SC |
1969 | unsigned int machs = cd->machs; |
1970 | ||
1971 | cd->int_insn_p = CGEN_INT_INSN_P; | |
1972 | ||
1973 | /* Data derived from the isa spec. */ | |
1974 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) | |
1975 | cd->default_insn_bitsize = UNSET; | |
1976 | cd->base_insn_bitsize = UNSET; | |
47b0e7ad | 1977 | cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ |
47b1a55a SC |
1978 | cd->max_insn_bitsize = 0; |
1979 | for (i = 0; i < MAX_ISAS; ++i) | |
a92e0d0a | 1980 | if (cgen_bitset_contains (isas, i)) |
47b1a55a SC |
1981 | { |
1982 | const CGEN_ISA *isa = & iq2000_cgen_isa_table[i]; | |
1983 | ||
1984 | /* Default insn sizes of all selected isas must be | |
1985 | equal or we set the result to 0, meaning "unknown". */ | |
1986 | if (cd->default_insn_bitsize == UNSET) | |
1987 | cd->default_insn_bitsize = isa->default_insn_bitsize; | |
1988 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) | |
47b0e7ad | 1989 | ; /* This is ok. */ |
47b1a55a SC |
1990 | else |
1991 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1992 | ||
1993 | /* Base insn sizes of all selected isas must be equal | |
1994 | or we set the result to 0, meaning "unknown". */ | |
1995 | if (cd->base_insn_bitsize == UNSET) | |
1996 | cd->base_insn_bitsize = isa->base_insn_bitsize; | |
1997 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) | |
47b0e7ad | 1998 | ; /* This is ok. */ |
47b1a55a SC |
1999 | else |
2000 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
2001 | ||
2002 | /* Set min,max insn sizes. */ | |
2003 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) | |
2004 | cd->min_insn_bitsize = isa->min_insn_bitsize; | |
2005 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) | |
2006 | cd->max_insn_bitsize = isa->max_insn_bitsize; | |
2007 | } | |
2008 | ||
2009 | /* Data derived from the mach spec. */ | |
2010 | for (i = 0; i < MAX_MACHS; ++i) | |
2011 | if (((1 << i) & machs) != 0) | |
2012 | { | |
2013 | const CGEN_MACH *mach = & iq2000_cgen_mach_table[i]; | |
2014 | ||
2015 | if (mach->insn_chunk_bitsize != 0) | |
2016 | { | |
2017 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) | |
2018 | { | |
a6743a54 AM |
2019 | opcodes_error_handler |
2020 | (/* xgettext:c-format */ | |
2021 | _("internal error: iq2000_cgen_rebuild_tables: " | |
2022 | "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), | |
2023 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); | |
47b1a55a SC |
2024 | abort (); |
2025 | } | |
2026 | ||
2027 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; | |
2028 | } | |
2029 | } | |
2030 | ||
2031 | /* Determine which hw elements are used by MACH. */ | |
2032 | build_hw_table (cd); | |
2033 | ||
2034 | /* Build the ifield table. */ | |
2035 | build_ifield_table (cd); | |
2036 | ||
2037 | /* Determine which operands are used by MACH/ISA. */ | |
2038 | build_operand_table (cd); | |
2039 | ||
2040 | /* Build the instruction table. */ | |
2041 | build_insn_table (cd); | |
2042 | } | |
2043 | ||
2044 | /* Initialize a cpu table and return a descriptor. | |
2045 | It's much like opening a file, and must be the first function called. | |
2046 | The arguments are a set of (type/value) pairs, terminated with | |
2047 | CGEN_CPU_OPEN_END. | |
2048 | ||
2049 | Currently supported values: | |
2050 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr | |
2051 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr | |
2052 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name | |
2053 | CGEN_CPU_OPEN_ENDIAN: specify endian choice | |
b3db6d07 | 2054 | CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice |
47b1a55a SC |
2055 | CGEN_CPU_OPEN_END: terminates arguments |
2056 | ||
2057 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) | |
37ec9240 | 2058 | precluded. */ |
47b1a55a SC |
2059 | |
2060 | CGEN_CPU_DESC | |
2061 | iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) | |
2062 | { | |
2063 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); | |
2064 | static int init_p; | |
a92e0d0a | 2065 | CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ |
47b1a55a SC |
2066 | unsigned int machs = 0; /* 0 = "unspecified" */ |
2067 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; | |
b3db6d07 | 2068 | enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; |
47b1a55a SC |
2069 | va_list ap; |
2070 | ||
2071 | if (! init_p) | |
2072 | { | |
2073 | init_tables (); | |
2074 | init_p = 1; | |
2075 | } | |
2076 | ||
2077 | memset (cd, 0, sizeof (*cd)); | |
2078 | ||
2079 | va_start (ap, arg_type); | |
2080 | while (arg_type != CGEN_CPU_OPEN_END) | |
2081 | { | |
2082 | switch (arg_type) | |
2083 | { | |
2084 | case CGEN_CPU_OPEN_ISAS : | |
a92e0d0a | 2085 | isas = va_arg (ap, CGEN_BITSET *); |
47b1a55a SC |
2086 | break; |
2087 | case CGEN_CPU_OPEN_MACHS : | |
2088 | machs = va_arg (ap, unsigned int); | |
2089 | break; | |
2090 | case CGEN_CPU_OPEN_BFDMACH : | |
2091 | { | |
2092 | const char *name = va_arg (ap, const char *); | |
2093 | const CGEN_MACH *mach = | |
2094 | lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name); | |
2095 | ||
42742084 AM |
2096 | if (mach != NULL) |
2097 | machs |= 1 << mach->num; | |
47b1a55a SC |
2098 | break; |
2099 | } | |
2100 | case CGEN_CPU_OPEN_ENDIAN : | |
2101 | endian = va_arg (ap, enum cgen_endian); | |
2102 | break; | |
b3db6d07 JM |
2103 | case CGEN_CPU_OPEN_INSN_ENDIAN : |
2104 | insn_endian = va_arg (ap, enum cgen_endian); | |
2105 | break; | |
47b1a55a | 2106 | default : |
a6743a54 AM |
2107 | opcodes_error_handler |
2108 | (/* xgettext:c-format */ | |
2109 | _("internal error: iq2000_cgen_cpu_open: " | |
2110 | "unsupported argument `%d'"), | |
2111 | arg_type); | |
47b1a55a SC |
2112 | abort (); /* ??? return NULL? */ |
2113 | } | |
2114 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); | |
2115 | } | |
2116 | va_end (ap); | |
2117 | ||
47b0e7ad | 2118 | /* Mach unspecified means "all". */ |
47b1a55a SC |
2119 | if (machs == 0) |
2120 | machs = (1 << MAX_MACHS) - 1; | |
47b0e7ad | 2121 | /* Base mach is always selected. */ |
47b1a55a | 2122 | machs |= 1; |
47b1a55a SC |
2123 | if (endian == CGEN_ENDIAN_UNKNOWN) |
2124 | { | |
2125 | /* ??? If target has only one, could have a default. */ | |
a6743a54 AM |
2126 | opcodes_error_handler |
2127 | (/* xgettext:c-format */ | |
2128 | _("internal error: iq2000_cgen_cpu_open: no endianness specified")); | |
47b1a55a SC |
2129 | abort (); |
2130 | } | |
2131 | ||
a92e0d0a | 2132 | cd->isas = cgen_bitset_copy (isas); |
47b1a55a SC |
2133 | cd->machs = machs; |
2134 | cd->endian = endian; | |
b3db6d07 JM |
2135 | cd->insn_endian |
2136 | = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); | |
47b1a55a SC |
2137 | |
2138 | /* Table (re)builder. */ | |
2139 | cd->rebuild_tables = iq2000_cgen_rebuild_tables; | |
2140 | iq2000_cgen_rebuild_tables (cd); | |
2141 | ||
2142 | /* Default to not allowing signed overflow. */ | |
2143 | cd->signed_overflow_ok_p = 0; | |
43e65147 | 2144 | |
47b1a55a SC |
2145 | return (CGEN_CPU_DESC) cd; |
2146 | } | |
2147 | ||
2148 | /* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. | |
2149 | MACH_NAME is the bfd name of the mach. */ | |
2150 | ||
2151 | CGEN_CPU_DESC | |
47b0e7ad | 2152 | iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) |
47b1a55a SC |
2153 | { |
2154 | return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
2155 | CGEN_CPU_OPEN_ENDIAN, endian, | |
2156 | CGEN_CPU_OPEN_END); | |
2157 | } | |
2158 | ||
2159 | /* Close a cpu table. | |
2160 | ??? This can live in a machine independent file, but there's currently | |
2161 | no place to put this file (there's no libcgen). libopcodes is the wrong | |
2162 | place as some simulator ports use this but they don't use libopcodes. */ | |
2163 | ||
2164 | void | |
47b0e7ad | 2165 | iq2000_cgen_cpu_close (CGEN_CPU_DESC cd) |
47b1a55a SC |
2166 | { |
2167 | unsigned int i; | |
75798298 | 2168 | const CGEN_INSN *insns; |
47b1a55a SC |
2169 | |
2170 | if (cd->macro_insn_table.init_entries) | |
2171 | { | |
2172 | insns = cd->macro_insn_table.init_entries; | |
2173 | for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) | |
47b0e7ad NC |
2174 | if (CGEN_INSN_RX ((insns))) |
2175 | regfree (CGEN_INSN_RX (insns)); | |
47b1a55a SC |
2176 | } |
2177 | ||
2178 | if (cd->insn_table.init_entries) | |
2179 | { | |
2180 | insns = cd->insn_table.init_entries; | |
2181 | for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) | |
47b0e7ad NC |
2182 | if (CGEN_INSN_RX (insns)) |
2183 | regfree (CGEN_INSN_RX (insns)); | |
43e65147 | 2184 | } |
47b1a55a | 2185 | |
d96bf37b AM |
2186 | free ((CGEN_INSN *) cd->macro_insn_table.init_entries); |
2187 | free ((CGEN_INSN *) cd->insn_table.init_entries); | |
2188 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); | |
2189 | free ((CGEN_HW_ENTRY *) cd->operand_table.entries); | |
47b1a55a SC |
2190 | free (cd); |
2191 | } | |
2192 |