[thirdparty/binutils-gdb.git] / sim / arm / armdefs.h

/*  armdefs.h -- ARMulator common definitions:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */

#include "config.h"
#include <stdio.h>
#include <stdlib.h>

#define FALSE 0
#define TRUE 1
#define LOW 0
#define HIGH 1
#define LOWHIGH 1
#define HIGHLOW 2

#ifndef __STDC__
typedef char *VoidStar;
#endif

#ifdef HAVE_STDINT_H
#include <stdint.h>
typedef uint32_t ARMword;
typedef int32_t ARMsword;
typedef uint64_t ARMdword;
typedef int64_t ARMsdword;
#else
typedef unsigned int ARMword;	/* must be 32 bits wide */
typedef signed int ARMsword;
typedef unsigned long long ARMdword;	/* Must be at least 64 bits wide.  */
typedef signed long long ARMsdword;
#endif
typedef struct ARMul_State ARMul_State;

typedef unsigned ARMul_CPInits (ARMul_State * state);
typedef unsigned ARMul_CPExits (ARMul_State * state);
typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword value);
typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword * value);
typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword * value);
typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
			     ARMword instr, ARMword value);
typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
			     ARMword instr);
typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
				ARMword * value);
typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
				 ARMword value);

struct ARMul_State
{
  ARMword Emulate;		/* to start and stop emulation */
  unsigned EndCondition;	/* reason for stopping */
  unsigned ErrorCode;		/* type of illegal instruction */
  ARMword Reg[16];		/* the current register file */
  ARMword RegBank[7][16];	/* all the registers */
  /* 40 bit accumulator.  We always keep this 64 bits wide,
     and move only 40 bits out of it in an MRA insn.  */
  ARMdword Accumulator;
  ARMword Cpsr;			/* the current psr */
  ARMword Spsr[7];		/* the exception psr's */
  ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags;	/* dummy flags for speed */
  ARMword SFlag;
#ifdef MODET
  ARMword TFlag;		/* Thumb state */
#endif
  ARMword Bank;			/* the current register bank */
  ARMword Mode;			/* the current mode */
  ARMword instr, pc, temp;	/* saved register state */
  ARMword loaded, decoded;	/* saved pipeline state */
  unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles;	/* emulated cycles used */
  unsigned long NumInstrs;	/* the number of instructions executed */
  unsigned NextInstr;
  unsigned VectorCatch;		/* caught exception mask */
  unsigned CallDebug;		/* set to call the debugger */
  unsigned CanWatch;		/* set by memory interface if its willing to suffer the
				   overhead of checking for watchpoints on each memory
				   access */
  unsigned MemReadDebug, MemWriteDebug;
  unsigned long StopHandle;

  unsigned char *MemDataPtr;	/* admin data */
  unsigned char *MemInPtr;	/* the Data In bus */
  unsigned char *MemOutPtr;	/* the Data Out bus (which you may not need */
  unsigned char *MemSparePtr;	/* extra space */
  ARMword MemSize;

  unsigned char *OSptr;		/* OS Handle */
  char *CommandLine;		/* Command Line from ARMsd */

  ARMul_CPInits *CPInit[16];	/* coprocessor initialisers */
  ARMul_CPExits *CPExit[16];	/* coprocessor finalisers */
  ARMul_LDCs *LDC[16];		/* LDC instruction */
  ARMul_STCs *STC[16];		/* STC instruction */
  ARMul_MRCs *MRC[16];		/* MRC instruction */
  ARMul_MCRs *MCR[16];		/* MCR instruction */
  ARMul_CDPs *CDP[16];		/* CDP instruction */
  ARMul_CPReads *CPRead[16];	/* Read CP register */
  ARMul_CPWrites *CPWrite[16];	/* Write CP register */
  unsigned char *CPData[16];	/* Coprocessor data */
  unsigned char const *CPRegWords[16];	/* map of coprocessor register sizes */
  unsigned long LastTime;	/* Value of last call to ARMul_Time() */
  ARMword CP14R0_CCD;		/* used to count 64 clock cycles with CP14 R0 bit
				   3 set */

  unsigned EventSet;		/* the number of events in the queue */
  unsigned long Now;		/* time to the nearest cycle */
  struct EventNode **EventPtr;	/* the event list */

  unsigned Exception;		/* enable the next four values */
  unsigned Debug;		/* show instructions as they are executed */
  unsigned NresetSig;		/* reset the processor */
  unsigned NfiqSig;
  unsigned NirqSig;

  unsigned abortSig;
  unsigned NtransSig;
  unsigned bigendSig;
  unsigned prog32Sig;
  unsigned data32Sig;
  unsigned lateabtSig;
  ARMword Vector;		/* synthesize aborts in cycle modes */
  ARMword Aborted;		/* sticky flag for aborts */
  ARMword Reseted;		/* sticky flag for Reset */
  ARMword Inted, LastInted;	/* sticky flags for interrupts */
  ARMword Base;			/* extra hand for base writeback */
  ARMword AbortAddr;		/* to keep track of Prefetch aborts */

  const struct Dbg_HostosInterface *hostif;

  unsigned is_v4;		/* Are we emulating a v4 architecture (or higher) ?  */
  unsigned is_v5;		/* Are we emulating a v5 architecture ?  */
  unsigned is_v5e;		/* Are we emulating a v5e architecture ?  */
  unsigned is_v6;		/* Are we emulating a v6 architecture ?  */
  unsigned is_XScale;		/* Are we emulating an XScale architecture ?  */
  unsigned is_iWMMXt;		/* Are we emulating an iWMMXt co-processor ?  */
  unsigned is_ep9312;		/* Are we emulating a Cirrus Maverick co-processor ?  */
  unsigned verbose;		/* Print various messages like the banner */
};

#define ResetPin NresetSig
#define FIQPin NfiqSig
#define IRQPin NirqSig
#define AbortPin abortSig
#define TransPin NtransSig
#define BigEndPin bigendSig
#define Prog32Pin prog32Sig
#define Data32Pin data32Sig
#define LateAbortPin lateabtSig

/***************************************************************************\
*                        Properties of ARM we know about                    *
\***************************************************************************/

/* The bitflags */
#define ARM_Fix26_Prop   0x01
#define ARM_Nexec_Prop   0x02
#define ARM_Debug_Prop   0x10
#define ARM_Isync_Prop   ARM_Debug_Prop
#define ARM_Lock_Prop    0x20
#define ARM_v4_Prop      0x40
#define ARM_v5_Prop      0x80
#define ARM_v5e_Prop     0x100
#define ARM_XScale_Prop  0x200
#define ARM_ep9312_Prop  0x400
#define ARM_iWMMXt_Prop  0x800
#define ARM_v6_Prop      0x1000

/***************************************************************************\
*                   Macros to extract instruction fields                    *
\***************************************************************************/

#define BIT(n) ( (ARMword)(instr>>(n))&1)	/* bit n of instruction */
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) )	/* bits m to n of instr */
#define TOPBITS(n) (instr >> (n))	/* bits 31 to n of instr */

/***************************************************************************\
*                      The hardware vector addresses                        *
\***************************************************************************/

#define ARMResetV 0L
#define ARMUndefinedInstrV 4L
#define ARMSWIV 8L
#define ARMPrefetchAbortV 12L
#define ARMDataAbortV 16L
#define ARMAddrExceptnV 20L
#define ARMIRQV 24L
#define ARMFIQV 28L
#define ARMErrorV 32L		/* This is an offset, not an address ! */

#define ARMul_ResetV ARMResetV
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
#define ARMul_SWIV ARMSWIV
#define ARMul_PrefetchAbortV ARMPrefetchAbortV
#define ARMul_DataAbortV ARMDataAbortV
#define ARMul_AddrExceptnV ARMAddrExceptnV
#define ARMul_IRQV ARMIRQV
#define ARMul_FIQV ARMFIQV

/***************************************************************************\
*                          Mode and Bank Constants                          *
\***************************************************************************/

#define USER26MODE   0L
#define FIQ26MODE    1L
#define IRQ26MODE    2L
#define SVC26MODE    3L
#define USER32MODE  16L
#define FIQ32MODE   17L
#define IRQ32MODE   18L
#define SVC32MODE   19L
#define ABORT32MODE 23L
#define UNDEF32MODE 27L
#define SYSTEMMODE  31L

#define ARM32BITMODE (state->Mode > 3)
#define ARM26BITMODE (state->Mode <= 3)
#define ARMMODE (state->Mode)
#define ARMul_MODEBITS 0x1fL
#define ARMul_MODE32BIT ARM32BITMODE
#define ARMul_MODE26BIT ARM26BITMODE

#define USERBANK 0
#define FIQBANK 1
#define IRQBANK 2
#define SVCBANK 3
#define ABORTBANK 4
#define UNDEFBANK 5
#define DUMMYBANK 6
#define SYSTEMBANK USERBANK

#define BANK_CAN_ACCESS_SPSR(bank)  \
  ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)

/***************************************************************************\
*                  Definitons of things in the emulator                     *
\***************************************************************************/

extern void ARMul_EmulateInit (void);
extern ARMul_State *ARMul_NewState (void);
extern void ARMul_Reset (ARMul_State * state);
extern ARMword ARMul_DoProg (ARMul_State * state);
extern ARMword ARMul_DoInstr (ARMul_State * state);

/***************************************************************************\
*                Definitons of things for event handling                    *
\***************************************************************************/

extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
				 unsigned (*func) ());
extern void ARMul_EnvokeEvent (ARMul_State * state);
extern unsigned long ARMul_Time (ARMul_State * state);

/***************************************************************************\
*                          Useful support routines                          *
\***************************************************************************/

extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
			     unsigned reg);
extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
			  ARMword value);
extern ARMword ARMul_GetPC (ARMul_State * state);
extern ARMword ARMul_GetNextPC (ARMul_State * state);
extern void ARMul_SetPC (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetR15 (ARMul_State * state);
extern void ARMul_SetR15 (ARMul_State * state, ARMword value);

extern ARMword ARMul_GetCPSR (ARMul_State * state);
extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);

/***************************************************************************\
*                  Definitons of things to handle aborts                    *
\***************************************************************************/

extern void ARMul_Abort (ARMul_State * state, ARMword address);
#define ARMul_ABORTWORD 0xefffffff	/* SWI -1 */
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
                                        state->AbortAddr = (address & ~3L)
#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
                                 state->Aborted = ARMul_DataAbortV ;
#define ARMul_CLEARABORT state->abortSig = LOW

/***************************************************************************\
*              Definitons of things in the memory interface                 *
\***************************************************************************/

extern unsigned ARMul_MemoryInit (ARMul_State * state,
				  unsigned long initmemsize);
extern void ARMul_MemoryExit (ARMul_State * state);

extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
				 ARMword isize);
extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
				 ARMword isize);
extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
				  ARMword isize);

extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);

extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
			      ARMword data);
extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
			      ARMword data);
extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
				 ARMword data);
extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
			     ARMword data);

extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
			       ARMword data);
extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
			       ARMword data);

extern void ARMul_Icycles (ARMul_State * state, unsigned number,
			   ARMword address);
extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
			   ARMword address);

extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
			     ARMword data);
extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
			     ARMword data);
extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
			     ARMword data);

extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
				ARMword, ARMword, ARMword, ARMword, ARMword,
				ARMword, ARMword, ARMword);

/***************************************************************************\
*            Definitons of things in the co-processor interface             *
\***************************************************************************/

#define ARMul_FIRST 0
#define ARMul_TRANSFER 1
#define ARMul_BUSY 2
#define ARMul_DATA 3
#define ARMul_INTERRUPT 4
#define ARMul_DONE 0
#define ARMul_CANT 1
#define ARMul_INC 3

#define ARMul_CP13_R0_FIQ	0x1
#define ARMul_CP13_R0_IRQ	0x2
#define ARMul_CP13_R8_PMUS	0x1

#define ARMul_CP14_R0_ENABLE	0x0001
#define ARMul_CP14_R0_CLKRST	0x0004
#define ARMul_CP14_R0_CCD	0x0008
#define ARMul_CP14_R0_INTEN0	0x0010
#define ARMul_CP14_R0_INTEN1	0x0020
#define ARMul_CP14_R0_INTEN2	0x0040
#define ARMul_CP14_R0_FLAG0	0x0100
#define ARMul_CP14_R0_FLAG1	0x0200
#define ARMul_CP14_R0_FLAG2	0x0400
#define ARMul_CP14_R10_MOE_IB	0x0004
#define ARMul_CP14_R10_MOE_DB	0x0008
#define ARMul_CP14_R10_MOE_BT	0x000c
#define ARMul_CP15_R1_ENDIAN	0x0080
#define ARMul_CP15_R1_ALIGN	0x0002
#define ARMul_CP15_R5_X		0x0400
#define ARMul_CP15_R5_ST_ALIGN	0x0001
#define ARMul_CP15_R5_IMPRE	0x0406
#define ARMul_CP15_R5_MMU_EXCPT	0x0400
#define ARMul_CP15_DBCON_M	0x0100
#define ARMul_CP15_DBCON_E1	0x000c
#define ARMul_CP15_DBCON_E0	0x0003

extern unsigned ARMul_CoProInit (ARMul_State * state);
extern void ARMul_CoProExit (ARMul_State * state);
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
			       ARMul_CPInits * init, ARMul_CPExits * exit,
			       ARMul_LDCs * ldc, ARMul_STCs * stc,
			       ARMul_MRCs * mrc, ARMul_MCRs * mcr,
			       ARMul_CDPs * cdp,
			       ARMul_CPReads * read, ARMul_CPWrites * write);
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
				 int store);
extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
extern int XScale_debug_moe (ARMul_State * state, int moe);

/***************************************************************************\
*               Definitons of things in the host environment                *
\***************************************************************************/

extern unsigned ARMul_OSInit (ARMul_State * state);
extern void ARMul_OSExit (ARMul_State * state);
extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
extern ARMword ARMul_OSLastErrorP (ARMul_State * state);

extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
				   ARMword pc);
extern int rdi_log;

/***************************************************************************\
*                            Host-dependent stuff                           *
\***************************************************************************/

#ifdef macintosh
pascal void SpinCursor (short increment);	/* copied from CursorCtl.h */
# define HOURGLASS           SpinCursor( 1 )
# define HOURGLASS_RATE      1023	/* 2^n - 1 */
#endif

extern void ARMul_UndefInstr      (ARMul_State *, ARMword);
extern void ARMul_FixCPSR         (ARMul_State *, ARMword, ARMword);
extern void ARMul_FixSPSR         (ARMul_State *, ARMword, ARMword);
extern void ARMul_ConsolePrint    (ARMul_State *, const char *, ...);
extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
Commit	Line	Data
c906108c SS	1	/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
380d9419	16	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
c906108c	17
c4793bac	18	#include "config.h"
c906108c SS	19	#include <stdio.h>
	20	#include <stdlib.h>
	21
	22	#define FALSE 0
	23	#define TRUE 1
	24	#define LOW 0
	25	#define HIGH 1
	26	#define LOWHIGH 1
	27	#define HIGHLOW 2
	28
	29	#ifndef __STDC__
dfcd3bfb	30	typedef char *VoidStar;
c906108c SS	31	#endif
c906108c SS	32
c4793bac PB	33	#ifdef HAVE_STDINT_H
	34	#include <stdint.h>
	35	typedef uint32_t ARMword;
	36	typedef int32_t ARMsword;
	37	typedef uint64_t ARMdword;
	38	typedef int64_t ARMsdword;
	39	#else
	40	typedef unsigned int ARMword; /* must be 32 bits wide */
	41	typedef signed int ARMsword;
f1129fb8	42	typedef unsigned long long ARMdword; /* Must be at least 64 bits wide. */
c4793bac PB	43	typedef signed long long ARMsdword;
c4793bac PB	44	#endif
dfcd3bfb JM	45	typedef struct ARMul_State ARMul_State;
	46
	47	typedef unsigned ARMul_CPInits (ARMul_State * state);
	48	typedef unsigned ARMul_CPExits (ARMul_State * state);
	49	typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
	50	ARMword instr, ARMword value);
	51	typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
	52	ARMword instr, ARMword * value);
	53	typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
	54	ARMword instr, ARMword * value);
	55	typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
	56	ARMword instr, ARMword value);
	57	typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
	58	ARMword instr);
	59	typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
	60	ARMword * value);
	61	typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
	62	ARMword value);
	63
	64	struct ARMul_State
	65	{
	66	ARMword Emulate; /* to start and stop emulation */
	67	unsigned EndCondition; /* reason for stopping */
	68	unsigned ErrorCode; /* type of illegal instruction */
	69	ARMword Reg[16]; /* the current register file */
	70	ARMword RegBank[7][16]; /* all the registers */
f1129fb8 NC	71	/* 40 bit accumulator. We always keep this 64 bits wide,
	72	and move only 40 bits out of it in an MRA insn. */
	73	ARMdword Accumulator;
dfcd3bfb JM	74	ARMword Cpsr; /* the current psr */
	75	ARMword Spsr[7]; /* the exception psr's */
	76	ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
f1129fb8	77	ARMword SFlag;
c906108c	78	#ifdef MODET
dfcd3bfb	79	ARMword TFlag; /* Thumb state */
c906108c	80	#endif
dfcd3bfb JM	81	ARMword Bank; /* the current register bank */
	82	ARMword Mode; /* the current mode */
	83	ARMword instr, pc, temp; /* saved register state */
	84	ARMword loaded, decoded; /* saved pipeline state */
	85	unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
	86	unsigned long NumInstrs; /* the number of instructions executed */
	87	unsigned NextInstr;
	88	unsigned VectorCatch; /* caught exception mask */
	89	unsigned CallDebug; /* set to call the debugger */
	90	unsigned CanWatch; /* set by memory interface if its willing to suffer the
	91	overhead of checking for watchpoints on each memory
	92	access */
	93	unsigned MemReadDebug, MemWriteDebug;
	94	unsigned long StopHandle;
	95
	96	unsigned char MemDataPtr; / admin data */
	97	unsigned char MemInPtr; / the Data In bus */
	98	unsigned char MemOutPtr; / the Data Out bus (which you may not need */
	99	unsigned char MemSparePtr; / extra space */
	100	ARMword MemSize;
	101
	102	unsigned char OSptr; / OS Handle */
	103	char CommandLine; / Command Line from ARMsd */
	104
	105	ARMul_CPInits CPInit[16]; / coprocessor initialisers */
	106	ARMul_CPExits CPExit[16]; / coprocessor finalisers */
	107	ARMul_LDCs LDC[16]; / LDC instruction */
	108	ARMul_STCs STC[16]; / STC instruction */
	109	ARMul_MRCs MRC[16]; / MRC instruction */
	110	ARMul_MCRs MCR[16]; / MCR instruction */
	111	ARMul_CDPs CDP[16]; / CDP instruction */
	112	ARMul_CPReads CPRead[16]; / Read CP register */
	113	ARMul_CPWrites CPWrite[16]; / Write CP register */
	114	unsigned char CPData[16]; / Coprocessor data */
	115	unsigned char const CPRegWords[16]; / map of coprocessor register sizes */
c3ae2f98 MG	116	unsigned long LastTime; /* Value of last call to ARMul_Time() */
	117	ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
	118	3 set */
dfcd3bfb JM	119
	120	unsigned EventSet; /* the number of events in the queue */
	121	unsigned long Now; /* time to the nearest cycle */
	122	struct EventNode *EventPtr; / the event list */
	123
	124	unsigned Exception; /* enable the next four values */
	125	unsigned Debug; /* show instructions as they are executed */
	126	unsigned NresetSig; /* reset the processor */
	127	unsigned NfiqSig;
	128	unsigned NirqSig;
	129
	130	unsigned abortSig;
	131	unsigned NtransSig;
	132	unsigned bigendSig;
	133	unsigned prog32Sig;
	134	unsigned data32Sig;
	135	unsigned lateabtSig;
	136	ARMword Vector; /* synthesize aborts in cycle modes */
	137	ARMword Aborted; /* sticky flag for aborts */
	138	ARMword Reseted; /* sticky flag for Reset */
	139	ARMword Inted, LastInted; /* sticky flags for interrupts */
	140	ARMword Base; /* extra hand for base writeback */
	141	ARMword AbortAddr; /* to keep track of Prefetch aborts */
	142
	143	const struct Dbg_HostosInterface *hostif;
	144
3943c96b NC	145	unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
3943c96b NC	146	unsigned is_v5; /* Are we emulating a v5 architecture ? */
f1129fb8	147	unsigned is_v5e; /* Are we emulating a v5e architecture ? */
8207e0f2	148	unsigned is_v6; /* Are we emulating a v6 architecture ? */
f1129fb8	149	unsigned is_XScale; /* Are we emulating an XScale architecture ? */
0f026fd0	150	unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
f603c8fe	151	unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
3943c96b	152	unsigned verbose; /* Print various messages like the banner */
dfcd3bfb	153	};
c906108c SS	154
	155	#define ResetPin NresetSig
	156	#define FIQPin NfiqSig
	157	#define IRQPin NirqSig
	158	#define AbortPin abortSig
	159	#define TransPin NtransSig
	160	#define BigEndPin bigendSig
	161	#define Prog32Pin prog32Sig
	162	#define Data32Pin data32Sig
	163	#define LateAbortPin lateabtSig
	164
	165	/***************************************************************************\
3943c96b	166	* Properties of ARM we know about *
c906108c	167	\***************************************************************************/
dfcd3bfb	168
c906108c SS	169	/* The bitflags */
	170	#define ARM_Fix26_Prop 0x01
	171	#define ARM_Nexec_Prop 0x02
	172	#define ARM_Debug_Prop 0x10
	173	#define ARM_Isync_Prop ARM_Debug_Prop
	174	#define ARM_Lock_Prop 0x20
3943c96b NC	175	#define ARM_v4_Prop 0x40
3943c96b NC	176	#define ARM_v5_Prop 0x80
f1129fb8 NC	177	#define ARM_v5e_Prop 0x100
f1129fb8 NC	178	#define ARM_XScale_Prop 0x200
f603c8fe	179	#define ARM_ep9312_Prop 0x400
0f026fd0	180	#define ARM_iWMMXt_Prop 0x800
8207e0f2	181	#define ARM_v6_Prop 0x1000
c906108c SS	182
	183	/***************************************************************************\
	184	* Macros to extract instruction fields *
	185	\***************************************************************************/
	186
dfcd3bfb JM	187	#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
	188	#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
	189	#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
c906108c SS	190
	191	/***************************************************************************\
	192	* The hardware vector addresses *
	193	\***************************************************************************/
	194
	195	#define ARMResetV 0L
	196	#define ARMUndefinedInstrV 4L
	197	#define ARMSWIV 8L
	198	#define ARMPrefetchAbortV 12L
	199	#define ARMDataAbortV 16L
	200	#define ARMAddrExceptnV 20L
	201	#define ARMIRQV 24L
	202	#define ARMFIQV 28L
dfcd3bfb	203	#define ARMErrorV 32L /* This is an offset, not an address ! */
c906108c SS	204
	205	#define ARMul_ResetV ARMResetV
	206	#define ARMul_UndefinedInstrV ARMUndefinedInstrV
	207	#define ARMul_SWIV ARMSWIV
	208	#define ARMul_PrefetchAbortV ARMPrefetchAbortV
	209	#define ARMul_DataAbortV ARMDataAbortV
	210	#define ARMul_AddrExceptnV ARMAddrExceptnV
	211	#define ARMul_IRQV ARMIRQV
	212	#define ARMul_FIQV ARMFIQV
	213
	214	/***************************************************************************\
	215	* Mode and Bank Constants *
	216	\***************************************************************************/
	217
c1a72ffd NC	218	#define USER26MODE 0L
	219	#define FIQ26MODE 1L
	220	#define IRQ26MODE 2L
	221	#define SVC26MODE 3L
	222	#define USER32MODE 16L
	223	#define FIQ32MODE 17L
	224	#define IRQ32MODE 18L
	225	#define SVC32MODE 19L
c906108c SS	226	#define ABORT32MODE 23L
c906108c SS	227	#define UNDEF32MODE 27L
c1a72ffd	228	#define SYSTEMMODE 31L
c906108c SS	229
	230	#define ARM32BITMODE (state->Mode > 3)
	231	#define ARM26BITMODE (state->Mode <= 3)
	232	#define ARMMODE (state->Mode)
	233	#define ARMul_MODEBITS 0x1fL
	234	#define ARMul_MODE32BIT ARM32BITMODE
	235	#define ARMul_MODE26BIT ARM26BITMODE
	236
	237	#define USERBANK 0
	238	#define FIQBANK 1
	239	#define IRQBANK 2
	240	#define SVCBANK 3
	241	#define ABORTBANK 4
	242	#define UNDEFBANK 5
	243	#define DUMMYBANK 6
b0eae074	244	#define SYSTEMBANK USERBANK
c1a72ffd NC	245
	246	#define BANK_CAN_ACCESS_SPSR(bank) \
	247	((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
c906108c SS	248
	249	/***************************************************************************\
	250	* Definitons of things in the emulator *
	251	\***************************************************************************/
	252
dfcd3bfb JM	253	extern void ARMul_EmulateInit (void);
	254	extern ARMul_State *ARMul_NewState (void);
	255	extern void ARMul_Reset (ARMul_State * state);
	256	extern ARMword ARMul_DoProg (ARMul_State * state);
	257	extern ARMword ARMul_DoInstr (ARMul_State * state);
c906108c SS	258
	259	/***************************************************************************\
	260	* Definitons of things for event handling *
	261	\***************************************************************************/
	262
dfcd3bfb JM	263	extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
	264	unsigned (*func) ());
	265	extern void ARMul_EnvokeEvent (ARMul_State * state);
	266	extern unsigned long ARMul_Time (ARMul_State * state);
c906108c SS	267
	268	/***************************************************************************\
	269	* Useful support routines *
	270	\***************************************************************************/
	271
dfcd3bfb JM	272	extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
	273	unsigned reg);
	274	extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
	275	ARMword value);
	276	extern ARMword ARMul_GetPC (ARMul_State * state);
	277	extern ARMword ARMul_GetNextPC (ARMul_State * state);
	278	extern void ARMul_SetPC (ARMul_State * state, ARMword value);
	279	extern ARMword ARMul_GetR15 (ARMul_State * state);
	280	extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
	281
	282	extern ARMword ARMul_GetCPSR (ARMul_State * state);
	283	extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
	284	extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
	285	extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
c906108c SS	286
	287	/***************************************************************************\
	288	* Definitons of things to handle aborts *
	289	\***************************************************************************/
	290
dfcd3bfb JM	291	extern void ARMul_Abort (ARMul_State * state, ARMword address);
dfcd3bfb JM	292	#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
c906108c SS	293	#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
	294	state->AbortAddr = (address & ~3L)
	295	#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
	296	state->Aborted = ARMul_DataAbortV ;
	297	#define ARMul_CLEARABORT state->abortSig = LOW
	298
	299	/***************************************************************************\
	300	* Definitons of things in the memory interface *
	301	\***************************************************************************/
	302
dfcd3bfb JM	303	extern unsigned ARMul_MemoryInit (ARMul_State * state,
	304	unsigned long initmemsize);
	305	extern void ARMul_MemoryExit (ARMul_State * state);
	306
	307	extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
	308	ARMword isize);
	309	extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
	310	ARMword isize);
	311	extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
	312	ARMword isize);
	313
	314	extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
	315	extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
	316	extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
	317	extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
	318
	319	extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
	320	ARMword data);
	321	extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
	322	ARMword data);
	323	extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
	324	ARMword data);
	325	extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
	326	ARMword data);
	327
	328	extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
	329	ARMword data);
	330	extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
	331	ARMword data);
	332
	333	extern void ARMul_Icycles (ARMul_State * state, unsigned number,
	334	ARMword address);
	335	extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
	336	ARMword address);
	337
	338	extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
	339	extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
917bca4f	340	extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
dfcd3bfb JM	341	extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
	342	ARMword data);
	343	extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
	344	ARMword data);
917bca4f NC	345	extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
917bca4f NC	346	ARMword data);
dfcd3bfb JM	347
	348	extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
	349	ARMword, ARMword, ARMword, ARMword, ARMword,
	350	ARMword, ARMword, ARMword);
c906108c SS	351
	352	/***************************************************************************\
	353	* Definitons of things in the co-processor interface *
	354	\***************************************************************************/
	355
	356	#define ARMul_FIRST 0
	357	#define ARMul_TRANSFER 1
	358	#define ARMul_BUSY 2
	359	#define ARMul_DATA 3
	360	#define ARMul_INTERRUPT 4
	361	#define ARMul_DONE 0
	362	#define ARMul_CANT 1
	363	#define ARMul_INC 3
	364
c3ae2f98 MG	365	#define ARMul_CP13_R0_FIQ 0x1
	366	#define ARMul_CP13_R0_IRQ 0x2
	367	#define ARMul_CP13_R8_PMUS 0x1
	368
	369	#define ARMul_CP14_R0_ENABLE 0x0001
	370	#define ARMul_CP14_R0_CLKRST 0x0004
	371	#define ARMul_CP14_R0_CCD 0x0008
	372	#define ARMul_CP14_R0_INTEN0 0x0010
	373	#define ARMul_CP14_R0_INTEN1 0x0020
	374	#define ARMul_CP14_R0_INTEN2 0x0040
	375	#define ARMul_CP14_R0_FLAG0 0x0100
	376	#define ARMul_CP14_R0_FLAG1 0x0200
	377	#define ARMul_CP14_R0_FLAG2 0x0400
	378	#define ARMul_CP14_R10_MOE_IB 0x0004
	379	#define ARMul_CP14_R10_MOE_DB 0x0008
	380	#define ARMul_CP14_R10_MOE_BT 0x000c
	381	#define ARMul_CP15_R1_ENDIAN 0x0080
	382	#define ARMul_CP15_R1_ALIGN 0x0002
	383	#define ARMul_CP15_R5_X 0x0400
	384	#define ARMul_CP15_R5_ST_ALIGN 0x0001
	385	#define ARMul_CP15_R5_IMPRE 0x0406
	386	#define ARMul_CP15_R5_MMU_EXCPT 0x0400
	387	#define ARMul_CP15_DBCON_M 0x0100
	388	#define ARMul_CP15_DBCON_E1 0x000c
	389	#define ARMul_CP15_DBCON_E0 0x0003
	390
dfcd3bfb JM	391	extern unsigned ARMul_CoProInit (ARMul_State * state);
	392	extern void ARMul_CoProExit (ARMul_State * state);
	393	extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
	394	ARMul_CPInits * init, ARMul_CPExits * exit,
	395	ARMul_LDCs * ldc, ARMul_STCs * stc,
	396	ARMul_MRCs * mrc, ARMul_MCRs * mcr,
	397	ARMul_CDPs * cdp,
	398	ARMul_CPReads * read, ARMul_CPWrites * write);
	399	extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
c3ae2f98 MG	400	extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
	401	int store);
	402	extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
	403	extern int XScale_debug_moe (ARMul_State * state, int moe);
c906108c SS	404
	405	/***************************************************************************\
	406	* Definitons of things in the host environment *
	407	\***************************************************************************/
	408
dfcd3bfb JM	409	extern unsigned ARMul_OSInit (ARMul_State * state);
	410	extern void ARMul_OSExit (ARMul_State * state);
	411	extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
	412	extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
c906108c	413
dfcd3bfb JM	414	extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
	415	extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
	416	ARMword pc);
	417	extern int rdi_log;
c906108c SS	418
	419	/***************************************************************************\
	420	* Host-dependent stuff *
	421	\***************************************************************************/
	422
	423	#ifdef macintosh
dfcd3bfb	424	pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
c906108c	425	# define HOURGLASS SpinCursor( 1 )
dfcd3bfb	426	# define HOURGLASS_RATE 1023 /* 2^n - 1 */
c906108c	427	#endif
6d358e86 NC	428
	429	extern void ARMul_UndefInstr (ARMul_State *, ARMword);
	430	extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
	431	extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
	432	extern void ARMul_ConsolePrint (ARMul_State , const char , ...);
	433	extern void ARMul_SelectProcessor (ARMul_State *, unsigned);