projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 49634642 NC |
1 | # Intel(r) Wireless MMX(tm) technology testcase for WSLL |
| 2 | # mach: xscale | |
| 3 | # as: -mcpu=xscale+iwmmxt | |
| 4 | ||
| 5 | .include "testutils.inc" | |
| 6 | ||
| 7 | start | |
| 8 | ||
| 9 | .global wsll | |
| 10 | wsll: | |
| 11 | # Enable access to CoProcessors 0 & 1 before | |
| 12 | # we attempt these instructions. | |
| 13 | ||
| 14 | mvi_h_gr r1, 3 | |
| 15 | mcr p15, 0, r1, cr15, cr1, 0 | |
| 16 | ||
| 17 | # Test Halfword Logical Shift Left | |
| 18 | ||
| 19 | mvi_h_gr r0, 0x12345678 | |
| 20 | mvi_h_gr r1, 0x9abcdef0 | |
| 21 | mvi_h_gr r2, 0x11111104 | |
| 22 | mvi_h_gr r3, 0x11111111 | |
| 23 | mvi_h_gr r4, 0 | |
| 24 | mvi_h_gr r5, 0 | |
| 25 | ||
| 26 | tmcrr wr0, r0, r1 | |
| 27 | tmcrr wr1, r2, r3 | |
| 28 | tmcrr wr2, r4, r5 | |
| 29 | ||
| 30 | wsllh wr2, wr0, wr1 | |
| 31 | ||
| 32 | tmrrc r0, r1, wr0 | |
| 33 | tmrrc r2, r3, wr1 | |
| 34 | tmrrc r4, r5, wr2 | |
| 35 | ||
| 36 | test_h_gr r0, 0x12345678 | |
| 37 | test_h_gr r1, 0x9abcdef0 | |
| 38 | test_h_gr r2, 0x11111104 | |
| 39 | test_h_gr r3, 0x11111111 | |
| 40 | test_h_gr r4, 0x23406780 | |
| 41 | test_h_gr r5, 0xabc0ef00 | |
| 42 | ||
| 43 | # Test Halfword Aritc Shift Left by CG register | |
| 44 | ||
| 45 | mvi_h_gr r0, 0x12345678 | |
| 46 | mvi_h_gr r1, 0x9abcdef0 | |
| 47 | mvi_h_gr r2, 0x11111104 | |
| 48 | mvi_h_gr r3, 0 | |
| 49 | mvi_h_gr r4, 0 | |
| 50 | ||
| 51 | tmcrr wr0, r0, r1 | |
| 52 | tmcr wcgr1, r2 | |
| 53 | tmcrr wr1, r3, r4 | |
| 54 | ||
| 55 | wsllhg wr1, wr0, wcgr1 | |
| 56 | ||
| 57 | tmrrc r0, r1, wr0 | |
| 58 | tmrc r2, wcgr1 | |
| 59 | tmrrc r3, r4, wr1 | |
| 60 | ||
| 61 | test_h_gr r0, 0x12345678 | |
| 62 | test_h_gr r1, 0x9abcdef0 | |
| 63 | test_h_gr r2, 0x11111104 | |
| 64 | test_h_gr r3, 0x23406780 | |
| 65 | test_h_gr r4, 0xabc0ef00 | |
| 66 | ||
| 67 | # Test Word Logical Shift Left | |
| 68 | ||
| 69 | mvi_h_gr r0, 0x12345678 | |
| 70 | mvi_h_gr r1, 0x9abcdef0 | |
| 71 | mvi_h_gr r2, 0x11111104 | |
| 72 | mvi_h_gr r3, 0x11111111 | |
| 73 | mvi_h_gr r4, 0 | |
| 74 | mvi_h_gr r5, 0 | |
| 75 | ||
| 76 | tmcrr wr0, r0, r1 | |
| 77 | tmcrr wr1, r2, r3 | |
| 78 | tmcrr wr2, r4, r5 | |
| 79 | ||
| 80 | wsllw wr2, wr0, wr1 | |
| 81 | ||
| 82 | tmrrc r0, r1, wr0 | |
| 83 | tmrrc r2, r3, wr1 | |
| 84 | tmrrc r4, r5, wr2 | |
| 85 | ||
| 86 | test_h_gr r0, 0x12345678 | |
| 87 | test_h_gr r1, 0x9abcdef0 | |
| 88 | test_h_gr r2, 0x11111104 | |
| 89 | test_h_gr r3, 0x11111111 | |
| 90 | test_h_gr r4, 0x23456780 | |
| 91 | test_h_gr r5, 0xabcdef00 | |
| 92 | ||
| 93 | # Test Word Logical Shift Left by CG register | |
| 94 | ||
| 95 | mvi_h_gr r0, 0x12345678 | |
| 96 | mvi_h_gr r1, 0x9abcdef0 | |
| 97 | mvi_h_gr r2, 0x11111104 | |
| 98 | mvi_h_gr r3, 0 | |
| 99 | mvi_h_gr r4, 0 | |
| 100 | ||
| 101 | tmcrr wr0, r0, r1 | |
| 102 | tmcr wcgr2, r2 | |
| 103 | tmcrr wr1, r3, r4 | |
| 104 | ||
| 105 | wsllwg wr1, wr0, wcgr2 | |
| 106 | ||
| 107 | tmrrc r0, r1, wr0 | |
| 108 | tmrc r2, wcgr2 | |
| 109 | tmrrc r3, r4, wr1 | |
| 110 | ||
| 111 | test_h_gr r0, 0x12345678 | |
| 112 | test_h_gr r1, 0x9abcdef0 | |
| 113 | test_h_gr r2, 0x11111104 | |
| 114 | test_h_gr r3, 0x23456780 | |
| 115 | test_h_gr r4, 0xabcdef00 | |
| 116 | ||
| 117 | # Test Double Word Logical Shift Left | |
| 118 | ||
| 119 | mvi_h_gr r0, 0x12345678 | |
| 120 | mvi_h_gr r1, 0x9abcdefc | |
| 121 | mvi_h_gr r2, 0x11111104 | |
| 122 | mvi_h_gr r3, 0x11111111 | |
| 123 | mvi_h_gr r4, 0 | |
| 124 | mvi_h_gr r5, 0 | |
| 125 | ||
| 126 | tmcrr wr0, r0, r1 | |
| 127 | tmcrr wr1, r2, r3 | |
| 128 | tmcrr wr2, r4, r5 | |
| 129 | ||
| 130 | wslld wr2, wr0, wr1 | |
| 131 | ||
| 132 | tmrrc r0, r1, wr0 | |
| 133 | tmrrc r2, r3, wr1 | |
| 134 | tmrrc r4, r5, wr2 | |
| 135 | ||
| 136 | test_h_gr r0, 0x12345678 | |
| 137 | test_h_gr r1, 0x9abcdefc | |
| 138 | test_h_gr r2, 0x11111104 | |
| 139 | test_h_gr r3, 0x11111111 | |
| 140 | test_h_gr r4, 0x23456780 | |
| 141 | test_h_gr r5, 0xabcdefc1 | |
| 142 | ||
| 143 | # Test Double Word Logical Shift Left by CG register | |
| 144 | ||
| 145 | mvi_h_gr r0, 0x12345678 | |
| 146 | mvi_h_gr r1, 0x9abcdefc | |
| 147 | mvi_h_gr r2, 0x11111104 | |
| 148 | mvi_h_gr r3, 0 | |
| 149 | mvi_h_gr r4, 0 | |
| 150 | ||
| 151 | tmcrr wr0, r0, r1 | |
| 152 | tmcr wcgr3, r2 | |
| 153 | tmcrr wr1, r3, r4 | |
| 154 | ||
| 155 | wslldg wr1, wr0, wcgr3 | |
| 156 | ||
| 157 | tmrrc r0, r1, wr0 | |
| 158 | tmrc r2, wcgr3 | |
| 159 | tmrrc r3, r4, wr1 | |
| 160 | ||
| 161 | test_h_gr r0, 0x12345678 | |
| 162 | test_h_gr r1, 0x9abcdefc | |
| 163 | test_h_gr r2, 0x11111104 | |
| 164 | test_h_gr r3, 0x23456780 | |
| 165 | test_h_gr r4, 0xabcdefc1 | |
| 166 | ||
| 167 | pass |