projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d7b4a70 MF |
1 | //Original:/testcases/core/c_dagmodim_lnz_imgebl/c_dagmodim_lnz_imgebl.dsp |
| 2 | // Spec Reference: dagmodim l not zero & i+m >= b+l | |
| 3 | # mach: bfin | |
| 4 | ||
| 5 | .include "testutils.inc" | |
| 6 | start | |
| 7 | ||
| 8 | ||
| 9 | INIT_R_REGS 0; | |
| 10 | ||
| 11 | imm32 i0, 0x00001000; | |
| 12 | imm32 i1, 0x00001100; | |
| 13 | imm32 i2, 0x00001010; | |
| 14 | imm32 i3, 0x00001001; | |
| 15 | ||
| 16 | imm32 b0, 0x00001000; | |
| 17 | imm32 b1, 0x00001000; | |
| 18 | imm32 b2, 0x00001000; | |
| 19 | imm32 b3, 0x00001000; | |
| 20 | ||
| 21 | imm32 l0, 0x00000001; | |
| 22 | imm32 l1, 0x00000002; | |
| 23 | imm32 l2, 0x00000003; | |
| 24 | imm32 l3, 0x00000004; | |
| 25 | ||
| 26 | imm32 m0, 0x00000015; | |
| 27 | imm32 m1, 0x00000016; | |
| 28 | imm32 m2, 0x00000017; | |
| 29 | imm32 m3, 0x00000018; | |
| 30 | ||
| 31 | I0 += M0; | |
| 32 | I1 += M1; | |
| 33 | I2 += M2; | |
| 34 | I3 += M3; | |
| 35 | R0 = I0; | |
| 36 | R1 = I1; | |
| 37 | R2 = I2; | |
| 38 | R3 = I3; | |
| 39 | I0 += M1; | |
| 40 | I1 += M2; | |
| 41 | I2 += M3; | |
| 42 | I3 += M0; | |
| 43 | R4 = I0; | |
| 44 | R5 = I1; | |
| 45 | R6 = I2; | |
| 46 | R7 = I3; | |
| 47 | ||
| 48 | CHECKREG r0, 0x00001014; | |
| 49 | CHECKREG r1, 0x00001114; | |
| 50 | CHECKREG r2, 0x00001024; | |
| 51 | CHECKREG r3, 0x00001015; | |
| 52 | CHECKREG r4, 0x00001029; | |
| 53 | CHECKREG r5, 0x00001129; | |
| 54 | CHECKREG r6, 0x00001039; | |
| 55 | CHECKREG r7, 0x00001026; | |
| 56 | ||
| 57 | I0 -= M2; | |
| 58 | I1 -= M3; | |
| 59 | I2 -= M0; | |
| 60 | I3 -= M1; | |
| 61 | R0 = I0; | |
| 62 | R1 = I1; | |
| 63 | R2 = I2; | |
| 64 | R3 = I3; | |
| 65 | I0 -= M3; | |
| 66 | I1 -= M2; | |
| 67 | I2 -= M1; | |
| 68 | I3 -= M0; | |
| 69 | R4 = I0; | |
| 70 | R5 = I1; | |
| 71 | R6 = I2; | |
| 72 | R7 = I3; | |
| 73 | CHECKREG r0, 0x00001012; | |
| 74 | CHECKREG r1, 0x00001111; | |
| 75 | CHECKREG r2, 0x00001024; | |
| 76 | CHECKREG r3, 0x00001010; | |
| 77 | CHECKREG r4, 0x00000FFB; | |
| 78 | CHECKREG r5, 0x000010FA; | |
| 79 | CHECKREG r6, 0x0000100E; | |
| 80 | CHECKREG r7, 0x00000FFF; | |
| 81 | ||
| 82 | I0 += M3 (BREV); | |
| 83 | I1 += M0 (BREV); | |
| 84 | I2 += M1 (BREV); | |
| 85 | I3 += M2 (BREV); | |
| 86 | R0 = I0; | |
| 87 | R1 = I1; | |
| 88 | R2 = I2; | |
| 89 | R3 = I3; | |
| 90 | I0 += M2 (BREV); | |
| 91 | I1 += M3 (BREV); | |
| 92 | I2 += M0 (BREV); | |
| 93 | I3 += M1 (BREV); | |
| 94 | R4 = I0; | |
| 95 | R5 = I1; | |
| 96 | R6 = I2; | |
| 97 | R7 = I3; | |
| 98 | CHECKREG r0, 0x00000FEF; | |
| 99 | CHECKREG r1, 0x000010E0; | |
| 100 | CHECKREG r2, 0x0000101B; | |
| 101 | CHECKREG r3, 0x00000FE7; | |
| 102 | CHECKREG r4, 0x00000FFB; | |
| 103 | CHECKREG r5, 0x000010F8; | |
| 104 | CHECKREG r6, 0x00001001; | |
| 105 | CHECKREG r7, 0x00000FF2; | |
| 106 | ||
| 107 | ||
| 108 | pass |