[thirdparty/binutils-gdb.git] / sim / testsuite / sim / bfin / c_seq_ex1_call_mv_pop.S

//Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp
// Spec Reference: sequencer stage ex1  ( call + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating

#include "test.h"
.include "testutils.inc"
start

include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0);     // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);

#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT  0xFFE02000
#endif
#ifndef EVT15
#define EVT15  0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif

GEN_INT_INIT(ITABLE) // set location for interrupt table

//
// Reset/Bootstrap Code
//   (Here we should set the processor operating modes, initialize registers,
//

BOOT:

                              // in reset mode now
LD32_LABEL(sp, KSTACK);   // setup the stack pointer
FP = SP;        // and frame pointer

LD32(p0, EVT);      // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
    [ P0 ++ ] = R0;

LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
    [ P0 ++ ] = R0;

LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
    [ P0 ++ ] = R0;

LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
    [ P0 ++ ] = R0;

    [ P0 ++ ] = R0;        // IVT4 not used

LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
    [ P0 ++ ] = R0;

LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
    [ P0 ++ ] = R0;

LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
    [ P0 ++ ] = R0;

LD32(p0, EVT_OVERRIDE);
    R0 = 0;
    [ P0 ++ ] = R0;
    R0 = -1;     // Change this to mask interrupts (*)
    [ P0 ] = R0;   // IMASK
CSYNC;

DUMMY:

    R0 = 0 (Z);

LT0 = r0;       // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;

ASTAT = r0;     // reset other internal regs

// The following code sets up the test for running in USER mode

LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
                        // ReturnFromInterrupt (RTI)
RETI = r0;      // We need to load the return address

// Comment the following line for a USER Mode test

JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode

RTI;

STARTSUP:
LD32_LABEL(p1, BEGIN);

LD32(p0, EVT15);
    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start

RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
                // SUPERVISOR MODE & go to different RAISE in supervisor mode
                // until the end of the test.

NOP;    // Workaround for Bug 217
RTI;

//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK);   // setup the stack pointer
FP = SP;            // set frame pointer
JUMP BEGIN;

//*********************************************************************

BEGIN:

                // COMMENT the following line for USER MODE tests
    [ -- SP ] = RETI;  // enable interrupts in supervisor mode

                // **** YOUR CODE GOES HERE ****

LD32_LABEL(p1, SUBR1);


    // PUT YOUR TEST HERE!
// PUSH
        R0 = 0x01;
        R1 = 0x02;
        R2 = 0x03;
        R3 = 0x04;
        R4 = 0x05;
        R5 = 0x06;
        R6 = 0x07;
        R7 = 0x08;


        [ -- SP ] = ( R7:0 );
//  RAISE 2;    // RTN
CALL (p1);
    P1 = R1;
    R2 = P1;
        [ -- SP ] = ( R7:0 );
        R1 = 0x12;
        R2 = 0x13;
        R3 = 0x14;
        R4 = 0x15;
        R5 = 0x16;
        R6 = 0x17;
        R7 = 0x18;

LABEL1:
//  RAISE 5;    // RTI
    P2 = R2;
    R3 = P2;

        [ -- SP ] = ( R7:0 );

        R2 = 0x23;
        R3 = 0x24;
        R4 = 0x25;
        R5 = 0x26;
        R6 = 0x27;
        R7 = 0x28;

//  RAISE 6;    // RTI
CALL SUBR2;
    P1 = R3;
    R4 = P1;
        [ -- SP ] = ( R7:0 );
// POP
        R0 = 0x00;
        R1 = 0x00;
        R2 = 0x00;
        R3 = 0x00;
        R4 = 0x00;
        R5 = 0x00;
        R6 = 0x00;
        R7 = 0x00;

LABEL2:
//  RAISE 7;    // RTI
    P4 = R4;
    R5 = P4;
        ( R7:0 ) = [ SP ++ ];


CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);

//  RAISE 8;    // RTI
CALL SUBR3;
    P3 = R5;
    R6 = P3;
        ( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
   R0 = 12;
   R1 = 13;
   R2 = 14;
   R3 = 15;
   R4 = 16;
   R5 = 17;
   R6 = 18;
   R7 = 19;


LABEL3:
//  RAISE 9;    // RTI
    P4 = R6;
    R7 = P4;
        ( R7:0 ) = [ SP ++ ];

CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000002);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000000);


END:
dbg_pass;            // End the test


SUBR1:				// should jump here
	I0 += 2;
	RTS;
	I3 += 2;                   // should not go here
	RTS;

SUBR2:				// should jump here
	I1 += 2;
	RTS;
	I3 += 2;                   // should not go here
	RTS;

SUBR3:				// should jump here
	I2 += 2;
	RTS;
	I3 += 2;                   // should not go here
	RTS;


//*********************************************************************

//
// Handlers for Events
//

EHANDLE:            // Emulation Handler 0
RTE;

RHANDLE:            // Reset Handler 1
RTI;

NHANDLE:            // NMI Handler 2
    I0 += 2;
RTN;

XHANDLE:            // Exception Handler 3
    R1 = 3;
RTX;

HWHANDLE:           // HW Error Handler 5
    I1 += 2;
RTI;

THANDLE:            // Timer Handler 6
    I2 += 2;
RTI;

I7HANDLE:           // IVG 7 Handler
    I3 += 2;
RTI;

I8HANDLE:           // IVG 8 Handler
    I0 += 2;
RTI;

I9HANDLE:           // IVG 9 Handler
    I0 += 2;
RTI;

I10HANDLE:          // IVG 10 Handler
    R7 = 10;
RTI;

I11HANDLE:          // IVG 11 Handler
    I0 = R0;
    I1 = R1;
    I2 = R2;
    I3 = R3;
    M0 = R4;
    R0 = 11;
RTI;

I12HANDLE:          // IVG 12 Handler
    R1 = 12;
RTI;

I13HANDLE:          // IVG 13 Handler
    R2 = 13;
RTI;

I14HANDLE:          // IVG 14 Handler
    R3 = 14;
RTI;

I15HANDLE:          // IVG 15 Handler
    R4 = 15;
RTI;

NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug

//
// Data Segment
//

.data
DATA:
    .space (0x10);

// Stack Segments (Both Kernel and User)

    .space (STACKSIZE);
KSTACK:

    .space (STACKSIZE);
USTACK:
Commit	Line	Data
1d7b4a70 MF	1	//Original:/proj/frio/dv/testcases/core/c_seq_ex1_call_mv_pop/c_seq_ex1_call_mv_pop.dsp
	2	// Spec Reference: sequencer stage ex1 ( call + regmv + pushpopmultiple)
	3	# mach: bfin
	4	# sim: --environment operating
	5
	6	#include "test.h"
	7	.include "testutils.inc"
	8	start
	9
	10	include(std.inc)
	11	include(selfcheck.inc)
	12	include(gen_int.inc)
	13	INIT_R_REGS(0);
	14	INIT_P_REGS(0);
	15	INIT_I_REGS(0); // initialize the dsp address regs
	16	INIT_M_REGS(0);
	17	INIT_L_REGS(0);
	18	INIT_B_REGS(0);
	19	//CHECK_INIT(p5, 0xe0000000);
	20	include(symtable.inc)
	21	CHECK_INIT_DEF(p5);
	22
	23	#ifndef STACKSIZE
	24	#define STACKSIZE 0x10
	25	#endif
	26	#ifndef EVT
	27	#define EVT 0xFFE02000
	28	#endif
	29	#ifndef EVT15
	30	#define EVT15 0xFFE0203C
	31	#endif
	32	#ifndef EVT_OVERRIDE
	33	#define EVT_OVERRIDE 0xFFE02100
	34	#endif
	35	#ifndef ITABLE
	36	#define ITABLE DATA_ADDR_1
	37	#endif
	38
	39	GEN_INT_INIT(ITABLE) // set location for interrupt table
	40
	41	//
	42	// Reset/Bootstrap Code
	43	// (Here we should set the processor operating modes, initialize registers,
	44	//
	45
	46	BOOT:
	47
	48	// in reset mode now
	49	LD32_LABEL(sp, KSTACK); // setup the stack pointer
	50	FP = SP; // and frame pointer
	51
	52	LD32(p0, EVT); // Setup Event Vectors and Handlers
	53	LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
	54	[ P0 ++ ] = R0;
	55
	56	LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
	57	[ P0 ++ ] = R0;
	58
	59	LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
	60	[ P0 ++ ] = R0;
	61
	62	LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
	63	[ P0 ++ ] = R0;
	64
65	[ P0 ++ ] = R0; // IVT4 not used
66
67	LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68	[ P0 ++ ] = R0;
69
70	LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
71	[ P0 ++ ] = R0;
72
73	LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74	[ P0 ++ ] = R0;
75
76	LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77	[ P0 ++ ] = R0;
78
79	LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80	[ P0 ++ ] = R0;
81
82	LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83	[ P0 ++ ] = R0;
84
85	LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86	[ P0 ++ ] = R0;
87
88	LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89	[ P0 ++ ] = R0;
90
91	LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92	[ P0 ++ ] = R0;
93
94	LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95	[ P0 ++ ] = R0;
96
97	LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98	[ P0 ++ ] = R0;
99
100	LD32(p0, EVT_OVERRIDE);
101	R0 = 0;
102	[ P0 ++ ] = R0;
103	R0 = -1; // Change this to mask interrupts (*)
104	[ P0 ] = R0; // IMASK
105	CSYNC;
106
107	DUMMY:
108
109	R0 = 0 (Z);
110
111	LT0 = r0; // set loop counters to something deterministic
112	LB0 = r0;
113	LC0 = r0;
114	LT1 = r0;
115	LB1 = r0;
116	LC1 = r0;
117
118	ASTAT = r0; // reset other internal regs
119
120	// The following code sets up the test for running in USER mode
121
122	LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
123	// ReturnFromInterrupt (RTI)
124	RETI = r0; // We need to load the return address
125
126	// Comment the following line for a USER Mode test
127
128	JUMP STARTSUP; // jump to code start for SUPERVISOR mode
129
130	RTI;
131
132	STARTSUP:
133	LD32_LABEL(p1, BEGIN);
134
135	LD32(p0, EVT15);
136	[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
137
138	RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
139	// SUPERVISOR MODE & go to different RAISE in supervisor mode
140	// until the end of the test.
141
142	NOP; // Workaround for Bug 217
143	RTI;
144
145	//
146	// The Main Program
147	//
148	STARTUSER:
149	LD32_LABEL(sp, USTACK); // setup the stack pointer
150	FP = SP; // set frame pointer
151	JUMP BEGIN;
152
153	//*********************************************************************
154
155	BEGIN:
156
157	// COMMENT the following line for USER MODE tests
158	[ -- SP ] = RETI; // enable interrupts in supervisor mode
159
160	// ** YOUR CODE GOES HERE **
161
162	LD32_LABEL(p1, SUBR1);
163
164
165	// PUT YOUR TEST HERE!
166	// PUSH
167	R0 = 0x01;
168	R1 = 0x02;
169	R2 = 0x03;
170	R3 = 0x04;
171	R4 = 0x05;
172	R5 = 0x06;
173	R6 = 0x07;
174	R7 = 0x08;
175
176
177	[ -- SP ] = ( R7:0 );
178	// RAISE 2; // RTN
179	CALL (p1);
180	P1 = R1;
181	R2 = P1;
182	[ -- SP ] = ( R7:0 );
183	R1 = 0x12;
184	R2 = 0x13;
185	R3 = 0x14;
186	R4 = 0x15;
187	R5 = 0x16;
188	R6 = 0x17;
189	R7 = 0x18;
190
191	LABEL1:
192	// RAISE 5; // RTI
193	P2 = R2;
194	R3 = P2;
195
196	[ -- SP ] = ( R7:0 );
197
198	R2 = 0x23;
199	R3 = 0x24;
200	R4 = 0x25;
201	R5 = 0x26;
202	R6 = 0x27;
203	R7 = 0x28;
204
205	// RAISE 6; // RTI
206	CALL SUBR2;
207	P1 = R3;
208	R4 = P1;
209	[ -- SP ] = ( R7:0 );
210	// POP
211	R0 = 0x00;
212	R1 = 0x00;
213	R2 = 0x00;
214	R3 = 0x00;
215	R4 = 0x00;
216	R5 = 0x00;
217	R6 = 0x00;
218	R7 = 0x00;
219
220	LABEL2:
221	// RAISE 7; // RTI
222	P4 = R4;
223	R5 = P4;
224	( R7:0 ) = [ SP ++ ];
225
226
227
228	CHECKREG(r0, 0x00000001);
229	CHECKREG(r1, 0x00000012);
230	CHECKREG(r2, 0x00000023);
231	CHECKREG(r3, 0x00000024);
232	CHECKREG(r4, 0x00000024);
233	CHECKREG(r5, 0x00000026);
234	CHECKREG(r6, 0x00000027);
235	CHECKREG(r7, 0x00000028);
236
237	// RAISE 8; // RTI
238	CALL SUBR3;
239	P3 = R5;
240	R6 = P3;
241	( R7:0 ) = [ SP ++ ];
242	CHECKREG(r0, 0x00000001);
243	CHECKREG(r1, 0x00000012);
244	CHECKREG(r2, 0x00000013);
245	CHECKREG(r3, 0x00000013);
246	CHECKREG(r4, 0x00000015);
247	CHECKREG(r5, 0x00000016);
248	CHECKREG(r6, 0x00000017);
249	CHECKREG(r7, 0x00000018);
250	R0 = 12;
251	R1 = 13;
252	R2 = 14;
253	R3 = 15;
254	R4 = 16;
255	R5 = 17;
256	R6 = 18;
257	R7 = 19;
258
259
260	LABEL3:
261	// RAISE 9; // RTI
262	P4 = R6;
263	R7 = P4;
264	( R7:0 ) = [ SP ++ ];
265
266	CHECKREG(r0, 0x00000001);
267	CHECKREG(r1, 0x00000002);
268	CHECKREG(r2, 0x00000002);
269	CHECKREG(r3, 0x00000004);
270	CHECKREG(r4, 0x00000005);
271	CHECKREG(r5, 0x00000006);
272	CHECKREG(r6, 0x00000007);
273	CHECKREG(r7, 0x00000008);
274	R0 = I0;
275	R1 = I1;
276	R2 = I2;
277	R3 = I3;
278	CHECKREG(r0, 0x00000002);
279	CHECKREG(r1, 0x00000002);
280	CHECKREG(r2, 0x00000002);
281	CHECKREG(r3, 0x00000000);
282
283
284	END:
285	dbg_pass; // End the test
286
287
288	SUBR1: // should jump here
289	I0 += 2;
290	RTS;
291	I3 += 2; // should not go here
292	RTS;
293
294	SUBR2: // should jump here
295	I1 += 2;
296	RTS;
297	I3 += 2; // should not go here
298	RTS;
299
300	SUBR3: // should jump here
301	I2 += 2;
302	RTS;
303	I3 += 2; // should not go here
304	RTS;
305
306
307
308	//*********************************************************************
309
310	//
311	// Handlers for Events
312	//
313
314	EHANDLE: // Emulation Handler 0
315	RTE;
316
317	RHANDLE: // Reset Handler 1
318	RTI;
319
320	NHANDLE: // NMI Handler 2
321	I0 += 2;
322	RTN;
323
324	XHANDLE: // Exception Handler 3
325	R1 = 3;
326	RTX;
327
328	HWHANDLE: // HW Error Handler 5
329	I1 += 2;
330	RTI;
331
332	THANDLE: // Timer Handler 6
333	I2 += 2;
334	RTI;
335
336	I7HANDLE: // IVG 7 Handler
337	I3 += 2;
338	RTI;
339
340	I8HANDLE: // IVG 8 Handler
341	I0 += 2;
342	RTI;
343
344	I9HANDLE: // IVG 9 Handler
345	I0 += 2;
346	RTI;
347
348	I10HANDLE: // IVG 10 Handler
349	R7 = 10;
350	RTI;
351
352	I11HANDLE: // IVG 11 Handler
353	I0 = R0;
354	I1 = R1;
355	I2 = R2;
356	I3 = R3;
357	M0 = R4;
358	R0 = 11;
359	RTI;
360
361	I12HANDLE: // IVG 12 Handler
362	R1 = 12;
363	RTI;
364
365	I13HANDLE: // IVG 13 Handler
366	R2 = 13;
367	RTI;
368
369	I14HANDLE: // IVG 14 Handler
370	R3 = 14;
371	RTI;
372
373	I15HANDLE: // IVG 15 Handler
374	R4 = 15;
375	RTI;
376
377	NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
378
379	//
380	// Data Segment
381	//
382
383	.data
384	DATA:
385	.space (0x10);
386
387	// Stack Segments (Both Kernel and User)
388
389	.space (STACKSIZE);
390	KSTACK:
391
392	.space (STACKSIZE);
393	USTACK: