projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a306116 | 1 | # frv testcase for mqaddhus $FRi,$FRj,$FRj |
| 086419a8 | 2 | # mach: frv fr500 |
| 4a306116 DB |
3 | |
| 4 | .include "../testutils.inc" | |
| 5 | ||
| 6 | start | |
| 7 | ||
| 8 | .global mqaddhus | |
| 9 | mqaddhus: | |
| 10 | set_fr_iimmed 0x0000,0x0000,fr10 | |
| 11 | set_fr_iimmed 0xdead,0x0000,fr11 | |
| 12 | set_fr_iimmed 0x0000,0x0000,fr12 | |
| 13 | set_fr_iimmed 0x0000,0xbeef,fr13 | |
| 14 | mqaddhus fr10,fr12,fr14 | |
| 15 | test_fr_limmed 0x0000,0x0000,fr14 | |
| 16 | test_fr_limmed 0xdead,0xbeef,fr15 | |
| 17 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 18 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 19 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 20 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 21 | ||
| 22 | set_fr_iimmed 0x0000,0xdead,fr10 | |
| 23 | set_fr_iimmed 0x1234,0x5678,fr11 | |
| 24 | set_fr_iimmed 0xbeef,0x0000,fr12 | |
| 25 | set_fr_iimmed 0x1111,0x1111,fr13 | |
| 26 | mqaddhus fr10,fr12,fr14 | |
| 27 | test_fr_limmed 0xbeef,0xdead,fr14 | |
| 28 | test_fr_limmed 0x2345,0x6789,fr15 | |
| 29 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 30 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 31 | test_spr_bits 1,0,0,msr0 ; msr0.aovf not set | |
| 32 | test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set | |
| 33 | ||
| 34 | set_fr_iimmed 0x7ffe,0x7ffe,fr10 | |
| 35 | set_fr_iimmed 0xfffe,0xfffe,fr11 | |
| 36 | set_fr_iimmed 0x0002,0x0001,fr12 | |
| 37 | set_fr_iimmed 0x0001,0x0002,fr13 | |
| 38 | mqaddhus fr10,fr12,fr14 | |
| 39 | test_fr_limmed 0x8000,0x7fff,fr14 | |
| 40 | test_fr_limmed 0xffff,0xffff,fr15 | |
| 41 | test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set | |
| 42 | test_spr_bits 2,1,1,msr0 ; msr0.ovf is set | |
| 43 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
| 44 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
| 45 | ||
| 46 | set_spr_immed 0,msr0 | |
| 47 | set_spr_immed 0,msr1 | |
| 48 | set_fr_iimmed 0x0002,0x0001,fr10 | |
| 49 | set_fr_iimmed 0x0001,0x0001,fr11 | |
| 50 | set_fr_iimmed 0xfffe,0xfffe,fr12 | |
| 51 | set_fr_iimmed 0x8000,0x8000,fr13 | |
| 52 | mqaddhus.p fr10,fr10,fr14 | |
| 53 | mqaddhus fr12,fr12,fr16 | |
| 54 | test_fr_limmed 0x0004,0x0002,fr14 | |
| 55 | test_fr_limmed 0x0002,0x0002,fr15 | |
| 56 | test_fr_limmed 0xffff,0xffff,fr16 | |
| 57 | test_fr_limmed 0xffff,0xffff,fr17 | |
| 58 | test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear | |
| 59 | test_spr_bits 2,1,0,msr0 ; msr0.ovf not set | |
| 60 | test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set | |
| 61 | test_spr_bits 2,1,1,msr1 ; msr1.ovf set | |
| 62 | test_spr_bits 1,0,1,msr0 ; msr0.aovf set | |
| 63 | test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set | |
| 64 | ||
| 65 | pass |