projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fe8b0df MS |
1 | # Hitachi H8 testcase 'addx' |
| 2 | # mach(): all | |
| 3 | # as(h8300): --defsym sim_cpu=0 | |
| 4 | # as(h8300h): --defsym sim_cpu=1 | |
| 5 | # as(h8300s): --defsym sim_cpu=2 | |
| 6 | # as(h8sx): --defsym sim_cpu=3 | |
| 7 | # ld(h8300h): -m h8300helf | |
| 8 | # ld(h8300s): -m h8300self | |
| 9 | # ld(h8sx): -m h8300sxelf | |
| 10 | ||
| 11 | .include "testutils.inc" | |
| 12 | ||
| 13 | # Instructions tested: | |
| 14 | # addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx | |
| 15 | # addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx | |
| 16 | # addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx | |
| 17 | # addx.b rs8, rd8 ; 0 e rs8 rd8 | |
| 18 | # addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ???? | |
| 19 | # addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ???? | |
| 20 | # addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8 | |
| 21 | # addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8 | |
| 22 | # addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ???? | |
| 23 | # addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ???? | |
| 24 | # | |
| 5fe8b0df MS |
25 | # word ops |
| 26 | # long ops | |
| 27 | ||
| 28 | .data | |
| 29 | byte_src: .byte 0x5 | |
| 30 | byte_dest: .byte 0 | |
| 31 | ||
| 32 | .align 2 | |
| 33 | word_src: .word 0x505 | |
| 34 | word_dest: .word 0 | |
| 35 | ||
| 36 | .align 4 | |
| 37 | long_src: .long 0x50505 | |
| 38 | long_dest: .long 0 | |
| 39 | ||
| 40 | ||
| 41 | start | |
| 42 | ||
| 43 | addx_b_imm8_0: | |
| 44 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 45 | set_ccr_zero | |
| 46 | ||
| 47 | ;; addx.b #xx:8,Rd ; Addx with carry initially zero. | |
| 48 | addx.b #5, r0l ; Immediate 8-bit operand | |
| 49 | ||
| 50 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 51 | test_ovf_clear | |
| 52 | test_zero_clear | |
| 53 | test_neg_set | |
| 54 | ||
| 55 | test_h_gr16 0xa5aa r0 ; add result: a5 + 5 | |
| 56 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
| 57 | test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 | |
| 58 | .endif | |
| 59 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 60 | test_gr_a5a5 2 | |
| 61 | test_gr_a5a5 3 | |
| 62 | test_gr_a5a5 4 | |
| 63 | test_gr_a5a5 5 | |
| 64 | test_gr_a5a5 6 | |
| 65 | test_gr_a5a5 7 | |
| 66 | ||
| 67 | addx_b_imm8_1: | |
| 68 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 69 | set_ccr_zero | |
| 70 | ||
| 71 | ;; addx.b #xx:8,Rd ; Addx with carry initially one. | |
| 3df3a316 | 72 | set_carry_flag |
| 5fe8b0df MS |
73 | addx.b #5, r0l ; Immediate 8-bit operand |
| 74 | ||
| 75 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 76 | test_ovf_clear | |
| 77 | test_zero_clear | |
| 78 | test_neg_set | |
| 79 | ||
| 80 | test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1 | |
| 81 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
| 82 | test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1 | |
| 83 | .endif | |
| 84 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 85 | test_gr_a5a5 2 | |
| 86 | test_gr_a5a5 3 | |
| 87 | test_gr_a5a5 4 | |
| 88 | test_gr_a5a5 5 | |
| 89 | test_gr_a5a5 6 | |
| 90 | test_gr_a5a5 7 | |
| 91 | ||
| 92 | .if (sim_cpu == h8sx) | |
| 93 | addx_b_imm8_rdind: | |
| 94 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 95 | set_ccr_zero | |
| 96 | ||
| 97 | ;; addx.b #xx:8,@eRd ; Addx to register indirect | |
| 98 | mov #byte_dest, er0 | |
| 99 | addx.b #5, @er0 | |
| 100 | ||
| 101 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 102 | test_ovf_clear | |
| 103 | test_zero_clear | |
| 104 | test_neg_clear | |
| 105 | ||
| 106 | test_h_gr32 byte_dest er0 ; er0 still contains address | |
| 107 | ||
| 108 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 109 | test_gr_a5a5 2 | |
| 110 | test_gr_a5a5 3 | |
| 111 | test_gr_a5a5 4 | |
| 112 | test_gr_a5a5 5 | |
| 113 | test_gr_a5a5 6 | |
| 114 | test_gr_a5a5 7 | |
| 115 | ||
| 116 | ;; Now check the result of the add to memory. | |
| 117 | cmp.b #5, @byte_dest | |
| 118 | beq .Lb1 | |
| 119 | fail | |
| 120 | .Lb1: | |
| 121 | ||
| 122 | addx_b_imm8_rdpostdec: | |
| 123 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 124 | set_ccr_zero | |
| 125 | ||
| 126 | ;; addx.b #xx:8,@eRd- ; Addx to register post-decrement | |
| 127 | mov #byte_dest, er0 | |
| 128 | addx.b #5, @er0- | |
| 129 | ||
| 130 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 131 | test_ovf_clear | |
| 132 | test_zero_clear | |
| 133 | test_neg_clear | |
| 134 | ||
| 135 | test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one | |
| 136 | ||
| 137 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 138 | test_gr_a5a5 2 | |
| 139 | test_gr_a5a5 3 | |
| 140 | test_gr_a5a5 4 | |
| 141 | test_gr_a5a5 5 | |
| 142 | test_gr_a5a5 6 | |
| 143 | test_gr_a5a5 7 | |
| 144 | ||
| 145 | ;; Now check the result of the add to memory. | |
| 146 | cmp.b #10, @byte_dest | |
| 147 | beq .Lb2 | |
| 148 | fail | |
| 149 | .Lb2: | |
| 150 | .endif | |
| 151 | ||
| 152 | addx_b_reg8_0: | |
| 153 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 154 | set_ccr_zero | |
| 155 | ||
| 156 | ;; addx.b Rs,Rd ; addx with carry initially zero | |
| 157 | mov.b #5, r0h | |
| 158 | addx.b r0h, r0l ; Register operand | |
| 159 | ||
| 160 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 161 | test_ovf_clear | |
| 162 | test_zero_clear | |
| 163 | test_neg_set | |
| 164 | ||
| 165 | test_h_gr16 0x05aa r0 ; add result: a5 + 5 | |
| 166 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
| 167 | test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 | |
| 168 | .endif | |
| 169 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 170 | test_gr_a5a5 2 | |
| 171 | test_gr_a5a5 3 | |
| 172 | test_gr_a5a5 4 | |
| 173 | test_gr_a5a5 5 | |
| 174 | test_gr_a5a5 6 | |
| 175 | test_gr_a5a5 7 | |
| 176 | ||
| 177 | addx_b_reg8_1: | |
| 178 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 179 | set_ccr_zero | |
| 180 | ||
| 181 | ;; addx.b Rs,Rd ; addx with carry initially one | |
| 182 | mov.b #5, r0h | |
| 3df3a316 | 183 | set_carry_flag |
| 5fe8b0df MS |
184 | addx.b r0h, r0l ; Register operand |
| 185 | ||
| 186 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 187 | test_ovf_clear | |
| 188 | test_zero_clear | |
| 189 | test_neg_set | |
| 190 | ||
| 191 | test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1 | |
| 192 | .if (sim_cpu) ; non-zero means h8300h, s, or sx | |
| 193 | test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1 | |
| 194 | .endif | |
| 195 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 196 | test_gr_a5a5 2 | |
| 197 | test_gr_a5a5 3 | |
| 198 | test_gr_a5a5 4 | |
| 199 | test_gr_a5a5 5 | |
| 200 | test_gr_a5a5 6 | |
| 201 | test_gr_a5a5 7 | |
| 202 | ||
| 203 | .if (sim_cpu == h8sx) | |
| 204 | addx_b_reg8_rdind: | |
| 205 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 206 | set_ccr_zero | |
| 207 | ||
| 208 | ;; addx.b rs8,@eRd ; Addx to register indirect | |
| 209 | mov #byte_dest, er0 | |
| 210 | mov.b #5, r1l | |
| 211 | addx.b r1l, @er0 | |
| 212 | ||
| 213 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 214 | test_ovf_clear | |
| 215 | test_zero_clear | |
| 216 | test_neg_clear | |
| 217 | ||
| 218 | test_h_gr32 byte_dest er0 ; er0 still contains address | |
| 219 | test_h_gr32 0xa5a5a505 er1 ; er1 has the test load | |
| 220 | ||
| 221 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 222 | test_gr_a5a5 3 | |
| 223 | test_gr_a5a5 4 | |
| 224 | test_gr_a5a5 5 | |
| 225 | test_gr_a5a5 6 | |
| 226 | test_gr_a5a5 7 | |
| 227 | ||
| 228 | ;; Now check the result of the add to memory. | |
| 229 | cmp.b #15, @byte_dest | |
| 230 | beq .Lb3 | |
| 231 | fail | |
| 232 | .Lb3: | |
| 233 | ||
| 234 | addx_b_reg8_rdpostdec: | |
| 235 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 236 | set_ccr_zero | |
| 237 | ||
| 238 | ;; addx.b rs8,@eRd- ; Addx to register post-decrement | |
| 239 | mov #byte_dest, er0 | |
| 240 | mov.b #5, r1l | |
| 241 | addx.b r1l, @er0- | |
| 242 | ||
| 243 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 244 | test_ovf_clear | |
| 245 | test_zero_clear | |
| 246 | test_neg_clear | |
| 247 | ||
| 248 | test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one | |
| 249 | test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load | |
| 250 | ||
| 251 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 252 | test_gr_a5a5 3 | |
| 253 | test_gr_a5a5 4 | |
| 254 | test_gr_a5a5 5 | |
| 255 | test_gr_a5a5 6 | |
| 256 | test_gr_a5a5 7 | |
| 257 | ||
| 258 | ;; Now check the result of the add to memory. | |
| 259 | cmp.b #20, @byte_dest | |
| 260 | beq .Lb4 | |
| 261 | fail | |
| 262 | .Lb4: | |
| 263 | ||
| 264 | addx_b_rsind_reg8: | |
| 265 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 266 | set_ccr_zero | |
| 267 | ||
| 268 | ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg | |
| 269 | mov #byte_src, er0 | |
| 270 | addx.b @er0, r1l | |
| 271 | ||
| 272 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 273 | test_ovf_clear | |
| 274 | test_zero_clear | |
| 275 | test_neg_set | |
| 276 | ||
| 277 | test_h_gr32 byte_src er0 ; er0 still contains address | |
| 278 | test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum | |
| 279 | ||
| 280 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 281 | test_gr_a5a5 3 | |
| 282 | test_gr_a5a5 4 | |
| 283 | test_gr_a5a5 5 | |
| 284 | test_gr_a5a5 6 | |
| 285 | test_gr_a5a5 7 | |
| 286 | ||
| 287 | addx_b_rspostdec_reg8: | |
| 288 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 289 | set_ccr_zero | |
| 290 | ||
| 291 | ;; addx.b @eRs-,rd8 ; Addx to register post-decrement | |
| 292 | mov #byte_src, er0 | |
| 293 | addx.b @er0-, r1l | |
| 294 | ||
| 295 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 296 | test_ovf_clear | |
| 297 | test_zero_clear | |
| 298 | test_neg_set | |
| 299 | ||
| 300 | test_h_gr32 byte_src-1 er0 ; er0 contains address minus one | |
| 301 | test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum | |
| 302 | ||
| 303 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 304 | test_gr_a5a5 3 | |
| 305 | test_gr_a5a5 4 | |
| 306 | test_gr_a5a5 5 | |
| 307 | test_gr_a5a5 6 | |
| 308 | test_gr_a5a5 7 | |
| 309 | ||
| 310 | addx_b_rsind_rsind: | |
| 311 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 312 | set_ccr_zero | |
| 313 | ||
| 314 | ;; addx.b @eRs,rd8 ; Addx from reg indirect to reg | |
| 315 | mov #byte_src, er0 | |
| 316 | mov #byte_dest, er1 | |
| 317 | addx.b @er0, @er1 | |
| 318 | ||
| 319 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 320 | test_ovf_clear | |
| 321 | test_zero_clear | |
| 322 | test_neg_clear | |
| 323 | ||
| 324 | test_h_gr32 byte_src er0 ; er0 still contains src address | |
| 325 | test_h_gr32 byte_dest er1 ; er1 still contains dst address | |
| 326 | ||
| 327 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 328 | test_gr_a5a5 3 | |
| 329 | test_gr_a5a5 4 | |
| 330 | test_gr_a5a5 5 | |
| 331 | test_gr_a5a5 6 | |
| 332 | test_gr_a5a5 7 | |
| 333 | ;; Now check the result of the add to memory. | |
| 334 | cmp.b #25, @byte_dest | |
| 335 | beq .Lb5 | |
| 336 | fail | |
| 337 | .Lb5: | |
| 338 | ||
| 339 | addx_b_rspostdec_rspostdec: | |
| 340 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 341 | set_ccr_zero | |
| 342 | ||
| 343 | ;; addx.b @eRs-,rd8 ; Addx to register post-decrement | |
| 344 | mov #byte_src, er0 | |
| 345 | mov #byte_dest, er1 | |
| 346 | addx.b @er0-, @er1- | |
| 347 | ||
| 348 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 349 | test_ovf_clear | |
| 350 | test_zero_clear | |
| 351 | test_neg_clear | |
| 352 | ||
| 353 | test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one | |
| 354 | test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one | |
| 355 | ||
| 356 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 357 | test_gr_a5a5 3 | |
| 358 | test_gr_a5a5 4 | |
| 359 | test_gr_a5a5 5 | |
| 360 | test_gr_a5a5 6 | |
| 361 | test_gr_a5a5 7 | |
| 362 | ;; Now check the result of the add to memory. | |
| 363 | cmp.b #30, @byte_dest | |
| 364 | beq .Lb6 | |
| 365 | fail | |
| 366 | .Lb6: | |
| 367 | ||
| 368 | addx_w_imm16_0: | |
| 369 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 370 | set_ccr_zero | |
| 371 | ||
| 372 | ;; addx.w #xx:16,Rd ; Addx with carry initially zero. | |
| 373 | addx.w #0x505, r0 ; Immediate 16-bit operand | |
| 374 | ||
| 375 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 376 | test_ovf_clear | |
| 377 | test_zero_clear | |
| 378 | test_neg_set | |
| 379 | ||
| 380 | test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505 | |
| 381 | test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505 | |
| 382 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 383 | test_gr_a5a5 2 | |
| 384 | test_gr_a5a5 3 | |
| 385 | test_gr_a5a5 4 | |
| 386 | test_gr_a5a5 5 | |
| 387 | test_gr_a5a5 6 | |
| 388 | test_gr_a5a5 7 | |
| 389 | ||
| 390 | addx_w_imm16_1: | |
| 391 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 392 | set_ccr_zero | |
| 393 | ||
| 394 | ;; addx.w #xx:16,Rd ; Addx with carry initially one. | |
| 3df3a316 | 395 | set_carry_flag |
| 5fe8b0df MS |
396 | addx.w #0x505, r0 ; Immediate 16-bit operand |
| 397 | ||
| 398 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 399 | test_ovf_clear | |
| 400 | test_zero_clear | |
| 401 | test_neg_set | |
| 402 | ||
| 403 | test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1 | |
| 404 | test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1 | |
| 405 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 406 | test_gr_a5a5 2 | |
| 407 | test_gr_a5a5 3 | |
| 408 | test_gr_a5a5 4 | |
| 409 | test_gr_a5a5 5 | |
| 410 | test_gr_a5a5 6 | |
| 411 | test_gr_a5a5 7 | |
| 412 | ||
| 413 | addx_w_imm16_rdind: | |
| 414 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 415 | set_ccr_zero | |
| 416 | ||
| 417 | ;; addx.w #xx:16,@eRd ; Addx to register indirect | |
| 418 | mov #word_dest, er0 | |
| 419 | addx.w #0x505, @er0 | |
| 420 | ||
| 421 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 422 | test_ovf_clear | |
| 423 | test_zero_clear | |
| 424 | test_neg_clear | |
| 425 | ||
| 426 | test_h_gr32 word_dest er0 ; er0 still contains address | |
| 427 | ||
| 428 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 429 | test_gr_a5a5 2 | |
| 430 | test_gr_a5a5 3 | |
| 431 | test_gr_a5a5 4 | |
| 432 | test_gr_a5a5 5 | |
| 433 | test_gr_a5a5 6 | |
| 434 | test_gr_a5a5 7 | |
| 435 | ||
| 436 | ;; Now check the result of the add to memory. | |
| 437 | cmp.w #0x505, @word_dest | |
| 438 | beq .Lw1 | |
| 439 | fail | |
| 440 | .Lw1: | |
| 441 | ||
| 442 | addx_w_imm16_rdpostdec: | |
| 443 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 444 | set_ccr_zero | |
| 445 | ||
| 446 | ;; addx.w #xx:16,@eRd- ; Addx to register post-decrement | |
| 447 | mov #word_dest, er0 | |
| 448 | addx.w #0x505, @er0- | |
| 449 | ||
| 450 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 451 | test_ovf_clear | |
| 452 | test_zero_clear | |
| 453 | test_neg_clear | |
| 454 | ||
| 455 | test_h_gr32 word_dest-2 er0 ; er0 contains address minus one | |
| 456 | ||
| 457 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 458 | test_gr_a5a5 2 | |
| 459 | test_gr_a5a5 3 | |
| 460 | test_gr_a5a5 4 | |
| 461 | test_gr_a5a5 5 | |
| 462 | test_gr_a5a5 6 | |
| 463 | test_gr_a5a5 7 | |
| 464 | ||
| 465 | ;; Now check the result of the add to memory. | |
| 466 | cmp.w #0xa0a, @word_dest | |
| 467 | beq .Lw2 | |
| 468 | fail | |
| 469 | .Lw2: | |
| 470 | ||
| 471 | addx_w_reg16_0: | |
| 472 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 473 | set_ccr_zero | |
| 474 | ||
| 475 | ;; addx.w Rs,Rd ; addx with carry initially zero | |
| 476 | mov.w #0x505, e0 | |
| 477 | addx.w e0, r0 ; Register operand | |
| 478 | ||
| 479 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 480 | test_ovf_clear | |
| 481 | test_zero_clear | |
| 482 | test_neg_set | |
| 483 | ||
| 484 | test_h_gr32 0x0505aaaa er0 ; add result: | |
| 485 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 486 | test_gr_a5a5 2 | |
| 487 | test_gr_a5a5 3 | |
| 488 | test_gr_a5a5 4 | |
| 489 | test_gr_a5a5 5 | |
| 490 | test_gr_a5a5 6 | |
| 491 | test_gr_a5a5 7 | |
| 492 | ||
| 493 | addx_w_reg16_1: | |
| 494 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 495 | set_ccr_zero | |
| 496 | ||
| 497 | ;; addx.w Rs,Rd ; addx with carry initially one | |
| 498 | mov.w #0x505, e0 | |
| 3df3a316 | 499 | set_carry_flag |
| 5fe8b0df MS |
500 | addx.w e0, r0 ; Register operand |
| 501 | ||
| 502 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 503 | test_ovf_clear | |
| 504 | test_zero_clear | |
| 505 | test_neg_set | |
| 506 | ||
| 507 | test_h_gr32 0x0505aaab er0 ; add result: | |
| 508 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 509 | test_gr_a5a5 2 | |
| 510 | test_gr_a5a5 3 | |
| 511 | test_gr_a5a5 4 | |
| 512 | test_gr_a5a5 5 | |
| 513 | test_gr_a5a5 6 | |
| 514 | test_gr_a5a5 7 | |
| 515 | ||
| 516 | addx_w_reg16_rdind: | |
| 517 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 518 | set_ccr_zero | |
| 519 | ||
| 520 | ;; addx.w rs8,@eRd ; Addx to register indirect | |
| 521 | mov #word_dest, er0 | |
| 522 | mov.w #0x505, r1 | |
| 523 | addx.w r1, @er0 | |
| 524 | ||
| 525 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 526 | test_ovf_clear | |
| 527 | test_zero_clear | |
| 528 | test_neg_clear | |
| 529 | ||
| 530 | test_h_gr32 word_dest er0 ; er0 still contains address | |
| 531 | test_h_gr32 0xa5a50505 er1 ; er1 has the test load | |
| 532 | ||
| 533 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 534 | test_gr_a5a5 3 | |
| 535 | test_gr_a5a5 4 | |
| 536 | test_gr_a5a5 5 | |
| 537 | test_gr_a5a5 6 | |
| 538 | test_gr_a5a5 7 | |
| 539 | ||
| 540 | ;; Now check the result of the add to memory. | |
| 541 | cmp.w #0xf0f, @word_dest | |
| 542 | beq .Lw3 | |
| 543 | fail | |
| 544 | .Lw3: | |
| 545 | ||
| 546 | addx_w_reg16_rdpostdec: | |
| 547 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 548 | set_ccr_zero | |
| 549 | ||
| 550 | ;; addx.w rs8,@eRd- ; Addx to register post-decrement | |
| 551 | mov #word_dest, er0 | |
| 552 | mov.w #0x505, r1 | |
| 553 | addx.w r1, @er0- | |
| 554 | ||
| 555 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 556 | test_ovf_clear | |
| 557 | test_zero_clear | |
| 558 | test_neg_clear | |
| 559 | ||
| 560 | test_h_gr32 word_dest-2 er0 ; er0 contains address minus one | |
| 561 | test_h_gr32 0xa5a50505 er1 ; er1 contains the test load | |
| 562 | ||
| 563 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 564 | test_gr_a5a5 3 | |
| 565 | test_gr_a5a5 4 | |
| 566 | test_gr_a5a5 5 | |
| 567 | test_gr_a5a5 6 | |
| 568 | test_gr_a5a5 7 | |
| 569 | ||
| 570 | ;; Now check the result of the add to memory. | |
| 571 | cmp.w #0x1414, @word_dest | |
| 572 | beq .Lw4 | |
| 573 | fail | |
| 574 | .Lw4: | |
| 575 | ||
| 576 | addx_w_rsind_reg16: | |
| 577 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 578 | set_ccr_zero | |
| 579 | ||
| 580 | ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg | |
| 581 | mov #word_src, er0 | |
| 582 | addx.w @er0, r1 | |
| 583 | ||
| 584 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 585 | test_ovf_clear | |
| 586 | test_zero_clear | |
| 587 | test_neg_set | |
| 588 | ||
| 589 | test_h_gr32 word_src er0 ; er0 still contains address | |
| 590 | test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum | |
| 591 | ||
| 592 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 593 | test_gr_a5a5 3 | |
| 594 | test_gr_a5a5 4 | |
| 595 | test_gr_a5a5 5 | |
| 596 | test_gr_a5a5 6 | |
| 597 | test_gr_a5a5 7 | |
| 598 | ||
| 599 | addx_w_rspostdec_reg16: | |
| 600 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 601 | set_ccr_zero | |
| 602 | ||
| 603 | ;; addx.w @eRs-,rd8 ; Addx to register post-decrement | |
| 604 | mov #word_src, er0 | |
| 605 | addx.w @er0-, r1 | |
| 606 | ||
| 607 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 608 | test_ovf_clear | |
| 609 | test_zero_clear | |
| 610 | test_neg_set | |
| 611 | ||
| 612 | test_h_gr32 word_src-2 er0 ; er0 contains address minus one | |
| 613 | test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum | |
| 614 | ||
| 615 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 616 | test_gr_a5a5 3 | |
| 617 | test_gr_a5a5 4 | |
| 618 | test_gr_a5a5 5 | |
| 619 | test_gr_a5a5 6 | |
| 620 | test_gr_a5a5 7 | |
| 621 | ||
| 622 | addx_w_rsind_rdind: | |
| 623 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 624 | set_ccr_zero | |
| 625 | ||
| 626 | ;; addx.w @eRs,rd8 ; Addx from reg indirect to reg | |
| 627 | mov #word_src, er0 | |
| 628 | mov #word_dest, er1 | |
| 629 | addx.w @er0, @er1 | |
| 630 | ||
| 631 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 632 | test_ovf_clear | |
| 633 | test_zero_clear | |
| 634 | test_neg_clear | |
| 635 | ||
| 636 | test_h_gr32 word_src er0 ; er0 still contains src address | |
| 637 | test_h_gr32 word_dest er1 ; er1 still contains dst address | |
| 638 | ||
| 639 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 640 | test_gr_a5a5 3 | |
| 641 | test_gr_a5a5 4 | |
| 642 | test_gr_a5a5 5 | |
| 643 | test_gr_a5a5 6 | |
| 644 | test_gr_a5a5 7 | |
| 645 | ;; Now check the result of the add to memory. | |
| 646 | cmp.w #0x1919, @word_dest | |
| 647 | beq .Lw5 | |
| 648 | fail | |
| 649 | .Lw5: | |
| 650 | ||
| 651 | addx_w_rspostdec_rdpostdec: | |
| 652 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 653 | set_ccr_zero | |
| 654 | ||
| 655 | ;; addx.w @eRs-,rd8 ; Addx to register post-decrement | |
| 656 | mov #word_src, er0 | |
| 657 | mov #word_dest, er1 | |
| 658 | addx.w @er0-, @er1- | |
| 659 | ||
| 660 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 661 | test_ovf_clear | |
| 662 | test_zero_clear | |
| 663 | test_neg_clear | |
| 664 | ||
| 665 | test_h_gr32 word_src-2 er0 ; er0 contains src address minus one | |
| 666 | test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one | |
| 667 | ||
| 668 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 669 | test_gr_a5a5 3 | |
| 670 | test_gr_a5a5 4 | |
| 671 | test_gr_a5a5 5 | |
| 672 | test_gr_a5a5 6 | |
| 673 | test_gr_a5a5 7 | |
| 674 | ;; Now check the result of the add to memory. | |
| 675 | cmp.w #0x1e1e, @word_dest | |
| 676 | beq .Lw6 | |
| 677 | fail | |
| 678 | .Lw6: | |
| 679 | ||
| 680 | addx_l_imm32_0: | |
| 681 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 682 | set_ccr_zero | |
| 683 | ||
| 684 | ;; addx.l #xx:32,Rd ; Addx with carry initially zero. | |
| 685 | addx.l #0x50505, er0 ; Immediate 32-bit operand | |
| 686 | ||
| 687 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 688 | test_ovf_clear | |
| 689 | test_zero_clear | |
| 690 | test_neg_set | |
| 691 | ||
| 692 | test_h_gr32 0xa5aaaaaa er0 ; add result: | |
| 693 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 694 | test_gr_a5a5 2 | |
| 695 | test_gr_a5a5 3 | |
| 696 | test_gr_a5a5 4 | |
| 697 | test_gr_a5a5 5 | |
| 698 | test_gr_a5a5 6 | |
| 699 | test_gr_a5a5 7 | |
| 700 | ||
| 701 | addx_l_imm32_1: | |
| 702 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 703 | set_ccr_zero | |
| 704 | ||
| 705 | ;; addx.l #xx:32,Rd ; Addx with carry initially one. | |
| 3df3a316 | 706 | set_carry_flag |
| 5fe8b0df MS |
707 | addx.l #0x50505, er0 ; Immediate 32-bit operand |
| 708 | ||
| 709 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 710 | test_ovf_clear | |
| 711 | test_zero_clear | |
| 712 | test_neg_set | |
| 713 | ||
| 714 | test_h_gr32 0xa5aaaaab er0 ; add result: | |
| 715 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 716 | test_gr_a5a5 2 | |
| 717 | test_gr_a5a5 3 | |
| 718 | test_gr_a5a5 4 | |
| 719 | test_gr_a5a5 5 | |
| 720 | test_gr_a5a5 6 | |
| 721 | test_gr_a5a5 7 | |
| 722 | ||
| 723 | addx_l_imm32_rdind: | |
| 724 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 725 | set_ccr_zero | |
| 726 | ||
| 727 | ;; addx.l #xx:32,@eRd ; Addx to register indirect | |
| 728 | mov #long_dest, er0 | |
| 729 | addx.l #0x50505, @er0 | |
| 730 | ||
| 731 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 732 | test_ovf_clear | |
| 733 | test_zero_clear | |
| 734 | test_neg_clear | |
| 735 | ||
| 736 | test_h_gr32 long_dest er0 ; er0 still contains address | |
| 737 | ||
| 738 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 739 | test_gr_a5a5 2 | |
| 740 | test_gr_a5a5 3 | |
| 741 | test_gr_a5a5 4 | |
| 742 | test_gr_a5a5 5 | |
| 743 | test_gr_a5a5 6 | |
| 744 | test_gr_a5a5 7 | |
| 745 | ||
| 746 | ;; Now check the result of the add to memory. | |
| 747 | cmp.l #0x50505, @long_dest | |
| 748 | beq .Ll1 | |
| 749 | fail | |
| 750 | .Ll1: | |
| 751 | ||
| 752 | addx_l_imm32_rdpostdec: | |
| 753 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 754 | set_ccr_zero | |
| 755 | ||
| 756 | ;; addx.l #xx:32,@eRd- ; Addx to register post-decrement | |
| 757 | mov #long_dest, er0 | |
| 758 | addx.l #0x50505, @er0- | |
| 759 | ||
| 760 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 761 | test_ovf_clear | |
| 762 | test_zero_clear | |
| 763 | test_neg_clear | |
| 764 | ||
| 765 | test_h_gr32 long_dest-4 er0 ; er0 contains address minus one | |
| 766 | ||
| 767 | test_gr_a5a5 1 ; Make sure other general regs not disturbed | |
| 768 | test_gr_a5a5 2 | |
| 769 | test_gr_a5a5 3 | |
| 770 | test_gr_a5a5 4 | |
| 771 | test_gr_a5a5 5 | |
| 772 | test_gr_a5a5 6 | |
| 773 | test_gr_a5a5 7 | |
| 774 | ||
| 775 | ;; Now check the result of the add to memory. | |
| 776 | cmp.l #0xa0a0a, @long_dest | |
| 777 | beq .Ll2 | |
| 778 | fail | |
| 779 | .Ll2: | |
| 780 | ||
| 781 | addx_l_reg32_0: | |
| 782 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 783 | set_ccr_zero | |
| 784 | ||
| 785 | ;; addx.l Rs,Rd ; addx with carry initially zero | |
| 786 | mov.l #0x50505, er0 | |
| 787 | addx.l er0, er1 ; Register operand | |
| 788 | ||
| 789 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 790 | test_ovf_clear | |
| 791 | test_zero_clear | |
| 792 | test_neg_set | |
| 793 | ||
| 794 | test_h_gr32 0x50505 er0 ; add load | |
| 795 | test_h_gr32 0xa5aaaaaa er1 ; add result: | |
| 796 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 797 | test_gr_a5a5 3 | |
| 798 | test_gr_a5a5 4 | |
| 799 | test_gr_a5a5 5 | |
| 800 | test_gr_a5a5 6 | |
| 801 | test_gr_a5a5 7 | |
| 802 | ||
| 803 | addx_l_reg32_1: | |
| 804 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 805 | set_ccr_zero | |
| 806 | ||
| 807 | ;; addx.l Rs,Rd ; addx with carry initially one | |
| 808 | mov.l #0x50505, er0 | |
| 3df3a316 | 809 | set_carry_flag |
| 5fe8b0df MS |
810 | addx.l er0, er1 ; Register operand |
| 811 | ||
| 812 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 813 | test_ovf_clear | |
| 814 | test_zero_clear | |
| 815 | test_neg_set | |
| 816 | ||
| 817 | test_h_gr32 0x50505 er0 ; add result: | |
| 818 | test_h_gr32 0xa5aaaaab er1 ; add result: | |
| 819 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 820 | test_gr_a5a5 3 | |
| 821 | test_gr_a5a5 4 | |
| 822 | test_gr_a5a5 5 | |
| 823 | test_gr_a5a5 6 | |
| 824 | test_gr_a5a5 7 | |
| 825 | ||
| 826 | addx_l_reg32_rdind: | |
| 827 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 828 | set_ccr_zero | |
| 829 | ||
| 830 | ;; addx.l rs8,@eRd ; Addx to register indirect | |
| 831 | mov #long_dest, er0 | |
| 832 | mov.l #0x50505, er1 | |
| 833 | addx.l er1, @er0 | |
| 834 | ||
| 835 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 836 | test_ovf_clear | |
| 837 | test_zero_clear | |
| 838 | test_neg_clear | |
| 839 | ||
| 840 | test_h_gr32 long_dest er0 ; er0 still contains address | |
| 841 | test_h_gr32 0x50505 er1 ; er1 has the test load | |
| 842 | ||
| 843 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 844 | test_gr_a5a5 3 | |
| 845 | test_gr_a5a5 4 | |
| 846 | test_gr_a5a5 5 | |
| 847 | test_gr_a5a5 6 | |
| 848 | test_gr_a5a5 7 | |
| 849 | ||
| 850 | ;; Now check the result of the add to memory. | |
| 851 | cmp.l #0xf0f0f, @long_dest | |
| 852 | beq .Ll3 | |
| 853 | fail | |
| 854 | .Ll3: | |
| 855 | ||
| 856 | addx_l_reg32_rdpostdec: | |
| 857 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 858 | set_ccr_zero | |
| 859 | ||
| 860 | ;; addx.l rs8,@eRd- ; Addx to register post-decrement | |
| 861 | mov #long_dest, er0 | |
| 862 | mov.l #0x50505, er1 | |
| 863 | addx.l er1, @er0- | |
| 864 | ||
| 865 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 866 | test_ovf_clear | |
| 867 | test_zero_clear | |
| 868 | test_neg_clear | |
| 869 | ||
| 870 | test_h_gr32 long_dest-4 er0 ; er0 contains address minus one | |
| 871 | test_h_gr32 0x50505 er1 ; er1 contains the test load | |
| 872 | ||
| 873 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 874 | test_gr_a5a5 3 | |
| 875 | test_gr_a5a5 4 | |
| 876 | test_gr_a5a5 5 | |
| 877 | test_gr_a5a5 6 | |
| 878 | test_gr_a5a5 7 | |
| 879 | ||
| 880 | ;; Now check the result of the add to memory. | |
| 881 | cmp.l #0x141414, @long_dest | |
| 882 | beq .Ll4 | |
| 883 | fail | |
| 884 | .Ll4: | |
| 885 | ||
| 886 | addx_l_rsind_reg32: | |
| 887 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 888 | set_ccr_zero | |
| 889 | ||
| 890 | ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg | |
| 891 | mov #long_src, er0 | |
| 892 | addx.l @er0, er1 | |
| 893 | ||
| 894 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 895 | test_ovf_clear | |
| 896 | test_zero_clear | |
| 897 | test_neg_set | |
| 898 | ||
| 899 | test_h_gr32 long_src er0 ; er0 still contains address | |
| 900 | test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum | |
| 901 | ||
| 902 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 903 | test_gr_a5a5 3 | |
| 904 | test_gr_a5a5 4 | |
| 905 | test_gr_a5a5 5 | |
| 906 | test_gr_a5a5 6 | |
| 907 | test_gr_a5a5 7 | |
| 908 | ||
| 909 | addx_l_rspostdec_reg32: | |
| 910 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 911 | set_ccr_zero | |
| 912 | ||
| 913 | ;; addx.l @eRs-,rd8 ; Addx to register post-decrement | |
| 914 | mov #long_src, er0 | |
| 915 | addx.l @er0-, er1 | |
| 916 | ||
| 917 | test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 | |
| 918 | test_ovf_clear | |
| 919 | test_zero_clear | |
| 920 | test_neg_set | |
| 921 | ||
| 922 | test_h_gr32 long_src-4 er0 ; er0 contains address minus one | |
| 923 | test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum | |
| 924 | ||
| 925 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 926 | test_gr_a5a5 3 | |
| 927 | test_gr_a5a5 4 | |
| 928 | test_gr_a5a5 5 | |
| 929 | test_gr_a5a5 6 | |
| 930 | test_gr_a5a5 7 | |
| 931 | ||
| 932 | addx_l_rsind_rdind: | |
| 933 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 934 | set_ccr_zero | |
| 935 | ||
| 936 | ;; addx.l @eRs,rd8 ; Addx from reg indirect to reg | |
| 937 | mov #long_src, er0 | |
| 938 | mov #long_dest, er1 | |
| 939 | addx.l @er0, @er1 | |
| 940 | ||
| 941 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 942 | test_ovf_clear | |
| 943 | test_zero_clear | |
| 944 | test_neg_clear | |
| 945 | ||
| 946 | test_h_gr32 long_src er0 ; er0 still contains src address | |
| 947 | test_h_gr32 long_dest er1 ; er1 still contains dst address | |
| 948 | ||
| 949 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 950 | test_gr_a5a5 3 | |
| 951 | test_gr_a5a5 4 | |
| 952 | test_gr_a5a5 5 | |
| 953 | test_gr_a5a5 6 | |
| 954 | test_gr_a5a5 7 | |
| 955 | ;; Now check the result of the add to memory. | |
| 956 | cmp.l #0x191919, @long_dest | |
| 957 | beq .Ll5 | |
| 958 | fail | |
| 959 | .Ll5: | |
| 960 | ||
| 961 | addx_l_rspostdec_rdpostdec: | |
| 962 | set_grs_a5a5 ; Fill all general regs with a fixed pattern | |
| 963 | set_ccr_zero | |
| 964 | ||
| 965 | ;; addx.l @eRs-,rd8 ; Addx to register post-decrement | |
| 966 | mov #long_src, er0 | |
| 967 | mov #long_dest, er1 | |
| 968 | addx.l @er0-, @er1- | |
| 969 | ||
| 970 | test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 | |
| 971 | test_ovf_clear | |
| 972 | test_zero_clear | |
| 973 | test_neg_clear | |
| 974 | ||
| 975 | test_h_gr32 long_src-4 er0 ; er0 contains src address minus one | |
| 976 | test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one | |
| 977 | ||
| 978 | test_gr_a5a5 2 ; Make sure other general regs not disturbed | |
| 979 | test_gr_a5a5 3 | |
| 980 | test_gr_a5a5 4 | |
| 981 | test_gr_a5a5 5 | |
| 982 | test_gr_a5a5 6 | |
| 983 | test_gr_a5a5 7 | |
| 984 | ;; Now check the result of the add to memory. | |
| 985 | cmp.l #0x1e1e1e, @long_dest | |
| 986 | beq .Ll6 | |
| 987 | fail | |
| 988 | .Ll6: | |
| 989 | .endif | |
| 990 | pass | |
| 991 | ||
| 992 | exit 0 |