projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| be8fb42b MS |
1 | # sh testcase for mac.w |
| 2 | # mach: all | |
| 3 | # as(sh): -defsym sim_cpu=0 | |
| 4 | # as(shdsp): -defsym sim_cpu=1 -dsp | |
| 5 | ||
| 6 | .include "testutils.inc" | |
| 7 | ||
| 8 | start | |
| 9 | set_grs_a5a5 | |
| 10 | ||
| 11 | # Prime {MACL, MACH} to #1. | |
| 12 | mov #1, r0 | |
| 13 | dmulu.l r0, r0 | |
| 14 | ||
| 15 | # Set up addresses. | |
| 16 | mov.l pfour00, r0 ! 85 | |
| 17 | mov.l pfour12, r1 ! 17 | |
| 18 | ||
| 19 | test: | |
| 20 | mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 | |
| 21 | ||
| 22 | check: | |
| 23 | # Check result. | |
| 24 | assert_sreg 0, mach | |
| 25 | assert_sreg 85*17+1, macl | |
| 26 | ||
| 27 | # Ensure post-increment occurred. | |
| 28 | assertreg0 four00+2 | |
| 29 | assertreg four12+2, r1 | |
| 30 | ||
| 31 | doubleinc: | |
| 32 | mov.l pfour00, r0 | |
| 33 | mac.w @r0+, @r0+ | |
| 34 | assertreg0 four00+4 | |
| 35 | ||
| 36 | set_greg 0xa5a5a5a5, r0 | |
| 37 | set_greg 0xa5a5a5a5, r1 | |
| 38 | ||
| 39 | test_grs_a5a5 | |
| 40 | ||
| 41 | pass | |
| 42 | exit 0 | |
| 43 | ||
| 44 | .align 2 | |
| 45 | four00: | |
| 46 | .word 85 | |
| 47 | .word 2 | |
| 48 | four12: | |
| 49 | .word 17 | |
| 50 | .word 3 | |
| 51 | ||
| 52 | ||
| 53 | pfour00: | |
| 54 | .long four00 | |
| 55 | pfour12: | |
| 56 | .long four12 |