[thirdparty/binutils-gdb.git] / sim / testsuite / sim / v850 / divu.cgs

# v850 divu
# mach: v850e
# as(v850e): -mv850e

	.include "testutils.inc"

	seti	6, r1
	seti	45, r2
	divu	r1, r2, r3

	flags	0
	reg	r1, 6
	reg	r2, 7
	reg	r3, 3

	seti	4, r1
	seti	0x40000000, r2
	divu	r1, r2, r3

	flags	0
	reg	r1, 4
	reg	r2, 0x10000000
	reg	r3, 0

# If the data is divided by zero, OV=1 and the quotient is undefined.
# According to NEC, the S and Z flags, and the output registers, are
# unchanged.

	noflags
	seti	0, r1
	seti	45, r2
	seti	67, r3
	divu	r1, r2, r3

	flags	v
	reg	r2, 45
	reg	r3, 67

	allflags
	seti	0, r1
	seti	45, r2
	seti	67, r3
	divu	r1, r2, r3

	flags	sat + c + v + s + z
	reg	r2, 45
	reg	r3, 67

# Zero / (N!=0) => normal

	noflags
	seti	45, r1
	seti	0, r2
	seti	67, r3
	divu	r1, r2, r3

	flags	z
	reg	r1, 45
	reg	r2, 0
	reg	r3, 0

# The Z flag is based on the quotient, not the remainder

	noflags
	seti	45, r1
	seti	16, r2
	divu	r1, r2, r3

	flags	z
	reg	r2, 0
	reg	r3, 16

# If the quot and rem registers are the same, the remainder is stored.

	seti	6, r1
	seti	45, r2
	divu	r1, r2, r2

	flags	0
	reg	r1, 6
	reg	r2, 3

	pass
Commit	Line	Data
c5fbc25b DD	1	# v850 divu
	2	# mach: v850e
	3	# as(v850e): -mv850e
	4
	5	.include "testutils.inc"
	6
	7	seti 6, r1
	8	seti 45, r2
	9	divu r1, r2, r3
	10
	11	flags 0
	12	reg r1, 6
	13	reg r2, 7
	14	reg r3, 3
	15
	16	seti 4, r1
	17	seti 0x40000000, r2
	18	divu r1, r2, r3
	19
	20	flags 0
	21	reg r1, 4
	22	reg r2, 0x10000000
	23	reg r3, 0
	24
	25	# If the data is divided by zero, OV=1 and the quotient is undefined.
	26	# According to NEC, the S and Z flags, and the output registers, are
	27	# unchanged.
	28
	29	noflags
	30	seti 0, r1
	31	seti 45, r2
	32	seti 67, r3
	33	divu r1, r2, r3
	34
	35	flags v
	36	reg r2, 45
	37	reg r3, 67
	38
	39	allflags
	40	seti 0, r1
	41	seti 45, r2
	42	seti 67, r3
	43	divu r1, r2, r3
	44
	45	flags sat + c + v + s + z
	46	reg r2, 45
	47	reg r3, 67
	48
	49	# Zero / (N!=0) => normal
	50
	51	noflags
	52	seti 45, r1
	53	seti 0, r2
	54	seti 67, r3
	55	divu r1, r2, r3
	56
	57	flags z
	58	reg r1, 45
	59	reg r2, 0
	60	reg r3, 0
	61
	62	# The Z flag is based on the quotient, not the remainder
	63
	64	noflags
65	seti 45, r1
66	seti 16, r2
67	divu r1, r2, r3
68
69	flags z
70	reg r2, 0
71	reg r3, 16
72
73	# If the quot and rem registers are the same, the remainder is stored.
74
75	seti 6, r1
76	seti 45, r2
77	divu r1, r2, r2
78
79	flags 0
80	reg r1, 6
81	reg r2, 3
82
83	pass