+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/gas.exp: Remove ns32k xfails.
+ * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h: Don't include bit_fix.h.
+ (struct fix): Rearrange some fields. Delete fx_im_disp and
+ fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
+ * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
+ (fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
+ (print_fixup): Don't print im_disp.
+ * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
+ and fx_im_disp.
+ * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
+ fx_no_overflow when fx_bit_fixP.
+ * config/tc-dlx.h: Include bit_fix.h.
+ (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
+ * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
+ fx_no_overflow when bit_fixP.
+ * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
+ (fix_im_disp, fix_bit_fixP): Adjust to suit.
+ (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * write.h (struct fix <fx_where>): Make unsigned.
+ (fix_new, fix_at_start, fix_new_exp): Adjust prototypes.
+ * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and
+ "size" parameters unsigned long.
+ (fix_new_internal): Likewise. Adjust error format string to suit.
+ * config/tc-mips.c (md_convert_frag): Remove cast of fx_where.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.
+ * config/tc-score7.c (s7_convert_frag): Likewise.
+
+2019-04-16 Alan Modra <amodra@gmail.com>
+
+ * frags.h (struct frag <fr_fix>): Use unsigned type.
+ * frags.c (frag_new): Assert that current size exceeds
+ old_frags_var_max_size.
+ * ehopt.c (get_cie_info): Adjust for unsigned fr_fix.
+ * listing.c (calc_hex): Likewise.
+ * write.c (cvt_frag_to_fill, write_relocs): Likewise.
+ * config/tc-arc.c (md_convert_frag): Likewise.
+ * config/tc-avr.c (avr_patch_gccisr_frag): Likewise.
+ * config/tc-mips.c (md_convert_frag): Likewise.
+ * config/tc-rl78.c (md_convert_frag): Likewise.
+ * config/tc-rx.c (md_convert_frag): Likewise.
+ * config/tc-sparc.c (md_apply_fix): Likewise.
+ * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.
+ (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (parse_sys_vldr_vstr): New function.
+ (OP_VLDR): New enum operand_parse_code enumerator.
+ (parse_operands): Add logic for OP_VLDR.
+ (do_t_vldr_vstr_sysreg): New function.
+ (do_vldr_vstr): Likewise.
+ (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
+ (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
+ Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
+ uses of VLDR and VSTR.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
+ above bad uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
+ VSTR valid uses.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
+ above examples.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
+ (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ enumerators.
+ (parse_vfp_reg_list): Add new partial_match parameter. Set
+ *partial_match to TRUE if at least one element in the register list has
+ matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
+ register lists which expect VPR as last element in the list.
+ (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
+ prototype.
+ (s_arm_unwind_save_vfp): Likewise.
+ (enum operand_parse_code): New OP_VRSDVLST enumerator.
+ (parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
+ Handle new OP_VRSDVLST case.
+ (do_t_vscclrm): New function.
+ (insns): New entry for VSCCLRM instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
+ instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
+ for above instructions.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
+ instruction.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
+ for above instructions.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (enum reg_list_els): Define earlier and add
+ REGLIST_RN and REGLIST_CLRM enumerators.
+ (parse_reg_list): Add etype parameter to distinguish between regular
+ core register list and CLRM register list. Add logic to
+ recognize CLRM register list.
+ (parse_vfp_reg_list): Assert type is not for core register list.
+ (s_arm_unwind_save_core): Update call to parse_reg_list to new
+ prototype.
+ (enum operand_parse_code): Declare OP_CLRMLST enumerator.
+ (parse_operands): Update call to parse_reg_list to new prototype. Add
+ logic for OP_CLRMLST.
+ (encode_thumb2_ldmstm): Rename into ...
+ (encode_thumb2_multi): This. Add do_io parameter. Add logic to
+ encode CLRM and guard LDM/STM only code by do_io.
+ (do_t_ldmstm): Adapt to use encode_thumb2_multi.
+ (do_t_push_pop): Likewise.
+ (do_t_clrm): New function.
+ (insns): Define CLRM.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
+ * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
+ for the LR operand and optional LR operand.
+ (parse_operands): Add switch cases for OP_LR and OP_oLR for
+ both type checking and value checking.
+ (encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
+ (v8_1_loop_reloc): New helper function for handling labels
+ for the low overhead loop instructions.
+ (do_t_loloop): New function to encode DLS, WLS and LE.
+ (insns): New entries for WLS, DLS and LE.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_ARM_THUMB_LOOP12.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-tloop.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
+ (do_t_v8_1_branch): New switch case for bfcsel.
+ (toU): Define.
+ (insns): New instruction for bfcsel.
+ (md_pcrel_from_section): New switch case
+ for BFD_RELOC_THUMB_PCREL_BFCSEL.
+ (md_appdy_fix): Likewise
+ (tc_gen_reloc): Likewise.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF13.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entrie for bfl.
+ (do_t_v8_1_branch): New switch case for bfl.
+ (insns): New instruction for bfl.
+ * testsuite/gas/arm/armv8_1-m-bfl.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl.s: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF19.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
+ (do_t_v8_1_branch): New switch cases for bfx and bflx.
+ (insns): New instruction for bfx and bflx.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
+ * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (T16_32_TAB): New entries for bf.
+ (do_t_branch_future): New.
+ (insns): New instruction for bf.
+ * testsuite/gas/arm/armv8_1-m-bf.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
+ * testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
+ * testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case for
+ BFD_RELOC_ARM_THUMB_BF17.
+ (md_appdy_fix): Likewise.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.
+ (arm_it): Member reloc renamed relocs and updated to an array.
+ Rest: Replace all occurrences of reloc to relocs[0].
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-arm.c (md_pcrel_from_section): New switch case
+ for BFD_RELOC_THUMB_PCREL_BRANCH5.
+ (v8_1_branch_value_check): New function to check branch
+ offsets.
+ (md_appdy_fix): New switch case for
+ BFD_RELOC_THUMB_PCREL_BRANCH5.
+ (tc_gen_reloc): Likewise.
+
+2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
+ (armv8_1m_main_ext_table): New extension table.
+ (arm_archs): Use the new extension table.
+ * doc/c-arm.texi: Add missing arch and document new extensions.
+ * testsuite/gas/arm/armv8.1-m.main-fp.d: New.
+ * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
+ * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
+ Tag_CPU_arch build attribute value. Reindent.
+ (get_aeabi_cpu_arch_from_fset): Update assert.
+ (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
+ * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
+
+2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
+ default ASEs for i6400.
+ * doc/c-mips.texi (-march): Document i6500.
+ * testsuite/gas/mips/elf_mach_i6400.d: New test.
+ * testsuite/gas/mips/elf_mach_i6500.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
+
+ * config/tc-mips.c (mips_set_options) <init_ase>: New field.
+ (file_mips_opts, mips_opts) <init_ase>: Initialize new field.
+ (file_mips_check_options): Propagate initial ASE settings.
+ (mips_after_parse_args, parse_code_option): Track the initial
+ ASE settings for a CPU.
+ (s_mipsset): Restore the initial ASE settings when reverting
+ to the default arch.
+ * testsuite/gas/mips/elf_mach_p6600.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2019-04-12 John Darrington <john@darrington.wattle.id.au>
+
+ config/tc-s12z.h: Remove definition of macro TC_M68K
+
+2019-04-01 John Darrington <john@darrington.wattle.id.au>
+
+ config/tc-s12z.c: Use bfd_boolean where appropriate.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * testsuite/gas/xtensa/loop-relax-2.d: New test definition.
+ * testsuite/gas/xtensa/loop-relax.d: New test definition.
+ * testsuite/gas/xtensa/loop-relax.s: New test source.
+ * testsuite/gas/xtensa/text-section-literals-1a.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-2.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-2.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-2a.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-3.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-3.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-4.d: New test
+ definition.
+ * testsuite/gas/xtensa/text-section-literals-4.s: New test
+ source.
+ * testsuite/gas/xtensa/text-section-literals-4a.d: New test
+ definition.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * testsuite/gas/xtensa/all.exp: Remove all expect-based
+ tests and all explicit run_dump_test / run_list_test
+ invocations. Add run_dump_tests for all .d files in the
+ test subdirectory.
+ * testsuite/gas/xtensa/entry_align.d: New test definition.
+ * testsuite/gas/xtensa/entry_align.l: New test output.
+ * testsuite/gas/xtensa/entry_misalign.d: New test definition.
+ * testsuite/gas/xtensa/entry_misalign2.d: New test definition.
+ * testsuite/gas/xtensa/j_too_far.d: New test definition.
+ * testsuite/gas/xtensa/j_too_far.l: New test output.
+ * testsuite/gas/xtensa/loop_align.d: New test definition.
+ * testsuite/gas/xtensa/loop_misalign.d: New test definition.
+ * testsuite/gas/xtensa/trampoline-2.d: New test definition.
+ * testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
+ * testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
+ no effect.
+ (get_literal_pool_location): Only search for the literal pool
+ when auto litpools is used, otherwise take one recorded in the
+ tc_segment_info_data.
+ (xtensa_assign_litpool_addresses): New function.
+ (xtensa_move_literals): Don't duplicate 'literal pool location
+ required...' error message. Call xtensa_assign_litpool_addresses.
+
+2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
+ (xtensa_mark_literal_pool_location): Don't add fill frag to literal
+ section that records literal pool location.
+ (md_begin): Call xtensa_mark_literal_pool_location when text
+ section literals or auto litpools are used.
+ (xtensa_elf_section_change_hook): Call
+ xtensa_mark_literal_pool_location when text section literals or
+ auto litpools are used, there's no literal pool location defined
+ for the current section and it's not .init or .fini.
+ * testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
+ * testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
+ * testsuite/gas/xtensa/auto-litpools.d: Likewise.
+
+2019-04-11 Sudakshina Das <sudi.das@arm.com>
+
+ * config/tc-aarch64.c (process_omitted_operand): Add case for
+ AARCH64_OPND_Rt_SP.
+ (parse_operands): Likewise.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-04-11 Sudakshina Das <sudi.das@arm.com>
+
+ * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
+ * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+ * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+
+2019-04-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
+ * testsuite/gas/i386/solaris/solaris.exp: New driver.
+ * testsuite/gas/i386/solaris/reloc64.d,
+ testsuite/gas/i386/solaris/x86-64-jump.d,
+ testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
+ testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
+ testsuite/gas/i386/solaris/x86-64-nop-3.d,
+ testsuite/gas/i386/solaris/x86-64-nop-4.d,
+ testsuite/gas/i386/solaris/x86-64-nop-5.d,
+ testsuite/gas/i386/solaris/x86-64-relax-2.d,
+ testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
+ * testsuite/gas/i386/reloc64.d,
+ testsuite/gas/i386/x86-64-jump.d,
+ testsuite/gas/i386/x86-64-mpx-branch-1.d,
+ testsuite/gas/i386/x86-64-mpx-branch-2.d,
+ testsuite/gas/i386/x86-64-nop-3.d,
+ testsuite/gas/i386/x86-64-nop-4.d,
+ testsuite/gas/i386/x86-64-nop-5.d,
+ testsuite/gas/i386/x86-64-relax-2.d,
+ testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
+
+2019-04-10 Alan Modra <amodra@gmail.com>
+
+ * config/te-cloudabi.h: New file.
+ * config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI
+ rather than TARGET_OS to select cloudabi.
+ * config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.
+ * configure.tgt (*-*-cloudabi*): Set em=cloudabi.
+
+2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
+
+ * testsuite/gas/mips/mips.exp: Run hwr-names test.
+ * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
+ the SEL field.
+ * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
+
+2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (output_insn): Support
+ GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
+ * testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
+ * testsuite/gas/i386/property-2.d: Updated.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+
+2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.
+ * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*
+ check.
+
+2019-04-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.
+ * testsuite/gas/i386/property-2.d: New file.
+ * testsuite/gas/i386/property-2.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+
+2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add .avx512_bf16.
+ (cpu_noarch): Add noavx512_bf16.
+ * doc/c-i386.texi: Document avx512_bf16.
+ * testsuite/gas/i386/avx512_bf16.d: New file.
+ * testsuite/gas/i386/avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
+ * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Add BF16 related tests.
+
+2019-04-05 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/bc.s,
+ * testsuite/gas/ppc/bcat.d,
+ * testsuite/gas/ppc/bcaterr.d,
+ * testsuite/gas/ppc/bcaterr.l,
+ * testsuite/gas/ppc/bcy.d,
+ * testsuite/gas/ppc/bcyerr.d,
+ * testsuite/gas/ppc/bcyerr.l: New tests.
+ * testsuite/gas/ppc/ppc.exp: Run them.
+
+2019-04-05 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/476.d: Remove trailing spaces.
+ * testsuite/gas/ppc/a2.d: Likewise.
+ * testsuite/gas/ppc/booke.d: Likewise.
+ * testsuite/gas/ppc/booke_xcoff.d: Likewise.
+ * testsuite/gas/ppc/e500.d: Likewise.
+ * testsuite/gas/ppc/e500mc.d: Likewise.
+ * testsuite/gas/ppc/e6500.d: Likewise.
+ * testsuite/gas/ppc/htm.d: Likewise.
+ * testsuite/gas/ppc/power6.d: Likewise.
+ * testsuite/gas/ppc/power8.d: Likewise.
+ * testsuite/gas/ppc/power9.d: Likewise.
+ * testsuite/gas/ppc/vle.d: Likewise.
+
+2019-04-04 Peter Bergner <bergner@linux.ibm.com>
+
+ PR gas/24349
+ * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
+ btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
+ bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
+ bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
+ bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
+ bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
+ bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
+ bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
+ bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
+ beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
+ bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
+ buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
+ bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
+ bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
+ bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
+ bttarl+): Add tests of extended mnemonics.
+ * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
+ to expect new extended mnemonics.
+ * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
+ to not use illegal BO value. Use a more convenient BI value.
+ * testsuite/gas/ppc/a2.d: Update tests for new expect output.
+
+2019-04-03 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (convert_frag_immed): Drop
+ convert_frag_immed_finish_loop invocation.
+ (convert_frag_immed_finish_loop): Drop declaration and
+ definition.
+ * config/xtensa-relax.c (widen_spec_list): Replace loop
+ widening that uses addi/addmi with widening that uses l32r
+ and const16.
+
+2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (arm_ext_table): New struct type.
+ (arm_arch_option_table): Add new 'arm_ext_table' field.
+ (ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.
+ (armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,
+ armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,
+ armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,
+ armv85a_ext_table, armv8m_main_ext_table,
+ armv8r_ext_table): New architecture extension tables.
+ (ARM_ARCH_OPT): Add new default field.
+ (ARM_ARCH_OPT2): New macro.
+ (arm_archs): Extend some architectures with the new architecture
+ extension tables mentioned above.
+ (arm_extensions): Add DEPRECATED comment with instructions to
+ use new table.
+ (arm_parse_extension): Change to use new extension tables.
+ (arm_parse_cpu): Don't change existing behavior.
+ (arm_parse_arch): Change to use new extension tables.
+ * doc/c-arm.texi: Document new architecture extensions.
+ * testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new
+ extension option rather than -mfpu and change expected behaviour to
+ sane outputs.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.
+ * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.
+ * testsuite/gas/arm/armv8_2+rdma-ext.d: New.
+ * testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.
+ * testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.
+ * testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.
+ * testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.
+ * testsuite/gas/arm/armv8m.main+fp.d: New.
+ * testsuite/gas/arm/armv8m.main+fp.dp.d: New.
+ * testsuite/gas/arm/attr-ext-fpv5-d16.d: New.
+ * testsuite/gas/arm/attr-ext-fpv5.d: New.
+ * testsuite/gas/arm/attr-ext-idiv.d: New.
+ * testsuite/gas/arm/attr-ext-mp.d: New.
+ * testsuite/gas/arm/attr-ext-neon-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.
+ * testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.
+ * testsuite/gas/arm/attr-ext-sec.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv3xd.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.
+ * testsuite/gas/arm/attr-ext-vfpv4.d: New.
+ * testsuite/gas/arm/dotprod-mandatory-ext.d: New.
+ * testsuite/gas/arm/fpv5-d16.s: New.
+ * testsuite/gas/arm/fpv5-sp-d16.s: New.
+
+2019-03-28 Alan Modra <amodra@gmail.com>
+
+ PR 24390
+ * testsuite/gas/ppc/476.d: Update mtfsb*.
+ * testsuite/gas/ppc/a2.d: Likewise.
+
+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * emul.h (struct emulation): Delete strip_underscore.
+ * emul-target.h (emul_strip_underscore): Don't define.
+ (emul_struct_name): Update initialization.
+
+2019-03-21 Alan Modra <amodra@gmail.com>
+
+ * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
+ * config/tc-pdp11.c (md_apply_fix): Likewise.
+ * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
+ BFD_RELOC_16, and BFD_RELOC_64.
+ * testsuite/gas/all/gas.exp: Move target exclusions for forward
+ test, but not cr16, to..
+ * testsuite/gas/all/forward.d: ..here, with explanation. Remove
+ d10v, d30v, and pdp11 xfails.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Don't check AVX for
+ EVEX vector load/store optimization. Check both operands for
+ ZMM register. Update EVEX vector load/store opcode check.
+ Choose EVEX Disp8 over VEX Disp32.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/optimize-1a.d: Likewise.
+ * testsuite/gas/i386/optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/optimize-1.s: Add ZMM register load
+ test.
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24352
+ * config/tc-i386.c (optimize_encoding): Check only
+ cpu_arch_flags.bitfield.cpuavx512vl.
+ * testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
+ change.
+ * testsuite/gas/i386/x86-64-optimize-2b.d: New file.
+ * testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
+
+2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24359
+ * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
+ x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
+ Remove optimize-6c and x86-64-optimize-7c tests.
+ * testsuite/gas/i386/noavx-3.l: Updated.
+ * testsuite/gas/i386/noavx-4.d: Likewise.
+ * testsuite/gas/i386/noavx-5.d: Likewise.
+ * testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
+ * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
+ * testsuite/gas/i386/nosse-5.s: Likewise.
+ * testsuite/gas/i386/optimize-6a.d: Removed.
+ * testsuite/gas/i386/optimize-6c.d: Likewise.
+ * testsuite/gas/i386/optimize-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+ * testsuite/gas/i386/optimize-6a.l: New file.
+ * testsuite/gas/i386/optimize-6a.s: Likewise.
+ * testsuite/gas/i386/optimize-7.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
+
+2019-03-18 Alan Modra <amodra@gmail.com>
+
+ * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
+ * as.c (macro_expr): Likewise.
+ * macro.c (buffer_and_nest): Likewise.
+ * read.c (temp_ilp): Remove FIXME.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.
+ * testsuite/gas/i386/avx512bw-intel.d: Likewise.
+ * testsuite/gas/i386/avx512bw.d: Likewise.
+ * testsuite/gas/i386/avx512f-intel.d: Likewise.
+ * testsuite/gas/i386/avx512f.d: Likewise.
+ * testsuite/gas/i386/disp32.d: Likewise.
+ * testsuite/gas/i386/intel-regs.d: Likewise.
+ * testsuite/gas/i386/pseudos.d: Likewise.
+ * testsuite/gas/i386/x86-64-disp32.d: Likewise.
+ * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24348
+ * config/tc-i386.c (optimize_encoding): Encode 128-bit and
+ 256-bit EVEX vector register load/store instructions as VEX
+ vector register load/store instructions for -O1.
+ * doc/c-i386.texi: Update -O1 documentation.
+ * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
+ * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
+ load/store instructions.
+ * testsuite/gas/i386/optimize-2.s: Likewise.
+ * testsuite/gas/i386/optimize-3.s: Likewise.
+ * testsuite/gas/i386/optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
+ * testsuite/gas/i386/optimize-1.d: Updated.
+ * testsuite/gas/i386/optimize-2.d: Likewise.
+ * testsuite/gas/i386/optimize-3.d: Likewise.
+ * testsuite/gas/i386/optimize-4.d: Likewise.
+ * testsuite/gas/i386/optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
+ * testsuite/gas/i386/optimize-7.d: New file.
+ * testsuite/gas/i386/optimize-7.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
+
+2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
+ VEX/EVEX vector register clearing instructions with 128-bit VEX
+ vector register clearing instructions at -O1.
+ * doc/c-i386.texi: Update -O1 and -O2 documentation.
+ * testsuite/gas/i386/i386.exp: Run optimize-1a and
+ x86-64-optimize-2a.
+ * testsuite/gas/i386/optimize-1a.d: New file.
+ * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
+
+2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24353
+ * config/tc-i386.c: Include <limits.h> if it exists and try
+ including <sys/param.h> if we have it.
+ (INT_MAX): Define if not defined.
+ (md_parse_option): Set optimize to INT_MAX for -Os.
+ * testsuite/gas/i386/optimize-2.s: Add a test.
+ * testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
+ * testsuite/gas/i386/optimize-2.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
+
+2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24352
+ * config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
+ with 128-bit VEX encoding only when AVX is enabled and with
+ 128-bit EVEX encoding only when AVX512VL is enabled.
+ * testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
+ * testsuite/gas/i386/optimize-6.s: New file.
+ * testsuite/gas/i386/optimize-6a.d: Likewise.
+ * testsuite/gas/i386/optimize-6b.d: Likewise.
+ * testsuite/gas/i386/optimize-6c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
+ * testsuite/gas/i386/x86-64-optimize-2.d: Updated.
+
+2019-03-15 Li Hao <li.hao296@zte.com.cn>
+
+ PR 24308
+ * config/tc-i386.c (parse_insn): Check mnemp before using it to
+ determine if a suffix can be trimmed.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.
+ (out_debug_aranges, out_debug_info): Likewise.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * symbols.h (symbol_temp_new_now_octets): Declare.
+ (symbol_set_value_now_octets, symbol_octets_p): Declare.
+ * symbols.c (struct symbol_flags): New member sy_octets.
+ (symbol_temp_new_now_octets): New function.
+ (resolve_symbol_value): Return octets instead of bytes if
+ sy_octets is set.
+ (symbol_set_value_now_octets): New function.
+ (symbol_octets_p): New function.
+
+2019-03-13 Christian Eggers <ceggers@gmx.de>
+
+ * dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
+
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
projects / thirdparty / binutils-gdb.git / blobdiff