/* Instruction printing code for the ARM
- Copyright (C) 1994-2016 Free Software Foundation, Inc.
+ Copyright (C) 1994-2019 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modification by James G. Smith (jsmith@cygnus.co.uk)
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "opcode/arm.h"
#include "opintl.h"
#include "safe-ctype.h"
+#include "libiberty.h"
#include "floatformat.h"
/* FIXME: This shouldn't be done here. */
#include "coff/internal.h"
#include "libcoff.h"
+#include "bfd.h"
#include "elf-bfd.h"
#include "elf/internal.h"
#include "elf/arm.h"
#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
#endif
-#ifndef NUM_ELEM
-#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
-#endif
-
/* Cached mapping symbol state. */
enum map_type
{
/* The features to use when disassembling optional instructions. */
arm_feature_set features;
- /* Whether any mapping symbols are present in the provided symbol
- table. -1 if we do not know yet, otherwise 0 or 1. */
- int has_mapping_symbols;
-
/* Track the last type (although this doesn't seem to be useful) */
enum map_type last_type;
/* Tracking symbol table information */
int last_mapping_sym;
+
+ /* The end range of the current range being disassembled. */
+ bfd_vma last_stop_offset;
bfd_vma last_mapping_addr;
};
const char * assembler; /* How to disassemble this insn. */
};
+enum isa {
+ ANY,
+ T32,
+ ARM
+};
+
+
+/* Shared (between Arm and Thumb mode) opcode. */
+struct sopcode32
+{
+ enum isa isa; /* Execution mode instruction availability. */
+ arm_feature_set arch; /* Architecture defining this insn. */
+ unsigned long value; /* If arch is 0 then value is a sentinel. */
+ unsigned long mask; /* Recognise insn if (op & mask) == value. */
+ const char * assembler; /* How to disassemble this insn. */
+};
+
struct opcode16
{
arm_feature_set arch; /* Architecture defining this insn. */
UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
+ %C print vscclrm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
+ %<bitfield>V print as a NEON D or Q register
%<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
} opcode_sentinels;
#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
+#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
+#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
-static const struct opcode32 coprocessor_opcodes[] =
+static const struct sopcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
"mia%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
"miaph%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
- {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800120, 0x0f800ff0,
"wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000a0, 0x0f800ff0,
"wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_CORE_LOW (0),
+ {ANY, ARM_FEATURE_CORE_LOW (0),
SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions. */
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* Armv8.1-M Mainline instructions. */
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
+
+ /* ARMv8-M Mainline Security Extensions instructions. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
+
/* Register load/store. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* VFP Fused multiply add instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
/* FP v5. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
"mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
"cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
"mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
"mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
"mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
"mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
+ /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
+
+ /* Dot Product instructions in the space of coprocessor 13. */
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+
+ /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+
/* V5 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
"cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
"mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
"mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
+ /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
+ cp_num: bit <11:8> == 0b1001.
+ cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
+
+ /* ARMv8.3 javascript conversion instruction. */
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
+
+ {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
/* Neon opcode table: This does not encode the top byte -- that is
/* NEON fused multiply add instructions. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
- 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
- 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
"vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b30600, 0xffb30e10,
+ 0xf3bb0600, 0xffbf0e10,
"vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3b70600, 0xffbf0e10,
+ "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
- 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
- 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00e10, 0xfea00e90,
"vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0xf2a00c10, 0xfea00e90,
+ "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
/* Three registers of different lengths. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
+ {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
+ 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
"%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
/* V8.2 RAS extension instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xe320f010, 0xffffffff, "esb"},
/* V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0x0320f005, 0x0fffffff, "sevl"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+ /* Defined in V8 but is in NOP space so available to all arch. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
/* MP Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
+ /* Speculation Barriers. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
+
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
+ /* ARMv8.5-A instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
+
/* ARM V6K NOP hints. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f001, 0x0fffffff, "yield%c"},
0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
{
/* Thumb instructions. */
+ /* ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
+
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
%a print the address of a plain load/store
%w print the width and signedness of a core load/store
%m print register mask for ldm/stm
+ %n print register mask for clrm
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
+ %G print a fallback offset for Branch Future instructions
+ %W print an offset for BF instruction
+ %Y print an offset for BFL instruction
+ %Z print an offset for BFCSEL instruction
+ %Q print an offset for Low Overhead Loop instructions
+ %P print an offset for Low Overhead Loop end instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
- %<bitfield>S as %<>R but r13 is UNPREDICTABLE
+ %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
- /* V8-M instructions. */
+ /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
+ instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf02fc001, 0xfffff001, "le\t%P"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
+
+ /* ARMv8-M and ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
/* ARM V8.2 RAS extension instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xf3af8010, 0xffffffff, "esb"},
/* V8 instructions. */
/* CRC32 instructions. */
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
+ 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
+ 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
+ 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
+ 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
+ 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
{ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
- 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
+ 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
+
+ /* Speculation Barriers. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
/* Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
+ /* ARMv8.5-A instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
+
/* Instructions defined in the basic V6T2 set. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
static const arm_regname regnames[] =
{
- { "raw" , "Select raw register names",
+ { "reg-names-raw", N_("Select raw register names"),
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
- { "gcc", "Select register names used by GCC",
+ { "reg-names-gcc", N_("Select register names used by GCC"),
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "std", "Select register names used in ARM's ISA documentation",
+ { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
- { "apcs", "Select register names used in the APCS",
+ { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
+ { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
+ { "reg-names-apcs", N_("Select register names used in the APCS"),
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "atpcs", "Select register names used in the ATPCS",
+ { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
- { "special-atpcs", "Select special register names used in the ATPCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
+ { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
};
static const char *const iwmmxt_wwnames[] =
/* Default to GCC register name set. */
static unsigned int regname_selected = 1;
-#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
+#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
#define arm_regnames regnames[regname_selected].reg_names
static bfd_boolean force_thumb = FALSE;
\f
/* Functions. */
-int
-get_arm_regname_num_options (void)
-{
- return NUM_ARM_REGNAMES;
-}
-
-int
-set_arm_regname_option (int option)
-{
- int old = regname_selected;
- regname_selected = option;
- return old;
-}
-
-int
-get_arm_regnames (int option,
- const char **setname,
- const char **setdescription,
- const char *const **register_names)
-{
- *setname = regnames[option].name;
- *setdescription = regnames[option].description;
- *register_names = regnames[option].reg_names;
- return 16;
-}
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
Returns pointer to following character of the format string and
long given,
bfd_boolean thumb)
{
- const struct opcode32 *insn;
+ const struct sopcode32 *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
unsigned long mask;
unsigned long value = 0;
int cond;
+ int cp_num;
struct arm_private_data *private_data = info->private_data;
arm_feature_set allowed_arches = ARM_ARCH_NONE;
- ARM_FEATURE_COPY (allowed_arches, private_data->features);
+ allowed_arches = private_data->features;
for (insn = coprocessor_opcodes; insn->assembler; insn++)
{
continue;
case SENTINEL_GENERIC_START:
- ARM_FEATURE_COPY (allowed_arches, private_data->features);
+ allowed_arches = private_data->features;
continue;
default:
mask = insn->mask;
value = insn->value;
+ cp_num = (given >> 8) & 0xf;
+
if (thumb)
{
/* The high 4 bits are 0xe for Arm conditional instructions, and
}
}
+ if ((insn->isa == T32 && !thumb)
+ || (insn->isa == ARM && thumb))
+ continue;
+
if ((given & mask) != value)
continue;
if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
continue;
+ if (insn->value == 0xfe000010 /* mcr2 */
+ || insn->value == 0xfe100010 /* mrc2 */
+ || insn->value == 0xfc100000 /* ldc2 */
+ || insn->value == 0xfc000000) /* stc2 */
+ {
+ if (cp_num == 9 || cp_num == 10 || cp_num == 11)
+ is_unpredictable = TRUE;
+ }
+ else if (insn->value == 0x0e000000 /* cdp */
+ || insn->value == 0xfe000000 /* cdp2 */
+ || insn->value == 0x0e000010 /* mcr */
+ || insn->value == 0x0e100010 /* mrc */
+ || insn->value == 0x0c100000 /* ldc */
+ || insn->value == 0x0c000000) /* stc */
+ {
+ /* Floating-point instructions. */
+ if (cp_num == 9 || cp_num == 10 || cp_num == 11)
+ continue;
+ }
+
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
case 'A':
{
int rn = (given >> 16) & 0xf;
- bfd_vma offset = given & 0xff;
+ bfd_vma offset = given & 0xff;
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
{
/* Not unindexed. The offset is scaled. */
- offset = offset * 4;
+ if (cp_num == 9)
+ /* vldr.16/vstr.16 will shift the address
+ left by 1 bit only. */
+ offset = offset * 2;
+ else
+ offset = offset * 4;
+
if (NEGATIVE_BIT_SET)
offset = - offset;
if (rn != 15)
info->print_address_func (offset + pc
+ info->bytes_per_chunk * 2
- (pc & 3),
- info);
+ info);
}
}
break;
}
break;
+ case 'C':
+ {
+ bfd_boolean single = ((given >> 8) & 1) == 0;
+ char reg_prefix = single ? 's' : 'd';
+ int Dreg = (given >> 22) & 0x1;
+ int Vdreg = (given >> 12) & 0xf;
+ int reg = single ? ((Vdreg << 1) | Dreg)
+ : ((Dreg << 4) | Vdreg);
+ int num = (given >> (single ? 0 : 1)) & 0x7f;
+ int maxreg = single ? 31 : 15;
+ int topreg = reg + num - 1;
+
+ if (!num)
+ func (stream, "{VPR}");
+ else if (num == 1)
+ func (stream, "{%c%d, VPR}", reg_prefix, reg);
+ else if (topreg > maxreg)
+ func (stream, "{%c%d-<overflow reg d%d, VPR}",
+ reg_prefix, reg, single ? topreg >> 1 : topreg);
+ else
+ func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
+ reg_prefix, topreg);
+ }
+ break;
+
case 'u':
if (cond != COND_UNCOND)
is_unpredictable = TRUE;
/* Fall through. */
case 'c':
+ if (cond != COND_UNCOND && cp_num == 9)
+ is_unpredictable = TRUE;
+
func (stream, "%s", arm_conditional[cond]);
break;
}
func (stream, "%s", arm_regnames[value]);
break;
+ case 'V':
+ if (given & (1 << 6))
+ goto Q;
+ /* FALLTHROUGH */
case 'D':
func (stream, "d%ld", value);
break;
case 'Q':
+ Q:
if (value & 1)
func (stream, "<illegal reg q%ld.5>", value >> 1);
else
default:
abort ();
}
- break;
-
- case 'y':
- case 'z':
- {
- int single = *c++ == 'y';
- int regno;
+ }
+ break;
- switch (*c)
- {
- case '4': /* Sm pair */
- case '0': /* Sm, Dm */
- regno = given & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 5) & 1;
- }
- else
- regno += ((given >> 5) & 1) << 4;
- break;
+ case 'y':
+ case 'z':
+ {
+ int single = *c++ == 'y';
+ int regno;
- case '1': /* Sd, Dd */
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
+ switch (*c)
+ {
+ case '4': /* Sm pair */
+ case '0': /* Sm, Dm */
+ regno = given & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 5) & 1;
+ }
+ else
+ regno += ((given >> 5) & 1) << 4;
+ break;
- case '2': /* Sn, Dn */
- regno = (given >> 16) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 7) & 1;
- }
- else
- regno += ((given >> 7) & 1) << 4;
- break;
+ case '1': /* Sd, Dd */
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ else
+ regno += ((given >> 22) & 1) << 4;
+ break;
- case '3': /* List */
- func (stream, "{");
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
+ case '2': /* Sn, Dn */
+ regno = (given >> 16) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 7) & 1;
+ }
+ else
+ regno += ((given >> 7) & 1) << 4;
+ break;
- default:
- abort ();
- }
+ case '3': /* List */
+ func (stream, "{");
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ else
+ regno += ((given >> 22) & 1) << 4;
+ break;
- func (stream, "%c%d", single ? 's' : 'd', regno);
+ default:
+ abort ();
+ }
- if (*c == '3')
- {
- int count = given & 0xff;
+ func (stream, "%c%d", single ? 's' : 'd', regno);
- if (single == 0)
- count >>= 1;
+ if (*c == '3')
+ {
+ int count = given & 0xff;
- if (--count)
- {
- func (stream, "-%c%d",
- single ? 's' : 'd',
- regno + count);
- }
+ if (single == 0)
+ count >>= 1;
- func (stream, "}");
- }
- else if (*c == '4')
- func (stream, ", %c%d", single ? 's' : 'd',
- regno + 1);
- }
- break;
+ if (--count)
+ {
+ func (stream, "-%c%d",
+ single ? 's' : 'd',
+ regno + count);
+ }
- case 'L':
- switch (given & 0x00400100)
- {
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
- default:
- break;
+ func (stream, "}");
}
- break;
+ else if (*c == '4')
+ func (stream, ", %c%d", single ? 's' : 'd',
+ regno + 1);
+ }
+ break;
- case 'Z':
+ case 'L':
+ switch (given & 0x00400100)
{
- /* given (20, 23) | given (0, 3) */
- value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", (int) value);
+ case 0x00000000: func (stream, "b"); break;
+ case 0x00400000: func (stream, "h"); break;
+ case 0x00000100: func (stream, "w"); break;
+ case 0x00400100: func (stream, "d"); break;
+ default:
+ break;
}
- break;
+ break;
- case 'l':
- /* This is like the 'A' operator, except that if
- the width field "M" is zero, then the offset is
- *not* multiplied by four. */
- {
- int offset = given & 0xff;
- int multiplier = (given & 0x00000100) ? 4 : 1;
+ case 'Z':
+ {
+ /* given (20, 23) | given (0, 3) */
+ value = ((given >> 16) & 0xf0) | (given & 0xf);
+ func (stream, "%d", (int) value);
+ }
+ break;
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+ case 'l':
+ /* This is like the 'A' operator, except that if
+ the width field "M" is zero, then the offset is
+ *not* multiplied by four. */
+ {
+ int offset = given & 0xff;
+ int multiplier = (given & 0x00000100) ? 4 : 1;
- if (multiplier > 1)
- {
- value_in_comment = offset * multiplier;
- if (NEGATIVE_BIT_SET)
- value_in_comment = - value_in_comment;
- }
+ func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
- if (offset)
- {
- if (PRE_BIT_SET)
- func (stream, ", #%s%d]%s",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier,
- WRITEBACK_BIT_SET ? "!" : "");
- else
- func (stream, "], #%s%d",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier);
- }
- else
- func (stream, "]");
- }
- break;
+ if (multiplier > 1)
+ {
+ value_in_comment = offset * multiplier;
+ if (NEGATIVE_BIT_SET)
+ value_in_comment = - value_in_comment;
+ }
- case 'r':
- {
- int imm4 = (given >> 4) & 0xf;
- int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
- int ubit = ! NEGATIVE_BIT_SET;
- const char *rm = arm_regnames [given & 0xf];
- const char *rn = arm_regnames [(given >> 16) & 0xf];
+ if (offset)
+ {
+ if (PRE_BIT_SET)
+ func (stream, ", #%s%d]%s",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier,
+ WRITEBACK_BIT_SET ? "!" : "");
+ else
+ func (stream, "], #%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ }
+ else
+ func (stream, "]");
+ }
+ break;
- switch (puw_bits)
- {
- case 1:
- case 3:
- func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4)
- func (stream, ", lsl #%d", imm4);
- break;
+ case 'r':
+ {
+ int imm4 = (given >> 4) & 0xf;
+ int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
+ int ubit = ! NEGATIVE_BIT_SET;
+ const char *rm = arm_regnames [given & 0xf];
+ const char *rn = arm_regnames [(given >> 16) & 0xf];
- case 4:
- case 5:
- case 6:
- case 7:
- func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4 > 0)
- func (stream, ", lsl #%d", imm4);
- func (stream, "]");
- if (puw_bits == 5 || puw_bits == 7)
- func (stream, "!");
- break;
+ switch (puw_bits)
+ {
+ case 1:
+ case 3:
+ func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
+ if (imm4)
+ func (stream, ", lsl #%d", imm4);
+ break;
- default:
- func (stream, "INVALID");
- }
- }
- break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
+ if (imm4 > 0)
+ func (stream, ", lsl #%d", imm4);
+ func (stream, "]");
+ if (puw_bits == 5 || puw_bits == 7)
+ func (stream, "!");
+ break;
- case 'i':
- {
- long imm5;
- imm5 = ((given & 0x100) >> 4) | (given & 0xf);
- func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
- }
- break;
+ default:
+ func (stream, "INVALID");
+ }
+ }
+ break;
- default:
- abort ();
+ case 'i':
+ {
+ long imm5;
+ imm5 = ((given & 0x100) >> 4) | (given & 0xf);
+ func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
}
+ break;
+
+ default:
+ abort ();
}
}
else
default:
abort ();
}
- break;
-
- default:
- abort ();
}
+ break;
+
+ default:
+ abort ();
}
}
else
case 'S':
allow_unpredictable = TRUE;
+ /* Fall through. */
case 's':
if ((given & 0x004f0000) == 0x004f0000)
{
default:
abort ();
}
- break;
-
- case 'e':
- {
- int imm;
+ }
+ break;
- imm = (given & 0xf) | ((given & 0xfff00) >> 4);
- func (stream, "%d", imm);
- value_in_comment = imm;
- }
- break;
+ case 'e':
+ {
+ int imm;
- case 'E':
- /* LSB and WIDTH fields of BFI or BFC. The machine-
- language instruction encodes LSB and MSB. */
- {
- long msb = (given & 0x001f0000) >> 16;
- long lsb = (given & 0x00000f80) >> 7;
- long w = msb - lsb + 1;
+ imm = (given & 0xf) | ((given & 0xfff00) >> 4);
+ func (stream, "%d", imm);
+ value_in_comment = imm;
+ }
+ break;
- if (w > 0)
- func (stream, "#%lu, #%lu", lsb, w);
- else
- func (stream, "(invalid: %lu:%lu)", lsb, msb);
- }
- break;
+ case 'E':
+ /* LSB and WIDTH fields of BFI or BFC. The machine-
+ language instruction encodes LSB and MSB. */
+ {
+ long msb = (given & 0x001f0000) >> 16;
+ long lsb = (given & 0x00000f80) >> 7;
+ long w = msb - lsb + 1;
- case 'R':
- /* Get the PSR/banked register name. */
- {
- const char * name;
- unsigned sysm = (given & 0x004f0000) >> 16;
+ if (w > 0)
+ func (stream, "#%lu, #%lu", lsb, w);
+ else
+ func (stream, "(invalid: %lu:%lu)", lsb, msb);
+ }
+ break;
- sysm |= (given & 0x300) >> 4;
- name = banked_regname (sysm);
+ case 'R':
+ /* Get the PSR/banked register name. */
+ {
+ const char * name;
+ unsigned sysm = (given & 0x004f0000) >> 16;
- if (name != NULL)
- func (stream, "%s", name);
- else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
- }
- break;
+ sysm |= (given & 0x300) >> 4;
+ name = banked_regname (sysm);
- case 'V':
- /* 16-bit unsigned immediate from a MOVT or MOVW
- instruction, encoded in bits 0:11 and 15:19. */
- {
- long hi = (given & 0x000f0000) >> 4;
- long lo = (given & 0x00000fff);
- long imm16 = hi | lo;
+ if (name != NULL)
+ func (stream, "%s", name);
+ else
+ func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ }
+ break;
- func (stream, "#%lu", imm16);
- value_in_comment = imm16;
- }
- break;
+ case 'V':
+ /* 16-bit unsigned immediate from a MOVT or MOVW
+ instruction, encoded in bits 0:11 and 15:19. */
+ {
+ long hi = (given & 0x000f0000) >> 4;
+ long lo = (given & 0x00000fff);
+ long imm16 = hi | lo;
- default:
- abort ();
+ func (stream, "#%lu", imm16);
+ value_in_comment = imm16;
}
+ break;
+
+ default:
+ abort ();
}
}
else
return;
}
}
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ return;
}
/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
mask. */
if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
func (stream, "!");
- break;
+ break;
case 'b':
/* Print ARM V6T2 CZB address: pc+4+6 bits. */
}
/* No match. */
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
+ return;
}
/* Return the name of an V7M special register. */
{
switch (regno)
{
- case 0: return "APSR";
- case 1: return "IAPSR";
- case 2: return "EAPSR";
- case 3: return "PSR";
- case 5: return "IPSR";
- case 6: return "EPSR";
- case 7: return "IEPSR";
- case 8: return "MSP";
- case 9: return "PSP";
- case 16: return "PRIMASK";
- case 17: return "BASEPRI";
- case 18: return "BASEPRI_MAX";
- case 19: return "FAULTMASK";
- case 20: return "CONTROL";
+ case 0x0: return "APSR";
+ case 0x1: return "IAPSR";
+ case 0x2: return "EAPSR";
+ case 0x3: return "PSR";
+ case 0x5: return "IPSR";
+ case 0x6: return "EPSR";
+ case 0x7: return "IEPSR";
+ case 0x8: return "MSP";
+ case 0x9: return "PSP";
+ case 0xa: return "MSPLIM";
+ case 0xb: return "PSPLIM";
+ case 0x10: return "PRIMASK";
+ case 0x11: return "BASEPRI";
+ case 0x12: return "BASEPRI_MAX";
+ case 0x13: return "FAULTMASK";
+ case 0x14: return "CONTROL";
+ case 0x88: return "MSP_NS";
+ case 0x89: return "PSP_NS";
+ case 0x8a: return "MSPLIM_NS";
+ case 0x8b: return "PSPLIM_NS";
+ case 0x90: return "PRIMASK_NS";
+ case 0x91: return "BASEPRI_NS";
+ case 0x93: return "FAULTMASK_NS";
+ case 0x94: return "CONTROL_NS";
+ case 0x98: return "SP_NS";
default: return "<unknown>";
}
}
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
+ bfd_boolean is_clrm = FALSE;
bfd_boolean is_unpredictable = FALSE;
signed long value_in_comment = 0;
const char *c = insn->assembler;
if (off || !U)
{
func (stream, ", #%c%u", U ? '+' : '-', off * 4);
- value_in_comment = off * 4 * U ? 1 : -1;
+ value_in_comment = off * 4 * (U ? 1 : -1);
}
func (stream, "]");
if (W)
if (W)
{
func (stream, "#%c%u", U ? '+' : '-', off * 4);
- value_in_comment = off * 4 * U ? 1 : -1;
+ value_in_comment = off * 4 * (U ? 1 : -1);
}
else
{
}
break;
+ case 'n':
+ is_clrm = TRUE;
+ /* Fall through. */
case 'm':
{
int started = 0;
if (started)
func (stream, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ if (is_clrm && reg == 13)
+ func (stream, "(invalid: %s)", arm_regnames[reg]);
+ else if (is_clrm && reg == 15)
+ func (stream, "%s", "APSR");
+ else
+ func (stream, "%s", arm_regnames[reg]);
}
func (stream, "}");
}
}
break;
+ case 'G':
+ {
+ unsigned int boff = (((given & 0x07800000) >> 23) << 1);
+ func (stream, "%x", boff);
+ }
+ break;
+
+ case 'W':
+ {
+ unsigned int immA = (given & 0x001f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
+ case 'Y':
+ {
+ unsigned int immA = (given & 0x007f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
+ case 'Z':
+ {
+ unsigned int immA = (given & 0x00010000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+
+ unsigned int T = (given & 0x00020000u) >> 17;
+ unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
+ unsigned int boffset = (T == 1) ? 4 : 2;
+ func (stream, ", ");
+ func (stream, "%x", endoffset + boffset);
+ }
+ break;
+
+ case 'Q':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 + imm32, info);
+ }
+ break;
+
+ case 'P':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 - imm32, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
}
/* No match. */
- abort ();
+ func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
+ return;
}
/* Print data bytes on INFO->STREAM. */
return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
}
-/* Parse an individual disassembler option. */
+/* Parse the string of disassembler options. */
-void
-parse_arm_disassembler_option (char *option)
+static void
+parse_arm_disassembler_options (const char *options)
{
- if (option == NULL)
- return;
+ const char *opt;
- if (CONST_STRNEQ (option, "reg-names-"))
+ FOR_EACH_DISASSEMBLER_OPTION (opt, options)
{
- int i;
-
- option += 10;
-
- for (i = NUM_ARM_REGNAMES; i--;)
- if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
- {
- regname_selected = i;
- break;
- }
+ if (CONST_STRNEQ (opt, "reg-names-"))
+ {
+ unsigned int i;
+ for (i = 0; i < NUM_ARM_OPTIONS; i++)
+ if (disassembler_options_cmp (opt, regnames[i].name) == 0)
+ {
+ regname_selected = i;
+ break;
+ }
- if (i < 0)
- /* XXX - should break 'option' at following delimiter. */
- fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
+ if (i >= NUM_ARM_OPTIONS)
+ /* xgettext: c-format */
+ opcodes_error_handler (_("unrecognised register name set: %s"),
+ opt);
+ }
+ else if (CONST_STRNEQ (opt, "force-thumb"))
+ force_thumb = 1;
+ else if (CONST_STRNEQ (opt, "no-force-thumb"))
+ force_thumb = 0;
+ else
+ /* xgettext: c-format */
+ opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
}
- else if (CONST_STRNEQ (option, "force-thumb"))
- force_thumb = 1;
- else if (CONST_STRNEQ (option, "no-force-thumb"))
- force_thumb = 0;
- else
- /* XXX - should break 'option' at following delimiter. */
- fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
return;
}
-/* Parse the string of disassembler options, spliting it at whitespaces
- or commas. (Whitespace separators supported for backwards compatibility). */
-
-static void
-parse_disassembler_options (char *options)
-{
- if (options == NULL)
- return;
-
- while (*options)
- {
- parse_arm_disassembler_option (options);
-
- /* Skip forward to next seperator. */
- while ((*options) && (! ISSPACE (*options)) && (*options != ','))
- ++ options;
- /* Skip forward past seperators. */
- while (ISSPACE (*options) || (*options == ','))
- ++ options;
- }
-}
+static bfd_boolean
+mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
+ enum map_type *map_symbol);
/* Search back through the insn stream to determine if this instruction is
conditionally executed. */
}
if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
{
- /* This could be an IT instruction. */
- seen_it = insn;
- it_count = count >> 1;
+ enum map_type type = MAP_ARM;
+ bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
+
+ if (!found || (found && type == MAP_THUMB))
+ {
+ /* This could be an IT instruction. */
+ seen_it = insn;
+ it_count = count >> 1;
+ }
}
if ((insn & 0xf800) >= 0xe800)
count++;
/* If the symbol has function type then use that. */
if (type == STT_FUNC || type == STT_GNU_IFUNC)
{
- if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
+ if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
+ == ST_BRANCH_TO_THUMB)
*map_type = MAP_THUMB;
else
*map_type = MAP_ARM;
return FALSE;
}
+/* Search the mapping symbol state for instruction at pc. This is only
+ applicable for elf target.
+
+ There is an assumption Here, info->private_data contains the correct AND
+ up-to-date information about current scan process. The information will be
+ used to speed this search process.
+
+ Return TRUE if the mapping state can be determined, and map_symbol
+ will be updated accordingly. Otherwise, return FALSE. */
+
+static bfd_boolean
+mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
+ enum map_type *map_symbol)
+{
+ bfd_vma addr, section_vma = 0;
+ int n, last_sym = -1;
+ bfd_boolean found = FALSE;
+ bfd_boolean can_use_search_opt_p = FALSE;
+
+ /* Default to DATA. A text section is required by the ABI to contain an
+ INSN mapping symbol at the start. A data section has no such
+ requirement, hence if no mapping symbol is found the section must
+ contain only data. This however isn't very useful if the user has
+ fully stripped the binaries. If this is the case use the section
+ attributes to determine the default. If we have no section default to
+ INSN as well, as we may be disassembling some raw bytes on a baremetal
+ HEX file or similar. */
+ enum map_type type = MAP_DATA;
+ if ((info->section && info->section->flags & SEC_CODE) || !info->section)
+ type = MAP_ARM;
+ struct arm_private_data *private_data;
+
+ if (info->private_data == NULL
+ || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
+ return FALSE;
+
+ private_data = info->private_data;
+
+ /* First, look for mapping symbols. */
+ if (info->symtab_size != 0)
+ {
+ if (pc <= private_data->last_mapping_addr)
+ private_data->last_mapping_sym = -1;
+
+ /* Start scanning at the start of the function, or wherever
+ we finished last time. */
+ n = info->symtab_pos + 1;
+
+ /* If the last stop offset is different from the current one it means we
+ are disassembling a different glob of bytes. As such the optimization
+ would not be safe and we should start over. */
+ can_use_search_opt_p
+ = private_data->last_mapping_sym >= 0
+ && info->stop_offset == private_data->last_stop_offset;
+
+ if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
+ n = private_data->last_mapping_sym;
+
+ /* Look down while we haven't passed the location being disassembled.
+ The reason for this is that there's no defined order between a symbol
+ and an mapping symbol that may be at the same address. We may have to
+ look at least one position ahead. */
+ for (; n < info->symtab_size; n++)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr > pc)
+ break;
+ if (get_map_sym_type (info, n, &type))
+ {
+ last_sym = n;
+ found = TRUE;
+ }
+ }
+
+ if (!found)
+ {
+ n = info->symtab_pos;
+ if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
+ n = private_data->last_mapping_sym;
+
+ /* No mapping symbol found at this address. Look backwards
+ for a preceeding one, but don't go pass the section start
+ otherwise a data section with no mapping symbol can pick up
+ a text mapping symbol of a preceeding section. The documentation
+ says section can be NULL, in which case we will seek up all the
+ way to the top. */
+ if (info->section)
+ section_vma = info->section->vma;
+
+ for (; n >= 0; n--)
+ {
+ addr = bfd_asymbol_value (info->symtab[n]);
+ if (addr < section_vma)
+ break;
+
+ if (get_map_sym_type (info, n, &type))
+ {
+ last_sym = n;
+ found = TRUE;
+ break;
+ }
+ }
+ }
+ }
+
+ /* If no mapping symbol was found, try looking up without a mapping
+ symbol. This is done by walking up from the current PC to the nearest
+ symbol. We don't actually have to loop here since symtab_pos will
+ contain the nearest symbol already. */
+ if (!found)
+ {
+ n = info->symtab_pos;
+ if (n >= 0 && get_sym_code_type (info, n, &type))
+ {
+ last_sym = n;
+ found = TRUE;
+ }
+ }
+
+ private_data->last_mapping_sym = last_sym;
+ private_data->last_type = type;
+ private_data->last_stop_offset = info->stop_offset;
+
+ *map_symbol = type;
+ return found;
+}
+
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
of the supplied arm_feature_set structure with bitmasks indicating
- the support base architectures and coprocessor extensions.
+ the supported base architectures and coprocessor extensions.
FIXME: This could more efficiently implemented as a constant array,
although it would also be less robust. */
select_arm_features (unsigned long mach,
arm_feature_set * features)
{
+ arm_feature_set arch_fset;
+ const arm_feature_set fpu_any = FPU_ANY;
+
#undef ARM_SET_FEATURES
#define ARM_SET_FEATURES(FSET) \
{ \
const arm_feature_set fset = FSET; \
- arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
- ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
+ arch_fset = fset; \
}
+ /* When several architecture versions share the same bfd_mach_arm_XXX value
+ the most featureful is chosen. */
switch (mach)
{
- case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
- case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
- case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
- case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
- case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
- case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
- case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
- case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
- case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
- case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
+ case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
+ case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
+ case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
+ case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
+ case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
+ case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
+ case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
+ case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
+ case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
+ case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
case bfd_mach_arm_ep9312:
- ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
- ARM_CEXT_MAVERICK | FPU_MAVERICK));
+ ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
+ ARM_CEXT_MAVERICK | FPU_MAVERICK));
break;
- case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
- case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
- /* If the machine type is unknown allow all
- architecture types and all extensions. */
- case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
+ case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
+ case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
+ case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
+ case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
+ case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
+ case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
+ case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
+ case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
+ case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
+ case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
+ case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
+ case bfd_mach_arm_8:
+ {
+ /* Add bits for extensions that Armv8.5-A recognizes. */
+ arm_feature_set armv8_5_ext_fset
+ = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
+ ARM_SET_FEATURES (ARM_ARCH_V8_5A);
+ ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
+ break;
+ }
+ case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
+ case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
+ case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
+ case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
+ /* If the machine type is unknown allow all architecture types and all
+ extensions. */
+ case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
default:
abort ();
}
-
#undef ARM_SET_FEATURES
+
+ /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
+ and thus on bfd_mach_arm_XXX value. Therefore for a given
+ bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
+ ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
}
if (info->disassembler_options)
{
- parse_disassembler_options (info->disassembler_options);
+ parse_arm_disassembler_options (info->disassembler_options);
/* To avoid repeated parsing of these options, we remove them here. */
info->disassembler_options = NULL;
during disassembly.... */
select_arm_features (info->mach, & private.features);
- private.has_mapping_symbols = -1;
private.last_mapping_sym = -1;
private.last_mapping_addr = 0;
+ private.last_stop_offset = 0;
info->private_data = & private;
}
&& bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
{
bfd_vma addr;
- int n, start;
+ int n;
int last_sym = -1;
enum map_type type = MAP_ARM;
- /* Start scanning at the start of the function, or wherever
- we finished last time. */
- /* PR 14006. When the address is 0 we are either at the start of the
- very first function, or else the first function in a new, unlinked
- executable section (eg because uf -ffunction-sections). Either way
- start scanning from the beginning of the symbol table, not where we
- left off last time. */
- if (pc == 0)
- start = 0;
- else
- {
- start = info->symtab_pos + 1;
- if (start < private_data->last_mapping_sym)
- start = private_data->last_mapping_sym;
- }
- found = FALSE;
-
- /* First, look for mapping symbols. */
- if (private_data->has_mapping_symbols != 0)
- {
- /* Scan up to the location being disassembled. */
- for (n = start; n < info->symtab_size; n++)
- {
- addr = bfd_asymbol_value (info->symtab[n]);
- if (addr > pc)
- break;
- if (get_map_sym_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- }
- }
-
- if (!found)
- {
- /* No mapping symbol found at this address. Look backwards
- for a preceding one. */
- for (n = start - 1; n >= 0; n--)
- {
- if (get_map_sym_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- break;
- }
- }
- }
-
- if (found)
- private_data->has_mapping_symbols = 1;
-
- /* No mapping symbols were found. A leading $d may be
- omitted for sections which start with data; but for
- compatibility with legacy and stripped binaries, only
- assume the leading $d if there is at least one mapping
- symbol in the file. */
- if (!found && private_data->has_mapping_symbols == -1)
- {
- /* Look for mapping symbols, in any section. */
- for (n = 0; n < info->symtab_size; n++)
- if (is_mapping_symbol (info, n, &type))
- {
- private_data->has_mapping_symbols = 1;
- break;
- }
- if (private_data->has_mapping_symbols == -1)
- private_data->has_mapping_symbols = 0;
- }
-
- if (!found && private_data->has_mapping_symbols == 1)
- {
- type = MAP_DATA;
- found = TRUE;
- }
- }
+ found = mapping_symbol_for_insn (pc, info, &type);
+ last_sym = private_data->last_mapping_sym;
- /* Next search for function symbols to separate ARM from Thumb
- in binaries without mapping symbols. */
- if (!found)
- {
- /* Scan up to the location being disassembled. */
- for (n = start; n < info->symtab_size; n++)
- {
- addr = bfd_asymbol_value (info->symtab[n]);
- if (addr > pc)
- break;
- if (get_sym_code_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- }
- }
-
- if (!found)
- {
- /* No mapping symbol found at this address. Look backwards
- for a preceding one. */
- for (n = start - 1; n >= 0; n--)
- {
- if (get_sym_code_type (info, n, &type))
- {
- last_sym = n;
- found = TRUE;
- break;
- }
- }
- }
- }
-
- private_data->last_mapping_sym = last_sym;
- private_data->last_type = type;
is_thumb = (private_data->last_type == MAP_THUMB);
is_data = (private_data->last_type == MAP_DATA);
es = *(elf_symbol_type **)(info->symbols);
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
- is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
- == ST_BRANCH_TO_THUMB)
- || type == STT_ARM_16BIT);
+ is_thumb =
+ ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
+ == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
}
else if (bfd_asymbol_flavour (*info->symbols)
== bfd_target_mach_o_flavour)
return print_insn (pc, info, TRUE);
}
+const disasm_options_and_args_t *
+disassembler_options_arm (void)
+{
+ static disasm_options_and_args_t *opts_and_args;
+
+ if (opts_and_args == NULL)
+ {
+ disasm_options_t *opts;
+ unsigned int i;
+
+ opts_and_args = XNEW (disasm_options_and_args_t);
+ opts_and_args->args = NULL;
+
+ opts = &opts_and_args->options;
+ opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
+ opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
+ opts->arg = NULL;
+ for (i = 0; i < NUM_ARM_OPTIONS; i++)
+ {
+ opts->name[i] = regnames[i].name;
+ if (regnames[i].description != NULL)
+ opts->description[i] = _(regnames[i].description);
+ else
+ opts->description[i] = NULL;
+ }
+ /* The array we return must be NULL terminated. */
+ opts->name[i] = NULL;
+ opts->description[i] = NULL;
+ }
+
+ return opts_and_args;
+}
+
void
print_arm_disassembler_options (FILE *stream)
{
- int i;
-
+ unsigned int i, max_len = 0;
fprintf (stream, _("\n\
The following ARM specific disassembler options are supported for use with\n\
the -M switch:\n"));
- for (i = NUM_ARM_REGNAMES; i--;)
- fprintf (stream, " reg-names-%s %*c%s\n",
- regnames[i].name,
- (int)(14 - strlen (regnames[i].name)), ' ',
- regnames[i].description);
+ for (i = 0; i < NUM_ARM_OPTIONS; i++)
+ {
+ unsigned int len = strlen (regnames[i].name);
+ if (max_len < len)
+ max_len = len;
+ }
- fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
- fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
+ for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
+ fprintf (stream, " %s%*c %s\n",
+ regnames[i].name,
+ (int)(max_len - strlen (regnames[i].name)), ' ',
+ _(regnames[i].description));
}
projects / thirdparty / binutils-gdb.git / blobdiff