x86: also optimize KXOR{D,Q} and KANDN{D,Q}

These can be converted to 2-byte VEX encoding when both source registers
are the same, by using KXORW / KANDNW as replacement.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4472821a2de3601aeae1f02885c1a4c043c3e80c..9682f66c724f98b51976480d07f67233db6c0a0c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2018-07-31  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (optimize_encoding): Also handle kandnd,
+       kandnq, kxord, and kxorq.
+       * testsuite/gas/i386/optimize-1.s: Add kandn and kxor tests.
+       * testsuite/gas/i386/optimize-1.d,
+       testsuite/gas/i386/optimize-4.d,
+       testsuite/gas/i386/optimize-5.d: Adjust expectations.
+
 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386.c (check_VecOperands): Convert masking handling

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 8761e9793d613d1630a2a7cbcfa35d7f21f24cbc..e07056f725f5c492edc86e9aa190f3039bf49596 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3942,7 +3942,11 @@ optimize_encoding (void)
                || i.tm.base_opcode == 0x66f8
                || i.tm.base_opcode == 0x66f9
                || i.tm.base_opcode == 0x66fa
-               || i.tm.base_opcode == 0x66fb)
+               || i.tm.base_opcode == 0x66fb
+               || i.tm.base_opcode == 0x42
+               || i.tm.base_opcode == 0x6642
+               || i.tm.base_opcode == 0x47
+               || i.tm.base_opcode == 0x6647)
               && i.tm.extension_opcode == None))
     {
       /* Optimize: -O2:
@@ -3973,6 +3977,12 @@ optimize_encoding (void)
             EVEX VOP %ymmM, %ymmM, %ymmN
               -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
               -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
+          VOP, one of kxord and kxorq:
+            VEX VOP %kM, %kM, %kN
+              -> VEX kxorw %kM, %kM, %kN
+          VOP, one of kandnd and kandnq:
+            VEX VOP %kM, %kM, %kN
+              -> VEX kandnw %kM, %kM, %kN
        */
       if (is_evex_encoding (&i.tm))
        {
@@ -3985,6 +3995,11 @@ optimize_encoding (void)
              i.tm.opcode_modifier.evex = 0;
            }
        }
+      else if (i.tm.operand_types[0].bitfield.regmask)
+       {
+         i.tm.base_opcode &= 0xff;
+         i.tm.opcode_modifier.vexw = VEXW0;
+       }
       else
        i.tm.opcode_modifier.vex = VEX128;
 

diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index 33ce43c8720053672462f0f2ba81d7e64c9430d7..4358c19c2145e65d9d116908f373b73abaa6f712 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -58,4 +58,8 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-1.s b/gas/testsuite/gas/i386/optimize-1.s
index 21b9594034538c1d2c9d68b724b20e6ef91a0dc7..f61a176de89b2fca49e41cdcc5ee1a6788630870 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-1.s
+++ b/gas/testsuite/gas/i386/optimize-1.s
@@ -66,3 +66,9 @@ _start:
        vpsubq %ymm1, %ymm1, %ymm5{z}{%k7}
        vpsubq %zmm1, %zmm1, %zmm5
        vpsubq %ymm1, %ymm1, %ymm5
+
+       kxord %k1, %k1, %k5
+       kxorq %k1, %k1, %k5
+
+       kandnd %k1, %k1, %k5
+       kandnq %k1, %k1, %k5

diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
index c9f50f5daa9192f1f0cbab113bda131d75af9c16..9f99dadf34f279bf876d30d6fca9ffeb69d48bf9 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-4.d
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -58,6 +58,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
 #pass

diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
index ba4601ef197c44b2d396f683ea973bd397c1edd1..cfd0df04a4109853fcbc494302b0576cb26e8314 100644 (file)
--- a/gas/testsuite/gas/i386/optimize-5.d
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -58,6 +58,10 @@ Disassembly of section .text:
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   c5 f1 fb e9             vpsubq %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 47 e9             kxorw  %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
+ +[a-f0-9]+:   c5 f4 42 e9             kandnw %k1,%k1,%k5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:   62 f1 f5 08 55 e9       vandnpd %xmm1,%xmm1,%xmm5
 #pass

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e5f93002083aa0f23efa7f41a149adb2ca663599..f469810795322ee6f2b443407b6593ccb1c91205 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-07-31  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
+       * i386-init.h, i386-tbl.h: Re-generate.
+
 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.h (ZEROING_MASKING) Rename to ...

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ed9513fe5711ac0ea4a62ff3b58cb11d3d1cfbb8..e65a9ac232c5e1afd4f4b564c3f44b6cb08ce7aa 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4211,7 +4211,7 @@ vpmovzxwq, 2, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Ve
 
 kaddd, 3, 0x664A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
 kandd, 3, 0x6641, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
-kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
+kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
 kmovd, 2, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex, RegMask }
 kmovd, 2, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex }
 knotd, 2, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
@@ -4219,10 +4219,10 @@ kord, 3, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|
 kortestd, 2, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
 ktestd, 2, 0x6699, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
 kxnord, 3, 0x6646, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
-kxord, 3, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
+kxord, 3, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
 
 kaddq, 3, 0x4A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
-kandnq, 3, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
+kandnq, 3, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
 kandq, 3, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
 kmovq, 2, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, RegMask }
 kmovq, 2, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex }
@@ -4233,7 +4233,7 @@ ktestq, 2, 0x99, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize
 kunpckdq, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
 kunpckwd, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
 kxnorq, 3, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
-kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
+kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
 
 kmovd, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
 kmovd, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 7c77137d1a4d1d804e466f91c4b242fca83e274f..1fc4b6e93704b757698824ff2a2b804daf307206 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -67739,7 +67739,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -67918,7 +67918,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -67958,7 +67958,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -68197,7 +68197,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,