opcodes/ChangeLog

   1 2018-07-31  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
   4         * i386-init.h, i386-tbl.h: Re-generate.
   5
   6 2018-07-31  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.h (ZEROING_MASKING) Rename to ...
   9         (DYNAMIC_MASKING): ... this. Adjust comment.
  10         * i386-opc.tbl (MaskingMorZ): Define.
  11         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  12         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  13         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  14         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  15         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  16         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  17         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  18         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  19         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  20
  21 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-opc.tbl: Use element rather than vector size for AVX512*
  24         scatter/gather insns.
  25         * i386-tbl.h: Re-generate.
  26
  27 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  30         (cpu_flags): Drop CpuVREX.
  31         * i386-opc.h (CpuVREX): Delete.
  32         (union i386_cpu_flags): Remove cpuvrex.
  33         * i386-init.h, i386-tbl.h: Re-generate.
  34
  35 2018-07-30  Jim Wilson  <jimw@sifive.com>
  36
  37         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  38         fields.
  39         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  40
  41 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  42
  43         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  44         * Makefile.in: Regenerated.
  45         * configure.ac: Add C-SKY.
  46         * configure: Regenerated.
  47         * csky-dis.c: New file.
  48         * csky-opc.h: New file.
  49         * disassemble.c (ARCH_csky): Define.
  50         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  51         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  52
  53 2018-07-27  Alan Modra  <amodra@gmail.com>
  54
  55         * ppc-opc.c (insert_sprbat): Correct function parameter and
  56         return type.
  57         (extract_sprbat): Likewise, variable too.
  58
  59 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  60             Alan Modra  <amodra@gmail.com>
  61
  62         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  63         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
  64         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
  65         support disjointed BAT.
  66         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
  67         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  68         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  69
  70 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  71             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  72
  73         * i386-gen.c (adjust_broadcast_modifier): New function.
  74         (process_i386_opcode_modifier): Add an argument for operands.
  75         Adjust the Broadcast value based on operands.
  76         (output_i386_opcode): Pass operand_types to
  77         process_i386_opcode_modifier.
  78         (process_i386_opcodes): Pass NULL as operands to
  79         process_i386_opcode_modifier.
  80         * i386-opc.h (BYTE_BROADCAST): New.
  81         (WORD_BROADCAST): Likewise.
  82         (DWORD_BROADCAST): Likewise.
  83         (QWORD_BROADCAST): Likewise.
  84         (i386_opcode_modifier): Expand broadcast to 3 bits.
  85         * i386-tbl.h: Regenerated.
  86
  87 2018-07-24  Alan Modra  <amodra@gmail.com>
  88
  89         PR 23430
  90         * or1k-desc.h: Regenerate.
  91
  92 2018-07-24  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
  95         vcvtusi2ss, and vcvtusi2sd.
  96         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
  97         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
  98         * i386-tbl.h: Re-generate.
  99
 100 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 101
 102         * arc-opc.c (extract_w6): Fix extending the sign.
 103
 104 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 105
 106         * arc-tbl.h (vewt): Allow it for ARC EM family.
 107
 108 2018-07-23  Alan Modra  <amodra@gmail.com>
 109
 110         PR 23419
 111         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 112         opcode variants for mtspr/mfspr encodings.
 113
 114 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 115             Maciej W. Rozycki  <macro@mips.com>
 116
 117         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 118         loongson3a descriptors.
 119         (parse_mips_ase_option): Handle -M loongson-mmi option.
 120         (print_mips_disassembler_options): Document -M loongson-mmi.
 121         * mips-opc.c (LMMI): New macro.
 122         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 123         instructions.
 124
 125 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 128         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 129         IgnoreSize and [XYZ]MMword where applicable.
 130         * i386-tbl.h: Re-generate.
 131
 132 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 135         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 136         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 137         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 138         * i386-tbl.h: Re-generate.
 139
 140 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 143         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 144         VPCLMULQDQ templates into their respective AVX512VL counterparts
 145         where possible, using Disp8ShiftVL and CheckRegSize instead of
 146         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 147         * i386-tbl.h: Re-generate.
 148
 149 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 152         AVX512VL counterparts where possible, using Disp8ShiftVL and
 153         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 154         IgnoreSize) as appropriate.
 155         * i386-tbl.h: Re-generate.
 156
 157 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-opc.tbl: Fold AVX512BW templates into their respective
 160         AVX512VL counterparts where possible, using Disp8ShiftVL and
 161         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 162         IgnoreSize) as appropriate.
 163         * i386-tbl.h: Re-generate.
 164
 165 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-opc.tbl: Fold AVX512CD templates into their respective
 168         AVX512VL counterparts where possible, using Disp8ShiftVL and
 169         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 170         IgnoreSize) as appropriate.
 171         * i386-tbl.h: Re-generate.
 172
 173 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.h (DISP8_SHIFT_VL): New.
 176         * i386-opc.tbl (Disp8ShiftVL):  Define.
 177         (various): Fold AVX512VL templates into their respective
 178         AVX512F counterparts where possible, using Disp8ShiftVL and
 179         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 180         IgnoreSize) as appropriate.
 181         * i386-tbl.h: Re-generate.
 182
 183 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 184
 185         * Makefile.am: Change dependencies and rule for
 186         $(srcdir)/i386-init.h.
 187         * Makefile.in: Re-generate.
 188         * i386-gen.c (process_i386_opcodes): New local variable
 189         "marker". Drop opening of input file. Recognize marker and line
 190         number directives.
 191         * i386-opc.tbl (OPCODE_I386_H): Define.
 192         (i386-opc.h): Include it.
 193         (None): Undefine.
 194
 195 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         PR gas/23418
 198         * i386-opc.h (Byte): Update comments.
 199         (Word): Likewise.
 200         (Dword): Likewise.
 201         (Fword): Likewise.
 202         (Qword): Likewise.
 203         (Tbyte): Likewise.
 204         (Xmmword): Likewise.
 205         (Ymmword): Likewise.
 206         (Zmmword): Likewise.
 207         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 208         vcvttps2uqq.
 209         * i386-tbl.h: Regenerated.
 210
 211 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 212
 213         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 214         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 215         * aarch64-asm-2.c: Regenerate.
 216         * aarch64-dis-2.c: Regenerate.
 217         * aarch64-opc-2.c: Regenerate.
 218
 219 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 220
 221         PR binutils/23192
 222         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 223         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 224         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 225         sqdmulh, sqrdmulh): Use Em16.
 226
 227 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 228
 229         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 230         csdb together with them.
 231         (thumb32_opcodes): Likewise.
 232
 233 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 236         requiring 32-bit registers as operands 2 and 3. Improve
 237         comments.
 238         (mwait, mwaitx): Fold templates. Improve comments.
 239         OPERAND_TYPE_INOUTPORTREG.
 240         * i386-tbl.h: Re-generate.
 241
 242 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-gen.c (operand_type_init): Remove
 245         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 246         OPERAND_TYPE_INOUTPORTREG.
 247         * i386-init.h: Re-generate.
 248
 249 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 252         (wrssq, wrussq): Add Qword.
 253         * i386-tbl.h: Re-generate.
 254
 255 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-opc.h: Rename OTMax to OTNum.
 258         (OTNumOfUints): Adjust calculation.
 259         (OTUnused): Directly alias to OTNum.
 260
 261 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 262
 263         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 264         `reg_xys'.
 265         (lea_reg_xys): Likewise.
 266         (print_insn_loop_primitive): Rename `reg' local variable to
 267         `reg_dxy'.
 268
 269 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 270
 271         PR binutils/23242
 272         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 273
 274 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 275
 276         PR binutils/23369
 277         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 278         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 279
 280 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 281
 282         PR tdep/8282
 283         * mips-dis.c (mips_option_arg_t): New enumeration.
 284         (mips_options): New variable.
 285         (disassembler_options_mips): New function.
 286         (print_mips_disassembler_options): Reimplement in terms of
 287         `disassembler_options_mips'.
 288         * arm-dis.c (disassembler_options_arm): Adapt to using the
 289         `disasm_options_and_args_t' structure.
 290         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 291         * s390-dis.c (disassembler_options_s390): Likewise.
 292
 293 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 294
 295         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 296         expected result.
 297         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 298         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 299         * testsuite/ld-arm/tls-longplt.d: Likewise.
 300
 301 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 302
 303         PR binutils/23192
 304         * aarch64-asm-2.c: Regenerate.
 305         * aarch64-dis-2.c: Likewise.
 306         * aarch64-opc-2.c: Likewise.
 307         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 308         * aarch64-opc.c (operand_general_constraint_met_p,
 309         aarch64_print_operand): Likewise.
 310         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 311         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 312         fmlal2, fmlsl2.
 313         (AARCH64_OPERANDS): Add Em2.
 314
 315 2018-06-26  Nick Clifton  <nickc@redhat.com>
 316
 317         * po/uk.po: Updated Ukranian translation.
 318         * po/de.po: Updated German translation.
 319         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 320
 321 2018-06-26  Nick Clifton  <nickc@redhat.com>
 322
 323         * nfp-dis.c: Fix spelling mistake.
 324
 325 2018-06-24  Nick Clifton  <nickc@redhat.com>
 326
 327         * configure: Regenerate.
 328         * po/opcodes.pot: Regenerate.
 329
 330 2018-06-24  Nick Clifton  <nickc@redhat.com>
 331
 332         2.31 branch created.
 333
 334 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 335
 336         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 337         * aarch64-asm-2.c: Regenerate.
 338         * aarch64-dis-2.c: Likewise.
 339
 340 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 341
 342         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 343         `-M ginv' option description.
 344
 345 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 346
 347         PR gas/23305
 348         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 349         la and lla.
 350
 351 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 352
 353         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 354         * configure.ac: Remove AC_PREREQ.
 355         * Makefile.in: Re-generate.
 356         * aclocal.m4: Re-generate.
 357         * configure: Re-generate.
 358
 359 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 360
 361         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 362         mips64r6 descriptors.
 363         (parse_mips_ase_option): Handle -Mginv option.
 364         (print_mips_disassembler_options): Document -Mginv.
 365         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 366         (GINV): New macro.
 367         (mips_opcodes): Define ginvi and ginvt.
 368
 369 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 370             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 371
 372         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 373         * mips-opc.c (CRC, CRC64): New macros.
 374         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 375         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 376         crc32cd for CRC64.
 377
 378 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 379
 380         PR 20319
 381         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 382         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 383
 384 2018-06-06  Alan Modra  <amodra@gmail.com>
 385
 386         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 387         setjmp.  Move init for some other vars later too.
 388
 389 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 390
 391         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 392         (dis_private): Add new fields for property section tracking.
 393         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 394         (xtensa_instruction_fits): New functions.
 395         (fetch_data): Bump minimal fetch size to 4.
 396         (print_insn_xtensa): Make struct dis_private static.
 397         Load and prepare property table on section change.
 398         Don't disassemble literals. Don't disassemble instructions that
 399         cross property table boundaries.
 400
 401 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * configure: Regenerated.
 404
 405 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 408         * i386-tbl.h: Re-generate.
 409
 410 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-opc.tbl (sldt, str): Add NoRex64.
 413         * i386-tbl.h: Re-generate.
 414
 415 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.tbl (invpcid): Add Oword.
 418         * i386-tbl.h: Re-generate.
 419
 420 2018-06-01  Alan Modra  <amodra@gmail.com>
 421
 422         * sysdep.h (_bfd_error_handler): Don't declare.
 423         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 424         * rl78-decode.opc: Likewise.
 425         * msp430-decode.c: Regenerate.
 426         * rl78-decode.c: Regenerate.
 427
 428 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 429
 430         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 431         * i386-init.h : Regenerated.
 432
 433 2018-05-25  Alan Modra  <amodra@gmail.com>
 434
 435         * Makefile.in: Regenerate.
 436         * po/POTFILES.in: Regenerate.
 437
 438 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 439
 440         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 441         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 442         (insert_bab, extract_bab, insert_btab, extract_btab,
 443         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 444         (BAT, BBA VBA RBS XB6S): Delete macros.
 445         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 446         (BB, BD, RBX, XC6): Update for new macros.
 447         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 448         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 449         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 450         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 451
 452 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 453
 454         * Makefile.am: Add support for s12z architecture.
 455         * configure.ac: Likewise.
 456         * disassemble.c: Likewise.
 457         * disassemble.h: Likewise.
 458         * Makefile.in: Regenerate.
 459         * configure: Regenerate.
 460         * s12z-dis.c: New file.
 461         * s12z.h: New file.
 462
 463 2018-05-18  Alan Modra  <amodra@gmail.com>
 464
 465         * nfp-dis.c: Don't #include libbfd.h.
 466         (init_nfp3200_priv): Use bfd_get_section_contents.
 467         (nit_nfp6000_mecsr_sec): Likewise.
 468
 469 2018-05-17  Nick Clifton  <nickc@redhat.com>
 470
 471         * po/zh_CN.po: Updated simplified Chinese translation.
 472
 473 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 474
 475         PR binutils/23109
 476         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 477         * aarch64-dis-2.c: Regenerate.
 478
 479 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 480
 481         PR binutils/21446
 482         * aarch64-asm.c (opintl.h): Include.
 483         (aarch64_ins_sysreg): Enforce read/write constraints.
 484         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 485         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 486         (F_REG_READ, F_REG_WRITE): New.
 487         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 488         AARCH64_OPND_SYSREG.
 489         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 490         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 491         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 492         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 493         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 494         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 495         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 496         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 497         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 498         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 499         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 500         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 501         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 502         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 503         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 504         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 505         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 506
 507 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 508
 509         PR binutils/21446
 510         * aarch64-dis.c (no_notes: New.
 511         (parse_aarch64_dis_option): Support notes.
 512         (aarch64_decode_insn, print_operands): Likewise.
 513         (print_aarch64_disassembler_options): Document notes.
 514         * aarch64-opc.c (aarch64_print_operand): Support notes.
 515
 516 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 517
 518         PR binutils/21446
 519         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 520         and take error struct.
 521         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 522         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 523         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 524         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 525         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 526         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 527         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 528         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 529         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 530         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 531         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 532         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 533         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 534         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 535         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 536         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 537         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 538         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 539         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 540         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 541         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 542         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 543         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 544         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 545         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 546         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 547         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 548         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 549         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 550         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 551         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 552         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 553         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 554         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 555         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 556         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 557         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 558         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 559         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 560         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 561         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 562         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 563         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 564         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 565         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 566         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 567         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 568         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 569         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 570         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 571         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 572         (determine_disassembling_preference, aarch64_decode_insn,
 573         print_insn_aarch64_word, print_insn_data): Take errors struct.
 574         (print_insn_aarch64): Use errors.
 575         * aarch64-asm-2.c: Regenerate.
 576         * aarch64-dis-2.c: Regenerate.
 577         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 578         boolean in aarch64_insert_operan.
 579         (print_operand_extractor): Likewise.
 580         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 581
 582 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 583
 584         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 585
 586 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 589
 590 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 591
 592         * cr16-opc.c (cr16_instruction): Comment typo fix.
 593         * hppa-dis.c (print_insn_hppa): Likewise.
 594
 595 2018-05-08  Jim Wilson  <jimw@sifive.com>
 596
 597         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 598         (match_c_slli64, match_srxi_as_c_srxi): New.
 599         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 600         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 601         <c.slli, c.srli, c.srai>: Use match_s_slli.
 602         <c.slli64, c.srli64, c.srai64>: New.
 603
 604 2018-05-08  Alan Modra  <amodra@gmail.com>
 605
 606         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 607         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 608         partition opcode space for index lookup.
 609
 610 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 611
 612         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 613         <insn_length>: ...with this.  Update usage.
 614         Remove duplicate call to *info->memory_error_func.
 615
 616 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 617             H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         * i386-dis.c (Gva): New.
 620         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 621         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 622         (prefix_table): New instructions (see prefix above).
 623         (mod_table): New instructions (see prefix above).
 624         (OP_G): Handle va_mode.
 625         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 626         CPU_MOVDIR64B_FLAGS.
 627         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 628         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 629         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 630         * i386-opc.tbl: Add movidir{i,64b}.
 631         * i386-init.h: Regenerated.
 632         * i386-tbl.h: Likewise.
 633
 634 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 637         AddrPrefixOpReg.
 638         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 639         (AddrPrefixOpReg): This.
 640         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 641         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 642
 643 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 644
 645         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 646         (vle_num_opcodes): Likewise.
 647         (spe2_num_opcodes): Likewise.
 648         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 649         initialization loop.
 650         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 651         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 652         only once.
 653
 654 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 655
 656         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 657
 658 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 659
 660         Makefile.am: Added nfp-dis.c.
 661         configure.ac: Added bfd_nfp_arch.
 662         disassemble.h: Added print_insn_nfp prototype.
 663         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 664         nfp-dis.c: New, for NFP support.
 665         po/POTFILES.in: Added nfp-dis.c to the list.
 666         Makefile.in: Regenerate.
 667         configure: Regenerate.
 668
 669 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 670
 671         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 672         templates into their base ones.
 673         * i386-tlb.h: Re-generate.
 674
 675 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 678         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 679         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 680         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 681         * i386-init.h: Re-generate.
 682
 683 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 684
 685         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 686         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 687         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 688         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 689         comment.
 690         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 691         and CpuRegMask.
 692         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 693         CpuRegMask: Delete.
 694         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 695         cpuregzmm, and cpuregmask.
 696         * i386-init.h: Re-generate.
 697         * i386-tbl.h: Re-generate.
 698
 699 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 700
 701         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 702         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 703         * i386-init.h: Re-generate.
 704
 705 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-gen.c (VexImmExt): Delete.
 708         * i386-opc.h (VexImmExt, veximmext): Delete.
 709         * i386-opc.tbl: Drop all VexImmExt uses.
 710         * i386-tlb.h: Re-generate.
 711
 712 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 715         register-only forms.
 716         * i386-tlb.h: Re-generate.
 717
 718 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 719
 720         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 721
 722 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 723
 724         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 725         PREFIX_0F1C.
 726         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 727         (cpu_flags): Add CpuCLDEMOTE.
 728         * i386-init.h: Regenerate.
 729         * i386-opc.h (enum): Add CpuCLDEMOTE,
 730         (i386_cpu_flags): Add cpucldemote.
 731         * i386-opc.tbl: Add cldemote.
 732         * i386-tbl.h: Regenerate.
 733
 734 2018-04-16  Alan Modra  <amodra@gmail.com>
 735
 736         * Makefile.am: Remove sh5 and sh64 support.
 737         * configure.ac: Likewise.
 738         * disassemble.c: Likewise.
 739         * disassemble.h: Likewise.
 740         * sh-dis.c: Likewise.
 741         * sh64-dis.c: Delete.
 742         * sh64-opc.c: Delete.
 743         * sh64-opc.h: Delete.
 744         * Makefile.in: Regenerate.
 745         * configure: Regenerate.
 746         * po/POTFILES.in: Regenerate.
 747
 748 2018-04-16  Alan Modra  <amodra@gmail.com>
 749
 750         * Makefile.am: Remove w65 support.
 751         * configure.ac: Likewise.
 752         * disassemble.c: Likewise.
 753         * disassemble.h: Likewise.
 754         * w65-dis.c: Delete.
 755         * w65-opc.h: Delete.
 756         * Makefile.in: Regenerate.
 757         * configure: Regenerate.
 758         * po/POTFILES.in: Regenerate.
 759
 760 2018-04-16  Alan Modra  <amodra@gmail.com>
 761
 762         * configure.ac: Remove we32k support.
 763         * configure: Regenerate.
 764
 765 2018-04-16  Alan Modra  <amodra@gmail.com>
 766
 767         * Makefile.am: Remove m88k support.
 768         * configure.ac: Likewise.
 769         * disassemble.c: Likewise.
 770         * disassemble.h: Likewise.
 771         * m88k-dis.c: Delete.
 772         * Makefile.in: Regenerate.
 773         * configure: Regenerate.
 774         * po/POTFILES.in: Regenerate.
 775
 776 2018-04-16  Alan Modra  <amodra@gmail.com>
 777
 778         * Makefile.am: Remove i370 support.
 779         * configure.ac: Likewise.
 780         * disassemble.c: Likewise.
 781         * disassemble.h: Likewise.
 782         * i370-dis.c: Delete.
 783         * i370-opc.c: Delete.
 784         * Makefile.in: Regenerate.
 785         * configure: Regenerate.
 786         * po/POTFILES.in: Regenerate.
 787
 788 2018-04-16  Alan Modra  <amodra@gmail.com>
 789
 790         * Makefile.am: Remove h8500 support.
 791         * configure.ac: Likewise.
 792         * disassemble.c: Likewise.
 793         * disassemble.h: Likewise.
 794         * h8500-dis.c: Delete.
 795         * h8500-opc.h: Delete.
 796         * Makefile.in: Regenerate.
 797         * configure: Regenerate.
 798         * po/POTFILES.in: Regenerate.
 799
 800 2018-04-16  Alan Modra  <amodra@gmail.com>
 801
 802         * configure.ac: Remove tahoe support.
 803         * configure: Regenerate.
 804
 805 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 808         umwait.
 809         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 810         64-bit mode.
 811         * i386-tbl.h: Regenerated.
 812
 813 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 814
 815         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 816         PREFIX_MOD_1_0FAE_REG_6.
 817         (va_mode): New.
 818         (OP_E_register): Use va_mode.
 819         * i386-dis-evex.h (prefix_table):
 820         New instructions (see prefixes above).
 821         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 822         (cpu_flags): Likewise.
 823         * i386-opc.h (enum): Likewise.
 824         (i386_cpu_flags): Likewise.
 825         * i386-opc.tbl: Add umonitor, umwait, tpause.
 826         * i386-init.h: Regenerate.
 827         * i386-tbl.h: Likewise.
 828
 829 2018-04-11  Alan Modra  <amodra@gmail.com>
 830
 831         * opcodes/i860-dis.c: Delete.
 832         * opcodes/i960-dis.c: Delete.
 833         * Makefile.am: Remove i860 and i960 support.
 834         * configure.ac: Likewise.
 835         * disassemble.c: Likewise.
 836         * disassemble.h: Likewise.
 837         * Makefile.in: Regenerate.
 838         * configure: Regenerate.
 839         * po/POTFILES.in: Regenerate.
 840
 841 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 842
 843         PR binutils/23025
 844         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 845         to 0.
 846         (print_insn): Clear vex instead of vex.evex.
 847
 848 2018-04-04  Nick Clifton  <nickc@redhat.com>
 849
 850         * po/es.po: Updated Spanish translation.
 851
 852 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 853
 854         * i386-gen.c (opcode_modifiers): Delete VecESize.
 855         * i386-opc.h (VecESize): Delete.
 856         (struct i386_opcode_modifier): Delete vecesize.
 857         * i386-opc.tbl: Drop VecESize.
 858         * i386-tlb.h: Re-generate.
 859
 860 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 863         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 864         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 865         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 866         * i386-tlb.h: Re-generate.
 867
 868 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 871         Fold AVX512 forms
 872         * i386-tlb.h: Re-generate.
 873
 874 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 877         (vex_len_table): Drop Y for vcvt*2si.
 878         (putop): Replace plain 'Y' handling by abort().
 879
 880 2018-03-28  Nick Clifton  <nickc@redhat.com>
 881
 882         PR 22988
 883         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 884         instructions with only a base address register.
 885         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 886         handle AARHC64_OPND_SVE_ADDR_R.
 887         (aarch64_print_operand): Likewise.
 888         * aarch64-asm-2.c: Regenerate.
 889         * aarch64_dis-2.c: Regenerate.
 890         * aarch64-opc-2.c: Regenerate.
 891
 892 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-opc.tbl: Drop VecESize from register only insn forms and
 895         memory forms not allowing broadcast.
 896         * i386-tlb.h: Re-generate.
 897
 898 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 901         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 902         sha256*): Drop Disp<N>.
 903
 904 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-dis.c (EbndS, bnd_swap_mode): New.
 907         (prefix_table): Use EbndS.
 908         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 909         * i386-opc.tbl (bndmov): Move misplaced Load.
 910         * i386-tlb.h: Re-generate.
 911
 912 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 915         templates allowing memory operands and folded ones for register
 916         only flavors.
 917         * i386-tlb.h: Re-generate.
 918
 919 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 922         256-bit templates. Drop redundant leftover Disp<N>.
 923         * i386-tlb.h: Re-generate.
 924
 925 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 926
 927         * riscv-opc.c (riscv_insn_types): New.
 928
 929 2018-03-13  Nick Clifton  <nickc@redhat.com>
 930
 931         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 932
 933 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 934
 935         * i386-opc.tbl: Add Optimize to clr.
 936         * i386-tbl.h: Regenerated.
 937
 938 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 939
 940         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 941         * i386-opc.h (OldGcc): Removed.
 942         (i386_opcode_modifier): Remove oldgcc.
 943         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 944         instructions for old (<= 2.8.1) versions of gcc.
 945         * i386-tbl.h: Regenerated.
 946
 947 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-opc.h (EVEXDYN): New.
 950         * i386-opc.tbl: Fold various AVX512VL templates.
 951         * i386-tlb.h: Re-generate.
 952
 953 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 956         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 957         vpexpandd, vpexpandq): Fold AFX512VF templates.
 958         * i386-tlb.h: Re-generate.
 959
 960 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 963         Fold 128- and 256-bit VEX-encoded templates.
 964         * i386-tlb.h: Re-generate.
 965
 966 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 969         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 970         vpexpandd, vpexpandq): Fold AVX512F templates.
 971         * i386-tlb.h: Re-generate.
 972
 973 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 976         64-bit templates. Drop Disp<N>.
 977         * i386-tlb.h: Re-generate.
 978
 979 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 982         and 256-bit templates.
 983         * i386-tlb.h: Re-generate.
 984
 985 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 986
 987         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 988         * i386-tlb.h: Re-generate.
 989
 990 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 991
 992         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 993         Drop NoAVX.
 994         * i386-tlb.h: Re-generate.
 995
 996 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 999         * i386-tlb.h: Re-generate.
1000
1001 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-gen.c (opcode_modifiers): Delete FloatD.
1004         * i386-opc.h (FloatD): Delete.
1005         (struct i386_opcode_modifier): Delete floatd.
1006         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1007         FloatD by D.
1008         * i386-tlb.h: Re-generate.
1009
1010 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1013
1014 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1017         * i386-tlb.h: Re-generate.
1018
1019 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1022         forms.
1023         * i386-tlb.h: Re-generate.
1024
1025 2018-03-07  Alan Modra  <amodra@gmail.com>
1026
1027         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1028         bfd_arch_rs6000.
1029         * disassemble.h (print_insn_rs6000): Delete.
1030         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1031         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1032         (print_insn_rs6000): Delete.
1033
1034 2018-03-03  Alan Modra  <amodra@gmail.com>
1035
1036         * sysdep.h (opcodes_error_handler): Define.
1037         (_bfd_error_handler): Declare.
1038         * Makefile.am: Remove stray #.
1039         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1040         EDIT" comment.
1041         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1042         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1043         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1044         opcodes_error_handler to print errors.  Standardize error messages.
1045         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1046         and include opintl.h.
1047         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1048         * i386-gen.c: Standardize error messages.
1049         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1050         * Makefile.in: Regenerate.
1051         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1052         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1053         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1054         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1055         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1056         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1057         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1058         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1059         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1060         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1061         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1062         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1063         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1064
1065 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1066
1067         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1068         vpsub[bwdq] instructions.
1069         * i386-tbl.h: Regenerated.
1070
1071 2018-03-01  Alan Modra  <amodra@gmail.com>
1072
1073         * configure.ac (ALL_LINGUAS): Sort.
1074         * configure: Regenerate.
1075
1076 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1077
1078         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1079         macro by assignements.
1080
1081 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1082
1083         PR gas/22871
1084         * i386-gen.c (opcode_modifiers): Add Optimize.
1085         * i386-opc.h (Optimize): New enum.
1086         (i386_opcode_modifier): Add optimize.
1087         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1088         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1089         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1090         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1091         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1092         vpxord and vpxorq.
1093         * i386-tbl.h: Regenerated.
1094
1095 2018-02-26  Alan Modra  <amodra@gmail.com>
1096
1097         * crx-dis.c (getregliststring): Allocate a large enough buffer
1098         to silence false positive gcc8 warning.
1099
1100 2018-02-22  Shea Levy <shea@shealevy.com>
1101
1102         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1103
1104 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1105
1106         * i386-opc.tbl: Add {rex},
1107         * i386-tbl.h: Regenerated.
1108
1109 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1110
1111         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1112         (mips16_opcodes): Replace `M' with `m' for "restore".
1113
1114 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1115
1116         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1117
1118 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1119
1120         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1121         variable to `function_index'.
1122
1123 2018-02-13  Nick Clifton  <nickc@redhat.com>
1124
1125         PR 22823
1126         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1127         about truncation of printing.
1128
1129 2018-02-12  Henry Wong <henry@stuffedcow.net>
1130
1131         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1132
1133 2018-02-05  Nick Clifton  <nickc@redhat.com>
1134
1135         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1136
1137 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1138
1139         * i386-dis.c (enum): Add pconfig.
1140         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1141         (cpu_flags): Add CpuPCONFIG.
1142         * i386-opc.h (enum): Add CpuPCONFIG.
1143         (i386_cpu_flags): Add cpupconfig.
1144         * i386-opc.tbl: Add PCONFIG instruction.
1145         * i386-init.h: Regenerate.
1146         * i386-tbl.h: Likewise.
1147
1148 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1149
1150         * i386-dis.c (enum): Add PREFIX_0F09.
1151         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1152         (cpu_flags): Add CpuWBNOINVD.
1153         * i386-opc.h (enum): Add CpuWBNOINVD.
1154         (i386_cpu_flags): Add cpuwbnoinvd.
1155         * i386-opc.tbl: Add WBNOINVD instruction.
1156         * i386-init.h: Regenerate.
1157         * i386-tbl.h: Likewise.
1158
1159 2018-01-17  Jim Wilson  <jimw@sifive.com>
1160
1161         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1162
1163 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1164
1165         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1166         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1167         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1168         (cpu_flags): Add CpuIBT, CpuSHSTK.
1169         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1170         (i386_cpu_flags): Add cpuibt, cpushstk.
1171         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1172         * i386-init.h: Regenerate.
1173         * i386-tbl.h: Likewise.
1174
1175 2018-01-16  Nick Clifton  <nickc@redhat.com>
1176
1177         * po/pt_BR.po: Updated Brazilian Portugese translation.
1178         * po/de.po: Updated German translation.
1179
1180 2018-01-15  Jim Wilson  <jimw@sifive.com>
1181
1182         * riscv-opc.c (match_c_nop): New.
1183         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1184
1185 2018-01-15  Nick Clifton  <nickc@redhat.com>
1186
1187         * po/uk.po: Updated Ukranian translation.
1188
1189 2018-01-13  Nick Clifton  <nickc@redhat.com>
1190
1191         * po/opcodes.pot: Regenerated.
1192
1193 2018-01-13  Nick Clifton  <nickc@redhat.com>
1194
1195         * configure: Regenerate.
1196
1197 2018-01-13  Nick Clifton  <nickc@redhat.com>
1198
1199         2.30 branch created.
1200
1201 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1202
1203         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1204         * i386-tbl.h: Regenerate.
1205
1206 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1209         * i386-tbl.h: Re-generate.
1210
1211 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1212
1213         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1214         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1215         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1216         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1217         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1218         Disp8MemShift of AVX512VL forms.
1219         * i386-tbl.h: Re-generate.
1220
1221 2018-01-09  Jim Wilson  <jimw@sifive.com>
1222
1223         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1224         then the hi_addr value is zero.
1225
1226 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1227
1228         * arm-dis.c (arm_opcodes): Add csdb.
1229         (thumb32_opcodes): Add csdb.
1230
1231 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1232
1233         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1234         * aarch64-asm-2.c: Regenerate.
1235         * aarch64-dis-2.c: Regenerate.
1236         * aarch64-opc-2.c: Regenerate.
1237
1238 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1239
1240         PR gas/22681
1241         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1242         Remove AVX512 vmovd with 64-bit operands.
1243         * i386-tbl.h: Regenerated.
1244
1245 2018-01-05  Jim Wilson  <jimw@sifive.com>
1246
1247         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1248         jalr.
1249
1250 2018-01-03  Alan Modra  <amodra@gmail.com>
1251
1252         Update year range in copyright notice of all files.
1253
1254 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1255
1256         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1257         and OPERAND_TYPE_REGZMM entries.
1258
1259 For older changes see ChangeLog-2017
1260 \f
1261 Copyright (C) 2018 Free Software Foundation, Inc.
1262
1263 Copying and distribution of this file, with or without modification,
1264 are permitted in any medium without royalty provided the copyright
1265 notice and this notice are preserved.
1266
1267 Local Variables:
1268 mode: change-log
1269 left-margin: 8
1270 fill-column: 74
1271 version-control: never
1272 End: