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morello: Fix encoding of ldtr/sttr
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2021-09-24  Alex Coplanmorello: Fix encoding of ldtr/sttr
2021-08-10  Matthew Malcomsongas: Add whitespace in morello-capinit test output...
2021-08-10  Matthew Malcomsongas: ADR_LO21_PCREL accounts for LSB in symbol
2021-08-10  Matthew Malcomsongas: Remove requirement of getting a target symbol
2021-08-10  Matthew Malcomsongas: Allow MORELLO branch relocations to addresses...
2021-08-04  Matthew MalcomsonApply changes to allow compiling with -ansi
2021-07-30  Matthew Malcomsongas: aarch64: Accept `purecap` and `hybrid` ABI parameters
2021-07-29  Matthew Malcomsongas: aarch64: Make chericap and capinit auto-align
2021-07-29  Matthew MalcomsonFixing missed ChangeLog entries.
2021-07-29  Matthew Malcomsongas: aarch64: Require 16 bytes for Morello capinit...
2021-07-29  Matthew Malcomsongas: aarch64: Introduce the chericap directive
2021-07-29  Matthew Malcomsongas: aarch64: Fixing expression calculation using C64...
2021-07-20  Matthew Malcomsongas: Use correct data type in parse_operands
2021-07-13  Alex Coplangas: Fix uninitialized c64 member of aarch64_fix struct
2020-10-20  Siddhesh Poyarekar[Morello] TLS Descriptor support
2020-10-20  Siddhesh Poyarekar[Morello] Capability support for exception headers
2020-10-20  Siddhesh Poyarekar[Morello] Implement branch relocations
2020-10-20  Siddhesh Poyarekar[Morello] GOT Relocations
2020-10-20  Siddhesh Poyarekar[Morello] Allow lo12 relocations for alternate base...
2020-10-20  Siddhesh Poyarekar[Morello] Capability data relocations
2020-10-20  Siddhesh Poyarekar[Morello] Add Morello relocations for ADRP
2020-10-20  Siddhesh Poyarekar[Morello] Make DC, IC capability aware in C64.
2020-10-20  Siddhesh Poyarekar[Morello] Add Morello system registers
2020-10-20  Siddhesh Poyarekar[Morello] ADR, ADRP and ADRDP
2020-10-20  Siddhesh Poyarekar[Morello] Implement LDUR/STUR fallback for LDR/STR...
2020-10-20  Siddhesh Poyarekar[Morello] altbase: Remaining LD/ST
2020-10-20  Siddhesh Poyarekar[Morello] altbase: LDUR/STUR
2020-10-20  Siddhesh Poyarekar[Morello] altbase: LDR/STR
2020-10-20  Siddhesh Poyarekar[Morello] Loads and stores with alternate base
2020-10-20  Siddhesh Poyarekar[Morello] All remaining load and store instructions
2020-10-20  Siddhesh Poyarekar[Morello] LDR immediate
2020-10-20  Siddhesh Poyarekar[Morello] Load and store instructions.
2020-10-20  Siddhesh Poyarekar[Morello] Load and branch instructions
2020-10-20  Siddhesh Poyarekar[Morello] Capability sealing and unsealing instructions
2020-10-20  Siddhesh Poyarekar[Morello] Capability construction and modification...
2020-10-20  Siddhesh Poyarekar[Morello] CLRTAG, CLRPERM
2020-10-20  Siddhesh Poyarekar[Morello] Miscellaneous Morello Instructions
2020-10-20  Siddhesh Poyarekar[Morello] Branch and return instructions
2020-10-20  Siddhesh Poyarekar[Morello] Add BICFLGS
2020-10-20  Siddhesh Poyarekar[Morello] ADD and SUB instructions
2020-10-20  Siddhesh Poyarekar[Morello] Add MOV and CPY instructions for capabilities
2020-10-20  Siddhesh Poyarekar[Morello] Identify branch source and target using mappi...
2020-10-20  Siddhesh Poyarekar[Morello] Set LSB for c64 symbols in object code
2020-10-20  Siddhesh Poyarekar[Morello] Add mapping symbol to identify C64 code sections
2020-10-20  Siddhesh Poyarekar[AArch64] Initial commit for Morello architecture
2020-10-20  Siddhesh Poyarekar[AArch64] Prefer error messages from opcodes enabled...
2020-10-17  H.J. Lugas: Add a -gdwarf-5 debug_line test with .s file
2020-10-17  H.J. Lugas: Replace dwarf5-line-2.S with dwarf5-line-3.S
2020-10-17  H.J. Lugas: Always use as_where for preprocessed assembly...
2020-10-16  H.J. Lugas: Reuse the input file entry in the file table
2020-10-16  Cui,LiliEnhancement for avx-vnni patch
2020-10-14  H.J. Lux86: Support Intel AVX VNNI
2020-10-14  Lili Cuix86: Add support for Intel HRESET instruction
2020-10-14  Lili Cuix86: Support Intel UINTR
2020-10-14  H.J. Lux86: Remove the prefix byte from non-VEX/EVEX base_opcode
2020-10-14  H.J. Lux86: Rename VexOpcode to OpcodePrefix
2020-10-09  H.J. Lux86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker
2020-10-06  Alex Coplanaarch64: Fix bogus type punning in parse_barrier()...
2020-10-06  Sergey BelyashavA small set of code improvements for the Z80 assembler.
2020-10-06  Alan ModraFix gas sh-link-zero test for hppa64-hpux
2020-10-05  Przemyslaw Wirkus[PATCH][GAS][AArch64] Update Cortex-X1 feature flags
2020-10-05  Przemyslaw Wirkus[PATCH][GAS][arm] Update Cortex-X1 feature flags
2020-10-05  Kamil RytarowskiAdd NetBSD AArch64 GAS support.
2020-10-05  Samanta NavarroFix spelling mistakes
2020-10-05  T.K. Chiai386: Allow non-absolute segment values for lcall/ljmp
2020-10-05  H.J. Lux86-64: Always display suffix for %LQ in 64bit
2020-10-05  H.J. Lux86: Clear modrm if not needed
2020-10-05  Nick CliftonGAS: Update the .section directive so that a numeric...
2020-10-03  H.J. Lux86: Update register operand check for AddrPrefixOpReg
2020-10-02  Przemyslaw Wirkusarm: add support for Cortex-A78 and Cortex-A78AE
2020-10-02  Nick CliftonFix the mve-vcvtne-it assembler test for the arm-*...
2020-10-01  Nick CliftonAdd new directive to GAS: .attach_to_group.
2020-09-30  H.J. Lux86: Check register operand for AddrPrefixOpReg
2020-09-30  Przemyslaw Wirkus[GAS][AArch64] Add support for Cortex-A78 and Cortex...
2020-09-30  Alex CoplanNEWS: Mention recent Arm CPU support
2020-09-30  Alex Coplanaarch64: Add support for Neoverse N2 CPU
2020-09-30  Alan Modragcc-4.4.7 warning fixes
2020-09-29  Przemyslaw WirkusAdd a note about recent changes to the AArch64 assemble...
2020-09-28  Przemyslaw WirkusThis patch adds support for Cortex-X1 for ARM.
2020-09-28  Przemyslaw WirkusThis patch introduces ETMv4 (Embedded Trace Macrocell...
2020-09-28  Przemyslaw WirkusThis patch adds support for Cortex-X1
2020-09-28  Przemyslaw WirkusThis patch introduces ETE (Embedded Trace Extension...
2020-09-28  Przemyslaw WirkusThis patch introduces TRBE (Trace Buffer Extension...
2020-09-28  Alex Coplanarm: Add missing Neoverse V1 feature
2020-09-28  Alex Coplanaarch64: Neoverse V1 tweaks
2020-09-26  Alan Modraubsan: opcodes/csky-opc.h:929 shift exponent 536870912
2020-09-24  Jim WilsonRISC-V: Error for relaxable branch in absolute section.
2020-09-24  Mark Wielaardreadelf: Show Unit Type for DWARF5
2020-09-24  Alex Coplanarm: Add support for Neoverse V1 CPU
2020-09-24  Alex Coplanaarch64: Add support for Neoverse V1 CPU
2020-09-24  Alex Coplanarm: Add support for Neoverse N2 CPU
2020-09-24  Cui,LiliAdd support for Intel TDX instructions.
2020-09-23  Cooper QuCSKY: Add objdump option -M abi-names.
2020-09-23  Terry GuoEnable support to Intel Keylocker instructions
2020-09-21  Alan ModraPR26569, R_RISCV_RVC_JUMP results in buffer overflow
2020-09-18  David Faustbpf: xBPF SDIV, SMOD instructions
2020-09-18  Nick CliftonEnsure that space allocated by assembler directives...
2020-09-17  Alan ModraTidy gas i386.exp
2020-09-16  Alan ModraTidy elf_symbol_from
2020-09-15  H.J. LuPE/x86-64: Display PE relocation names
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