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2020-10-22  Przemyslaw Wirkus[PATCH][GAS][AArch64] Define BRBE system registers
2020-10-22  Przemyslaw Wirkusaarch64: Define CSRE system registers
2020-10-22  H.J. Luopcodes/po/es.po: Remove the duplicated entry
2020-10-22  Dr. David Alan GilbertFix printf formatting errors where "0x" is used as...
2020-10-20  Ganesh Gopalasubra... Add AMD znver3 processor support
2020-10-16  Cui,LiliEnhancement for avx-vnni patch
2020-10-14  H.J. Lux86: Support Intel AVX VNNI
2020-10-14  Lili Cuix86: Add support for Intel HRESET instruction
2020-10-14  Lili Cuix86: Support Intel UINTR
2020-10-14  H.J. Lux86: Remove the prefix byte from non-VEX/EVEX base_opcode
2020-10-14  H.J. Lux86: Rename VexOpcode to OpcodePrefix
2020-10-05  Samanta NavarroFix spelling mistakes
2020-10-05  H.J. Lux86-64: Always display suffix for %LQ in 64bit
2020-10-05  H.J. Lux86: Clear modrm if not needed
2020-09-28  Przemyslaw WirkusThis patch introduces ETMv4 (Embedded Trace Macrocell...
2020-09-28  Przemyslaw WirkusThis patch introduces ETE (Embedded Trace Extension...
2020-09-28  Przemyslaw WirkusThis patch introduces TRBE (Trace Buffer Extension...
2020-09-26  Alan Modraubsan: opcodes/csky-opc.h:929 shift exponent 536870912
2020-09-25  Cui,LiliPut together MOD_VEX_0F38* in i386-dis.c,
2020-09-24  Andrew Burgesscsky/opcodes: enclose if body in curly braces
2020-09-24  Cui,LiliAdd support for Intel TDX instructions.
2020-09-23  Cooper QuCSKY: Add objdump option -M abi-names.
2020-09-23  Terry GuoEnable support to Intel Keylocker instructions
2020-09-21  Alan Modrarx-dis.c:103:3: suspicious concatenation of string...
2020-09-18  David Faustbpf: xBPF SDIV, SMOD instructions
2020-09-17  Andrew Burgessopcodes/csky: return the default disassembler when...
2020-09-16  Alan ModraTidy elf_symbol_from
2020-09-10  Nick CliftonStop symbols generated by the annobin gcc plugin from...
2020-09-10  Cooper QuCSKY: Add L2Cache instructions for CK860.
2020-09-10  Cooper QuCSKY: Add new arches while refine the cpu option process.
2020-09-10  Nick CliftonFix compile time warnings when building for the CSKY...
2020-09-10  Alan Modrasprintf arg overlaps destination
2020-09-09  Cooper QuCSKY: Change mvtc and mulsw's ISA flag.
2020-09-09  Cooper QuCSKY: Add FPUV3 instructions, which supported by ck860f.
2020-09-08  Alex Coplanaarch64: Add support for Armv8-R system registers
2020-09-08  Alex Coplanaarch64: Add support for Armv8-R DFB alias
2020-09-08  Alex Coplanaarch64: Add base support for Armv8-R
2020-09-02  Alan Modraubsan: v850-opc.c:412 left shift cannot be represented
2020-09-02  Alan Modraubsan: i386-dis.c
2020-09-02  Alan Modraubsan: csky-dis.c:1038 left shift cannot be represented
2020-09-02  Alan Modraubsan: crx-dis.c:571 left shift of negative value
2020-09-02  Alan Modraubsan: *-ibld.c
2020-09-02  Alan Modraubsan: bfin-dis.c:160 shift exponent 32 is too large
2020-09-02  Cooper QuCSKY: Add CPU CK803r3.
2020-09-02  Cooper QuCSKY: Fix Encode of mulsws.
2020-09-01  Alan Modramep: ubsan: mep-ibld.c:1635,1645,1652 left shift of...
2020-08-31  Cooper QuCSKY: Refine operand format error reporting.
2020-08-30  Alan Modracr16 disassembly error of disp20 fields
2020-08-29  Alan ModraPR26446 UBSAN: tc-csky.c:2618,4022 index out of bounds
2020-08-28  Alan ModraPR26449, PR26450 UBSAN: frv-ibld.c:135 left shift
2020-08-28  Cooper QuCSKY: Support attribute section.
2020-08-26  Jose E. Marchesiopcodes: Add missing entries to ebpf_isa_attr
2020-08-26  David Faustbpf: add xBPF ISA
2020-08-25  Alan ModraPR26504, ASAN: parse_disassembler_options vax-dis.c:142
2020-08-24  Cooper QuCSKY: Add new arch CK860.
2020-08-24  Cooper QuCSKY: Add ck803r2 series cpu.
2020-08-21  Nick CliftonFix problems with the AArch64 linker exposed by testing...
2020-08-21  Cooper QuCSKY: Support two operands form for bloop.
2020-08-18  Alan ModraCorrect vcmpsq, vcmpuq and xvtlsbb BF field
2020-08-18  Peter BergnerAdd ChangeLog entries for previous commit.
2020-08-18  Peter BergnerPowerPC: Rename xvcvbf16sp to xvcvbf16spn
2020-08-12  Alex Coplanaarch64: Add support for MPAM system registers
2020-08-12  Nick CliftonUpdated Serbian and Russian translations for various...
2020-08-11  Alan ModraPowerPC CELL cctp*
2020-08-10  Przemyslaw Wirkus[aarch64] GAS doesn't validate the architecture version...
2020-08-10  Alan ModraImplement missing powerpc mtspr and mfspr extended...
2020-08-10  Alan ModraImplement missing powerpc extended mnemonics
2020-08-10  Alan ModraPrioritise mtfprd and mtvrd over mtvsrd in PowerPC...
2020-08-04  Christian GroesslerZ8k: fix sout/soudb opcodes with direct address
2020-07-30  H.J. Lux86: Add {disp16} pseudo prefix
2020-07-29  Andreas ArnezPR26279 Work around maybe-uninitialized warning in...
2020-07-24  Nick CliftonUpdated German translation for the opcodes sub-directory
2020-07-21  Jan BeulichRevert "x86: Don't display eiz with no scale"
2020-07-15  H.J. Lux86: Don't display eiz with no scale
2020-07-15  Jan Beulichx86: move putop() case labels to restore alphabetic...
2020-07-15  Jan Beulichx86: make PUSH/POP disassembly uniform
2020-07-15  Jan Beulichx86: avoid attaching suffixes to unambiguous insns
2020-07-14  H.J. Lux86-64: Zero-extend lower 32 bits displacement to 64...
2020-07-14  Claudiu Zissulescuarc: Detect usage of illegal double register pairs
2020-07-14  Jan Beulichx86/Intel: debug registers are named DRn
2020-07-14  Jan Beulichx86: drop Rm and the 'L' macro
2020-07-14  Jan Beulichx86: drop Rdq, Rd, and MaskR
2020-07-14  Jan Beulichx86: simplify decode of opcodes valid only without...
2020-07-14  Jan Beulichx86: also use %BW / %DQ for kshift*
2020-07-14  Jan Beulichx86: simplify decode of opcodes valid with (embedded...
2020-07-14  Jan Beulichx86: drop further EVEX table entries that can be served...
2020-07-14  Jan Beulichx86: drop need_vex_reg
2020-07-14  Jan Beulichx86: drop Vex128 and Vex256
2020-07-14  Jan Beulichx86: replace %LW by %DQ
2020-07-14  Jan Beulichx86: merge/move logic determining the EVEX disp8 shift
2020-07-14  Jan Beulichx86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}
2020-07-14  Jan Beulichx86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel...
2020-07-14  Jan Beulichx86: fold VCMP_Fixup() into CMP_Fixup()
2020-07-14  Jan Beulichx86: don't disassemble MOVBE with two suffixes
2020-07-14  Jan Beulichx86: avoid attaching suffix to register-only CRC32
2020-07-14  Jan Beulichx86-64: don't hide an empty but meaningless REX prefix
2020-07-14  Jan Beulichx86: drop dead code from OP_IMREG()
2020-07-10  Lili Cuix86: Add support for Intel AMX instructions
2020-07-08  Jan Beulichx86: various XOP insns lack L and/or W bit decoding
2020-07-08  Jan Beulichx86: FMA4 scalar insns ignore VEX.L
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