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1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
8d9254fc | 2 | Copyright (C) 1987-2020 Free Software Foundation, Inc. |
1bb87f28 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
3e2cc1d1 | 4 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
7a6cf439 | 5 | at Cygnus Support. |
1bb87f28 | 6 | |
7ec022b2 | 7 | This file is part of GCC. |
1bb87f28 | 8 | |
7ec022b2 | 9 | GCC is free software; you can redistribute it and/or modify |
1bb87f28 | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
1bb87f28 JW |
12 | any later version. |
13 | ||
7ec022b2 | 14 | GCC is distributed in the hope that it will be useful, |
1bb87f28 JW |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
1bb87f28 | 22 | |
1910440e RS |
23 | #include "config/vxworks-dummy.h" |
24 | ||
1bb87f28 | 25 | /* Note that some other tm.h files include this one and then override |
a0a301fc DE |
26 | whatever definitions are necessary. */ |
27 | ||
8d12174d | 28 | #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () |
9b8466f4 | 29 | |
b4c522fa IB |
30 | /* Target CPU versions for D. */ |
31 | #define TARGET_D_CPU_VERSIONS sparc_d_target_versions | |
32 | ||
a0a301fc DE |
33 | /* Specify this in a cover file to provide bi-architecture (32/64) support. */ |
34 | /* #define SPARC_BI_ARCH */ | |
35 | ||
36 | /* Macro used later in this file to determine default architecture. */ | |
37 | #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
7a6cf439 | 38 | |
a0a301fc DE |
39 | /* TARGET_ARCH{32,64} are the main macros to decide which of the two |
40 | architectures to compile for. We allow targets to choose compile time or | |
41 | runtime selection. */ | |
959eb758 | 42 | #ifdef IN_LIBGCC2 |
afdac905 | 43 | #if defined(__sparcv9) || defined(__arch64__) |
959eb758 DM |
44 | #define TARGET_ARCH32 0 |
45 | #else | |
46 | #define TARGET_ARCH32 1 | |
afdac905 | 47 | #endif /* sparc64 */ |
959eb758 | 48 | #else |
53f4a9f6 | 49 | #ifdef SPARC_BI_ARCH |
7c7dae65 | 50 | #define TARGET_ARCH32 (!TARGET_64BIT) |
a0a301fc DE |
51 | #else |
52 | #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
959eb758 | 53 | #endif /* SPARC_BI_ARCH */ |
53f4a9f6 | 54 | #endif /* IN_LIBGCC2 */ |
7c7dae65 | 55 | #define TARGET_ARCH64 (!TARGET_ARCH32) |
a0a301fc | 56 | |
ed38d6fe EB |
57 | /* Code model selection in 64-bit environment. |
58 | ||
59 | The machine mode used for addresses is 32-bit wide: | |
60 | ||
61 | TARGET_CM_32: 32-bit address space. | |
62 | It is the code model used when generating 32-bit code. | |
63 | ||
64 | The machine mode used for addresses is 64-bit wide: | |
65 | ||
66 | TARGET_CM_MEDLOW: 32-bit address space. | |
67 | The executable must be in the low 32 bits of memory. | |
68 | This avoids generating %uhi and %ulo terms. Programs | |
69 | can be statically or dynamically linked. | |
70 | ||
71 | TARGET_CM_MEDMID: 44-bit address space. | |
72 | The executable must be in the low 44 bits of memory, | |
73 | and the %[hml]44 terms are used. The text and data | |
74 | segments have a maximum size of 2GB (31-bit span). | |
75 | The maximum offset from any instruction to the label | |
76 | _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
77 | ||
78 | TARGET_CM_MEDANY: 64-bit address space. | |
79 | The text and data segments have a maximum size of 2GB | |
80 | (31-bit span) and may be located anywhere in memory. | |
81 | The maximum offset from any instruction to the label | |
82 | _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
83 | ||
84 | TARGET_CM_EMBMEDANY: 64-bit address space. | |
85 | The text and data segments have a maximum size of 2GB | |
86 | (31-bit span) and may be located anywhere in memory. | |
87 | The global register %g4 contains the start address of | |
88 | the data segment. Programs are statically linked and | |
89 | PIC is not supported. | |
90 | ||
91 | Different code models are not supported in 32-bit environment. */ | |
a0a301fc | 92 | |
1405bf4c EB |
93 | #define TARGET_CM_MEDLOW (sparc_code_model == CM_MEDLOW) |
94 | #define TARGET_CM_MEDMID (sparc_code_model == CM_MEDMID) | |
95 | #define TARGET_CM_MEDANY (sparc_code_model == CM_MEDANY) | |
96 | #define TARGET_CM_EMBMEDANY (sparc_code_model == CM_EMBMEDANY) | |
a0a301fc | 97 | |
1405bf4c | 98 | /* Default code model to be overridden in 64-bit environment. */ |
a330e73b | 99 | #define SPARC_DEFAULT_CMODEL CM_32 |
6f64bf5f | 100 | |
5e77eb53 EB |
101 | /* Do not use the .note.GNU-stack convention by default. */ |
102 | #define NEED_INDICATE_EXEC_STACK 0 | |
103 | ||
a0a301fc DE |
104 | /* This is call-clobbered in the normal ABI, but is reserved in the |
105 | home grown (aka upward compatible) embedded ABI. */ | |
106 | #define EMBMEDANY_BASE_REG "%g4" | |
107 | \f | |
108 | /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
109 | and specified by the user via --with-cpu=foo. | |
110 | This specifies the cpu implementation, not the architecture size. */ | |
3aabf9a5 | 111 | /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit |
8947065c | 112 | capable cpu's. */ |
2163f11b | 113 | #define TARGET_CPU_sparc 0 |
07981468 KE |
114 | #define TARGET_CPU_v7 0 /* alias */ |
115 | #define TARGET_CPU_cypress 0 /* alias */ | |
116 | #define TARGET_CPU_v8 1 /* generic v8 implementation */ | |
117 | #define TARGET_CPU_supersparc 2 | |
118 | #define TARGET_CPU_hypersparc 3 | |
119 | #define TARGET_CPU_leon 4 | |
38ae58ca | 120 | #define TARGET_CPU_leon3 5 |
d81230b5 DH |
121 | #define TARGET_CPU_leon3v7 6 |
122 | #define TARGET_CPU_sparclite 7 | |
123 | #define TARGET_CPU_f930 7 /* alias */ | |
124 | #define TARGET_CPU_f934 7 /* alias */ | |
125 | #define TARGET_CPU_sparclite86x 8 | |
126 | #define TARGET_CPU_sparclet 9 | |
127 | #define TARGET_CPU_tsc701 9 /* alias */ | |
128 | #define TARGET_CPU_v9 10 /* generic v9 implementation */ | |
129 | #define TARGET_CPU_sparcv9 10 /* alias */ | |
130 | #define TARGET_CPU_sparc64 10 /* alias */ | |
131 | #define TARGET_CPU_ultrasparc 11 | |
132 | #define TARGET_CPU_ultrasparc3 12 | |
133 | #define TARGET_CPU_niagara 13 | |
134 | #define TARGET_CPU_niagara2 14 | |
135 | #define TARGET_CPU_niagara3 15 | |
136 | #define TARGET_CPU_niagara4 16 | |
690f24b7 | 137 | #define TARGET_CPU_niagara7 19 |
bcc3c3f1 | 138 | #define TARGET_CPU_m8 20 |
bafb031b | 139 | |
8947065c | 140 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ |
fae15c93 | 141 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ |
4c837a1e | 142 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ |
9eeaed6e | 143 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ |
3e64c239 DM |
144 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ |
145 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ | |
690f24b7 | 146 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ |
bcc3c3f1 JM |
147 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ |
148 | || TARGET_CPU_DEFAULT == TARGET_CPU_m8 | |
345a6161 DM |
149 | |
150 | #define CPP_CPU32_DEFAULT_SPEC "" | |
151 | #define ASM_CPU32_DEFAULT_SPEC "" | |
152 | ||
a0a301fc | 153 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 |
bafb031b | 154 | /* ??? What does Sun's CC pass? */ |
345a6161 | 155 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
bafb031b DE |
156 | /* ??? It's not clear how other assemblers will handle this, so by default |
157 | use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
158 | is handled in sol2.h. */ | |
345a6161 | 159 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" |
bafb031b | 160 | #endif |
a0a301fc | 161 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc |
345a6161 DM |
162 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
163 | #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
164 | #endif | |
fae15c93 VM |
165 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 |
166 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
167 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
168 | #endif | |
4c837a1e DM |
169 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara |
170 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
171 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
172 | #endif | |
9eeaed6e DM |
173 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 |
174 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
175 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
176 | #endif | |
3e64c239 DM |
177 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 |
178 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
e8b141b5 | 179 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG |
3e64c239 DM |
180 | #endif |
181 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 | |
182 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
8b98b5fd | 183 | #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG |
3e64c239 | 184 | #endif |
690f24b7 JM |
185 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 |
186 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
187 | #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG | |
188 | #endif | |
bcc3c3f1 JM |
189 | #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 |
190 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
191 | #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG | |
192 | #endif | |
345a6161 DM |
193 | |
194 | #else | |
195 | ||
196 | #define CPP_CPU64_DEFAULT_SPEC "" | |
197 | #define ASM_CPU64_DEFAULT_SPEC "" | |
198 | ||
8947065c RH |
199 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ |
200 | || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
345a6161 DM |
201 | #define CPP_CPU32_DEFAULT_SPEC "" |
202 | #define ASM_CPU32_DEFAULT_SPEC "" | |
203 | #endif | |
8947065c | 204 | |
345a6161 DM |
205 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet |
206 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
207 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
bafb031b | 208 | #endif |
8947065c | 209 | |
345a6161 DM |
210 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite |
211 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
212 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
213 | #endif | |
214 | ||
07981468 KE |
215 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x |
216 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" | |
217 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
218 | #endif | |
219 | ||
8947065c RH |
220 | #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc |
221 | #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
222 | #define ASM_CPU32_DEFAULT_SPEC "" | |
223 | #endif | |
224 | ||
225 | #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
226 | #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
227 | #define ASM_CPU32_DEFAULT_SPEC "" | |
228 | #endif | |
229 | ||
38ae58ca EB |
230 | #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ |
231 | || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 | |
07981468 | 232 | #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" |
1f65ae7a | 233 | #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG |
8947065c RH |
234 | #endif |
235 | ||
d81230b5 DH |
236 | #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 |
237 | #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" | |
238 | #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG | |
239 | #endif | |
240 | ||
345a6161 DM |
241 | #endif |
242 | ||
243 | #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
3aabf9a5 | 244 | #error Unrecognized value in TARGET_CPU_DEFAULT. |
bafb031b DE |
245 | #endif |
246 | ||
345a6161 DM |
247 | #ifdef SPARC_BI_ARCH |
248 | ||
249 | #define CPP_CPU_DEFAULT_SPEC \ | |
250 | (DEFAULT_ARCH32_P ? "\ | |
251 | %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
252 | %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
253 | " : "\ | |
254 | %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
255 | %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
256 | ") | |
257 | #define ASM_CPU_DEFAULT_SPEC \ | |
258 | (DEFAULT_ARCH32_P ? "\ | |
259 | %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
260 | %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
261 | " : "\ | |
262 | %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
263 | %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
264 | ") | |
265 | ||
266 | #else /* !SPARC_BI_ARCH */ | |
267 | ||
268 | #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
269 | #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
270 | ||
271 | #endif /* !SPARC_BI_ARCH */ | |
272 | ||
885d8175 | 273 | /* Define macros to distinguish architectures. */ |
857458c4 | 274 | |
bafb031b DE |
275 | /* Common CPP definitions used by CPP_SPEC amongst the various targets |
276 | for handling -mcpu=xxx switches. */ | |
277 | #define CPP_CPU_SPEC "\ | |
9b7c06d2 | 278 | %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ |
bafb031b DE |
279 | %{mcpu=sparclite:-D__sparclite__} \ |
280 | %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
07981468 | 281 | %{mcpu=sparclite86x:-D__sparclite86x__} \ |
bafb031b DE |
282 | %{mcpu=v8:-D__sparc_v8__} \ |
283 | %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
8947065c | 284 | %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ |
07981468 | 285 | %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ |
38ae58ca | 286 | %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ |
d81230b5 | 287 | %{mcpu=leon3v7:-D__leon__} \ |
bafb031b DE |
288 | %{mcpu=v9:-D__sparc_v9__} \ |
289 | %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
fae15c93 | 290 | %{mcpu=ultrasparc3:-D__sparc_v9__} \ |
4c837a1e | 291 | %{mcpu=niagara:-D__sparc_v9__} \ |
9eeaed6e | 292 | %{mcpu=niagara2:-D__sparc_v9__} \ |
3e64c239 DM |
293 | %{mcpu=niagara3:-D__sparc_v9__} \ |
294 | %{mcpu=niagara4:-D__sparc_v9__} \ | |
690f24b7 | 295 | %{mcpu=niagara7:-D__sparc_v9__} \ |
bcc3c3f1 | 296 | %{mcpu=m8:-D__sparc_v9__} \ |
3a7b4385 | 297 | %{!mcpu*:%(cpp_cpu_default)} \ |
7a6cf439 | 298 | " |
9b8466f4 NB |
299 | #define CPP_ARCH32_SPEC "" |
300 | #define CPP_ARCH64_SPEC "-D__arch64__" | |
345a6161 | 301 | |
a0a301fc DE |
302 | #define CPP_ARCH_DEFAULT_SPEC \ |
303 | (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
304 | ||
305 | #define CPP_ARCH_SPEC "\ | |
306 | %{m32:%(cpp_arch32)} \ | |
307 | %{m64:%(cpp_arch64)} \ | |
308 | %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
309 | " | |
310 | ||
b11b0904 EB |
311 | /* Macros to distinguish the endianness, window model and FP support. */ |
312 | #define CPP_OTHER_SPEC "\ | |
b11b0904 EB |
313 | %{mflat:-D_FLAT} \ |
314 | %{msoft-float:-D_SOFT_FLOAT} \ | |
315 | " | |
a0a301fc DE |
316 | |
317 | /* Macros to distinguish the particular subtarget. */ | |
318 | #define CPP_SUBTARGET_SPEC "" | |
319 | ||
b11b0904 EB |
320 | #define CPP_SPEC \ |
321 | "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" | |
a0a301fc | 322 | |
b1fc14e5 RS |
323 | /* This used to translate -dalign to -malign, but that is no good |
324 | because it can't turn off the usual meaning of making debugging dumps. */ | |
bafb031b | 325 | |
f2060fbe | 326 | #define CC1_SPEC "" |
bafb031b | 327 | |
bafb031b DE |
328 | /* Override in target specific files. */ |
329 | #define ASM_CPU_SPEC "\ | |
9b7c06d2 | 330 | %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ |
bafb031b | 331 | %{mcpu=sparclite:-Asparclite} \ |
8d72ec32 | 332 | %{mcpu=sparclite86x:-Asparclite} \ |
bafb031b | 333 | %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ |
a5c037e2 | 334 | %{mcpu=v8:-Av8} \ |
89deeb3b DM |
335 | %{mcpu=supersparc:-Av8} \ |
336 | %{mcpu=hypersparc:-Av8} \ | |
1f65ae7a EB |
337 | %{mcpu=leon:" AS_LEON_FLAG "} \ |
338 | %{mcpu=leon3:" AS_LEON_FLAG "} \ | |
d81230b5 | 339 | %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ |
284d86e9 | 340 | %{mv8plus:-Av8plus} \ |
bafb031b | 341 | %{mcpu=v9:-Av9} \ |
284d86e9 | 342 | %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ |
fae15c93 | 343 | %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ |
4c837a1e | 344 | %{mcpu=niagara:%{!mv8plus:-Av9b}} \ |
9eeaed6e | 345 | %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ |
e8b141b5 | 346 | %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ |
8b98b5fd | 347 | %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ |
690f24b7 | 348 | %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ |
bcc3c3f1 | 349 | %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ |
3a7b4385 | 350 | %{!mcpu*:%(asm_cpu_default)} \ |
bafb031b DE |
351 | " |
352 | ||
e632a26c DE |
353 | /* Word size selection, among other things. |
354 | This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
355 | ||
a0a301fc | 356 | #define ASM_ARCH32_SPEC "-32" |
6149cebb | 357 | #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" |
a0a301fc | 358 | #define ASM_ARCH_DEFAULT_SPEC \ |
e632a26c | 359 | (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) |
a0a301fc DE |
360 | |
361 | #define ASM_ARCH_SPEC "\ | |
362 | %{m32:%(asm_arch32)} \ | |
363 | %{m64:%(asm_arch64)} \ | |
364 | %{!m32:%{!m64:%(asm_arch_default)}} \ | |
365 | " | |
366 | ||
e95b1e6a JJ |
367 | #ifdef HAVE_AS_RELAX_OPTION |
368 | #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" | |
369 | #else | |
370 | #define ASM_RELAX_SPEC "" | |
371 | #endif | |
372 | ||
a0a301fc DE |
373 | /* Special flags to the Sun-4 assembler when using pipe for input. */ |
374 | ||
375 | #define ASM_SPEC "\ | |
428b3812 | 376 | %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ |
e95b1e6a | 377 | %(asm_cpu) %(asm_relax)" |
a0a301fc | 378 | |
bafb031b DE |
379 | /* This macro defines names of additional specifications to put in the specs |
380 | that can be used in various specifications like CC1_SPEC. Its definition | |
381 | is an initializer with a subgrouping for each command option. | |
382 | ||
383 | Each subgrouping contains a string constant, that defines the | |
7ec022b2 | 384 | specification name, and a string constant that used by the GCC driver |
bafb031b DE |
385 | program. |
386 | ||
387 | Do not define this macro if it does not need to do anything. */ | |
1bb87f28 | 388 | |
a0a301fc | 389 | #define EXTRA_SPECS \ |
829245be KG |
390 | { "cpp_cpu", CPP_CPU_SPEC }, \ |
391 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
392 | { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
393 | { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
394 | { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
395 | { "cpp_arch", CPP_ARCH_SPEC }, \ | |
b11b0904 | 396 | { "cpp_other", CPP_OTHER_SPEC }, \ |
829245be KG |
397 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ |
398 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
399 | { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
400 | { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
401 | { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
e95b1e6a | 402 | { "asm_relax", ASM_RELAX_SPEC }, \ |
829245be KG |
403 | { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ |
404 | { "asm_arch", ASM_ARCH_SPEC }, \ | |
bafb031b | 405 | SUBTARGET_EXTRA_SPECS |
1bb87f28 | 406 | |
bafb031b | 407 | #define SUBTARGET_EXTRA_SPECS |
bbd7687d DM |
408 | |
409 | /* Because libgcc can generate references back to libc (via .umul etc.) we have | |
410 | to list libc again after the second libgcc. */ | |
f37866e8 | 411 | #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L} %G %{!nolibc:%L}" |
bbd7687d | 412 | |
bafb031b | 413 | \f |
82d6b402 RH |
414 | #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") |
415 | #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
7a6cf439 DE |
416 | |
417 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
418 | #define WCHAR_TYPE "short unsigned int" |
419 | #define WCHAR_TYPE_SIZE 16 | |
7a6cf439 | 420 | \f |
bafb031b | 421 | /* Mask of all CPU selection flags. */ |
938a807a EB |
422 | #define MASK_ISA \ |
423 | (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ | |
aa47faf0 | 424 | + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) |
6f64bf5f | 425 | |
938a807a EB |
426 | /* Mask of all CPU feature flags. */ |
427 | #define MASK_FEATURES \ | |
428 | (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ | |
867ba4b9 SH |
429 | + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ |
430 | + MASK_POPC + MASK_SUBXC) | |
938a807a | 431 | |
aa47faf0 EB |
432 | /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ |
433 | #define TARGET_HARD_MUL \ | |
434 | (TARGET_SPARCLITE || TARGET_SPARCLET \ | |
435 | || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) | |
bfd6bc60 | 436 | |
aa47faf0 EB |
437 | /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y |
438 | to get high 32 bits. False in 64-bit or V8+ because multiply stores | |
439 | a 64-bit result in a register. */ | |
440 | #define TARGET_HARD_MUL32 \ | |
441 | (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) | |
bfd6bc60 | 442 | |
bafb031b DE |
443 | /* MASK_APP_REGS must always be the default because that's what |
444 | FIXED_REGISTERS is set to and -ffixed- is processed before | |
5efd84c5 NF |
445 | TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process |
446 | -mno-app-regs). */ | |
33074e5f | 447 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) |
84ab3bfb | 448 | |
6afca97d DE |
449 | /* Recast the cpu class to be the cpu attribute. |
450 | Every file includes us, but not every file includes insn-attr.h. */ | |
451 | #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
bafb031b | 452 | |
7816bea0 DJ |
453 | /* Support for a compile-time default CPU, et cetera. The rules are: |
454 | --with-cpu is ignored if -mcpu is specified. | |
455 | --with-tune is ignored if -mtune is specified. | |
456 | --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu | |
457 | are specified. */ | |
458 | #define OPTION_DEFAULT_SPECS \ | |
459 | {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
460 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
c6869789 | 461 | {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } |
7a6cf439 DE |
462 | \f |
463 | /* target machine storage layout */ | |
464 | ||
1bb87f28 JW |
465 | /* Define this if most significant bit is lowest numbered |
466 | in instructions that operate on numbered bit-fields. */ | |
467 | #define BITS_BIG_ENDIAN 1 | |
468 | ||
469 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
1bb87f28 JW |
470 | #define BYTES_BIG_ENDIAN 1 |
471 | ||
472 | /* Define this if most significant word of a multiword number is the lowest | |
473 | numbered. */ | |
1bb87f28 JW |
474 | #define WORDS_BIG_ENDIAN 1 |
475 | ||
7a6cf439 | 476 | #define MAX_BITS_PER_WORD 64 |
1bb87f28 JW |
477 | |
478 | /* Width of a word, in units (bytes). */ | |
6f64bf5f | 479 | #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) |
8b156b3e JJ |
480 | #ifdef IN_LIBGCC2 |
481 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
482 | #else | |
ef0e53ce | 483 | #define MIN_UNITS_PER_WORD 4 |
8b156b3e | 484 | #endif |
7a6cf439 DE |
485 | |
486 | /* Now define the sizes of the C data types. */ | |
7a6cf439 | 487 | #define SHORT_TYPE_SIZE 16 |
a0a301fc DE |
488 | #define INT_TYPE_SIZE 32 |
489 | #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
7a6cf439 DE |
490 | #define LONG_LONG_TYPE_SIZE 64 |
491 | #define FLOAT_TYPE_SIZE 32 | |
492 | #define DOUBLE_TYPE_SIZE 64 | |
a2cd689a | 493 | |
9e1395f1 JM |
494 | /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the |
495 | SPARC ABI says that it is 128-bit wide. */ | |
496 | /* #define LONG_DOUBLE_TYPE_SIZE 128 */ | |
1bb87f28 | 497 | |
a2cd689a EB |
498 | /* The widest floating-point format really supported by the hardware. */ |
499 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
500 | ||
baa48dfa | 501 | /* Width in bits of a pointer. This is the size of ptr_mode. */ |
7a6cf439 | 502 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 | 503 | |
baa48dfa PB |
504 | /* This is the machine mode used for addresses. */ |
505 | #define Pmode (TARGET_ARCH64 ? DImode : SImode) | |
506 | ||
3276910d RK |
507 | /* If we have to extend pointers (only when TARGET_ARCH64 and not |
508 | TARGET_PTR64), we want to do it unsigned. This macro does nothing | |
509 | if ptr_mode and Pmode are the same. */ | |
510 | #define POINTERS_EXTEND_UNSIGNED 1 | |
511 | ||
1bb87f28 | 512 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
6f64bf5f | 513 | #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
514 | |
515 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
a594a19c | 516 | /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because |
2358ff91 | 517 | then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ |
6f64bf5f | 518 | #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) |
eaac029f | 519 | |
2358ff91 | 520 | /* Temporary hack until the FIXME above is fixed. */ |
a594a19c | 521 | #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) |
1bb87f28 | 522 | |
10d1b70f | 523 | /* ALIGN FRAMES on double word boundaries */ |
63b8ef40 | 524 | #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) |
10d1b70f | 525 | |
1bb87f28 | 526 | /* Allocation boundary (in *bits*) for the code of a function. */ |
efa3896a | 527 | #define FUNCTION_BOUNDARY 32 |
1bb87f28 JW |
528 | |
529 | /* Alignment of field after `int : 0' in a structure. */ | |
6f64bf5f | 530 | #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
531 | |
532 | /* Every structure's size must be a multiple of this. */ | |
533 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
534 | ||
43a88a8c | 535 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
1bb87f28 JW |
536 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
537 | ||
538 | /* No data type wants to be aligned rounder than this. */ | |
6f64bf5f | 539 | #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 540 | |
77a02b01 JW |
541 | /* The best alignment to use in cases where we have a choice. */ |
542 | #define FASTEST_ALIGNMENT 64 | |
543 | ||
c219ddf7 BK |
544 | /* Define this macro as an expression for the alignment of a structure |
545 | (given by STRUCT as a tree node) if the alignment computed in the | |
546 | usual way is COMPUTED and the alignment explicitly specified was | |
547 | SPECIFIED. | |
548 | ||
549 | The default is to use SPECIFIED if it is larger; otherwise, use | |
550 | the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ | |
551 | #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ | |
552 | (TARGET_FASTER_STRUCTS ? \ | |
553 | ((TREE_CODE (STRUCT) == RECORD_TYPE \ | |
554 | || TREE_CODE (STRUCT) == UNION_TYPE \ | |
555 | || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ | |
556 | && TYPE_FIELDS (STRUCT) != 0 \ | |
557 | ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ | |
558 | : MAX ((COMPUTED), (SPECIFIED))) \ | |
559 | : MAX ((COMPUTED), (SPECIFIED))) | |
560 | ||
59e08d4f EB |
561 | /* An integer expression for the size in bits of the largest integer machine |
562 | mode that should actually be used. We allow pairs of registers. */ | |
563 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) | |
564 | ||
0a222ba7 EB |
565 | /* We need 2 words, so we can save the stack pointer and the return register |
566 | of the function containing a non-local goto target. */ | |
567 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
568 | ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) | |
569 | ||
1bb87f28 JW |
570 | /* Make arrays of chars word-aligned for the same reasons. */ |
571 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
572 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
573 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 574 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 575 | |
9eb061d7 AL |
576 | /* Make local arrays of chars word-aligned for the same reasons. */ |
577 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) | |
578 | ||
b4ac57ab | 579 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 580 | when given unaligned data. */ |
b4ac57ab | 581 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
582 | |
583 | /* Things that must be doubleword aligned cannot go in the text section, | |
584 | because the linker fails to align the text section enough! | |
7a6cf439 | 585 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 | 586 | #define MAX_TEXT_ALIGN 32 |
1bb87f28 JW |
587 | \f |
588 | /* Standard register usage. */ | |
589 | ||
590 | /* Number of actual hardware registers. | |
591 | The hardware registers are assigned numbers for the compiler | |
592 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
593 | All registers that the compiler knows about must be given numbers, | |
594 | even those that are not normally considered general registers. | |
595 | ||
7a6cf439 | 596 | SPARC has 32 integer registers and 32 floating point registers. |
a7b376ee | 597 | 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not |
7a6cf439 | 598 | accessible. We still account for them to simplify register computations |
112cdef5 | 599 | (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so |
7a6cf439 | 600 | 32+32+32+4 == 100. |
563c12b0 | 601 | Register 100 is used as the integer condition code register. |
490a6733 EB |
602 | Register 101 is used as the soft frame pointer register. |
603 | Register 102 is used as the general status register by VIS instructions. */ | |
1bb87f28 | 604 | |
10b859c0 | 605 | #define FIRST_PSEUDO_REGISTER 103 |
6afca97d | 606 | |
5a53588f DM |
607 | #define SPARC_FIRST_INT_REG 0 |
608 | #define SPARC_LAST_INT_REG 31 | |
4fb4e4b8 | 609 | #define SPARC_FIRST_FP_REG 32 |
6afca97d | 610 | /* Additional V9 fp regs. */ |
4fb4e4b8 DE |
611 | #define SPARC_FIRST_V9_FP_REG 64 |
612 | #define SPARC_LAST_V9_FP_REG 95 | |
c4ce6853 DE |
613 | /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ |
614 | #define SPARC_FIRST_V9_FCC_REG 96 | |
615 | #define SPARC_LAST_V9_FCC_REG 99 | |
616 | /* V8 fcc reg. */ | |
617 | #define SPARC_FCC_REG 96 | |
618 | /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
619 | #define SPARC_ICC_REG 100 | |
10b859c0 | 620 | #define SPARC_GSR_REG 102 |
1bb87f28 | 621 | |
4fb4e4b8 DE |
622 | /* Nonzero if REGNO is an fp reg. */ |
623 | #define SPARC_FP_REG_P(REGNO) \ | |
624 | ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
625 | ||
5a53588f DM |
626 | /* Nonzero if REGNO is an int reg. */ |
627 | #define SPARC_INT_REG_P(REGNO) \ | |
628 | (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) | |
629 | ||
4fb4e4b8 DE |
630 | /* Argument passing regs. */ |
631 | #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
b11b0904 | 632 | #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) |
4fb4e4b8 DE |
633 | #define SPARC_FP_ARG_FIRST 32 |
634 | ||
1bb87f28 JW |
635 | /* 1 for registers that have pervasive standard uses |
636 | and are not available for the register allocator. | |
4fb4e4b8 | 637 | |
7a6cf439 | 638 | On non-v9 systems: |
34ad7aaf JW |
639 | g1 is free to use as temporary. |
640 | g2-g4 are reserved for applications. Gcc normally uses them as | |
641 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 | 642 | g5 through g7 are reserved for the operating system. |
4fb4e4b8 | 643 | |
7a6cf439 | 644 | On v9 systems: |
a0a301fc DE |
645 | g1,g5 are free to use as temporaries, and are free to use between calls |
646 | if the call is to an external function via the PLT. | |
647 | g4 is free to use as a temporary in the non-embedded case. | |
648 | g4 is reserved in the embedded case. | |
4fb4e4b8 | 649 | g2-g3 are reserved for applications. Gcc normally uses them as |
bafb031b | 650 | temporaries, but this can be disabled via the -mno-app-regs option. |
a0a301fc DE |
651 | g6-g7 are reserved for the operating system (or application in |
652 | embedded case). | |
7a6cf439 DE |
653 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must |
654 | currently be a fixed register until this pattern is rewritten. | |
655 | Register 1 is also used when restoring call-preserved registers in large | |
6afca97d DE |
656 | stack frames. |
657 | ||
658 | Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
5efd84c5 | 659 | TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. |
6afca97d | 660 | */ |
7a6cf439 | 661 | |
7a6cf439 | 662 | #define FIXED_REGISTERS \ |
e48addee | 663 | {1, 0, 2, 2, 2, 2, 1, 1, \ |
7a6cf439 DE |
664 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
665 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
b11b0904 | 666 | 0, 0, 0, 0, 0, 0, 0, 1, \ |
7a6cf439 DE |
667 | \ |
668 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
669 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
670 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
671 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
672 | \ | |
673 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
674 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
675 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
676 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
677 | \ | |
490a6733 | 678 | 0, 0, 0, 0, 1, 1, 1} |
1bb87f28 | 679 | |
9250444b EB |
680 | /* 1 for registers not available across function calls. |
681 | Unlike the above, this need not include the FIXED_REGISTERS, but any | |
682 | registers that can be used without being saved. | |
683 | The latter must include the registers where values are returned | |
684 | and the register where structure-value addresses are passed. | |
685 | Aside from that, you can include as many other registers as you like. */ | |
686 | ||
687 | #define CALL_REALLY_USED_REGISTERS \ | |
688 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
689 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
690 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
691 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
692 | \ | |
693 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
694 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
695 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
696 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
697 | \ | |
698 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
699 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
700 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
bafb031b DE |
701 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
702 | \ | |
10b859c0 | 703 | 1, 1, 1, 1, 1, 1, 1} |
1bb87f28 | 704 | |
fae778eb | 705 | /* Due to the ARCH64 discrepancy above we must override this next |
ec8e621d | 706 | macro too. */ |
98ccb32d | 707 | #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) |
284d86e9 | 708 | |
e31a1967 EB |
709 | /* Value is 1 if it is OK to rename a hard register FROM to another hard |
710 | register TO. We cannot rename %g1 as it may be used before the save | |
711 | register window instruction in the prologue. */ | |
712 | #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) | |
713 | ||
9ba43127 EB |
714 | /* Select a register mode required for caller save of hard regno REGNO. |
715 | Contrary to what is documented, the default is not the smallest suitable | |
716 | mode but the largest suitable mode for the given (REGNO, NREGS) pair and | |
717 | it quickly creates paradoxical subregs that can be problematic. */ | |
718 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
ba8fa8da | 719 | ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) |
9ba43127 | 720 | |
1bb87f28 JW |
721 | /* Specify the registers used for certain standard purposes. |
722 | The values of these macros are register numbers. */ | |
723 | ||
1bb87f28 JW |
724 | /* Register to use for pushing function arguments. */ |
725 | #define STACK_POINTER_REGNUM 14 | |
726 | ||
563c12b0 RH |
727 | /* The stack bias (amount by which the hardware register is offset by). */ |
728 | #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) | |
729 | ||
4fb4e4b8 | 730 | /* Actual top-of-stack address is 92/176 greater than the contents of the |
7a6cf439 DE |
731 | stack pointer register for !v9/v9. That is: |
732 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
4fb4e4b8 DE |
733 | address, and 6*4 bytes for the 6 register parameters. |
734 | - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
735 | parameter regs. */ | |
563c12b0 | 736 | #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) |
1ccfa253 | 737 | |
1bb87f28 | 738 | /* Base register for access to local variables of the function. */ |
563c12b0 RH |
739 | #define HARD_FRAME_POINTER_REGNUM 30 |
740 | ||
741 | /* The soft frame pointer does not have the stack bias applied. */ | |
742 | #define FRAME_POINTER_REGNUM 101 | |
743 | ||
563c12b0 RH |
744 | #define INIT_EXPANDERS \ |
745 | do { \ | |
b9f92c0b | 746 | if (crtl->emit.regno_pointer_align) \ |
563c12b0 | 747 | { \ |
b9f92c0b EB |
748 | /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\ |
749 | if (SPARC_STACK_BIAS) \ | |
750 | { \ | |
751 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \ | |
752 | = BITS_PER_UNIT; \ | |
753 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \ | |
754 | = BITS_PER_UNIT; \ | |
755 | } \ | |
756 | \ | |
757 | /* In 32-bit mode, not everything is double-word aligned. */ \ | |
758 | if (TARGET_ARCH32) \ | |
759 | { \ | |
760 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \ | |
761 | = BITS_PER_WORD; \ | |
762 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \ | |
763 | = BITS_PER_WORD; \ | |
764 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \ | |
765 | = BITS_PER_WORD; \ | |
766 | } \ | |
563c12b0 RH |
767 | } \ |
768 | } while (0) | |
1bb87f28 | 769 | |
1bb87f28 | 770 | /* Base register for access to arguments of the function. */ |
5c56efde | 771 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 772 | |
6098b63e | 773 | /* Register in which static-chain is passed to a function. This must |
c8392688 | 774 | not be a register used by the prologue. */ |
6f64bf5f | 775 | #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) |
1bb87f28 | 776 | |
a6fed83f | 777 | /* Register which holds the global offset table, if any. */ |
a6fed83f EB |
778 | #define GLOBAL_OFFSET_TABLE_REGNUM 23 |
779 | ||
46336a0e EB |
780 | /* Register which holds offset table for position-independent data references. |
781 | The original SPARC ABI imposes no requirement on the choice of the register | |
782 | so we use a pseudo-register to make sure it is properly saved and restored | |
783 | around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry | |
784 | to PLT entries so we use the canonical GOT register in this case. */ | |
a6fed83f | 785 | #define PIC_OFFSET_TABLE_REGNUM \ |
46336a0e | 786 | (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) |
1bb87f28 | 787 | |
82d6b402 RH |
788 | /* Pick a default value we can notice from override_options: |
789 | !v9: Default is on. | |
7a946186 AT |
790 | v9: Default is off. |
791 | Originally it was -1, but later on the container of options changed to | |
792 | unsigned byte, so we decided to pick 127 as default value, which does | |
793 | reflect an undefined default value in case of 0/1. */ | |
7a946186 | 794 | #define DEFAULT_PCC_STRUCT_RETURN 127 |
82d6b402 | 795 | |
1bb87f28 JW |
796 | /* Functions which return large structures get the address |
797 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
798 | Must reserve 64 bytes for the in and local registers. |
799 | v9: Functions which return large structures get the address to place the | |
800 | wanted value from an invisible first argument. */ | |
1bb87f28 | 801 | #define STRUCT_VALUE_OFFSET 64 |
1bb87f28 JW |
802 | \f |
803 | /* Define the classes of registers for register constraints in the | |
804 | machine description. Also define ranges of constants. | |
805 | ||
806 | One of the classes must always be named ALL_REGS and include all hard regs. | |
807 | If there is more than one class, another class must be named NO_REGS | |
808 | and contain no registers. | |
809 | ||
810 | The name GENERAL_REGS must be the name of a class (or an alias for | |
811 | another name such as ALL_REGS). This is the class of registers | |
812 | that is allowed by "g" or "r" in a register constraint. | |
813 | Also, registers outside this class are allocated only when | |
814 | instructions express preferences for them. | |
815 | ||
816 | The classes must be numbered in nondecreasing order; that is, | |
817 | a larger-numbered class must never be contained completely | |
818 | in a smaller-numbered class. | |
819 | ||
820 | For any two classes, it is very desirable that there be another | |
821 | class that represents their union. */ | |
822 | ||
4fb4e4b8 DE |
823 | /* The SPARC has various kinds of registers: general, floating point, |
824 | and condition codes [well, it has others as well, but none that we | |
825 | care directly about]. | |
24b63396 JW |
826 | |
827 | For v9 we must distinguish between the upper and lower floating point | |
828 | registers because the upper ones can't hold SFmode values. | |
f939c3e6 RS |
829 | TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that |
830 | register(s) satisfying a group need for a class will also satisfy a | |
831 | single need for that class. EXTRA_FP_REGS is a bit of a misnomer as | |
832 | it covers all 64 fp regs. | |
24b63396 JW |
833 | |
834 | It is important that one class contains all the general and all the standard | |
835 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
836 | because reg_class_record() will bias the selection in favor of fp regs, | |
837 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
838 | because FP_REGS > GENERAL_REGS. | |
839 | ||
107a4b41 NS |
840 | It is also important that one class contain all the general and all |
841 | the fp regs. Otherwise when spilling a DFmode reg, it may be from | |
842 | EXTRA_FP_REGS but find_reloads() may use class | |
843 | GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die | |
844 | because the compiler thinks it doesn't have a spill reg when in | |
845 | fact it does. | |
24b63396 | 846 | |
7a6cf439 DE |
847 | v9 also has 4 floating point condition code registers. Since we don't |
848 | have a class that is the union of FPCC_REGS with either of the others, | |
849 | it is important that it appear first. Otherwise the compiler will die | |
850 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
490a6733 | 851 | constraints. */ |
7a6cf439 | 852 | |
284d86e9 JC |
853 | enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, |
854 | EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 | 855 | ALL_REGS, LIM_REG_CLASSES }; |
1bb87f28 JW |
856 | |
857 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
858 | ||
80ffc95e | 859 | /* Give names of register classes as strings for dump file. */ |
1bb87f28 JW |
860 | |
861 | #define REG_CLASS_NAMES \ | |
284d86e9 JC |
862 | { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ |
863 | "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
864 | "ALL_REGS" } | |
1bb87f28 JW |
865 | |
866 | /* Define which registers fit in which classes. | |
867 | This is an initializer for a vector of HARD_REG_SET | |
868 | of length N_REG_CLASSES. */ | |
869 | ||
563c12b0 RH |
870 | #define REG_CLASS_CONTENTS \ |
871 | {{0, 0, 0, 0}, /* NO_REGS */ \ | |
872 | {0, 0, 0, 0xf}, /* FPCC_REGS */ \ | |
873 | {0xffff, 0, 0, 0}, /* I64_REGS */ \ | |
874 | {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ | |
875 | {0, -1, 0, 0}, /* FP_REGS */ \ | |
876 | {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ | |
877 | {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ | |
878 | {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ | |
10b859c0 | 879 | {-1, -1, -1, 0x7f}} /* ALL_REGS */ |
1bb87f28 | 880 | |
948bf106 EB |
881 | /* The same information, inverted: |
882 | Return the class number of the smallest class containing | |
883 | reg number REGNO. This could be a conditional expression | |
884 | or could index an array. */ | |
885 | ||
886 | extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
887 | ||
888 | #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] | |
889 | ||
3aabf9a5 EC |
890 | /* This is the order in which to allocate registers normally. |
891 | ||
af54350e | 892 | We put %f0-%f7 last among the float registers, so as to make it more |
6a4bb1fa | 893 | likely that a pseudo-register which dies in the float return register |
af54350e DM |
894 | area will get allocated to the float return register, thus saving a move |
895 | instruction at the end of the function. | |
896 | ||
897 | Similarly for integer return value registers. | |
898 | ||
899 | We know in this case that we will not end up with a leaf function. | |
900 | ||
fae778eb | 901 | The register allocator is given the global and out registers first |
af54350e DM |
902 | because these registers are call clobbered and thus less useful to |
903 | global register allocation. | |
904 | ||
905 | Next we list the local and in registers. They are not call clobbered | |
906 | and thus very useful for global register allocation. We list the input | |
907 | registers before the locals so that it is more likely the incoming | |
908 | arguments received in those registers can just stay there and not be | |
909 | reloaded. */ | |
6afca97d | 910 | |
7a6cf439 | 911 | #define REG_ALLOC_ORDER \ |
af54350e DM |
912 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
913 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
914 | 15, /* %o7 */ \ | |
915 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
916 | 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ | |
7a6cf439 | 917 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ |
7a6cf439 DE |
918 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ |
919 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
920 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
921 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
4fb4e4b8 DE |
922 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ |
923 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
af54350e DM |
924 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ |
925 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
10b859c0 | 926 | 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ |
1bb87f28 JW |
927 | |
928 | /* This is the order in which to allocate registers for | |
af54350e DM |
929 | leaf functions. If all registers can fit in the global and |
930 | output registers, then we have the possibility of having a leaf | |
931 | function. | |
932 | ||
933 | The macro actually mentioned the input registers first, | |
934 | because they get renumbered into the output registers once | |
935 | we know really do have a leaf function. | |
936 | ||
937 | To be more precise, this register allocation order is used | |
938 | when %o7 is found to not be clobbered right before register | |
939 | allocation. Normally, the reason %o7 would be clobbered is | |
940 | due to a call which could not be transformed into a sibling | |
941 | call. | |
942 | ||
943 | As a consequence, it is possible to use the leaf register | |
944 | allocation order and not end up with a leaf function. We will | |
945 | not get suboptimal register allocation in that case because by | |
946 | definition of being potentially leaf, there were no function | |
947 | calls. Therefore, allocation order within the local register | |
948 | window is not critical like it is when we do have function calls. */ | |
6afca97d | 949 | |
7a6cf439 | 950 | #define REG_LEAF_ALLOC_ORDER \ |
af54350e DM |
951 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
952 | 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ | |
953 | 15, /* %o7 */ \ | |
954 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
955 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
956 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
957 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
958 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
959 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
960 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
961 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
962 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
963 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
964 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
10b859c0 | 965 | 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ |
3aabf9a5 | 966 | |
5a733826 | 967 | #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () |
1bb87f28 | 968 | |
7d167afd JJ |
969 | extern char sparc_leaf_regs[]; |
970 | #define LEAF_REGISTERS sparc_leaf_regs | |
1bb87f28 | 971 | |
d70e94ec | 972 | extern char leaf_reg_remap[]; |
1bb87f28 | 973 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) |
1bb87f28 | 974 | |
1bb87f28 JW |
975 | /* The class value for index registers, and the one for base regs. */ |
976 | #define INDEX_REG_CLASS GENERAL_REGS | |
977 | #define BASE_REG_CLASS GENERAL_REGS | |
978 | ||
24b63396 | 979 | /* Local macro to handle the two v9 classes of FP regs. */ |
24b63396 | 980 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) |
24b63396 | 981 | |
bcc3c3f1 JM |
982 | /* Predicate for 2-bit and 5-bit unsigned constants. */ |
983 | #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) | |
984 | #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) | |
985 | ||
8b98b5fd DM |
986 | /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ |
987 | #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) | |
1ccfa253 DE |
988 | #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) |
989 | #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
990 | #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
0e5d569c EB |
991 | |
992 | /* 10- and 11-bit immediates are only used for a few specific insns. | |
18c5947f DE |
993 | SMALL_INT is used throughout the port so we continue to use it. */ |
994 | #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
0e5d569c EB |
995 | |
996 | /* Predicate for constants that can be loaded with a sethi instruction. | |
997 | This is the general, 64-bit aware, bitwise version that ensures that | |
998 | only constants whose representation fits in the mask | |
999 | ||
1000 | 0x00000000fffffc00 | |
1001 | ||
1002 | are accepted. It will reject, for example, negative SImode constants | |
1003 | on 64-bit hosts, so correct handling is to mask the value beforehand | |
1004 | according to the mode of the instruction. */ | |
1ccfa253 | 1005 | #define SPARC_SETHI_P(X) \ |
7d6040e8 AO |
1006 | (((unsigned HOST_WIDE_INT) (X) \ |
1007 | & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) | |
0e5d569c EB |
1008 | |
1009 | /* Version of the above predicate for SImode constants and below. */ | |
7d6040e8 AO |
1010 | #define SPARC_SETHI32_P(X) \ |
1011 | (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) | |
1bb87f28 | 1012 | |
1bb87f28 JW |
1013 | /* Return the maximum number of consecutive registers |
1014 | needed to represent mode MODE in a register of class CLASS. */ | |
1015 | /* On SPARC, this is the size of MODE in words. */ | |
1016 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1017 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1018 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1019 | \f |
1020 | /* Stack layout; function entry, exit and calling. */ | |
1021 | ||
1bb87f28 JW |
1022 | /* Define this if pushing a word on the stack |
1023 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1024 | #define STACK_GROWS_DOWNWARD 1 |
1bb87f28 | 1025 | |
a4d05547 | 1026 | /* Define this to nonzero if the nominal address of the stack frame |
1bb87f28 JW |
1027 | is at the high-address end of the local variables; |
1028 | that is, each additional local variable allocated | |
1029 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1030 | #define FRAME_GROWS_DOWNWARD 1 |
1bb87f28 | 1031 | |
1bb87f28 | 1032 | /* Offset of first parameter from the argument pointer register value. |
7a6cf439 DE |
1033 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1034 | even if this function isn't going to use it. | |
4fb4e4b8 | 1035 | v9: This is 128 for the ins and locals. */ |
7a6cf439 | 1036 | #define FIRST_PARM_OFFSET(FNDECL) \ |
563c12b0 | 1037 | (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) |
1bb87f28 | 1038 | |
2c849145 JM |
1039 | /* Offset from the argument pointer register value to the CFA. |
1040 | This is different from FIRST_PARM_OFFSET because the register window | |
1041 | comes between the CFA and the arguments. */ | |
c2c9f6c9 | 1042 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 |
71038426 | 1043 | |
1bb87f28 | 1044 | /* When a parameter is passed in a register, stack space is still |
82d6b402 RH |
1045 | allocated for it. |
1046 | !v9: All 6 possible integer registers have backing store allocated. | |
80ffc95e | 1047 | v9: Only space for the arguments passed is allocated. */ |
82d6b402 RH |
1048 | /* ??? Ideally, we'd use zero here (as the minimum), but zero has special |
1049 | meaning to the backend. Further, we need to be able to detect if a | |
1050 | varargs/unprototyped function is called, as they may want to spill more | |
1051 | registers than we've provided space. Ugly, ugly. So for now we retain | |
1052 | all 6 slots even for v9. */ | |
4fb4e4b8 | 1053 | #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) |
1bb87f28 | 1054 | |
563c12b0 | 1055 | /* Definitions for register elimination. */ |
3aabf9a5 | 1056 | |
563c12b0 | 1057 | #define ELIMINABLE_REGS \ |
e387e99b JJ |
1058 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
1059 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } | |
563c12b0 | 1060 | |
9e6a4b77 SB |
1061 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1062 | do \ | |
1063 | { \ | |
1064 | (OFFSET) = sparc_initial_elimination_offset ((TO)); \ | |
1065 | } \ | |
1066 | while (0) | |
563c12b0 | 1067 | |
1bb87f28 | 1068 | /* Keep the stack pointer constant throughout the function. |
b4ac57ab | 1069 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1070 | doesn't behave itself when the stack pointer moves within |
1071 | the function! */ | |
f73ad30e | 1072 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1bb87f28 | 1073 | |
92ea370b TW |
1074 | /* Define this macro if the target machine has "register windows". This |
1075 | C expression returns the register number as seen by the called function | |
1076 | corresponding to register number OUT as seen by the calling function. | |
1077 | Return OUT if register number OUT is not an outbound register. */ | |
1078 | ||
1079 | #define INCOMING_REGNO(OUT) \ | |
b11b0904 | 1080 | ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
92ea370b TW |
1081 | |
1082 | /* Define this macro if the target machine has "register windows". This | |
1083 | C expression returns the register number as seen by the calling function | |
1084 | corresponding to register number IN as seen by the called function. | |
1085 | Return IN if register number IN is not an inbound register. */ | |
1086 | ||
1087 | #define OUTGOING_REGNO(IN) \ | |
b11b0904 | 1088 | ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
92ea370b | 1089 | |
2a3e384f RH |
1090 | /* Define this macro if the target machine has register windows. This |
1091 | C expression returns true if the register is call-saved but is in the | |
1092 | register window. */ | |
1093 | ||
1094 | #define LOCAL_REGNO(REGNO) \ | |
b11b0904 | 1095 | (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) |
2a3e384f | 1096 | |
34aaacec JW |
1097 | /* Define the size of space to allocate for the return value of an |
1098 | untyped_call. */ | |
1099 | ||
d24088cc | 1100 | #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) |
34aaacec | 1101 | |
1bb87f28 | 1102 | /* 1 if N is a possible register number for function argument passing. |
4fb4e4b8 | 1103 | On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ |
1bb87f28 | 1104 | |
7a6cf439 | 1105 | #define FUNCTION_ARG_REGNO_P(N) \ |
9e3b2fe3 EB |
1106 | (((N) >= 8 && (N) <= 13) \ |
1107 | || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) | |
1bb87f28 JW |
1108 | \f |
1109 | /* Define a data type for recording info about an argument list | |
1110 | during the scan of that argument list. This data type should | |
1111 | hold all necessary information about the function itself | |
1112 | and about the args processed so far, enough to enable macros | |
1113 | such as FUNCTION_ARG to determine where the next arg should go. | |
1114 | ||
7a6cf439 | 1115 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1116 | of arguments scanned so far (including the invisible argument, |
1117 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1118 | Thus 7 or more means all following args should go on the stack. |
1119 | ||
4fb4e4b8 | 1120 | For v9, we also need to know whether a prototype is present. */ |
7a6cf439 | 1121 | |
7a6cf439 | 1122 | struct sparc_args { |
4fb4e4b8 | 1123 | int words; /* number of words passed so far */ |
5e7a8ee0 KH |
1124 | int prototype_p; /* nonzero if a prototype is present */ |
1125 | int libcall_p; /* nonzero if a library call */ | |
7a6cf439 DE |
1126 | }; |
1127 | #define CUMULATIVE_ARGS struct sparc_args | |
1128 | ||
1bb87f28 JW |
1129 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1130 | for a call to a function whose data type is FNTYPE. | |
4fb4e4b8 | 1131 | For a library call, FNTYPE is 0. */ |
1bb87f28 | 1132 | |
0f6937fe | 1133 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1134 | init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); |
1bb87f28 | 1135 | |
1bb87f28 | 1136 | \f |
4b69d2a3 RS |
1137 | /* Generate the special assembly code needed to tell the assembler whatever |
1138 | it might need to know about the return value of a function. | |
1139 | ||
56149abc | 1140 | For SPARC assemblers, we need to output a .proc pseudo-op which conveys |
4b69d2a3 RS |
1141 | information to the assembler relating to peephole optimization (done in |
1142 | the assembler). */ | |
1143 | ||
1144 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
4f70758f | 1145 | fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) |
4b69d2a3 | 1146 | |
1cb36a98 | 1147 | /* Output the special assembly code needed to tell the assembler some |
3aabf9a5 | 1148 | register is used as global register variable. |
730f0207 JJ |
1149 | |
1150 | SPARC 64bit psABI declares registers %g2 and %g3 as application | |
1151 | registers and %g6 and %g7 as OS registers. Any object using them | |
1152 | should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them | |
1153 | and how they are used (scratch or some global variable). | |
1154 | Linker will then refuse to link together objects which use those | |
1155 | registers incompatibly. | |
1156 | ||
1157 | Unless the registers are used for scratch, two different global | |
1158 | registers cannot be declared to the same name, so in the unlikely | |
1159 | case of a global register variable occupying more than one register | |
1160 | we prefix the second and following registers with .gnu.part1. etc. */ | |
1161 | ||
94fcbf65 | 1162 | extern GTY(()) char sparc_hard_reg_printed[8]; |
1cb36a98 | 1163 | |
1cb36a98 RH |
1164 | #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ |
1165 | do { \ | |
1166 | if (TARGET_ARCH64) \ | |
1167 | { \ | |
4edd6298 | 1168 | int end = end_hard_regno (DECL_MODE (decl), REGNO); \ |
730f0207 JJ |
1169 | int reg; \ |
1170 | for (reg = (REGNO); reg < 8 && reg < end; reg++) \ | |
1171 | if ((reg & ~1) == 2 || (reg & ~1) == 6) \ | |
1cb36a98 | 1172 | { \ |
730f0207 JJ |
1173 | if (reg == (REGNO)) \ |
1174 | fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ | |
1cb36a98 RH |
1175 | else \ |
1176 | fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
730f0207 JJ |
1177 | reg, reg - (REGNO), (NAME)); \ |
1178 | sparc_hard_reg_printed[reg] = 1; \ | |
1cb36a98 RH |
1179 | } \ |
1180 | } \ | |
1181 | } while (0) | |
c4ce6853 | 1182 | \f |
89a8b315 RH |
1183 | /* Emit rtl for profiling. */ |
1184 | #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) | |
6f334f44 | 1185 | |
89a8b315 RH |
1186 | /* All the work done in PROFILE_HOOK, but still required. */ |
1187 | #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) | |
1bb87f28 | 1188 | |
2be15d0f | 1189 | /* Set the name of the mcount function for the system. */ |
2be15d0f | 1190 | #define MCOUNT_FUNCTION "*mcount" |
c4ce6853 | 1191 | \f |
1bb87f28 JW |
1192 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1193 | the stack pointer does not matter. The value is tested only in | |
b11b0904 EB |
1194 | functions that have frame pointers. */ |
1195 | #define EXIT_IGNORE_STACK 1 | |
1bb87f28 | 1196 | |
1bb87f28 | 1197 | /* Length in units of the trampoline for entering a nested function. */ |
c6b0465b JC |
1198 | #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) |
1199 | ||
bc6d3f91 | 1200 | /* Alignment required for trampolines, in bits. */ |
bc6d3f91 | 1201 | #define TRAMPOLINE_ALIGNMENT 128 |
6a4bb1fa | 1202 | \f |
953fe179 JW |
1203 | /* Generate RTL to flush the register windows so as to make arbitrary frames |
1204 | available. */ | |
b11b0904 EB |
1205 | #define SETUP_FRAME_ADDRESSES() \ |
1206 | do { \ | |
1207 | if (!TARGET_FLAT) \ | |
1208 | emit_insn (gen_flush_register_windows ());\ | |
1209 | } while (0) | |
953fe179 JW |
1210 | |
1211 | /* Given an rtx for the address of a frame, | |
1212 | return an rtx for the address of the word in the frame | |
60b85c4c | 1213 | that holds the dynamic chain--the previous frame's address. */ |
8773135d | 1214 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
0a81f074 | 1215 | plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) |
953fe179 | 1216 | |
224869d9 EB |
1217 | /* Given an rtx for the frame pointer, |
1218 | return an rtx for the address of the frame. */ | |
0a81f074 | 1219 | #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) |
224869d9 | 1220 | |
953fe179 JW |
1221 | /* The return address isn't on the stack, it is in a register, so we can't |
1222 | access it from the current frame pointer. We can access it from the | |
1223 | previous frame pointer though by reading a value from the register window | |
1224 | save area. */ | |
2e612c47 | 1225 | #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 |
953fe179 | 1226 | |
5b6faa70 | 1227 | /* This is the offset of the return address to the true next instruction to be |
80ffc95e | 1228 | executed for the current function. */ |
6f64bf5f | 1229 | #define RETURN_ADDR_OFFSET \ |
e3b5732b | 1230 | (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) |
5b6faa70 | 1231 | |
953fe179 JW |
1232 | /* The current return address is in %i7. The return address of anything |
1233 | farther back is in the register window save area at [%fp+60]. */ | |
1234 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
1235 | returns, and +12 for structure returns. */ | |
b11b0904 | 1236 | #define RETURN_ADDR_REGNUM 31 |
953fe179 JW |
1237 | #define RETURN_ADDR_RTX(count, frame) \ |
1238 | ((count == -1) \ | |
b11b0904 | 1239 | ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ |
284d86e9 | 1240 | : gen_rtx_MEM (Pmode, \ |
0a81f074 | 1241 | memory_address (Pmode, plus_constant (Pmode, frame, \ |
cd49f073 AM |
1242 | 15 * UNITS_PER_WORD \ |
1243 | + SPARC_STACK_BIAS)))) | |
9704efe6 | 1244 | |
d60bee3a DE |
1245 | /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's |
1246 | +12, but always using +8 is close enough for frame unwind purposes. | |
1247 | Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
1248 | is something you can return to. */ | |
b11b0904 | 1249 | #define INCOMING_RETURN_ADDR_REGNUM 15 |
d60bee3a | 1250 | #define INCOMING_RETURN_ADDR_RTX \ |
0a81f074 RS |
1251 | plus_constant (word_mode, \ |
1252 | gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) | |
b11b0904 EB |
1253 | #define DWARF_FRAME_RETURN_COLUMN \ |
1254 | DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) | |
d60bee3a DE |
1255 | |
1256 | /* The offset from the incoming value of %sp to the top of the stack frame | |
1257 | for the current function. On sparc64, we have to account for the stack | |
1258 | bias if present. */ | |
1259 | #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
1260 | ||
1150a841 | 1261 | /* Describe how we implement __builtin_eh_return. */ |
b11b0904 | 1262 | #define EH_RETURN_REGNUM 1 |
1150a841 | 1263 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) |
b11b0904 EB |
1264 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) |
1265 | ||
1266 | /* Define registers used by the epilogue and return instruction. */ | |
1267 | #define EPILOGUE_USES(REGNO) \ | |
1268 | ((REGNO) == RETURN_ADDR_REGNUM \ | |
1269 | || (TARGET_FLAT \ | |
1270 | && epilogue_completed \ | |
1271 | && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ | |
1272 | || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) | |
17e9e88c JJ |
1273 | |
1274 | /* Select a format to encode pointers in exception handling data. CODE | |
1275 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1276 | true if the symbol may be affected by dynamic relocations. | |
1277 | ||
1278 | If assembler and linker properly support .uaword %r_disp32(foo), | |
1279 | then use PC relative 32-bit relocations instead of absolute relocs | |
1280 | for shared libraries. On sparc64, use pc relative 32-bit relocs even | |
cf7b8b0d JJ |
1281 | for binaries, to save memory. |
1282 | ||
1283 | binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the | |
1284 | symbol %r_disp32() is against was not local, but .hidden. In that | |
1285 | case, we have to use DW_EH_PE_absptr for pic personality. */ | |
17e9e88c | 1286 | #ifdef HAVE_AS_SPARC_UA_PCREL |
cf7b8b0d | 1287 | #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN |
17e9e88c JJ |
1288 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ |
1289 | (flag_pic \ | |
1290 | ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ | |
1291 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1292 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1293 | : DW_EH_PE_absptr)) | |
cf7b8b0d JJ |
1294 | #else |
1295 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1296 | (flag_pic \ | |
1297 | ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ | |
1298 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1299 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1300 | : DW_EH_PE_absptr)) | |
1301 | #endif | |
17e9e88c JJ |
1302 | |
1303 | /* Emit a PC-relative relocation. */ | |
1304 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
1305 | do { \ | |
1306 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
1307 | fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ | |
1308 | assemble_name (FILE, LABEL); \ | |
1309 | fputc (')', FILE); \ | |
1310 | } while (0) | |
1311 | #endif | |
1bb87f28 JW |
1312 | \f |
1313 | /* Addressing modes, and classification of registers for them. */ | |
1314 | ||
1bb87f28 JW |
1315 | /* Macros to check register numbers against specific register classes. */ |
1316 | ||
1317 | /* These assume that REGNO is a hard or pseudo reg number. | |
1318 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1319 | or a pseudo reg currently allocated to a suitable hard reg. | |
1320 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1321 | has been allocated, which happens in reginfo.c during register |
1322 | allocation. */ | |
1bb87f28 JW |
1323 | |
1324 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
5a53588f DM |
1325 | (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ |
1326 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
563c12b0 RH |
1327 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) |
1328 | ||
1329 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
1330 | ||
1bb87f28 | 1331 | #define REGNO_OK_FOR_FP_P(REGNO) \ |
4f70758f KG |
1332 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ |
1333 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
0a222ba7 | 1334 | |
7a6cf439 DE |
1335 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ |
1336 | (TARGET_V9 \ | |
4f70758f KG |
1337 | && (((unsigned) (REGNO) - 96 < (unsigned)4) \ |
1338 | || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1bb87f28 JW |
1339 | \f |
1340 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1341 | ||
1342 | #define MAX_REGS_PER_ADDRESS 2 | |
1343 | ||
7aca9b9c JW |
1344 | /* Recognize any constant value that is a valid address. |
1345 | When PIC, we do not accept an address that would require a scratch reg | |
1346 | to load into a register. */ | |
1bb87f28 | 1347 | |
5751a10b | 1348 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
7aca9b9c JW |
1349 | |
1350 | /* Define this, so that when PIC, reload won't try to reload invalid | |
1351 | addresses which require two reload registers. */ | |
1352 | ||
5751a10b | 1353 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
1bb87f28 | 1354 | \f |
1cb36a98 RH |
1355 | /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ |
1356 | ||
1357 | #ifdef HAVE_AS_OFFSETABLE_LO10 | |
1358 | #define USE_AS_OFFSETABLE_LO10 1 | |
1359 | #else | |
1360 | #define USE_AS_OFFSETABLE_LO10 0 | |
1361 | #endif | |
1bb87f28 | 1362 | \f |
8947065c RH |
1363 | /* Try a machine-dependent way of reloading an illegitimate address |
1364 | operand. If we find one, push the reload and jump to WIN. This | |
58e6223e EB |
1365 | macro is used in only one place: `find_reloads_address' in reload.c. */ |
1366 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1367 | do { \ | |
1368 | int win; \ | |
1369 | (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
1370 | (int)(TYPE), (IND_LEVELS), &win); \ | |
1371 | if (win) \ | |
1372 | goto WIN; \ | |
8947065c | 1373 | } while (0) |
1bb87f28 JW |
1374 | \f |
1375 | /* Specify the machine mode that this machine uses | |
1376 | for the index in the tablejump instruction. */ | |
67cb8900 JJ |
1377 | /* If we ever implement any of the full models (such as CM_FULLANY), |
1378 | this has to be DImode in that case */ | |
d1accaa3 | 1379 | #ifdef HAVE_GAS_SUBSECTION_ORDERING |
67cb8900 JJ |
1380 | #define CASE_VECTOR_MODE \ |
1381 | (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
d1accaa3 JJ |
1382 | #else |
1383 | /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
80ffc95e | 1384 | we have to sign extend which slows things down. */ |
d1accaa3 JJ |
1385 | #define CASE_VECTOR_MODE \ |
1386 | (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1387 | #endif | |
1bb87f28 | 1388 | |
1bb87f28 JW |
1389 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1390 | #define DEFAULT_SIGNED_CHAR 1 | |
1391 | ||
1392 | /* Max number of bytes we can move from memory to memory | |
1393 | in one reasonably fast instruction. */ | |
2eef2ef1 | 1394 | #define MOVE_MAX 8 |
1bb87f28 | 1395 | |
5162e02a | 1396 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
76715c32 | 1397 | move-instruction pairs, we will do a cpymem or libcall instead. */ |
5162e02a | 1398 | |
e04ad03d | 1399 | #define MOVE_RATIO(speed) ((speed) ? 8 : 3) |
5162e02a | 1400 | |
9a63901f RK |
1401 | /* Define if operations between registers always perform the operation |
1402 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1403 | #define WORD_REGISTER_OPERATIONS 1 |
9a63901f RK |
1404 | |
1405 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1406 | will either zero-extend or sign-extend. The value of this macro should | |
1407 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1408 | done, UNKNOWN if none. */ |
9a63901f | 1409 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
1bb87f28 JW |
1410 | |
1411 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
1412 | For RISC chips, it means that access to memory by bytes is no | |
1413 | better than access by words when possible, so grab a whole word | |
1414 | and maybe make use of that. */ | |
1415 | #define SLOW_BYTE_ACCESS 1 | |
1416 | ||
d969caf8 | 1417 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
80ffc95e | 1418 | few bits. */ |
d969caf8 | 1419 | #define SHIFT_COUNT_TRUNCATED 1 |
1bb87f28 | 1420 | |
dc78280f DM |
1421 | /* For SImode, we make sure the top 32-bits of the register are clear and |
1422 | then we subtract 32 from the lzd instruction result. */ | |
1423 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1424 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) | |
1425 | ||
1bb87f28 | 1426 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
4d449554 | 1427 | return the mode to be used for the comparison. For floating-point, |
ff7e7ee0 | 1428 | CCFP[E]mode is used. CCNZmode should be used when the first operand |
7913f3d0 | 1429 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
922bd191 | 1430 | processing is needed. */ |
e267e177 | 1431 | #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) |
1bb87f28 | 1432 | |
5e7a8ee0 | 1433 | /* Return nonzero if MODE implies a floating point inequality can be |
56149abc | 1434 | reversed. For SPARC this is always true because we have a full |
46238b7d JJ |
1435 | compliment of ordered and unordered comparisons, but until generic |
1436 | code knows how to reverse it correctly we keep the old definition. */ | |
1437 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) | |
b331b745 | 1438 | |
3276910d RK |
1439 | /* A function address in a call instruction for indexing purposes. */ |
1440 | #define FUNCTION_MODE Pmode | |
1bb87f28 JW |
1441 | |
1442 | /* Define this if addresses of constant functions | |
1443 | shouldn't be put through pseudo regs where they can be cse'd. | |
1444 | Desirable on machines where ordinary constants are expensive | |
1445 | but a CALL with constant address is cheap. */ | |
1e8552c2 | 1446 | #define NO_FUNCTION_CSE 1 |
1bb87f28 | 1447 | |
c15c90bb ZW |
1448 | /* The _Q_* comparison libcalls return booleans. */ |
1449 | #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) | |
8248e2bc | 1450 | |
4e7d5d27 DM |
1451 | /* Assume by default that the _Qp_* 64-bit libcalls are implemented such |
1452 | that the inputs are fully consumed before the output memory is clobbered. */ | |
1453 | ||
1454 | #define TARGET_BUGGY_QP_LIB 0 | |
1455 | ||
c15c90bb ZW |
1456 | /* Assume by default that we do not have the Solaris-specific conversion |
1457 | routines nor 64-bit integer multiply and divide routines. */ | |
78e9b5df | 1458 | |
45dcc026 JJ |
1459 | #define SUN_CONVERSION_LIBFUNCS 0 |
1460 | #define DITF_CONVERSION_LIBFUNCS 0 | |
1461 | #define SUN_INTEGER_MULTIPLY_64 0 | |
c5c60e15 | 1462 | |
227efe87 EB |
1463 | /* A C expression for the cost of a branch instruction. A value of 1 |
1464 | is the default; other values are interpreted relative to that. */ | |
1465 | #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ | |
1466 | (sparc_branch_cost (SPEED_P, PREDICTABLE_P)) | |
1bb87f28 JW |
1467 | \f |
1468 | /* Control the assembler format that we output. */ | |
1469 | ||
1ccfa253 DE |
1470 | /* A C string constant describing how to begin a comment in the target |
1471 | assembler language. The compiler assumes that the comment will end at | |
1472 | the end of the line. */ | |
1473 | ||
1474 | #define ASM_COMMENT_START "!" | |
1475 | ||
1bb87f28 JW |
1476 | /* Output to assembler file text saying following lines |
1477 | may contain character constants, extra white space, comments, etc. */ | |
1478 | ||
1479 | #define ASM_APP_ON "" | |
1480 | ||
1481 | /* Output to assembler file text saying following lines | |
1482 | no longer contain unusual constructs. */ | |
1483 | ||
1484 | #define ASM_APP_OFF "" | |
1485 | ||
1bb87f28 JW |
1486 | /* How to refer to registers in assembler output. |
1487 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1488 | ||
7a6cf439 DE |
1489 | #define REGISTER_NAMES \ |
1490 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
1491 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
1492 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
1493 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
1494 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
1495 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
1496 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
1497 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
1498 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
1499 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
1500 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
1501 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
10b859c0 | 1502 | "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } |
ea3fa5f7 | 1503 | |
c4ce6853 | 1504 | /* Define additional names for use in asm clobbers and asm declarations. */ |
ea3fa5f7 | 1505 | |
c4ce6853 DE |
1506 | #define ADDITIONAL_REGISTER_NAMES \ |
1507 | {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
ea3fa5f7 | 1508 | |
5bcb3f13 JM |
1509 | /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length |
1510 | can run past this up to a continuation point. Once we used 1500, but | |
1511 | a single entry in C++ can run more than 500 bytes, due to the length of | |
1512 | mangled symbol names. dbxout.c should really be fixed to do | |
1513 | continuations when they are actually needed instead of trying to | |
1514 | guess... */ | |
1515 | #define DBX_CONTIN_LENGTH 1000 | |
1bb87f28 | 1516 | |
1bb87f28 JW |
1517 | /* This is how to output a command to make the user-level label named NAME |
1518 | defined for reference from other files. */ | |
1519 | ||
506a61b1 KG |
1520 | /* Globalizing directive for a label. */ |
1521 | #define GLOBAL_ASM_OP "\t.global " | |
1bb87f28 | 1522 | |
80ffc95e | 1523 | /* The prefix to add to user-visible assembler symbols. */ |
1bb87f28 | 1524 | |
4e0c8ad2 | 1525 | #define USER_LABEL_PREFIX "_" |
1bb87f28 | 1526 | |
1bb87f28 JW |
1527 | /* This is how to store into the string LABEL |
1528 | the symbol_ref name of an internal numbered label where | |
1529 | PREFIX is the class of label and NUM is the number within the class. | |
1530 | This is suitable for output with `assemble_name'. */ | |
1531 | ||
1532 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
4f70758f | 1533 | sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) |
1bb87f28 | 1534 | |
e0d80184 DM |
1535 | /* This is how we hook in and defer the case-vector until the end of |
1536 | the function. */ | |
e0d80184 DM |
1537 | #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ |
1538 | sparc_defer_case_vector ((LAB),(VEC), 0) | |
1539 | ||
1540 | #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
1541 | sparc_defer_case_vector ((LAB),(VEC), 1) | |
1542 | ||
1bb87f28 JW |
1543 | /* This is how to output an element of a case-vector that is absolute. */ |
1544 | ||
1545 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
1546 | do { \ |
1547 | char label[30]; \ | |
1548 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
67cb8900 | 1549 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 1550 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
1551 | else \ |
1552 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 1553 | assemble_name (FILE, label); \ |
e0d80184 | 1554 | fputc ('\n', FILE); \ |
4b69d2a3 | 1555 | } while (0) |
1bb87f28 JW |
1556 | |
1557 | /* This is how to output an element of a case-vector that is relative. | |
1558 | (SPARC uses such vectors only when generating PIC.) */ | |
1559 | ||
33f7f353 | 1560 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
4b69d2a3 RS |
1561 | do { \ |
1562 | char label[30]; \ | |
e0d80184 | 1563 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ |
67cb8900 | 1564 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 1565 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
1566 | else \ |
1567 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 1568 | assemble_name (FILE, label); \ |
e0d80184 DM |
1569 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ |
1570 | fputc ('-', FILE); \ | |
1571 | assemble_name (FILE, label); \ | |
1572 | fputc ('\n', FILE); \ | |
4b69d2a3 | 1573 | } while (0) |
1bb87f28 | 1574 | |
d1accaa3 JJ |
1575 | /* This is what to output before and after case-vector (both |
1576 | relative and absolute). If .subsection -1 works, we put case-vectors | |
1577 | at the beginning of the current section. */ | |
1578 | ||
1579 | #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
1580 | ||
1581 | #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
1582 | fprintf(FILE, "\t.subsection\t-1\n") | |
1583 | ||
1584 | #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
1585 | fprintf(FILE, "\t.previous\n") | |
1586 | ||
1587 | #endif | |
1588 | ||
1bb87f28 JW |
1589 | /* This is how to output an assembler line |
1590 | that says to advance the location counter | |
1591 | to a multiple of 2**LOG bytes. */ | |
1592 | ||
1593 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1594 | if ((LOG) != 0) \ | |
3f1a2e57 | 1595 | fprintf (FILE, "\t.align %d\n", (1 << (LOG))) |
1bb87f28 JW |
1596 | |
1597 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
16998094 | 1598 | fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
1bb87f28 JW |
1599 | |
1600 | /* This says how to output an assembler line | |
1601 | to define a global common symbol. */ | |
1602 | ||
1603 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 1604 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 1605 | assemble_name ((FILE), (NAME)), \ |
16998094 | 1606 | fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) |
1bb87f28 | 1607 | |
b277ceaf JW |
1608 | /* This says how to output an assembler line to define a local common |
1609 | symbol. */ | |
1bb87f28 | 1610 | |
b277ceaf JW |
1611 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
1612 | ( fputs ("\t.reserve ", (FILE)), \ | |
1613 | assemble_name ((FILE), (NAME)), \ | |
16998094 | 1614 | fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ |
b277ceaf | 1615 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) |
1bb87f28 | 1616 | |
101d9529 JM |
1617 | /* A C statement (sans semicolon) to output to the stdio stream |
1618 | FILE the assembler definition of uninitialized global DECL named | |
1619 | NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
1620 | Try to use asm_output_aligned_bss to implement this macro. */ | |
1621 | ||
1622 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1623 | do { \ | |
101d9529 JM |
1624 | ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ |
1625 | } while (0) | |
1626 | ||
c14f2655 RS |
1627 | /* Output #ident as a .ident. */ |
1628 | ||
a8781821 SB |
1629 | #undef TARGET_ASM_OUTPUT_IDENT |
1630 | #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive | |
c14f2655 | 1631 | |
4e5b002b EB |
1632 | /* Prettify the assembly. */ |
1633 | ||
1634 | extern int sparc_indent_opcode; | |
1635 | ||
1636 | #define ASM_OUTPUT_OPCODE(FILE, PTR) \ | |
1637 | do { \ | |
1638 | if (sparc_indent_opcode) \ | |
1639 | { \ | |
1640 | putc (' ', FILE); \ | |
1641 | sparc_indent_opcode = 0; \ | |
1642 | } \ | |
1643 | } while (0) | |
1644 | ||
fdbe66f2 EB |
1645 | /* TLS support defaulting to original Sun flavor. GNU extensions |
1646 | must be activated in separate configuration files. */ | |
5751a10b JJ |
1647 | #ifdef HAVE_AS_TLS |
1648 | #define TARGET_TLS 1 | |
1649 | #else | |
1650 | #define TARGET_TLS 0 | |
1651 | #endif | |
fdbe66f2 | 1652 | |
5751a10b JJ |
1653 | #define TARGET_SUN_TLS TARGET_TLS |
1654 | #define TARGET_GNU_TLS 0 | |
1655 | ||
5b1efcb7 | 1656 | #ifdef HAVE_AS_FMAF_HPC_VIS3 |
e8b141b5 | 1657 | #define AS_NIAGARA3_FLAG "d" |
5b1efcb7 EB |
1658 | #else |
1659 | #define AS_NIAGARA3_FLAG "b" | |
e8b141b5 DM |
1660 | #endif |
1661 | ||
8b98b5fd DM |
1662 | #ifdef HAVE_AS_SPARC4 |
1663 | #define AS_NIAGARA4_FLAG "-xarch=sparc4" | |
1664 | #else | |
1665 | #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG | |
1666 | #endif | |
1667 | ||
690f24b7 JM |
1668 | #ifdef HAVE_AS_SPARC5_VIS4 |
1669 | #define AS_NIAGARA7_FLAG "-xarch=sparc5" | |
1670 | #else | |
1671 | #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG | |
1672 | #endif | |
1673 | ||
bcc3c3f1 JM |
1674 | #ifdef HAVE_AS_SPARC6 |
1675 | #define AS_M8_FLAG "-xarch=sparc6" | |
1676 | #else | |
1677 | #define AS_M8_FLAG AS_NIAGARA7_FLAG | |
1678 | #endif | |
1679 | ||
1f65ae7a EB |
1680 | #ifdef HAVE_AS_LEON |
1681 | #define AS_LEON_FLAG "-Aleon" | |
d81230b5 | 1682 | #define AS_LEONV7_FLAG "-Aleon" |
1f65ae7a EB |
1683 | #else |
1684 | #define AS_LEON_FLAG "-Av8" | |
d81230b5 | 1685 | #define AS_LEONV7_FLAG "-Av7" |
1f65ae7a EB |
1686 | #endif |
1687 | ||
c5fcd670 AT |
1688 | /* We use gcc _mcount for profiling. */ |
1689 | #define NO_PROFILE_COUNTERS 0 | |
a0bd60d1 DM |
1690 | |
1691 | /* Debug support */ | |
1692 | #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ | |
1693 | #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS | |
1694 | ||
1695 | #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) | |
6cc7fb90 RH |
1696 | |
1697 | /* By default, use the weakest memory model for the cpu. */ | |
1698 | #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL | |
1699 | #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT | |
1700 | #endif | |
fde66fde EB |
1701 | |
1702 | /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ | |
1703 | #define SPARC_LOW_FE_EXCEPT_VALUES 0 | |
eaac029f EB |
1704 | |
1705 | #define TARGET_SUPPORTS_WIDE_INT 1 |