1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2023 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; -------------------------------------------------------------------
23 ;; -------------------------------------------------------------------
25 ;; Condition-code iterators.
26 (define_mode_iterator CC_ONLY [CC])
27 (define_mode_iterator CCFP_CCFPE [CCFP CCFPE])
29 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
30 (define_mode_iterator GPI [SI DI])
32 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
33 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
35 ;; "Iterator" for just TI -- features like @pattern only work with iterators.
36 (define_mode_iterator JUST_TI [TI])
38 ;; Iterator for QI and HI modes
39 (define_mode_iterator SHORT [QI HI])
41 ;; Iterators for single modes, for "@" patterns.
42 (define_mode_iterator SI_ONLY [SI])
43 (define_mode_iterator DI_ONLY [DI])
45 ;; Iterator for all integer modes (up to 64-bit)
46 (define_mode_iterator ALLI [QI HI SI DI])
48 ;; Iterator for all integer modes (up to 128-bit)
49 (define_mode_iterator ALLI_TI [QI HI SI DI TI])
51 ;; Iterator for all integer modes that can be extended (up to 64-bit)
52 (define_mode_iterator ALLX [QI HI SI])
54 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
55 (define_mode_iterator GPF [SF DF])
57 ;; Iterator for all scalar floating point modes (HF, SF, DF)
58 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
60 ;; Iterator for all scalar floating point modes (HF, SF, DF)
61 (define_mode_iterator GPF_HF [HF SF DF])
63 ;; Iterator for all 16-bit scalar floating point modes (HF, BF)
64 (define_mode_iterator HFBF [HF BF])
66 ;; Iterator for all scalar floating point modes suitable for moving, including
67 ;; special BF type and decimal floating point types (HF, SF, DF, TF, BF,
69 (define_mode_iterator GPF_TF_F16_MOV [HF BF SF DF TF SD DD TD])
71 ;; Iterator for scalar 32bit fp modes (SF, SD)
72 (define_mode_iterator SFD [SD SF])
74 ;; Iterator for scalar 64bit fp modes (DF, DD)
75 (define_mode_iterator DFD [DD DF])
77 ;; Iterator for scalar 128bit fp modes (TF, TD)
78 (define_mode_iterator TFD [TD TF])
80 ;; Double vector modes.
81 (define_mode_iterator VDF [V2SF V4HF])
83 ;; Iterator for all scalar floating point modes (SF, DF, TF, SD, DD, and TD)
84 (define_mode_iterator GPF_TF [SF DF TF SD DD TD])
86 ;; Integer Advanced SIMD modes.
87 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
89 ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
90 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
92 ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
93 ;; integer modes; 64-bit scalar integer mode.
94 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
96 ;; Double vector modes.
97 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF V4BF])
99 ;; Double vector modes suitable for moving. Includes BFmode.
100 (define_mode_iterator VDMOV [V8QI V4HI V4HF V4BF V2SI V2SF])
102 ;; All modes stored in registers d0-d31.
103 (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
105 ;; Copy of the above.
106 (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
108 ;; All modes suitable to store/load pair (2 elements) using STP/LDP.
109 (define_mode_iterator VP_2E [V2SI V2SF V2DI V2DF])
111 ;; Advanced SIMD, 64-bit container, all integer modes.
112 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
114 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
115 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
117 ;; Quad vector modes.
118 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF])
120 ;; Copy of the above.
121 (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF])
123 ;; Quad vector modes suitable for moving. Includes BFmode.
124 (define_mode_iterator VQMOV [V16QI V8HI V4SI V2DI V8HF V8BF V4SF V2DF])
126 ;; VQMOV without 2-element modes.
127 (define_mode_iterator VQMOV_NO2E [V16QI V8HI V4SI V8HF V8BF V4SF])
129 ;; Double integer vector modes.
130 (define_mode_iterator VD_I [V8QI V4HI V2SI DI])
132 ;; Quad integer vector modes.
133 (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
135 ;; VQ without 2 element modes.
136 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF V8BF])
138 ;; 2 element quad vector modes.
139 (define_mode_iterator VQ_2E [V2DI V2DF])
141 ;; BFmode vector modes.
142 (define_mode_iterator VBF [V4BF V8BF])
144 ;; This mode iterator allows :P to be used for patterns that operate on
145 ;; addresses in different modes. In LP64, only DI will match, while in
146 ;; ILP32, either can match.
147 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
148 (DI "ptr_mode == DImode || Pmode == DImode")])
150 ;; This mode iterator allows :PTR to be used for patterns that operate on
151 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
152 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
154 ;; Advanced SIMD Float modes suitable for moving, loading and storing.
155 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF
158 ;; Advanced SIMD Float modes.
159 (define_mode_iterator VDQF [V2SF V4SF V2DF])
160 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
161 (V8HF "TARGET_SIMD_F16INST")
164 ;; Advanced SIMD Float modes, and DF.
165 (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
166 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
167 (V8HF "TARGET_SIMD_F16INST")
169 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
170 (V8HF "TARGET_SIMD_F16INST")
172 (HF "TARGET_SIMD_F16INST")
175 ;; Scalar and vetor modes for SF, DF.
176 (define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
178 ;; Advanced SIMD single Float modes.
179 (define_mode_iterator VDQSF [V2SF V4SF])
181 ;; Quad vector Float modes with half/single elements.
182 (define_mode_iterator VQ_HSF [V8HF V4SF])
184 ;; Modes suitable to use as the return type of a vcond expression.
185 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
187 ;; All scalar and Advanced SIMD Float modes.
188 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
190 ;; Advanced SIMD Float modes with 2 elements.
191 (define_mode_iterator V2F [V2SF V2DF])
193 ;; All Advanced SIMD modes on which we support any arithmetic operations.
194 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
196 ;; All Advanced SIMD modes suitable for moving, loading, and storing.
197 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
198 V4HF V8HF V4BF V8BF V2SF V4SF V2DF])
200 ;; The VALL_F16 modes except the 128-bit 2-element ones.
201 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
202 V4HF V8HF V2SF V4SF])
204 ;; All Advanced SIMD modes barring HF modes, plus DI.
205 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
207 ;; All Advanced SIMD modes and DI.
208 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
209 V4HF V8HF V4BF V8BF V2SF V4SF V2DF DI])
211 ;; All Advanced SIMD modes, plus DI and DF.
212 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI V4BF V8BF
213 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
215 ;; All Advanced SIMD polynomial modes and DI.
216 (define_mode_iterator VALLP [V8QI V16QI V4HI V8HI V2DI DI])
218 ;; All Advanced SIMD polynomial modes.
219 (define_mode_iterator VALLP_NO_DI [V8QI V16QI V4HI V8HI V2DI])
221 ;; Advanced SIMD modes for Integer reduction across lanes.
222 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
224 ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
225 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
227 ;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended).
228 (define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI])
230 ;; Advanced SIMD modes for Integer widening reduction across lanes.
231 (define_mode_iterator VDQV_L [V8QI V16QI V4HI V8HI V4SI V2SI])
233 ;; All double integer narrow-able modes.
234 (define_mode_iterator VDN [V4HI V2SI DI])
236 ;; All quad integer narrow-able modes.
237 (define_mode_iterator VQN [V8HI V4SI V2DI])
239 ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
241 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
243 ;; All quad integer widen-able modes.
244 (define_mode_iterator VQW [V16QI V8HI V4SI])
246 ;; Double vector modes for combines.
247 (define_mode_iterator VDC [V8QI V4HI V4BF V4HF V2SI V2SF DI DF])
249 ;; VDC plus SI and SF.
250 (define_mode_iterator VDCSIF [V8QI V4HI V4BF V4HF V2SI V2SF SI SF DI DF])
252 ;; Polynomial modes for vector combines.
253 (define_mode_iterator VDC_P [V8QI V4HI DI])
255 ;; Advanced SIMD modes except double int.
256 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
257 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
258 V4HF V8HF V2SF V4SF V2DF])
260 ;; Advanced SIMD modes for S type.
261 (define_mode_iterator VDQ_SI [V2SI V4SI])
263 ;; Advanced SIMD modes for S and D.
264 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
266 ;; Advanced SIMD modes for H, S and D.
267 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
268 (V8HI "TARGET_SIMD_F16INST")
271 ;; Scalar and Advanced SIMD modes for S and D.
272 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
274 ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
275 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
276 (V8HI "TARGET_SIMD_F16INST")
278 (HI "TARGET_SIMD_F16INST")
281 ;; Advanced SIMD modes for Q and H types.
282 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
284 ;; Advanced SIMD modes for H and S types.
285 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
287 ;; Advanced SIMD modes for H, S and D types.
288 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
290 ;; Advanced SIMD and scalar integer modes for H and S.
291 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
293 ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
294 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
296 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
297 (define_mode_iterator VD_HSI [V4HI V2SI])
299 ;; Scalar 64-bit container: 16, 32-bit integer modes
300 (define_mode_iterator SD_HSI [HI SI])
302 ;; Scalar 64-bit container: 16-bit, 32-bit and 64-bit integer modes.
303 (define_mode_iterator SD_HSDI [HI SI DI])
305 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
306 (define_mode_iterator VQ_HSI [V8HI V4SI])
309 (define_mode_iterator VB [V8QI V16QI])
311 ;; 2 and 4 lane SI modes.
312 (define_mode_iterator VS [V2SI V4SI])
314 (define_mode_iterator TX [TI TF TD])
316 (define_mode_iterator VTX [TI TF TD V16QI V8HI V4SI V2DI V8HF V4SF V2DF V8BF])
318 ;; Advanced SIMD opaque structure modes.
319 (define_mode_iterator VSTRUCT [OI CI XI])
321 ;; Advanced SIMD 64-bit vector structure modes.
322 (define_mode_iterator VSTRUCT_D [V2x8QI V2x4HI V2x2SI V2x1DI
323 V2x4HF V2x2SF V2x1DF V2x4BF
324 V3x8QI V3x4HI V3x2SI V3x1DI
325 V3x4HF V3x2SF V3x1DF V3x4BF
326 V4x8QI V4x4HI V4x2SI V4x1DI
327 V4x4HF V4x2SF V4x1DF V4x4BF])
329 ;; Advanced SIMD 64-bit 2-vector structure modes.
330 (define_mode_iterator VSTRUCT_2D [V2x8QI V2x4HI V2x2SI V2x1DI
331 V2x4HF V2x2SF V2x1DF V2x4BF])
333 ;; Advanced SIMD 64-bit 3-vector structure modes.
334 (define_mode_iterator VSTRUCT_3D [V3x8QI V3x4HI V3x2SI V3x1DI
335 V3x4HF V3x2SF V3x1DF V3x4BF])
337 ;; Advanced SIMD 64-bit 4-vector structure modes.
338 (define_mode_iterator VSTRUCT_4D [V4x8QI V4x4HI V4x2SI V4x1DI
339 V4x4HF V4x2SF V4x1DF V4x4BF])
341 ;; Advanced SIMD 64-bit 2-vector structure modes minus V2x1DI and V2x1DF.
342 (define_mode_iterator VSTRUCT_2DNX [V2x8QI V2x4HI V2x2SI V2x4HF
345 ;; Advanced SIMD 64-bit 3-vector structure modes minus V3x1DI and V3x1DF.
346 (define_mode_iterator VSTRUCT_3DNX [V3x8QI V3x4HI V3x2SI V3x4HF
349 ;; Advanced SIMD 64-bit 4-vector structure modes minus V4x1DI and V4x1DF.
350 (define_mode_iterator VSTRUCT_4DNX [V4x8QI V4x4HI V4x2SI V4x4HF
353 ;; Advanced SIMD 64-bit structure modes with 64-bit elements.
354 (define_mode_iterator VSTRUCT_DX [V2x1DI V2x1DF V3x1DI V3x1DF V4x1DI V4x1DF])
356 ;; Advanced SIMD 64-bit 2-vector structure modes with 64-bit elements.
357 (define_mode_iterator VSTRUCT_2DX [V2x1DI V2x1DF])
359 ;; Advanced SIMD 64-bit 3-vector structure modes with 64-bit elements.
360 (define_mode_iterator VSTRUCT_3DX [V3x1DI V3x1DF])
362 ;; Advanced SIMD 64-bit 4-vector structure modes with 64-bit elements.
363 (define_mode_iterator VSTRUCT_4DX [V4x1DI V4x1DF])
365 ;; Advanced SIMD 128-bit vector structure modes.
366 (define_mode_iterator VSTRUCT_Q [V2x16QI V2x8HI V2x4SI V2x2DI
367 V2x8HF V2x4SF V2x2DF V2x8BF
368 V3x16QI V3x8HI V3x4SI V3x2DI
369 V3x8HF V3x4SF V3x2DF V3x8BF
370 V4x16QI V4x8HI V4x4SI V4x2DI
371 V4x8HF V4x4SF V4x2DF V4x8BF])
373 ;; Advanced SIMD 128-bit 2-vector structure modes.
374 (define_mode_iterator VSTRUCT_2Q [V2x16QI V2x8HI V2x4SI V2x2DI
375 V2x8HF V2x4SF V2x2DF V2x8BF])
377 ;; Advanced SIMD 128-bit 3-vector structure modes.
378 (define_mode_iterator VSTRUCT_3Q [V3x16QI V3x8HI V3x4SI V3x2DI
379 V3x8HF V3x4SF V3x2DF V3x8BF])
381 ;; Advanced SIMD 128-bit 4-vector structure modes.
382 (define_mode_iterator VSTRUCT_4Q [V4x16QI V4x8HI V4x4SI V4x2DI
383 V4x8HF V4x4SF V4x2DF V4x8BF])
385 ;; Advanced SIMD 2-vector structure modes.
386 (define_mode_iterator VSTRUCT_2QD [V2x8QI V2x4HI V2x2SI V2x1DI
387 V2x4HF V2x2SF V2x1DF V2x4BF
388 V2x16QI V2x8HI V2x4SI V2x2DI
389 V2x8HF V2x4SF V2x2DF V2x8BF])
391 ;; Advanced SIMD 3-vector structure modes.
392 (define_mode_iterator VSTRUCT_3QD [V3x8QI V3x4HI V3x2SI V3x1DI
393 V3x4HF V3x2SF V3x1DF V3x4BF
394 V3x16QI V3x8HI V3x4SI V3x2DI
395 V3x8HF V3x4SF V3x2DF V3x8BF])
397 ;; Advanced SIMD 4-vector structure modes.
398 (define_mode_iterator VSTRUCT_4QD [V4x8QI V4x4HI V4x2SI V4x1DI
399 V4x4HF V4x2SF V4x1DF V4x4BF
400 V4x16QI V4x8HI V4x4SI V4x2DI
401 V4x8HF V4x4SF V4x2DF V4x8BF])
403 ;; Advanced SIMD vector structure modes.
404 (define_mode_iterator VSTRUCT_QD [V2x8QI V2x4HI V2x2SI V2x1DI
405 V2x4HF V2x2SF V2x1DF V2x4BF
406 V3x8QI V3x4HI V3x2SI V3x1DI
407 V3x4HF V3x2SF V3x1DF V3x4BF
408 V4x8QI V4x4HI V4x2SI V4x1DI
409 V4x4HF V4x2SF V4x1DF V4x4BF
410 V2x16QI V2x8HI V2x4SI V2x2DI
411 V2x8HF V2x4SF V2x2DF V2x8BF
412 V3x16QI V3x8HI V3x4SI V3x2DI
413 V3x8HF V3x4SF V3x2DF V3x8BF
414 V4x16QI V4x8HI V4x4SI V4x2DI
415 V4x8HF V4x4SF V4x2DF V4x8BF])
417 ;; Double scalar modes
418 (define_mode_iterator DX [DI DF DD])
420 ;; Duplicate of the above
421 (define_mode_iterator DX2 [DI DF DD])
423 ;; Single scalar modes
424 (define_mode_iterator SX [SI SF])
426 ;; Duplicate of the above
427 (define_mode_iterator SX2 [SI SF])
429 ;; Single and double integer and float modes
430 (define_mode_iterator DSX [DF DI SF SI])
433 ;; Modes available for Advanced SIMD <f>mul operations.
434 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
435 (V4HF "TARGET_SIMD_F16INST")
436 (V8HF "TARGET_SIMD_F16INST")
439 ;; The subset of VMUL for which VCOND is a vector mode.
440 (define_mode_iterator VMULD [V4HI V8HI V2SI V4SI
441 (V4HF "TARGET_SIMD_F16INST")
442 (V8HF "TARGET_SIMD_F16INST")
445 ;; Iterators for single modes, for "@" patterns.
446 (define_mode_iterator VNx16QI_ONLY [VNx16QI])
447 (define_mode_iterator VNx8HI_ONLY [VNx8HI])
448 (define_mode_iterator VNx8BF_ONLY [VNx8BF])
449 (define_mode_iterator VNx4SI_ONLY [VNx4SI])
450 (define_mode_iterator VNx4SF_ONLY [VNx4SF])
451 (define_mode_iterator VNx2DI_ONLY [VNx2DI])
452 (define_mode_iterator VNx2DF_ONLY [VNx2DF])
454 ;; All SVE vector structure modes.
455 (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
456 VNx16BF VNx16HF VNx8SF VNx4DF
457 VNx48QI VNx24HI VNx12SI VNx6DI
458 VNx24BF VNx24HF VNx12SF VNx6DF
459 VNx64QI VNx32HI VNx16SI VNx8DI
460 VNx32BF VNx32HF VNx16SF VNx8DF])
462 ;; All fully-packed SVE vector modes.
463 (define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI
464 VNx8BF VNx8HF VNx4SF VNx2DF])
466 ;; All fully-packed SVE integer vector modes.
467 (define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI])
469 ;; All fully-packed SVE floating-point vector modes.
470 (define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
472 ;; Fully-packed SVE integer vector modes that have 8-bit or 16-bit elements.
473 (define_mode_iterator SVE_FULL_BHI [VNx16QI VNx8HI])
475 ;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
477 (define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
479 ;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
480 (define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI
481 VNx8BF VNx8HF VNx4SF VNx2DF])
483 ;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit
485 (define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI])
487 ;; Fully-packed SVE integer vector modes that have 16-bit or 32-bit
489 (define_mode_iterator SVE_FULL_HSI [VNx8HI VNx4SI])
491 ;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit
493 (define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF])
495 ;; Fully-packed SVE integer vector modes that have 16-bit or 64-bit elements.
496 (define_mode_iterator SVE_FULL_HDI [VNx8HI VNx2DI])
498 ;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements.
499 (define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
501 ;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements.
502 (define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI])
504 ;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
506 (define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
508 ;; Same, but with the appropriate conditions for FMMLA support.
509 (define_mode_iterator SVE_MATMULF [(VNx4SF "TARGET_SVE_F32MM")
510 (VNx2DF "TARGET_SVE_F64MM")])
512 ;; Fully-packed SVE vector modes that have 32-bit elements.
513 (define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF])
515 ;; Fully-packed SVE vector modes that have 64-bit elements.
516 (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF])
518 ;; All partial SVE integer modes.
519 (define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI
523 ;; All SVE vector modes.
524 (define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI
533 ;; All SVE integer vector modes.
534 (define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
539 ;; SVE integer vector modes whose elements are 16 bits or wider.
540 (define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI
544 ;; SVE modes with 2 or 4 elements.
545 (define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2BF VNx2SI VNx2SF
547 VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF])
549 ;; SVE integer modes with 2 or 4 elements.
550 (define_mode_iterator SVE_24I [VNx2QI VNx2HI VNx2SI VNx2DI
551 VNx4QI VNx4HI VNx4SI])
553 ;; SVE modes with 2 elements.
554 (define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2BF
555 VNx2SI VNx2SF VNx2DI VNx2DF])
557 ;; SVE integer modes with 2 elements, excluding the widest element.
558 (define_mode_iterator SVE_2BHSI [VNx2QI VNx2HI VNx2SI])
560 ;; SVE integer modes with 2 elements, excluding the narrowest element.
561 (define_mode_iterator SVE_2HSDI [VNx2HI VNx2SI VNx2DI])
563 ;; SVE modes with 4 elements.
564 (define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4BF VNx4SI VNx4SF])
566 ;; SVE integer modes with 4 elements, excluding the widest element.
567 (define_mode_iterator SVE_4BHI [VNx4QI VNx4HI])
569 ;; SVE integer modes with 4 elements, excluding the narrowest element.
570 (define_mode_iterator SVE_4HSI [VNx4HI VNx4SI])
572 ;; SVE integer modes that can form the input to an SVE2 PMULL[BT] instruction.
573 (define_mode_iterator SVE2_PMULL_PAIR_I [VNx16QI VNx4SI
574 (VNx2DI "TARGET_SVE2_AES")])
576 ;; Modes involved in extending or truncating SVE data, for 8 elements per
578 (define_mode_iterator VNx8_NARROW [VNx8QI])
579 (define_mode_iterator VNx8_WIDE [VNx8HI])
581 ;; ...same for 4 elements per 128-bit block.
582 (define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI])
583 (define_mode_iterator VNx4_WIDE [VNx4SI])
585 ;; ...same for 2 elements per 128-bit block.
586 (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])
587 (define_mode_iterator VNx2_WIDE [VNx2DI])
589 ;; All SVE predicate modes.
590 (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
592 ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
593 (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
595 ;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements.
596 (define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI])
598 ;; Bfloat16 modes to which V4SF can be converted
599 (define_mode_iterator V4SF_TO_BF [V4BF V8BF])
601 ;; ------------------------------------------------------------------
602 ;; Unspec enumerations for Advance SIMD. These could well go into
603 ;; aarch64.md but for their use in int_iterators here.
604 ;; ------------------------------------------------------------------
606 (define_c_enum "unspec"
608 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
609 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
610 UNSPEC_ABS ; Used in aarch64-simd.md.
611 UNSPEC_FMAX ; Used in aarch64-simd.md.
612 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
613 UNSPEC_FMAXV ; Used in aarch64-simd.md.
614 UNSPEC_FMIN ; Used in aarch64-simd.md.
615 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
616 UNSPEC_FMINV ; Used in aarch64-simd.md.
617 UNSPEC_FADDV ; Used in aarch64-simd.md.
618 UNSPEC_ADDV ; Used in aarch64-simd.md.
619 UNSPEC_SADDLV ; Used in aarch64-simd.md.
620 UNSPEC_UADDLV ; Used in aarch64-simd.md.
621 UNSPEC_SMAXV ; Used in aarch64-simd.md.
622 UNSPEC_SMINV ; Used in aarch64-simd.md.
623 UNSPEC_UMAXV ; Used in aarch64-simd.md.
624 UNSPEC_UMINV ; Used in aarch64-simd.md.
625 UNSPEC_SHADD ; Used in aarch64-simd.md.
626 UNSPEC_UHADD ; Used in aarch64-simd.md.
627 UNSPEC_SRHADD ; Used in aarch64-simd.md.
628 UNSPEC_URHADD ; Used in aarch64-simd.md.
629 UNSPEC_SHSUB ; Used in aarch64-simd.md.
630 UNSPEC_UHSUB ; Used in aarch64-simd.md.
631 UNSPEC_ADDHN ; Used in aarch64-simd.md.
632 UNSPEC_RADDHN ; Used in aarch64-simd.md.
633 UNSPEC_SUBHN ; Used in aarch64-simd.md.
634 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
635 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
636 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
637 UNSPEC_PMUL ; Used in aarch64-simd.md.
638 UNSPEC_FMULX ; Used in aarch64-simd.md.
639 UNSPEC_USQADD ; Used in aarch64-simd.md.
640 UNSPEC_SUQADD ; Used in aarch64-simd.md.
641 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
642 UNSPEC_SSRA ; Used in aarch64-simd.md.
643 UNSPEC_USRA ; Used in aarch64-simd.md.
644 UNSPEC_SRSRA ; Used in aarch64-simd.md.
645 UNSPEC_URSRA ; Used in aarch64-simd.md.
646 UNSPEC_SRSHR ; Used in aarch64-simd.md.
647 UNSPEC_URSHR ; Used in aarch64-simd.md.
648 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
649 UNSPEC_SQSHL ; Used in aarch64-simd.md.
650 UNSPEC_UQSHL ; Used in aarch64-simd.md.
651 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
652 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
653 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
654 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
655 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
656 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
657 UNSPEC_SSHL ; Used in aarch64-simd.md.
658 UNSPEC_USHL ; Used in aarch64-simd.md.
659 UNSPEC_SRSHL ; Used in aarch64-simd.md.
660 UNSPEC_URSHL ; Used in aarch64-simd.md.
661 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
662 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
663 UNSPEC_SSLI ; Used in aarch64-simd.md.
664 UNSPEC_USLI ; Used in aarch64-simd.md.
665 UNSPEC_SSRI ; Used in aarch64-simd.md.
666 UNSPEC_USRI ; Used in aarch64-simd.md.
667 UNSPEC_SSHLL ; Used in aarch64-simd.md.
668 UNSPEC_USHLL ; Used in aarch64-simd.md.
669 UNSPEC_ADDP ; Used in aarch64-simd.md.
670 UNSPEC_SADDLP ; Used in aarch64-simd.md.
671 UNSPEC_UADDLP ; Used in aarch64-simd.md.
672 UNSPEC_TBL ; Used in vector permute patterns.
673 UNSPEC_TBX ; Used in vector permute patterns.
674 UNSPEC_CONCAT ; Used in vector permute patterns.
676 ;; The following permute unspecs are generated directly by
677 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
678 ;; instructions would need a corresponding change there.
679 UNSPEC_ZIP1 ; Used in vector permute patterns.
680 UNSPEC_ZIP2 ; Used in vector permute patterns.
681 UNSPEC_UZP1 ; Used in vector permute patterns.
682 UNSPEC_UZP2 ; Used in vector permute patterns.
683 UNSPEC_TRN1 ; Used in vector permute patterns.
684 UNSPEC_TRN2 ; Used in vector permute patterns.
685 UNSPEC_EXT ; Used in vector permute patterns.
686 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
687 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
688 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
690 UNSPEC_AESE ; Used in aarch64-simd.md.
691 UNSPEC_AESD ; Used in aarch64-simd.md.
692 UNSPEC_AESMC ; Used in aarch64-simd.md.
693 UNSPEC_AESIMC ; Used in aarch64-simd.md.
694 UNSPEC_SHA1C ; Used in aarch64-simd.md.
695 UNSPEC_SHA1M ; Used in aarch64-simd.md.
696 UNSPEC_SHA1P ; Used in aarch64-simd.md.
697 UNSPEC_SHA1H ; Used in aarch64-simd.md.
698 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
699 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
700 UNSPEC_SHA256H ; Used in aarch64-simd.md.
701 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
702 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
703 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
704 UNSPEC_PMULL ; Used in aarch64-simd.md.
705 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
706 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
707 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
708 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
709 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
710 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
711 UNSPEC_FMINNM ; Used in aarch64-simd.md.
712 UNSPEC_SDOT ; Used in aarch64-simd.md.
713 UNSPEC_UDOT ; Used in aarch64-simd.md.
714 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
715 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
716 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
717 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
718 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
719 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
720 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
721 UNSPEC_SM4E ; Used in aarch64-simd.md.
722 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
723 UNSPEC_SHA512H ; Used in aarch64-simd.md.
724 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
725 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
726 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
727 UNSPEC_FMLAL ; Used in aarch64-simd.md.
728 UNSPEC_FMLSL ; Used in aarch64-simd.md.
729 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
730 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
731 UNSPEC_ADR ; Used in aarch64-sve.md.
732 UNSPEC_SEL ; Used in aarch64-sve.md.
733 UNSPEC_BRKA ; Used in aarch64-sve.md.
734 UNSPEC_BRKB ; Used in aarch64-sve.md.
735 UNSPEC_BRKN ; Used in aarch64-sve.md.
736 UNSPEC_BRKPA ; Used in aarch64-sve.md.
737 UNSPEC_BRKPB ; Used in aarch64-sve.md.
738 UNSPEC_PFIRST ; Used in aarch64-sve.md.
739 UNSPEC_PNEXT ; Used in aarch64-sve.md.
740 UNSPEC_CNTP ; Used in aarch64-sve.md.
741 UNSPEC_SADDV ; Used in aarch64-sve.md.
742 UNSPEC_UADDV ; Used in aarch64-sve.md.
743 UNSPEC_ANDV ; Used in aarch64-sve.md.
744 UNSPEC_IORV ; Used in aarch64-sve.md.
745 UNSPEC_XORV ; Used in aarch64-sve.md.
746 UNSPEC_ANDF ; Used in aarch64-sve.md.
747 UNSPEC_IORF ; Used in aarch64-sve.md.
748 UNSPEC_XORF ; Used in aarch64-sve.md.
749 UNSPEC_REVB ; Used in aarch64-sve.md.
750 UNSPEC_REVH ; Used in aarch64-sve.md.
751 UNSPEC_REVW ; Used in aarch64-sve.md.
752 UNSPEC_REVBHW ; Used in aarch64-sve.md.
753 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
754 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
755 UNSPEC_FMLA ; Used in aarch64-sve.md.
756 UNSPEC_FMLS ; Used in aarch64-sve.md.
757 UNSPEC_FEXPA ; Used in aarch64-sve.md.
758 UNSPEC_FMMLA ; Used in aarch64-sve.md.
759 UNSPEC_FTMAD ; Used in aarch64-sve.md.
760 UNSPEC_FTSMUL ; Used in aarch64-sve.md.
761 UNSPEC_FTSSEL ; Used in aarch64-sve.md.
762 UNSPEC_SMATMUL ; Used in aarch64-sve.md.
763 UNSPEC_UMATMUL ; Used in aarch64-sve.md.
764 UNSPEC_USMATMUL ; Used in aarch64-sve.md.
765 UNSPEC_TRN1Q ; Used in aarch64-sve.md.
766 UNSPEC_TRN2Q ; Used in aarch64-sve.md.
767 UNSPEC_UZP1Q ; Used in aarch64-sve.md.
768 UNSPEC_UZP2Q ; Used in aarch64-sve.md.
769 UNSPEC_ZIP1Q ; Used in aarch64-sve.md.
770 UNSPEC_ZIP2Q ; Used in aarch64-sve.md.
771 UNSPEC_TRN1_CONV ; Used in aarch64-sve.md.
772 UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md.
773 UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md.
774 UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md.
775 UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md.
776 UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md.
777 UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md.
778 UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md.
779 UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md.
780 UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md.
781 UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md.
782 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
783 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
784 UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md.
785 UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md.
786 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
787 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
788 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
789 UNSPEC_COND_FCMLA ; Used in aarch64-sve.md.
790 UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md.
791 UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md.
792 UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md.
793 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
794 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
795 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
796 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
797 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
798 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
799 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
800 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
801 UNSPEC_COND_FMAX ; Used in aarch64-sve.md.
802 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
803 UNSPEC_COND_FMIN ; Used in aarch64-sve.md.
804 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
805 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
806 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
807 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
808 UNSPEC_COND_FMULX ; Used in aarch64-sve.md.
809 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
810 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
811 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
812 UNSPEC_COND_FRECPX ; Used in aarch64-sve.md.
813 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
814 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
815 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
816 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
817 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
818 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
819 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
820 UNSPEC_COND_FSCALE ; Used in aarch64-sve.md.
821 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
822 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
823 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
824 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
825 UNSPEC_LASTA ; Used in aarch64-sve.md.
826 UNSPEC_LASTB ; Used in aarch64-sve.md.
827 UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md.
828 UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md.
829 UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md.
830 UNSPEC_LDFF1 ; Used in aarch64-sve.md.
831 UNSPEC_LDNF1 ; Used in aarch64-sve.md.
832 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
833 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
834 UNSPEC_FCMLA ; Used in aarch64-simd.md.
835 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
836 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
837 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
838 UNSPEC_FCMUL ; Used in aarch64-simd.md.
839 UNSPEC_FCMUL_CONJ ; Used in aarch64-simd.md.
840 UNSPEC_FCMLA_CONJ ; Used in aarch64-simd.md.
841 UNSPEC_FCMLA180_CONJ ; Used in aarch64-simd.md.
842 UNSPEC_ASRD ; Used in aarch64-sve.md.
843 UNSPEC_ADCLB ; Used in aarch64-sve2.md.
844 UNSPEC_ADCLT ; Used in aarch64-sve2.md.
845 UNSPEC_ADDHNB ; Used in aarch64-sve2.md.
846 UNSPEC_ADDHNT ; Used in aarch64-sve2.md.
847 UNSPEC_BDEP ; Used in aarch64-sve2.md.
848 UNSPEC_BEXT ; Used in aarch64-sve2.md.
849 UNSPEC_BGRP ; Used in aarch64-sve2.md.
850 UNSPEC_CADD270 ; Used in aarch64-sve2.md.
851 UNSPEC_CADD90 ; Used in aarch64-sve2.md.
852 UNSPEC_CDOT ; Used in aarch64-sve2.md.
853 UNSPEC_CDOT180 ; Used in aarch64-sve2.md.
854 UNSPEC_CDOT270 ; Used in aarch64-sve2.md.
855 UNSPEC_CDOT90 ; Used in aarch64-sve2.md.
856 UNSPEC_CMLA ; Used in aarch64-sve2.md.
857 UNSPEC_CMLA180 ; Used in aarch64-sve2.md.
858 UNSPEC_CMLA270 ; Used in aarch64-sve2.md.
859 UNSPEC_CMLA90 ; Used in aarch64-sve2.md.
860 UNSPEC_CMLA_CONJ ; Used in aarch64-sve2.md.
861 UNSPEC_CMLA180_CONJ ; Used in aarch64-sve2.md.
862 UNSPEC_CMUL ; Used in aarch64-sve2.md.
863 UNSPEC_CMUL_CONJ ; Used in aarch64-sve2.md.
864 UNSPEC_COND_FCVTLT ; Used in aarch64-sve2.md.
865 UNSPEC_COND_FCVTNT ; Used in aarch64-sve2.md.
866 UNSPEC_COND_FCVTX ; Used in aarch64-sve2.md.
867 UNSPEC_COND_FCVTXNT ; Used in aarch64-sve2.md.
868 UNSPEC_COND_FLOGB ; Used in aarch64-sve2.md.
869 UNSPEC_EORBT ; Used in aarch64-sve2.md.
870 UNSPEC_EORTB ; Used in aarch64-sve2.md.
871 UNSPEC_FADDP ; Used in aarch64-sve2.md.
872 UNSPEC_FMAXNMP ; Used in aarch64-sve2.md.
873 UNSPEC_FMAXP ; Used in aarch64-sve2.md.
874 UNSPEC_FMINNMP ; Used in aarch64-sve2.md.
875 UNSPEC_FMINP ; Used in aarch64-sve2.md.
876 UNSPEC_FMLALB ; Used in aarch64-sve2.md.
877 UNSPEC_FMLALT ; Used in aarch64-sve2.md.
878 UNSPEC_FMLSLB ; Used in aarch64-sve2.md.
879 UNSPEC_FMLSLT ; Used in aarch64-sve2.md.
880 UNSPEC_HISTCNT ; Used in aarch64-sve2.md.
881 UNSPEC_HISTSEG ; Used in aarch64-sve2.md.
882 UNSPEC_MATCH ; Used in aarch64-sve2.md.
883 UNSPEC_NMATCH ; Used in aarch64-sve2.md.
884 UNSPEC_PMULLB ; Used in aarch64-sve2.md.
885 UNSPEC_PMULLB_PAIR ; Used in aarch64-sve2.md.
886 UNSPEC_PMULLT ; Used in aarch64-sve2.md.
887 UNSPEC_PMULLT_PAIR ; Used in aarch64-sve2.md.
888 UNSPEC_RADDHNB ; Used in aarch64-sve2.md.
889 UNSPEC_RADDHNT ; Used in aarch64-sve2.md.
890 UNSPEC_RSHRNB ; Used in aarch64-sve2.md.
891 UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
892 UNSPEC_RSUBHNB ; Used in aarch64-sve2.md.
893 UNSPEC_RSUBHNT ; Used in aarch64-sve2.md.
894 UNSPEC_SABDLB ; Used in aarch64-sve2.md.
895 UNSPEC_SABDLT ; Used in aarch64-sve2.md.
896 UNSPEC_SADDLB ; Used in aarch64-sve2.md.
897 UNSPEC_SADDLBT ; Used in aarch64-sve2.md.
898 UNSPEC_SADDLT ; Used in aarch64-sve2.md.
899 UNSPEC_SADDWB ; Used in aarch64-sve2.md.
900 UNSPEC_SADDWT ; Used in aarch64-sve2.md.
901 UNSPEC_SBCLB ; Used in aarch64-sve2.md.
902 UNSPEC_SBCLT ; Used in aarch64-sve2.md.
903 UNSPEC_SHRNB ; Used in aarch64-sve2.md.
904 UNSPEC_SHRNT ; Used in aarch64-sve2.md.
905 UNSPEC_SLI ; Used in aarch64-sve2.md.
906 UNSPEC_SMAXP ; Used in aarch64-sve2.md.
907 UNSPEC_SMINP ; Used in aarch64-sve2.md.
908 UNSPEC_SMULHRS ; Used in aarch64-sve2.md.
909 UNSPEC_SMULHS ; Used in aarch64-sve2.md.
910 UNSPEC_SMULLB ; Used in aarch64-sve2.md.
911 UNSPEC_SMULLT ; Used in aarch64-sve2.md.
912 UNSPEC_SQCADD270 ; Used in aarch64-sve2.md.
913 UNSPEC_SQCADD90 ; Used in aarch64-sve2.md.
914 UNSPEC_SQDMULLB ; Used in aarch64-sve2.md.
915 UNSPEC_SQDMULLBT ; Used in aarch64-sve2.md.
916 UNSPEC_SQDMULLT ; Used in aarch64-sve2.md.
917 UNSPEC_SQRDCMLAH ; Used in aarch64-sve2.md.
918 UNSPEC_SQRDCMLAH180 ; Used in aarch64-sve2.md.
919 UNSPEC_SQRDCMLAH270 ; Used in aarch64-sve2.md.
920 UNSPEC_SQRDCMLAH90 ; Used in aarch64-sve2.md.
921 UNSPEC_SQRSHRNB ; Used in aarch64-sve2.md.
922 UNSPEC_SQRSHRNT ; Used in aarch64-sve2.md.
923 UNSPEC_SQRSHRUNB ; Used in aarch64-sve2.md.
924 UNSPEC_SQRSHRUNT ; Used in aarch64-sve2.md.
925 UNSPEC_SQSHRNB ; Used in aarch64-sve2.md.
926 UNSPEC_SQSHRNT ; Used in aarch64-sve2.md.
927 UNSPEC_SQSHRUNB ; Used in aarch64-sve2.md.
928 UNSPEC_SQSHRUNT ; Used in aarch64-sve2.md.
929 UNSPEC_SQXTNB ; Used in aarch64-sve2.md.
930 UNSPEC_SQXTNT ; Used in aarch64-sve2.md.
931 UNSPEC_SQXTUNB ; Used in aarch64-sve2.md.
932 UNSPEC_SQXTUNT ; Used in aarch64-sve2.md.
933 UNSPEC_SRI ; Used in aarch64-sve2.md.
934 UNSPEC_SSHLLB ; Used in aarch64-sve2.md.
935 UNSPEC_SSHLLT ; Used in aarch64-sve2.md.
936 UNSPEC_SSUBLB ; Used in aarch64-sve2.md.
937 UNSPEC_SSUBLBT ; Used in aarch64-sve2.md.
938 UNSPEC_SSUBLT ; Used in aarch64-sve2.md.
939 UNSPEC_SSUBLTB ; Used in aarch64-sve2.md.
940 UNSPEC_SSUBWB ; Used in aarch64-sve2.md.
941 UNSPEC_SSUBWT ; Used in aarch64-sve2.md.
942 UNSPEC_SUBHNB ; Used in aarch64-sve2.md.
943 UNSPEC_SUBHNT ; Used in aarch64-sve2.md.
944 UNSPEC_TBL2 ; Used in aarch64-sve2.md.
945 UNSPEC_UABDLB ; Used in aarch64-sve2.md.
946 UNSPEC_UABDLT ; Used in aarch64-sve2.md.
947 UNSPEC_UADDLB ; Used in aarch64-sve2.md.
948 UNSPEC_UADDLT ; Used in aarch64-sve2.md.
949 UNSPEC_UADDWB ; Used in aarch64-sve2.md.
950 UNSPEC_UADDWT ; Used in aarch64-sve2.md.
951 UNSPEC_UMAXP ; Used in aarch64-sve2.md.
952 UNSPEC_UMINP ; Used in aarch64-sve2.md.
953 UNSPEC_UMULHRS ; Used in aarch64-sve2.md.
954 UNSPEC_UMULHS ; Used in aarch64-sve2.md.
955 UNSPEC_UMULLB ; Used in aarch64-sve2.md.
956 UNSPEC_UMULLT ; Used in aarch64-sve2.md.
957 UNSPEC_UQRSHRNB ; Used in aarch64-sve2.md.
958 UNSPEC_UQRSHRNT ; Used in aarch64-sve2.md.
959 UNSPEC_UQSHRNB ; Used in aarch64-sve2.md.
960 UNSPEC_UQSHRNT ; Used in aarch64-sve2.md.
961 UNSPEC_UQXTNB ; Used in aarch64-sve2.md.
962 UNSPEC_UQXTNT ; Used in aarch64-sve2.md.
963 UNSPEC_USHLLB ; Used in aarch64-sve2.md.
964 UNSPEC_USHLLT ; Used in aarch64-sve2.md.
965 UNSPEC_USUBLB ; Used in aarch64-sve2.md.
966 UNSPEC_USUBLT ; Used in aarch64-sve2.md.
967 UNSPEC_USUBWB ; Used in aarch64-sve2.md.
968 UNSPEC_USUBWT ; Used in aarch64-sve2.md.
969 UNSPEC_USDOT ; Used in aarch64-simd.md.
970 UNSPEC_SUDOT ; Used in aarch64-simd.md.
971 UNSPEC_BFDOT ; Used in aarch64-simd.md.
972 UNSPEC_BFMLALB ; Used in aarch64-sve.md.
973 UNSPEC_BFMLALT ; Used in aarch64-sve.md.
974 UNSPEC_BFMMLA ; Used in aarch64-sve.md.
975 UNSPEC_BFCVTN ; Used in aarch64-simd.md.
976 UNSPEC_BFCVTN2 ; Used in aarch64-simd.md.
977 UNSPEC_BFCVT ; Used in aarch64-simd.md.
978 UNSPEC_FCVTXN ; Used in aarch64-simd.md.
981 ;; ------------------------------------------------------------------
982 ;; Unspec enumerations for Atomics. They are here so that they can be
983 ;; used in the int_iterators for atomic operations.
984 ;; ------------------------------------------------------------------
986 (define_c_enum "unspecv"
988 UNSPECV_LX ; Represent a load-exclusive.
989 UNSPECV_SX ; Represent a store-exclusive.
990 UNSPECV_LDA ; Represent an atomic load or load-acquire.
991 UNSPECV_LDAP ; Represent an atomic acquire load with RCpc semantics.
992 UNSPECV_STL ; Represent an atomic store or store-release.
993 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
994 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
995 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
996 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
997 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
998 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
999 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
1000 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
1001 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
1004 ;; -------------------------------------------------------------------
1006 ;; -------------------------------------------------------------------
1008 ;; "e" for signaling operations, "" for quiet operations.
1009 (define_mode_attr e [(CCFP "") (CCFPE "e")])
1011 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
1012 ;; 32-bit version and "%x0" in the 64-bit version.
1013 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
1015 ;; The size of access, in bytes.
1016 (define_mode_attr ldst_sz [(SI "4") (DI "8")])
1017 ;; Likewise for load/store pair.
1018 (define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
1020 ;; For inequal width int to float conversion
1021 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
1022 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
1024 ;; For width of fp registers in fcvt instruction
1025 (define_mode_attr fpw [(DI "s") (SI "d")])
1027 (define_mode_attr short_mask [(HI "65535") (QI "255")])
1029 ;; For constraints used in scalar immediate vector moves
1030 (define_mode_attr hq [(HI "h") (QI "q")])
1032 ;; For doubling width of an integer mode
1033 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
1035 (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
1037 (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
1039 ;; For scalar usage of vector/FP registers
1040 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
1041 (HF "h") (SF "s") (DF "d")
1042 (V8QI "") (V16QI "")
1047 (V8HF "") (V2DF "")])
1049 ;; For scalar usage of vector/FP registers, narrowing
1050 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
1051 (V8QI "") (V16QI "")
1055 (V4SF "") (V2DF "")])
1057 ;; For scalar usage of vector/FP registers, widening
1058 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
1059 (V8QI "") (V16QI "")
1063 (V4SF "") (V2DF "")])
1065 ;; Register Type Name and Vector Arrangement Specifier for when
1066 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
1068 (define_mode_attr rtn [(DI "d") (SI "")])
1069 (define_mode_attr vas [(DI "") (SI ".2s")])
1071 ;; Map a vector to the number of units in it, if the size of the mode
1073 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
1074 (V4HI "4") (V8HI "8")
1075 (V2SI "2") (V4SI "4")
1076 (V1DI "1") (V2DI "2")
1077 (V4HF "4") (V8HF "8")
1078 (V4BF "4") (V8BF "8")
1079 (V2SF "2") (V4SF "4")
1080 (V1DF "1") (V2DF "2")
1084 ;; Map a mode to the number of bits in it, if the size of the mode
1086 (define_mode_attr bitsize [(V8QI "64") (V16QI "128")
1087 (V4HI "64") (V8HI "128")
1088 (V2SI "64") (V4SI "128")
1091 ;; Map a floating point or integer mode to the appropriate register name prefix
1092 (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
1094 ;; Give the length suffix letter for a sign- or zero-extension.
1095 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
1097 ;; Give the number of bits in the mode
1098 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
1099 (define_mode_attr ZEROM [(QI "SI") (HI "SI") (SI "SI") (DI "DI")])
1100 (define_mode_attr zerom [(QI "si") (HI "si") (SI "si") (DI "di")])
1102 ;; Give the ordinal of the MSB in the mode
1103 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
1104 (HF "#15") (SF "#31") (DF "#63")])
1106 ;; The number of bits in a vector element, or controlled by a predicate
1108 (define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16")
1109 (VNx4BI "32") (VNx2BI "64")
1110 (VNx16QI "8") (VNx8HI "16")
1111 (VNx4SI "32") (VNx2DI "64")
1112 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
1114 ;; The number of bits in a vector container.
1115 (define_mode_attr container_bits [(VNx16QI "8")
1116 (VNx8HI "16") (VNx8QI "16") (VNx8HF "16")
1118 (VNx4SI "32") (VNx4HI "32") (VNx4QI "32")
1119 (VNx4SF "32") (VNx4HF "32") (VNx4BF "32")
1120 (VNx2DI "64") (VNx2SI "64") (VNx2HI "64")
1121 (VNx2QI "64") (VNx2DF "64") (VNx2SF "64")
1122 (VNx2HF "64") (VNx2BF "64")])
1124 ;; Attribute to describe constants acceptable in logical operations
1125 (define_mode_attr lconst [(SI "K") (DI "L")])
1127 ;; Attribute to describe constants acceptable in logical and operations
1128 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
1130 ;; Map a mode to a specific constraint character.
1131 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
1133 ;; Map modes to Usg and Usj constraints for SISD right shifts
1134 (define_mode_attr cmode_simd [(SI "g") (DI "j")])
1136 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
1137 (V4HI "4h") (V8HI "8h")
1138 (V4BF "4h") (V8BF "8h")
1139 (V2SI "2s") (V4SI "4s")
1141 (V2DI "2d") (V2SF "2s")
1142 (V4SF "4s") (V2DF "2d")
1143 (V4HF "4h") (V8HF "8h")
1144 (V2x8QI "8b") (V2x4HI "4h")
1145 (V2x2SI "2s") (V2x1DI "1d")
1146 (V2x4HF "4h") (V2x2SF "2s")
1147 (V2x1DF "1d") (V2x4BF "4h")
1148 (V2x16QI "16b") (V2x8HI "8h")
1149 (V2x4SI "4s") (V2x2DI "2d")
1150 (V2x8HF "8h") (V2x4SF "4s")
1151 (V2x2DF "2d") (V2x8BF "8h")
1152 (V3x8QI "8b") (V3x4HI "4h")
1153 (V3x2SI "2s") (V3x1DI "1d")
1154 (V3x4HF "4h") (V3x2SF "2s")
1155 (V3x1DF "1d") (V3x4BF "4h")
1156 (V3x16QI "16b") (V3x8HI "8h")
1157 (V3x4SI "4s") (V3x2DI "2d")
1158 (V3x8HF "8h") (V3x4SF "4s")
1159 (V3x2DF "2d") (V3x8BF "8h")
1160 (V4x8QI "8b") (V4x4HI "4h")
1161 (V4x2SI "2s") (V4x1DI "1d")
1162 (V4x4HF "4h") (V4x2SF "2s")
1163 (V4x1DF "1d") (V4x4BF "4h")
1164 (V4x16QI "16b") (V4x8HI "8h")
1165 (V4x4SI "4s") (V4x2DI "2d")
1166 (V4x8HF "8h") (V4x4SF "4s")
1167 (V4x2DF "2d") (V4x8BF "8h")])
1169 ;; Map mode to type used in widening multiplies.
1170 (define_mode_attr Vcondtype [(V4HI "4h") (V8HI "4h") (V2SI "2s") (V4SI "2s")])
1172 ;; Map lane mode to name
1173 (define_mode_attr Qlane [(V4HI "_v4hi") (V8HI "q_v4hi")
1174 (V2SI "_v2si") (V4SI "q_v2si")])
1176 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
1177 (V4SI "32") (V2DI "64")])
1179 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
1180 (V4HI ".4h") (V8HI ".8h")
1181 (V2SI ".2s") (V4SI ".4s")
1182 (V2DI ".2d") (V4HF ".4h")
1183 (V8HF ".8h") (V4BF ".4h")
1184 (V8BF ".8h") (V2SF ".2s")
1185 (V4SF ".4s") (V2DF ".2d")
1191 ;; Register suffix narrowed modes for VQN.
1192 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
1197 ;; Mode-to-individual element type mapping.
1198 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
1199 (V4HI "h") (V8HI "h")
1200 (V2SI "s") (V4SI "s")
1202 (V4HF "h") (V8HF "h")
1203 (V2SF "s") (V4SF "s")
1205 (V2x8QI "b") (V2x4HI "h")
1206 (V2x2SI "s") (V2x1DI "d")
1207 (V2x4HF "h") (V2x2SF "s")
1208 (V2x1DF "d") (V2x4BF "h")
1209 (V2x16QI "b") (V2x8HI "h")
1210 (V2x4SI "s") (V2x2DI "d")
1211 (V2x8HF "h") (V2x4SF "s")
1212 (V2x2DF "d") (V2x8BF "h")
1213 (V3x8QI "b") (V3x4HI "h")
1214 (V3x2SI "s") (V3x1DI "d")
1215 (V3x4HF "h") (V3x2SF "s")
1216 (V3x1DF "d") (V3x4BF "h")
1217 (V3x16QI "b") (V3x8HI "h")
1218 (V3x4SI "s") (V3x2DI "d")
1219 (V3x8HF "h") (V3x4SF "s")
1220 (V3x2DF "d") (V3x8BF "h")
1221 (V4x8QI "b") (V4x4HI "h")
1222 (V4x2SI "s") (V4x1DI "d")
1223 (V4x4HF "h") (V4x2SF "s")
1224 (V4x1DF "d") (V4x4BF "h")
1225 (V4x16QI "b") (V4x8HI "h")
1226 (V4x4SI "s") (V4x2DI "d")
1227 (V4x8HF "h") (V4x4SF "s")
1228 (V4x2DF "d") (V4x8BF "h")
1229 (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d")
1230 (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
1231 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
1232 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
1233 (VNx8BF "h") (VNx4BF "h") (VNx2BF "h")
1234 (VNx4SI "s") (VNx2SI "s")
1235 (VNx4SF "s") (VNx2SF "s")
1238 (BF "h") (V4BF "h") (V8BF "h")
1244 ;; Like Vetype, but map to types that are a quarter of the element size.
1245 (define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
1247 ;; Equivalent of "size" for a vector element.
1248 (define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
1249 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
1250 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
1251 (VNx8BF "h") (VNx4BF "h") (VNx2BF "h")
1252 (VNx4SI "w") (VNx2SI "w")
1253 (VNx4SF "w") (VNx2SF "w")
1256 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
1257 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
1258 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
1259 (VNx16BF "h") (VNx24BF "h") (VNx32BF "h")
1260 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
1261 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
1262 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
1263 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
1265 ;; The Z register suffix for an SVE mode's element container, i.e. the
1266 ;; Vetype of full SVE modes that have the same number of elements.
1267 (define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d")
1268 (VNx8HI "h") (VNx4HI "s") (VNx2HI "d")
1269 (VNx8HF "h") (VNx4HF "s") (VNx2HF "d")
1270 (VNx8BF "h") (VNx4BF "s") (VNx2BF "d")
1271 (VNx4SI "s") (VNx2SI "d")
1272 (VNx4SF "s") (VNx2SF "d")
1276 ;; The instruction mnemonic suffix for an SVE mode's element container,
1277 ;; i.e. the Vewtype of full SVE modes that have the same number of elements.
1278 (define_mode_attr Vcwtype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "w") (VNx2QI "d")
1279 (VNx8HI "h") (VNx4HI "w") (VNx2HI "d")
1280 (VNx8HF "h") (VNx4HF "w") (VNx2HF "d")
1281 (VNx8BF "h") (VNx4BF "w") (VNx2BF "d")
1282 (VNx4SI "w") (VNx2SI "d")
1283 (VNx4SF "w") (VNx2SF "d")
1287 ;; Vetype is used everywhere in scheduling type and assembly output,
1288 ;; sometimes they are not the same, for example HF modes on some
1289 ;; instructions. stype is defined to represent scheduling type
1291 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
1292 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
1293 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
1294 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
1297 ;; Mode-to-bitwise operation type mapping.
1298 (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
1299 (V4HI "8b") (V8HI "16b")
1300 (V2SI "8b") (V4SI "16b")
1301 (V2DI "16b") (V4HF "8b")
1302 (V8HF "16b") (V2SF "8b")
1303 (V4SF "16b") (V2DF "16b")
1306 (V4BF "8b") (V8BF "16b")])
1308 ;; Advanced SIMD vector structure to element modes.
1309 (define_mode_attr VSTRUCT_ELT [(V2x8QI "V8QI") (V2x4HI "V4HI")
1310 (V2x2SI "V2SI") (V2x1DI "DI")
1311 (V2x4HF "V4HF") (V2x2SF "V2SF")
1312 (V2x1DF "DF") (V2x4BF "V4BF")
1313 (V3x8QI "V8QI") (V3x4HI "V4HI")
1314 (V3x2SI "V2SI") (V3x1DI "DI")
1315 (V3x4HF "V4HF") (V3x2SF "V2SF")
1316 (V3x1DF "DF") (V3x4BF "V4BF")
1317 (V4x8QI "V8QI") (V4x4HI "V4HI")
1318 (V4x2SI "V2SI") (V4x1DI "DI")
1319 (V4x4HF "V4HF") (V4x2SF "V2SF")
1320 (V4x1DF "DF") (V4x4BF "V4BF")
1321 (V2x16QI "V16QI") (V2x8HI "V8HI")
1322 (V2x4SI "V4SI") (V2x2DI "V2DI")
1323 (V2x8HF "V8HF") (V2x4SF "V4SF")
1324 (V2x2DF "V2DF") (V2x8BF "V8BF")
1325 (V3x16QI "V16QI") (V3x8HI "V8HI")
1326 (V3x4SI "V4SI") (V3x2DI "V2DI")
1327 (V3x8HF "V8HF") (V3x4SF "V4SF")
1328 (V3x2DF "V2DF") (V3x8BF "V8BF")
1329 (V4x16QI "V16QI") (V4x8HI "V8HI")
1330 (V4x4SI "V4SI") (V4x2DI "V2DI")
1331 (V4x8HF "V8HF") (V4x4SF "V4SF")
1332 (V4x2DF "V2DF") (V4x8BF "V8BF")])
1334 ;; Advanced SIMD vector structure to element modes in lower case.
1335 (define_mode_attr vstruct_elt [(V2x8QI "v8qi") (V2x4HI "v4hi")
1336 (V2x2SI "v2si") (V2x1DI "di")
1337 (V2x4HF "v4hf") (V2x2SF "v2sf")
1338 (V2x1DF "df") (V2x4BF "v4bf")
1339 (V3x8QI "v8qi") (V3x4HI "v4hi")
1340 (V3x2SI "v2si") (V3x1DI "di")
1341 (V3x4HF "v4hf") (V3x2SF "v2sf")
1342 (V3x1DF "df") (V3x4BF "v4bf")
1343 (V4x8QI "v8qi") (V4x4HI "v4hi")
1344 (V4x2SI "v2si") (V4x1DI "di")
1345 (V4x4HF "v4hf") (V4x2SF "v2sf")
1346 (V4x1DF "df") (V4x4BF "v4bf")
1347 (V2x16QI "v16qi") (V2x8HI "v8hi")
1348 (V2x4SI "v4si") (V2x2DI "v2di")
1349 (V2x8HF "v8hf") (V2x4SF "v4sf")
1350 (V2x2DF "v2df") (V2x8BF "v8bf")
1351 (V3x16QI "v16qi") (V3x8HI "v8hi")
1352 (V3x4SI "v4si") (V3x2DI "v2di")
1353 (V3x8HF "v8hf") (V3x4SF "v4sf")
1354 (V3x2DF "v2df") (V3x8BF "v8bf")
1355 (V4x16QI "v16qi") (V4x8HI "v8hi")
1356 (V4x4SI "v4si") (V4x2DI "v2di")
1357 (V4x8HF "v8hf") (V4x4SF "v4sf")
1358 (V4x2DF "v2df") (V4x8BF "v8bf")])
1360 ;; Define element mode for each vector mode.
1361 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
1362 (V4HI "HI") (V8HI "HI")
1363 (V2SI "SI") (V4SI "SI")
1364 (DI "DI") (V2DI "DI")
1365 (V4HF "HF") (V8HF "HF")
1366 (V2SF "SF") (V4SF "SF")
1367 (DF "DF") (V2DF "DF")
1370 (V4BF "BF") (V8BF "BF")
1371 (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI")
1372 (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI")
1373 (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF")
1374 (VNx8BF "BF") (VNx4BF "BF") (VNx2BF "BF")
1375 (VNx4SI "SI") (VNx2SI "SI")
1376 (VNx4SF "SF") (VNx2SF "SF")
1380 ;; Define element mode for each vector mode (lower case).
1381 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
1382 (V4HI "hi") (V8HI "hi")
1383 (V2SI "si") (V4SI "si")
1384 (DI "di") (V2DI "di")
1385 (V4HF "hf") (V8HF "hf")
1386 (V2SF "sf") (V4SF "sf")
1387 (V2DF "df") (DF "df")
1390 (V4BF "bf") (V8BF "bf")
1391 (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi")
1392 (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi")
1393 (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf")
1394 (VNx8BF "bf") (VNx4BF "bf") (VNx2BF "bf")
1395 (VNx4SI "si") (VNx2SI "si")
1396 (VNx4SF "sf") (VNx2SF "sf")
1400 ;; Element mode with floating-point values replaced by like-sized integers.
1401 (define_mode_attr VEL_INT [(VNx16QI "QI")
1402 (VNx8HI "HI") (VNx8HF "HI") (VNx8BF "HI")
1403 (VNx4SI "SI") (VNx4SF "SI")
1404 (VNx2DI "DI") (VNx2DF "DI")])
1406 ;; Gives the mode of the 128-bit lowpart of an SVE vector.
1407 (define_mode_attr V128 [(VNx16QI "V16QI")
1408 (VNx8HI "V8HI") (VNx8HF "V8HF") (VNx8BF "V8BF")
1409 (VNx4SI "V4SI") (VNx4SF "V4SF")
1410 (VNx2DI "V2DI") (VNx2DF "V2DF")])
1412 ;; ...and again in lower case.
1413 (define_mode_attr v128 [(VNx16QI "v16qi")
1414 (VNx8HI "v8hi") (VNx8HF "v8hf") (VNx8BF "v8bf")
1415 (VNx4SI "v4si") (VNx4SF "v4sf")
1416 (VNx2DI "v2di") (VNx2DF "v2df")])
1418 ;; 64-bit container modes the inner or scalar source mode.
1419 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
1420 (V4HI "V4HI") (V8HI "V4HI")
1421 (V2SI "V2SI") (V4SI "V2SI")
1422 (DI "DI") (V2DI "DI")
1423 (V4HF "V4HF") (V8HF "V4HF")
1424 (V2SF "V2SF") (V4SF "V2SF")
1427 ;; 128-bit container modes the inner or scalar source mode.
1428 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
1429 (V4HI "V8HI") (V8HI "V8HI")
1430 (V2SI "V4SI") (V4SI "V4SI")
1431 (DI "V2DI") (V2DI "V2DI")
1432 (V4HF "V8HF") (V8HF "V8HF")
1433 (V2SF "V4SF") (V4SF "V4SF")
1434 (V2DF "V2DF") (SI "V4SI")
1435 (HI "V8HI") (QI "V16QI")])
1437 ;; Half modes of all vector modes.
1438 (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
1439 (V4HI "V2HI") (V8HI "V4HI")
1440 (V2SI "SI") (V4SI "V2SI")
1441 (V2DI "DI") (V2SF "SF")
1442 (V4SF "V2SF") (V4HF "V2HF")
1443 (V8HF "V4HF") (V2DF "DF")
1446 ;; Half modes of all vector modes, in lower-case.
1447 (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
1448 (V4HI "v2hi") (V8HI "v4hi")
1449 (V8HF "v4hf") (V8BF "v4bf")
1450 (V2SI "si") (V4SI "v2si")
1451 (V2DI "di") (V2SF "sf")
1452 (V4SF "v2sf") (V2DF "df")])
1454 ;; Single-element half modes of quad vector modes.
1455 (define_mode_attr V1HALF [(V2DI "V1DI") (V2DF "V1DF")])
1457 ;; Single-element half modes of quad vector modes, in lower-case
1458 (define_mode_attr V1half [(V2DI "v1di") (V2DF "v1df")])
1460 ;; Double modes of vector modes.
1461 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
1462 (V4HF "V8HF") (V4BF "V8BF")
1463 (V2SI "V4SI") (V2SF "V4SF")
1464 (SI "V2SI") (SF "V2SF")
1465 (DI "V2DI") (DF "V2DF")])
1467 ;; Register suffix for double-length mode.
1468 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
1470 ;; Double modes of vector modes (lower case).
1471 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
1472 (V4HF "v8hf") (V4BF "v8bf")
1473 (V2SI "v4si") (V2SF "v4sf")
1474 (SI "v2si") (DI "v2di")
1477 ;; Modes with double-width elements.
1478 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
1479 (V4HI "V2SI") (V8HI "V4SI")
1480 (V2SI "DI") (V4SI "V2DI")])
1482 ;; Narrowed modes for VDN.
1483 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
1485 (define_mode_attr Vnarrowd [(V4HI "v8qi") (V2SI "v4hi")
1488 ;; Narrowed double-modes for VQN (Used for XTN).
1489 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
1493 (define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi")
1496 ;; Narrowed quad-modes for VQN (Used for XTN2).
1497 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
1500 ;; Narrowed modes of vector modes.
1501 (define_mode_attr VNARROW [(VNx8HI "VNx16QI")
1502 (VNx4SI "VNx8HI") (VNx4SF "VNx8HF")
1503 (VNx2DI "VNx4SI") (VNx2DF "VNx4SF")])
1505 ;; Register suffix narrowed modes for VQN.
1506 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
1509 ;; Register suffix narrowed modes for VQN.
1510 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
1513 ;; Widened modes of vector modes.
1514 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
1515 (V2SI "V2DI") (V16QI "V8HI")
1516 (V8HI "V4SI") (V4SI "V2DI")
1518 (V8HF "V4SF") (V4SF "V2DF")
1519 (V4HF "V4SF") (V2SF "V2DF")
1520 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
1521 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
1523 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
1526 ;; Predicate mode associated with VWIDE.
1527 (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
1529 ;; Widened modes of vector modes, lowercase
1530 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
1531 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
1533 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
1534 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
1537 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
1538 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
1539 (V2SI "2d") (V16QI "8h")
1540 (V8HI "4s") (V4SI "2d")
1541 (V8HF "4s") (V4SF "2d")])
1543 ;; Widened scalar register suffixes.
1544 (define_mode_attr Vwstype [(V8QI "h") (V4HI "s")
1545 (V2SI "") (V16QI "h")
1546 (V8HI "s") (V4SI "d")])
1547 ;; Add a .1d for V2SI.
1548 (define_mode_attr Vwsuf [(V8QI "") (V4HI "")
1549 (V2SI ".1d") (V16QI "")
1550 (V8HI "") (V4SI "")])
1552 ;; Scalar mode of widened vector reduction.
1553 (define_mode_attr VWIDE_S [(V8QI "HI") (V4HI "SI")
1554 (V2SI "DI") (V16QI "HI")
1555 (V8HI "SI") (V4SI "DI")])
1557 ;; Widened mode with half the element register suffixes for VD_BHSI/VQW/VQ_HSF.
1558 (define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s")
1559 (V2SI "1d") (V16QI "8h")
1560 (V8HI "4s") (V4SI "2d")])
1562 ;; SVE vector after narrowing.
1563 (define_mode_attr Ventype [(VNx8HI "b")
1564 (VNx4SI "h") (VNx4SF "h")
1565 (VNx2DI "s") (VNx2DF "s")])
1567 ;; SVE vector after widening.
1568 (define_mode_attr Vewtype [(VNx16QI "h")
1569 (VNx8HI "s") (VNx8HF "s")
1570 (VNx4SI "d") (VNx4SF "d")
1573 ;; Widened mode register suffixes for VDW/VQW.
1574 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
1575 (V2SI ".2d") (V16QI ".8h")
1576 (V8HI ".4s") (V4SI ".2d")
1577 (V4HF ".4s") (V2SF ".2d")
1580 ;; Lower part register suffixes for VQW/VQ_HSF.
1581 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
1582 (V4SI "2s") (V8HF "4h")
1585 ;; Whether a mode fits in W or X registers (i.e. "w" for 32-bit modes
1586 ;; and "x" for 64-bit modes).
1587 (define_mode_attr single_wx [(SI "w") (SF "w")
1588 (V8QI "x") (V4HI "x")
1589 (V4HF "x") (V4BF "x")
1590 (V2SI "x") (V2SF "x")
1593 ;; Whether a mode fits in S or D registers (i.e. "s" for 32-bit modes
1594 ;; and "d" for 64-bit modes).
1595 (define_mode_attr single_type [(SI "s") (SF "s")
1596 (V8QI "d") (V4HI "d")
1597 (V4HF "d") (V4BF "d")
1598 (V2SI "d") (V2SF "d")
1601 ;; Whether a double-width mode fits in D or Q registers (i.e. "d" for
1602 ;; 32-bit modes and "q" for 64-bit modes).
1603 (define_mode_attr single_dtype [(SI "d") (SF "d")
1604 (V8QI "q") (V4HI "q")
1605 (V4HF "q") (V4BF "q")
1606 (V2SI "q") (V2SF "q")
1609 ;; Define corresponding core/FP element mode for each vector mode.
1610 (define_mode_attr vw [(V8QI "w") (V16QI "w")
1611 (V4HI "w") (V8HI "w")
1612 (V2SI "w") (V4SI "w")
1614 (V2SF "s") (V4SF "s")
1617 ;; Corresponding core element mode for each vector mode. This is a
1618 ;; variation on <vw> mapping FP modes to GP regs.
1619 (define_mode_attr vwcore [(V8QI "w") (V16QI "w")
1620 (V4HI "w") (V8HI "w")
1621 (V2SI "w") (V4SI "w")
1623 (V4HF "w") (V8HF "w")
1624 (V4BF "w") (V8BF "w")
1625 (V2SF "w") (V4SF "w")
1627 (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
1628 (VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
1629 (VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
1630 (VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
1631 (VNx4SI "w") (VNx2SI "w")
1632 (VNx4SF "w") (VNx2SF "w")
1636 ;; Like vwcore, but for the container mode rather than the element mode.
1637 (define_mode_attr vccore [(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "x")
1638 (VNx8HI "w") (VNx4HI "w") (VNx2HI "x")
1639 (VNx4SI "w") (VNx2SI "x")
1642 ;; Double vector types for ALLX.
1643 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
1645 ;; Mode with floating-point values replaced by like-sized integers.
1646 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
1647 (V4HI "V4HI") (V8HI "V8HI")
1648 (V2SI "V2SI") (V4SI "V4SI")
1649 (DI "DI") (V2DI "V2DI")
1650 (V4HF "V4HI") (V8HF "V8HI")
1651 (V4BF "V4HI") (V8BF "V8HI")
1652 (V2SF "V2SI") (V4SF "V4SI")
1653 (DF "DI") (V2DF "V2DI")
1657 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
1659 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
1660 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
1663 ;; Lower case mode with floating-point values replaced by like-sized integers.
1664 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
1665 (V4HI "v4hi") (V8HI "v8hi")
1666 (V2SI "v2si") (V4SI "v4si")
1667 (DI "di") (V2DI "v2di")
1668 (V4HF "v4hi") (V8HF "v8hi")
1669 (V4BF "v4hi") (V8BF "v8hi")
1670 (V2SF "v2si") (V4SF "v4si")
1671 (DF "di") (V2DF "v2di")
1674 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
1676 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
1677 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
1680 ;; Floating-point equivalent of selected modes.
1681 (define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
1683 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
1684 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
1685 (define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
1687 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
1688 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
1690 ;; Maps full and partial vector modes of any element type to a full-vector
1691 ;; integer mode with the same number of units.
1692 (define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI")
1693 (VNx4QI "VNx4SI") (VNx2QI "VNx2DI")
1694 (VNx8HI "VNx8HI") (VNx4HI "VNx4SI")
1696 (VNx4SI "VNx4SI") (VNx2SI "VNx2DI")
1698 (VNx8HF "VNx8HI") (VNx4HF "VNx4SI")
1700 (VNx8BF "VNx8HI") (VNx4BF "VNx4SI")
1702 (VNx4SF "VNx4SI") (VNx2SF "VNx2DI")
1705 ;; Lower-case version of V_INT_CONTAINER.
1706 (define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi")
1707 (VNx4QI "vnx4si") (VNx2QI "vnx2di")
1708 (VNx8HI "vnx8hi") (VNx4HI "vnx4si")
1710 (VNx4SI "vnx4si") (VNx2SI "vnx2di")
1712 (VNx8HF "vnx8hi") (VNx4HF "vnx4si")
1714 (VNx8BF "vnx8hi") (VNx4BF "vnx4si")
1716 (VNx4SF "vnx4si") (VNx2SF "vnx2di")
1719 ;; Mode for vector conditional operations where the comparison has
1720 ;; different type from the lhs.
1721 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
1722 (V2DI "V2DF") (V2SF "V2SI")
1723 (V4SF "V4SI") (V2DF "V2DI")])
1725 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
1726 (V2DI "v2df") (V2SF "v2si")
1727 (V4SF "v4si") (V2DF "v2di")])
1729 ;; Lower case element modes (as used in shift immediate patterns).
1730 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
1731 (V4HI "hi") (V8HI "hi")
1732 (V2SI "si") (V4SI "si")
1733 (DI "di") (V2DI "di")
1737 ;; Like ve_mode but for the half-width modes.
1738 (define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")])
1740 ;; Vm for lane instructions is restricted to FP_LO_REGS.
1741 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
1742 (V2SI "w") (V4SI "w") (SI "w")])
1744 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")
1745 (V2x8QI "T") (V2x16QI "T")
1746 (V2x4HI "T") (V2x8HI "T")
1747 (V2x2SI "T") (V2x4SI "T")
1748 (V2x1DI "T") (V2x2DI "T")
1749 (V2x4HF "T") (V2x8HF "T")
1750 (V2x2SF "T") (V2x4SF "T")
1751 (V2x1DF "T") (V2x2DF "T")
1752 (V2x4BF "T") (V2x8BF "T")
1753 (V3x8QI "U") (V3x16QI "U")
1754 (V3x4HI "U") (V3x8HI "U")
1755 (V3x2SI "U") (V3x4SI "U")
1756 (V3x1DI "U") (V3x2DI "U")
1757 (V3x4HF "U") (V3x8HF "U")
1758 (V3x2SF "U") (V3x4SF "U")
1759 (V3x1DF "U") (V3x2DF "U")
1760 (V3x4BF "U") (V3x8BF "U")
1761 (V4x8QI "V") (V4x16QI "V")
1762 (V4x4HI "V") (V4x8HI "V")
1763 (V4x2SI "V") (V4x4SI "V")
1764 (V4x1DI "V") (V4x2DI "V")
1765 (V4x4HF "V") (V4x8HF "V")
1766 (V4x2SF "V") (V4x4SF "V")
1767 (V4x1DF "V") (V4x2DF "V")
1768 (V4x4BF "V") (V4x8BF "V")])
1770 ;; This is both the number of Q-Registers needed to hold the corresponding
1771 ;; opaque large integer mode, and the number of elements touched by the
1772 ;; ld..._lane and st..._lane operations.
1773 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")
1774 (V2x8QI "2") (V2x16QI "2")
1775 (V2x4HI "2") (V2x8HI "2")
1776 (V2x2SI "2") (V2x4SI "2")
1777 (V2x1DI "2") (V2x2DI "2")
1778 (V2x4HF "2") (V2x8HF "2")
1779 (V2x2SF "2") (V2x4SF "2")
1780 (V2x1DF "2") (V2x2DF "2")
1781 (V2x4BF "2") (V2x8BF "2")
1782 (V3x8QI "3") (V3x16QI "3")
1783 (V3x4HI "3") (V3x8HI "3")
1784 (V3x2SI "3") (V3x4SI "3")
1785 (V3x1DI "3") (V3x2DI "3")
1786 (V3x4HF "3") (V3x8HF "3")
1787 (V3x2SF "3") (V3x4SF "3")
1788 (V3x1DF "3") (V3x2DF "3")
1789 (V3x4BF "3") (V3x8BF "3")
1790 (V4x8QI "4") (V4x16QI "4")
1791 (V4x4HI "4") (V4x8HI "4")
1792 (V4x2SI "4") (V4x4SI "4")
1793 (V4x1DI "4") (V4x2DI "4")
1794 (V4x4HF "4") (V4x8HF "4")
1795 (V4x2SF "4") (V4x4SF "4")
1796 (V4x1DF "4") (V4x2DF "4")
1797 (V4x4BF "4") (V4x8BF "4")])
1799 ;; Mode for atomic operation suffixes
1800 (define_mode_attr atomic_sfx
1801 [(QI "b") (HI "h") (SI "") (DI "")])
1803 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
1804 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
1805 (SF "si") (DF "di") (SI "sf") (DI "df")
1806 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
1807 (V8HI "v8hf") (HF "hi") (HI "hf")])
1808 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
1809 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
1810 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1811 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
1812 (V8HI "V8HF") (HF "HI") (HI "HF")])
1815 ;; for the inequal width integer to fp conversions
1816 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1817 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
1819 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1820 (V4HI "V8HI") (V8HI "V4HI")
1821 (V8BF "V4BF") (V4BF "V8BF")
1822 (V2SI "V4SI") (V4SI "V2SI")
1823 (DI "V2DI") (V2DI "DI")
1824 (V2SF "V4SF") (V4SF "V2SF")
1825 (V4HF "V8HF") (V8HF "V4HF")
1826 (DF "V2DF") (V2DF "DF")])
1828 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1829 (V4HI "to_128") (V8HI "to_64")
1830 (V2SI "to_128") (V4SI "to_64")
1831 (DI "to_128") (V2DI "to_64")
1832 (V4HF "to_128") (V8HF "to_64")
1833 (V2SF "to_128") (V4SF "to_64")
1834 (V4BF "to_128") (V8BF "to_64")
1835 (DF "to_128") (V2DF "to_64")])
1837 ;; For certain vector-by-element multiplication instructions we must
1838 ;; constrain the 16-bit cases to use only V0-V15. This is covered by
1839 ;; the 'x' constraint. All other modes may use the 'w' constraint.
1840 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
1841 (V4HI "x") (V8HI "x")
1842 (V4HF "x") (V8HF "x")
1843 (V2SF "w") (V4SF "w")
1844 (V2DF "w") (DF "w")])
1846 ;; Defined to 'f' for types whose element type is a float type.
1847 (define_mode_attr f [(V8QI "") (V16QI "")
1851 (V4HF "f") (V8HF "f")
1852 (V2SF "f") (V4SF "f")
1853 (V2DF "f") (DF "f")])
1855 ;; Defined to '_fp' for types whose element type is a float type.
1856 (define_mode_attr fp [(V8QI "") (V16QI "")
1860 (V4HF "_fp") (V8HF "_fp")
1861 (V2SF "_fp") (V4SF "_fp")
1862 (V2DF "_fp") (DF "_fp")
1865 ;; Defined to '_q' for 128-bit types.
1866 (define_mode_attr q [(V8QI "") (V16QI "_q")
1867 (V4HI "") (V8HI "_q")
1868 (V4BF "") (V8BF "_q")
1869 (V2SI "") (V4SI "_q")
1871 (V4HF "") (V8HF "_q")
1872 (V4BF "") (V8BF "_q")
1873 (V2SF "") (V4SF "_q")
1875 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")
1876 (V2x8QI "") (V2x16QI "_q")
1877 (V2x4HI "") (V2x8HI "_q")
1878 (V2x2SI "") (V2x4SI "_q")
1879 (V2x1DI "") (V2x2DI "_q")
1880 (V2x4HF "") (V2x8HF "_q")
1881 (V2x2SF "") (V2x4SF "_q")
1882 (V2x1DF "") (V2x2DF "_q")
1883 (V2x4BF "") (V2x8BF "_q")
1884 (V3x8QI "") (V3x16QI "_q")
1885 (V3x4HI "") (V3x8HI "_q")
1886 (V3x2SI "") (V3x4SI "_q")
1887 (V3x1DI "") (V3x2DI "_q")
1888 (V3x4HF "") (V3x8HF "_q")
1889 (V3x2SF "") (V3x4SF "_q")
1890 (V3x1DF "") (V3x2DF "_q")
1891 (V3x4BF "") (V3x8BF "_q")
1892 (V4x8QI "") (V4x16QI "_q")
1893 (V4x4HI "") (V4x8HI "_q")
1894 (V4x2SI "") (V4x4SI "_q")
1895 (V4x1DI "") (V4x2DI "_q")
1896 (V4x4HF "") (V4x8HF "_q")
1897 (V4x2SF "") (V4x4SF "_q")
1898 (V4x1DF "") (V4x2DF "_q")
1899 (V4x4BF "") (V4x8BF "_q")])
1901 ;; Equivalent of the "q" attribute for the <VDBL> mode.
1902 (define_mode_attr dblq [(SI "") (SF "")
1903 (V8QI "_q") (V4HI "_q")
1904 (V4HF "_q") (V4BF "_q")
1905 (V2SI "_q") (V2SF "_q")
1906 (DI "_q") (DF "_q")])
1908 (define_mode_attr vp [(V8QI "v") (V16QI "v")
1909 (V4HI "v") (V8HI "v")
1910 (V2SI "p") (V4SI "v")
1911 (V2DI "p") (V2DF "p")
1912 (V2SF "p") (V4SF "v")
1913 (V4HF "v") (V8HF "v")])
1915 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1916 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1917 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1918 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
1921 ;; Register suffix for DOTPROD input types from the return type.
1922 (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1924 ;; Register suffix for BFDOT input types from the return type.
1925 (define_mode_attr Vbfdottype [(V2SF "4h") (V4SF "8h")])
1927 ;; Sum of lengths of instructions needed to move vector registers of a mode.
1928 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")
1929 (V2x8QI "8") (V2x16QI "8")
1930 (V2x4HI "8") (V2x8HI "8")
1931 (V2x2SI "8") (V2x4SI "8")
1932 (V2x1DI "8") (V2x2DI "8")
1933 (V2x4HF "8") (V2x8HF "8")
1934 (V2x2SF "8") (V2x4SF "8")
1935 (V2x1DF "8") (V2x2DF "8")
1936 (V2x4BF "8") (V2x8BF "8")
1937 (V3x8QI "12") (V3x16QI "12")
1938 (V3x4HI "12") (V3x8HI "12")
1939 (V3x2SI "12") (V3x4SI "12")
1940 (V3x1DI "12") (V3x2DI "12")
1941 (V3x4HF "12") (V3x8HF "12")
1942 (V3x2SF "12") (V3x4SF "12")
1943 (V3x1DF "12") (V3x2DF "12")
1944 (V3x4BF "12") (V3x8BF "12")
1945 (V4x8QI "16") (V4x16QI "16")
1946 (V4x4HI "16") (V4x8HI "16")
1947 (V4x2SI "16") (V4x4SI "16")
1948 (V4x1DI "16") (V4x2DI "16")
1949 (V4x4HF "16") (V4x8HF "16")
1950 (V4x2SF "16") (V4x4SF "16")
1951 (V4x1DF "16") (V4x2DF "16")
1952 (V4x4BF "16") (V4x8BF "16")])
1954 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1955 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1956 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1958 ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1959 (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1961 ;; Width of 2nd and 3rd arguments to bf16 vector multiply add/sub
1962 (define_mode_attr VBFMLA_W [(V2SF "V4BF") (V4SF "V8BF")])
1964 (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1966 (define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1968 (define_mode_attr isquadop [(V8QI "") (V16QI "q") (V4BF "") (V8BF "q")])
1970 (define_code_attr f16mac [(plus "a") (minus "s")])
1972 ;; Map smax to smin and umax to umin.
1973 (define_code_attr max_opp [(smax "smin") (umax "umin")])
1975 ;; Same as above, but louder.
1976 (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1978 ;; The number of subvectors in an SVE_STRUCT.
1979 (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1980 (VNx8SI "2") (VNx4DI "2")
1982 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1983 (VNx48QI "3") (VNx24HI "3")
1984 (VNx12SI "3") (VNx6DI "3")
1986 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1987 (VNx64QI "4") (VNx32HI "4")
1988 (VNx16SI "4") (VNx8DI "4")
1990 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1992 ;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1993 ;; equal to vector_count * 4.
1994 (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1995 (VNx8SI "8") (VNx4DI "8")
1997 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1998 (VNx48QI "12") (VNx24HI "12")
1999 (VNx12SI "12") (VNx6DI "12")
2001 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
2002 (VNx64QI "16") (VNx32HI "16")
2003 (VNx16SI "16") (VNx8DI "16")
2005 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
2007 ;; The type of a subvector in an SVE_STRUCT.
2008 (define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
2009 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
2011 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
2012 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
2014 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
2016 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
2017 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
2019 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
2021 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
2022 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
2024 ;; ...and again in lower case.
2025 (define_mode_attr vsingle [(VNx32QI "vnx16qi")
2026 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
2028 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
2029 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
2031 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
2033 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
2034 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
2036 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
2038 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
2039 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
2041 ;; The predicate mode associated with an SVE data mode. For structure modes
2042 ;; this is equivalent to the <VPRED> of the subvector mode.
2043 (define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI")
2044 (VNx4QI "VNx4BI") (VNx2QI "VNx2BI")
2045 (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI")
2046 (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI")
2047 (VNx8BF "VNx8BI") (VNx4BF "VNx4BI") (VNx2BF "VNx2BI")
2048 (VNx4SI "VNx4BI") (VNx2SI "VNx2BI")
2049 (VNx4SF "VNx4BI") (VNx2SF "VNx2BI")
2053 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
2055 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
2056 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
2058 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
2060 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
2061 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
2063 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
2065 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
2066 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
2068 ;; ...and again in lower case.
2069 (define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi")
2070 (VNx4QI "vnx4bi") (VNx2QI "vnx2bi")
2071 (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi")
2072 (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi")
2073 (VNx8BF "vnx8bi") (VNx4BF "vnx4bi") (VNx2BF "vnx2bi")
2074 (VNx4SI "vnx4bi") (VNx2SI "vnx2bi")
2075 (VNx4SF "vnx4bi") (VNx2SF "vnx2bi")
2079 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
2081 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
2082 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
2084 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
2086 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
2087 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
2089 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
2091 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
2092 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
2094 (define_mode_attr VDOUBLE [(VNx16QI "VNx32QI")
2095 (VNx8HI "VNx16HI") (VNx8HF "VNx16HF")
2097 (VNx4SI "VNx8SI") (VNx4SF "VNx8SF")
2098 (VNx2DI "VNx4DI") (VNx2DF "VNx4DF")])
2100 ;; On AArch64 the By element instruction doesn't have a 2S variant.
2101 ;; However because the instruction always selects a pair of values
2102 ;; The normal 3SAME instruction can be used here instead.
2103 (define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
2104 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
2107 ;; The number of bytes controlled by a predicate
2108 (define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
2109 (VNx4BI "4") (VNx2BI "8")])
2111 ;; Two-nybble mask for partial vector modes: nunits, byte size.
2112 (define_mode_attr self_mask [(VNx8QI "0x81")
2119 ;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above.
2120 (define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41")
2122 (VNx4SI "0x43") (VNx2SI "0x23")
2125 ;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index.
2126 (define_mode_attr sve_lane_con [(VNx8HI "y") (VNx4SI "y") (VNx2DI "x")
2127 (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")])
2129 ;; The constraint to use for an SVE FCMLA lane index.
2130 (define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")])
2132 ;; -------------------------------------------------------------------
2134 ;; -------------------------------------------------------------------
2136 ;; This code iterator allows the various shifts supported on the core
2137 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert rotate])
2139 ;; This code iterator allows all shifts except for rotates.
2140 (define_code_iterator SHIFT_no_rotate [ashift ashiftrt lshiftrt])
2142 ;; This code iterator allows the shifts supported in arithmetic instructions
2143 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
2145 (define_code_iterator SHIFTRT [ashiftrt lshiftrt])
2147 ;; Code iterator for logical operations
2148 (define_code_iterator LOGICAL [and ior xor])
2150 ;; LOGICAL with plus, for when | gets converted to +.
2151 (define_code_iterator LOGICAL_OR_PLUS [and ior xor plus])
2153 ;; LOGICAL without AND.
2154 (define_code_iterator LOGICAL_OR [ior xor])
2156 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
2157 (define_code_iterator NLOGICAL [and ior])
2159 ;; Code iterator for unary negate and bitwise complement.
2160 (define_code_iterator NEG_NOT [neg not])
2162 ;; Code iterator for sign/zero extension
2163 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
2164 (define_code_iterator ANY_EXTEND2 [sign_extend zero_extend])
2166 ;; All division operations (signed/unsigned)
2167 (define_code_iterator ANY_DIV [div udiv])
2169 ;; Code iterator for sign/zero extraction
2170 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
2172 ;; Code iterator for equality comparisons
2173 (define_code_iterator EQL [eq ne])
2175 ;; Code iterator for less-than and greater/equal-to
2176 (define_code_iterator LTGE [lt ge])
2178 ;; Iterator for __sync_<op> operations that where the operation can be
2179 ;; represented directly RTL. This is all of the sync operations bar
2181 (define_code_iterator atomic_op [plus minus ior xor and])
2183 ;; Iterator for integer conversions
2184 (define_code_iterator FIXUORS [fix unsigned_fix])
2186 ;; Iterator for float conversions
2187 (define_code_iterator FLOATUORS [float unsigned_float])
2189 ;; Code iterator for variants of vector max and min.
2190 (define_code_iterator MAXMIN [smax smin umax umin])
2192 ;; Code iterator for min/max ops but without UMAX.
2193 (define_code_iterator MAXMIN_NOUMAX [smax smin umin])
2195 (define_code_iterator FMAXMIN [smax smin])
2197 ;; Signed and unsigned max operations.
2198 (define_code_iterator USMAX [smax umax])
2200 ;; Code iterator for plus and minus.
2201 (define_code_iterator ADDSUB [plus minus])
2203 ;; Code iterator for variants of vector saturating binary ops.
2204 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
2206 ;; Code iterator for variants of vector saturating unary ops.
2207 (define_code_iterator UNQOPS [ss_neg ss_abs])
2209 ;; Code iterator for signed variants of vector saturating binary ops.
2210 (define_code_iterator SBINQOPS [ss_plus ss_minus])
2212 ;; Code iterator for unsigned variants of vector saturating binary ops.
2213 (define_code_iterator UBINQOPS [us_plus us_minus])
2215 ;; Modular and saturating addition.
2216 (define_code_iterator ANY_PLUS [plus ss_plus us_plus])
2218 ;; Saturating addition.
2219 (define_code_iterator SAT_PLUS [ss_plus us_plus])
2221 ;; Modular and saturating subtraction.
2222 (define_code_iterator ANY_MINUS [minus ss_minus us_minus])
2224 ;; Saturating subtraction.
2225 (define_code_iterator SAT_MINUS [ss_minus us_minus])
2227 ;; Comparison operators for <F>CM.
2228 (define_code_iterator COMPARISONS [lt le eq ge gt])
2230 ;; Unsigned comparison operators.
2231 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
2233 ;; Unsigned comparison operators.
2234 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
2236 ;; Signed and unsigned saturating truncations.
2237 (define_code_iterator SAT_TRUNC [ss_truncate us_truncate])
2239 ;; SVE integer unary operations.
2240 (define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount
2241 (ss_abs "TARGET_SVE2")
2242 (ss_neg "TARGET_SVE2")])
2244 ;; SVE integer binary operations.
2245 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
2246 ashift ashiftrt lshiftrt
2248 (ss_plus "TARGET_SVE2")
2249 (us_plus "TARGET_SVE2")
2250 (ss_minus "TARGET_SVE2")
2251 (us_minus "TARGET_SVE2")])
2253 ;; SVE integer binary division operations.
2254 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
2256 ;; SVE integer binary operations that have an immediate form.
2257 (define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
2259 ;; SVE floating-point operations with an unpredicated all-register form.
2260 (define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
2262 ;; SVE integer comparisons.
2263 (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
2265 ;; -------------------------------------------------------------------
2267 ;; -------------------------------------------------------------------
2268 ;; Map rtl objects to optab names
2269 (define_code_attr optab [(ashift "ashl")
2274 (sign_extend "extend")
2275 (zero_extend "zero_extend")
2276 (sign_extract "extv")
2277 (zero_extract "extzv")
2279 (unsigned_fix "fixuns")
2281 (unsigned_float "floatuns")
2284 (popcount "popcount")
2317 (define_code_attr addsub [(ss_plus "add")
2322 ;; For comparison operators we use the FCM* and CM* instructions.
2323 ;; As there are no CMLE or CMLT instructions which act on 3 vector
2324 ;; operands, we must use CMGE or CMGT and swap the order of the
2327 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
2328 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
2329 (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
2330 (ltu "2") (leu "2") (geu "1") (gtu "1")])
2331 (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
2332 (ltu "1") (leu "1") (geu "2") (gtu "2")])
2334 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
2335 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
2338 ;; The AArch64 condition associated with an rtl comparison code.
2339 (define_code_attr cmp_op [(lt "lt")
2350 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
2351 (unsigned_fix "fixuns_trunc")])
2353 ;; Optab prefix for sign/zero-extending operations
2354 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
2356 (fix "") (unsigned_fix "u")
2357 (float "s") (unsigned_float "u")
2358 (ss_plus "s") (us_plus "u")
2359 (ss_minus "s") (us_minus "u")])
2361 ;; Similar for the instruction mnemonics
2362 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
2363 (lshiftrt "lsr") (rotatert "ror") (rotate "ror")])
2364 ;; True if shift is rotate left.
2365 (define_code_attr is_rotl [(ashift "0") (ashiftrt "0")
2366 (lshiftrt "0") (rotatert "0") (rotate "1")])
2368 ;; Op prefix for shift right and accumulate.
2369 (define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
2371 ;; op prefix for shift right and narrow.
2372 (define_code_attr srn_op [(ashiftrt "r") (lshiftrt "")])
2374 ;; Map shift operators onto underlying bit-field instructions
2375 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
2376 (lshiftrt "ubfx") (rotatert "extr")])
2378 ;; Logical operator instruction mnemonics
2379 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
2381 ;; Operation names for negate and bitwise complement.
2382 (define_code_attr neg_not_op [(neg "neg") (not "not")])
2384 ;; csinv, csneg insn suffixes.
2385 (define_code_attr neg_not_cs [(neg "neg") (not "inv")])
2387 ;; Similar, but when the second operand is inverted.
2388 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
2390 ;; Similar, but when both operands are inverted.
2391 (define_code_attr logical_nn [(and "nor") (ior "nand")])
2393 ;; Sign- or zero-extending data-op
2394 (define_code_attr su [(sign_extend "s") (zero_extend "u")
2395 (sign_extract "s") (zero_extract "u")
2396 (fix "s") (unsigned_fix "u")
2397 (div "s") (udiv "u")
2398 (smax "s") (umax "u")
2399 (smin "s") (umin "u")
2400 (ss_truncate "s") (us_truncate "u")])
2402 ;; "s" for signed ops, empty for unsigned ones.
2403 (define_code_attr s [(sign_extend "s") (zero_extend "")])
2405 ;; Map signed/unsigned ops to the corresponding extension.
2406 (define_code_attr paired_extend [(ss_plus "sign_extend")
2407 (us_plus "zero_extend")
2408 (ss_minus "sign_extend")
2409 (us_minus "zero_extend")])
2411 ;; Whether a shift is left or right.
2412 (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
2414 ;; Emit conditional branch instructions.
2415 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
2417 ;; Emit cbz/cbnz depending on comparison type.
2418 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
2420 ;; Emit inverted cbz/cbnz depending on comparison type.
2421 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
2423 ;; Emit tbz/tbnz depending on comparison type.
2424 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
2426 ;; Emit inverted tbz/tbnz depending on comparison type.
2427 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
2429 ;; Max/min attributes.
2430 (define_code_attr maxmin [(smax "max")
2435 ;; MLA/MLS attributes.
2436 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
2438 ;; Atomic operations
2439 (define_code_attr atomic_optab
2440 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
2442 (define_code_attr atomic_op_operand
2443 [(ior "aarch64_logical_operand")
2444 (xor "aarch64_logical_operand")
2445 (and "aarch64_logical_operand")
2446 (plus "aarch64_plus_operand")
2447 (minus "aarch64_plus_operand")])
2449 ;; Constants acceptable for atomic operations.
2450 ;; This definition must appear in this file before the iterators it refers to.
2451 (define_code_attr const_atomic
2452 [(plus "IJ") (minus "IJ")
2453 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
2454 (and "<lconst_atomic>")])
2456 ;; Attribute to describe constants acceptable in atomic logical operations
2457 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
2459 ;; The integer SVE instruction that implements an rtx code.
2460 (define_code_attr sve_int_op [(plus "add")
2488 (define_code_attr sve_int_op_rev [(plus "add")
2506 (us_minus "uqsubr")])
2508 ;; The floating-point SVE instruction that implements an rtx code.
2509 (define_code_attr sve_fp_op [(plus "fadd")
2513 ;; The SVE immediate constraint to use for an rtl code.
2514 (define_code_attr sve_imm_con [(mult "vsm")
2530 ;; The prefix letter to use when printing an immediate operand.
2531 (define_code_attr sve_imm_prefix [(mult "")
2537 ;; The predicate to use for the second input operand in a cond_<optab><mode>
2539 (define_code_attr sve_pred_int_rhs2_operand
2540 [(plus "register_operand")
2541 (minus "register_operand")
2542 (mult "register_operand")
2543 (smax "register_operand")
2544 (umax "register_operand")
2545 (smin "register_operand")
2546 (umin "register_operand")
2547 (ashift "aarch64_sve_lshift_operand")
2548 (ashiftrt "aarch64_sve_rshift_operand")
2549 (lshiftrt "aarch64_sve_rshift_operand")
2550 (and "aarch64_sve_pred_and_operand")
2551 (ior "register_operand")
2552 (xor "register_operand")
2553 (ss_plus "register_operand")
2554 (us_plus "register_operand")
2555 (ss_minus "register_operand")
2556 (us_minus "register_operand")])
2558 (define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
2559 (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")])
2561 ;; -------------------------------------------------------------------
2563 ;; -------------------------------------------------------------------
2565 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
2566 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
2568 ;; The unspec codes for the SABDL, UABDL AdvancedSIMD instructions.
2569 (define_int_iterator ABDL [UNSPEC_SABDL UNSPEC_UABDL])
2571 ;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
2572 (define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
2574 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
2575 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
2577 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
2578 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
2580 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
2581 UNSPEC_SMAXV UNSPEC_SMINV])
2583 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
2584 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
2586 (define_int_iterator FMAXMINNMV [UNSPEC_FMAXNMV UNSPEC_FMINNMV])
2588 (define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
2590 (define_int_iterator USADDLP [UNSPEC_SADDLP UNSPEC_UADDLP])
2592 (define_int_iterator USADDLV [UNSPEC_SADDLV UNSPEC_UADDLV])
2594 (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
2596 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
2597 UNSPEC_SRHADD UNSPEC_URHADD
2598 UNSPEC_SHSUB UNSPEC_UHSUB])
2600 (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
2602 (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
2604 (define_int_iterator BSL_DUP [1 2])
2606 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
2608 (define_int_iterator DOTPROD_I8MM [UNSPEC_USDOT UNSPEC_SUDOT])
2609 (define_int_iterator DOTPROD_US_ONLY [UNSPEC_USDOT])
2611 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
2612 UNSPEC_SUBHN UNSPEC_RSUBHN])
2614 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
2615 UNSPEC_FMAXNM UNSPEC_FMINNM])
2617 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
2618 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
2620 (define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
2621 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
2623 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
2625 (define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS
2626 UNSPEC_SMULHRS UNSPEC_UMULHRS])
2628 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
2630 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
2631 UNSPEC_SRSHL UNSPEC_URSHL])
2633 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
2635 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
2636 UNSPEC_SQRSHL UNSPEC_UQRSHL])
2638 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
2639 UNSPEC_SRSRA UNSPEC_URSRA])
2641 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
2642 UNSPEC_SSRI UNSPEC_USRI])
2645 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
2647 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
2649 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
2650 UNSPEC_SQSHRN UNSPEC_UQSHRN
2651 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
2653 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
2655 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
2656 UNSPEC_TRN1 UNSPEC_TRN2
2657 UNSPEC_UZP1 UNSPEC_UZP2])
2659 (define_int_iterator PERMUTEQ [UNSPEC_ZIP1Q UNSPEC_ZIP2Q
2660 UNSPEC_TRN1Q UNSPEC_TRN2Q
2661 UNSPEC_UZP1Q UNSPEC_UZP2Q])
2663 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
2664 UNSPEC_UZP1 UNSPEC_UZP2])
2666 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
2668 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
2669 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
2672 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
2673 UNSPEC_FRINTA UNSPEC_FRINTN])
2675 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
2676 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
2678 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
2679 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
2680 UNSPEC_CRC32CW UNSPEC_CRC32CX])
2682 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
2683 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
2685 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
2687 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
2689 (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
2691 (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
2692 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
2694 (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
2696 ;; Iterators for fp16 operations
2698 (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
2700 (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
2702 (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
2703 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
2705 (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
2707 (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
2709 (define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB])
2711 (define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB])
2713 (define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB
2714 UNSPEC_REVH UNSPEC_REVW])
2716 (define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE])
2718 (define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA])
2720 (define_int_iterator SVE_INT_SHIFT_IMM [UNSPEC_ASRD
2721 (UNSPEC_SQSHLU "TARGET_SVE2")
2722 (UNSPEC_SRSHR "TARGET_SVE2")
2723 (UNSPEC_URSHR "TARGET_SVE2")])
2725 (define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS])
2727 (define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL])
2729 (define_int_iterator SVE_BFLOAT_TERNARY_LONG [UNSPEC_BFDOT
2734 (define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE [UNSPEC_BFDOT
2738 (define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
2746 (define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
2752 (define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
2764 ;; Same as SVE_COND_FP_UNARY, but without codes that have a dedicated
2765 ;; <optab><mode>2 expander.
2766 (define_int_iterator SVE_COND_FP_UNARY_OPTAB [UNSPEC_COND_FABS
2775 UNSPEC_COND_FRINTZ])
2777 (define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
2778 (define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
2779 (define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
2781 (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
2791 ;; Same as SVE_COND_FP_BINARY, but without codes that have a dedicated
2792 ;; <optab><mode>3 expander.
2793 (define_int_iterator SVE_COND_FP_BINARY_OPTAB [UNSPEC_COND_FADD
2802 (define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE])
2804 (define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD])
2805 (define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB])
2806 (define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL])
2808 (define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX
2814 (define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV
2817 (define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90
2818 UNSPEC_COND_FCADD270])
2820 (define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX
2823 UNSPEC_COND_FMINNM])
2825 ;; Floating-point max/min operations that correspond to optabs,
2826 ;; as opposed to those that are internal to the port.
2827 (define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
2828 UNSPEC_COND_FMINNM])
2830 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
2835 (define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA
2837 UNSPEC_COND_FCMLA180
2838 UNSPEC_COND_FCMLA270])
2840 (define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE
2841 UNSPEC_COND_CMPGE_WIDE
2842 UNSPEC_COND_CMPGT_WIDE
2843 UNSPEC_COND_CMPHI_WIDE
2844 UNSPEC_COND_CMPHS_WIDE
2845 UNSPEC_COND_CMPLE_WIDE
2846 UNSPEC_COND_CMPLO_WIDE
2847 UNSPEC_COND_CMPLS_WIDE
2848 UNSPEC_COND_CMPLT_WIDE
2849 UNSPEC_COND_CMPNE_WIDE])
2851 ;; SVE FP comparisons that accept #0.0.
2852 (define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
2859 (define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE
2864 (define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS])
2866 (define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90
2867 UNSPEC_FCMLA180 UNSPEC_FCMLA270])
2869 (define_int_iterator SVE_WHILE [UNSPEC_WHILELE UNSPEC_WHILELO
2870 UNSPEC_WHILELS UNSPEC_WHILELT
2871 (UNSPEC_WHILEGE "TARGET_SVE2")
2872 (UNSPEC_WHILEGT "TARGET_SVE2")
2873 (UNSPEC_WHILEHI "TARGET_SVE2")
2874 (UNSPEC_WHILEHS "TARGET_SVE2")
2875 (UNSPEC_WHILERW "TARGET_SVE2")
2876 (UNSPEC_WHILEWR "TARGET_SVE2")])
2878 (define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR])
2880 (define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE
2881 UNSPEC_ASHIFTRT_WIDE
2882 UNSPEC_LSHIFTRT_WIDE])
2884 (define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
2886 (define_int_iterator SVE_PRED_LOAD [UNSPEC_PRED_X UNSPEC_LD1_SVE])
2888 (define_int_attr pred_load [(UNSPEC_PRED_X "_x") (UNSPEC_LD1_SVE "")])
2890 (define_int_iterator SVE2_U32_UNARY [UNSPEC_URECPE UNSPEC_RSQRTE])
2892 (define_int_iterator SVE2_INT_UNARY_NARROWB [UNSPEC_SQXTNB
2896 (define_int_iterator SVE2_INT_UNARY_NARROWT [UNSPEC_SQXTNT
2900 (define_int_iterator SVE2_INT_BINARY [UNSPEC_SQDMULH
2903 (define_int_iterator SVE2_INT_BINARY_LANE [UNSPEC_SQDMULH
2906 (define_int_iterator SVE2_INT_BINARY_LONG [UNSPEC_SABDLB
2928 (define_int_iterator SVE2_INT_BINARY_LONG_LANE [UNSPEC_SMULLB
2935 (define_int_iterator SVE2_INT_BINARY_NARROWB [UNSPEC_ADDHNB
2940 (define_int_iterator SVE2_INT_BINARY_NARROWT [UNSPEC_ADDHNT
2945 (define_int_iterator SVE2_INT_BINARY_PAIR [UNSPEC_ADDP
2951 (define_int_iterator SVE2_FP_BINARY_PAIR [UNSPEC_FADDP
2957 (define_int_iterator SVE2_INT_BINARY_PAIR_LONG [UNSPEC_SADALP UNSPEC_UADALP])
2959 (define_int_iterator SVE2_INT_BINARY_WIDE [UNSPEC_SADDWB
2968 (define_int_iterator SVE2_INT_SHIFT_IMM_LONG [UNSPEC_SSHLLB
2973 (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWB [UNSPEC_RSHRNB
2982 (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWT [UNSPEC_RSHRNT
2991 (define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI])
2993 (define_int_iterator SVE2_INT_CADD [UNSPEC_CADD90
2998 (define_int_iterator SVE2_INT_BITPERM [UNSPEC_BDEP UNSPEC_BEXT UNSPEC_BGRP])
3000 (define_int_iterator SVE2_INT_TERNARY [UNSPEC_ADCLB
3009 (define_int_iterator SVE2_INT_TERNARY_LANE [UNSPEC_SQRDMLAH
3012 (define_int_iterator SVE2_FP_TERNARY_LONG [UNSPEC_FMLALB
3017 (define_int_iterator SVE2_FP_TERNARY_LONG_LANE [UNSPEC_FMLALB
3022 (define_int_iterator SVE2_INT_CMLA [UNSPEC_CMLA
3029 UNSPEC_SQRDCMLAH270])
3031 ;; Unlike the normal CMLA instructions these represent the actual operation
3032 ;; to be performed. They will always need to be expanded into multiple
3033 ;; sequences consisting of CMLA.
3034 (define_int_iterator SVE2_INT_CMLA_OP [UNSPEC_CMLA
3037 UNSPEC_CMLA180_CONJ])
3039 ;; Unlike the normal CMLA instructions these represent the actual operation
3040 ;; to be performed. They will always need to be expanded into multiple
3041 ;; sequences consisting of CMLA.
3042 (define_int_iterator SVE2_INT_CMUL_OP [UNSPEC_CMUL
3045 ;; Same as SVE2_INT_CADD but exclude the saturating instructions
3046 (define_int_iterator SVE2_INT_CADD_OP [UNSPEC_CADD90
3049 (define_int_iterator SVE2_INT_CDOT [UNSPEC_CDOT
3054 (define_int_iterator SVE2_INT_ADD_BINARY_LONG [UNSPEC_SABDLB
3063 (define_int_iterator SVE2_INT_QADD_BINARY_LONG [UNSPEC_SQDMULLB
3067 (define_int_iterator SVE2_INT_SUB_BINARY_LONG [UNSPEC_SMULLB
3072 (define_int_iterator SVE2_INT_QSUB_BINARY_LONG [UNSPEC_SQDMULLB
3076 (define_int_iterator SVE2_INT_ADD_BINARY_LONG_LANE [UNSPEC_SMULLB
3081 (define_int_iterator SVE2_INT_QADD_BINARY_LONG_LANE [UNSPEC_SQDMULLB
3084 (define_int_iterator SVE2_INT_SUB_BINARY_LONG_LANE [UNSPEC_SMULLB
3089 (define_int_iterator SVE2_INT_QSUB_BINARY_LONG_LANE [UNSPEC_SQDMULLB
3092 (define_int_iterator SVE2_COND_INT_UNARY_FP [UNSPEC_COND_FLOGB])
3094 (define_int_iterator SVE2_COND_FP_UNARY_LONG [UNSPEC_COND_FCVTLT])
3096 (define_int_iterator SVE2_COND_FP_UNARY_NARROWB [UNSPEC_COND_FCVTX])
3098 (define_int_iterator SVE2_COND_INT_BINARY [UNSPEC_SHADD
3111 (define_int_iterator SVE2_COND_INT_BINARY_NOREV [UNSPEC_SUQADD
3114 (define_int_iterator SVE2_COND_INT_BINARY_REV [UNSPEC_SHADD
3125 (define_int_iterator SVE2_COND_INT_SHIFT [UNSPEC_SQSHL
3128 (define_int_iterator SVE2_MATCH [UNSPEC_MATCH UNSPEC_NMATCH])
3130 (define_int_iterator SVE2_PMULL [UNSPEC_PMULLB UNSPEC_PMULLT])
3132 (define_int_iterator SVE2_PMULL_PAIR [UNSPEC_PMULLB_PAIR UNSPEC_PMULLT_PAIR])
3134 (define_int_iterator FCADD [UNSPEC_FCADD90
3137 (define_int_iterator FCMLA [UNSPEC_FCMLA
3142 (define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X
3143 UNSPEC_FRINT64Z UNSPEC_FRINT64X])
3145 (define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB])
3147 (define_int_iterator SVE_BRKP [UNSPEC_BRKPA UNSPEC_BRKPB])
3149 (define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB])
3151 (define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT])
3153 (define_int_iterator MATMUL [UNSPEC_SMATMUL UNSPEC_UMATMUL
3156 (define_int_iterator FMMLA [UNSPEC_FMMLA])
3158 (define_int_iterator BF_MLA [UNSPEC_BFMLALB
3161 (define_int_iterator FCMLA_OP [UNSPEC_FCMLA
3164 UNSPEC_FCMLA180_CONJ])
3166 (define_int_iterator FCMUL_OP [UNSPEC_FCMUL
3169 ;; Iterators for atomic operations.
3171 (define_int_iterator ATOMIC_LDOP
3172 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
3173 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
3175 (define_int_attr atomic_ldop
3176 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
3177 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
3179 (define_int_attr atomic_ldoptab
3180 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
3181 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
3183 ;; -------------------------------------------------------------------
3184 ;; Int Iterators Attributes.
3185 ;; -------------------------------------------------------------------
3187 ;; The optab associated with an operation. Note that for ANDF, IORF
3188 ;; and XORF, the optab pattern is not actually defined; we just use this
3189 ;; name for consistency with the integer patterns.
3190 (define_int_attr optab [(UNSPEC_ANDF "and")
3193 (UNSPEC_SADDV "sadd")
3194 (UNSPEC_UADDV "uadd")
3198 (UNSPEC_FRECPE "frecpe")
3199 (UNSPEC_FRECPS "frecps")
3200 (UNSPEC_RSQRTE "frsqrte")
3201 (UNSPEC_RSQRTS "frsqrts")
3202 (UNSPEC_RBIT "rbit")
3203 (UNSPEC_REVB "revb")
3204 (UNSPEC_REVH "revh")
3205 (UNSPEC_REVW "revw")
3206 (UNSPEC_UMAXV "umax")
3207 (UNSPEC_UMINV "umin")
3208 (UNSPEC_SMAXV "smax")
3209 (UNSPEC_SMINV "smin")
3210 (UNSPEC_CADD90 "cadd90")
3211 (UNSPEC_CADD270 "cadd270")
3212 (UNSPEC_CDOT "cdot")
3213 (UNSPEC_CDOT90 "cdot90")
3214 (UNSPEC_CDOT180 "cdot180")
3215 (UNSPEC_CDOT270 "cdot270")
3216 (UNSPEC_CMLA "cmla")
3217 (UNSPEC_CMLA90 "cmla90")
3218 (UNSPEC_CMLA180 "cmla180")
3219 (UNSPEC_CMLA270 "cmla270")
3220 (UNSPEC_FADDV "plus")
3221 (UNSPEC_FMAXNMV "smax")
3222 (UNSPEC_FMAXV "smax_nan")
3223 (UNSPEC_FMINNMV "smin")
3224 (UNSPEC_FMINV "smin_nan")
3225 (UNSPEC_SMUL_HIGHPART "smulh")
3226 (UNSPEC_UMUL_HIGHPART "umulh")
3228 (UNSPEC_FMLS "fnma")
3229 (UNSPEC_FCMLA "fcmla")
3230 (UNSPEC_FCMLA90 "fcmla90")
3231 (UNSPEC_FCMLA180 "fcmla180")
3232 (UNSPEC_FCMLA270 "fcmla270")
3233 (UNSPEC_FEXPA "fexpa")
3234 (UNSPEC_FTSMUL "ftsmul")
3235 (UNSPEC_FTSSEL "ftssel")
3236 (UNSPEC_PMULLB "pmullb")
3237 (UNSPEC_PMULLB_PAIR "pmullb_pair")
3238 (UNSPEC_PMULLT "pmullt")
3239 (UNSPEC_PMULLT_PAIR "pmullt_pair")
3240 (UNSPEC_SMATMUL "smatmul")
3241 (UNSPEC_SQCADD90 "sqcadd90")
3242 (UNSPEC_SQCADD270 "sqcadd270")
3243 (UNSPEC_SQRDCMLAH "sqrdcmlah")
3244 (UNSPEC_SQRDCMLAH90 "sqrdcmlah90")
3245 (UNSPEC_SQRDCMLAH180 "sqrdcmlah180")
3246 (UNSPEC_SQRDCMLAH270 "sqrdcmlah270")
3247 (UNSPEC_TRN1Q "trn1q")
3248 (UNSPEC_TRN2Q "trn2q")
3249 (UNSPEC_UMATMUL "umatmul")
3250 (UNSPEC_USMATMUL "usmatmul")
3251 (UNSPEC_UZP1Q "uzp1q")
3252 (UNSPEC_UZP2Q "uzp2q")
3253 (UNSPEC_WHILERW "vec_check_raw_alias")
3254 (UNSPEC_WHILEWR "vec_check_war_alias")
3255 (UNSPEC_ZIP1Q "zip1q")
3256 (UNSPEC_ZIP2Q "zip2q")
3257 (UNSPEC_COND_FABS "abs")
3258 (UNSPEC_COND_FADD "add")
3259 (UNSPEC_COND_FCADD90 "cadd90")
3260 (UNSPEC_COND_FCADD270 "cadd270")
3261 (UNSPEC_COND_FCMLA "fcmla")
3262 (UNSPEC_COND_FCMLA90 "fcmla90")
3263 (UNSPEC_COND_FCMLA180 "fcmla180")
3264 (UNSPEC_COND_FCMLA270 "fcmla270")
3265 (UNSPEC_COND_FCVT "fcvt")
3266 (UNSPEC_COND_FCVTZS "fix_trunc")
3267 (UNSPEC_COND_FCVTZU "fixuns_trunc")
3268 (UNSPEC_COND_FDIV "div")
3269 (UNSPEC_COND_FMAX "fmax_nan")
3270 (UNSPEC_COND_FMAXNM "smax")
3271 (UNSPEC_COND_FMIN "fmin_nan")
3272 (UNSPEC_COND_FMINNM "smin")
3273 (UNSPEC_COND_FMLA "fma")
3274 (UNSPEC_COND_FMLS "fnma")
3275 (UNSPEC_COND_FMUL "mul")
3276 (UNSPEC_COND_FMULX "mulx")
3277 (UNSPEC_COND_FNEG "neg")
3278 (UNSPEC_COND_FNMLA "fnms")
3279 (UNSPEC_COND_FNMLS "fms")
3280 (UNSPEC_COND_FRECPX "frecpx")
3281 (UNSPEC_COND_FRINTA "round")
3282 (UNSPEC_COND_FRINTI "nearbyint")
3283 (UNSPEC_COND_FRINTM "floor")
3284 (UNSPEC_COND_FRINTN "frintn")
3285 (UNSPEC_COND_FRINTP "ceil")
3286 (UNSPEC_COND_FRINTX "rint")
3287 (UNSPEC_COND_FRINTZ "btrunc")
3288 (UNSPEC_COND_FSCALE "fscale")
3289 (UNSPEC_COND_FSQRT "sqrt")
3290 (UNSPEC_COND_FSUB "sub")
3291 (UNSPEC_COND_SCVTF "float")
3292 (UNSPEC_COND_UCVTF "floatuns")])
3294 (define_int_attr fmaxmin [(UNSPEC_FMAX "fmax_nan")
3295 (UNSPEC_FMAXNM "fmax")
3296 (UNSPEC_FMAXNMV "fmax")
3297 (UNSPEC_FMIN "fmin_nan")
3298 (UNSPEC_FMINNM "fmin")
3299 (UNSPEC_FMINNMV "fmin")
3300 (UNSPEC_COND_FMAXNM "fmax")
3301 (UNSPEC_COND_FMINNM "fmin")])
3303 (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
3304 (UNSPEC_UMINV "umin")
3305 (UNSPEC_SMAXV "smax")
3306 (UNSPEC_SMINV "smin")
3307 (UNSPEC_FMAX "fmax")
3308 (UNSPEC_FMAXNMV "fmaxnm")
3309 (UNSPEC_FMAXV "fmax")
3310 (UNSPEC_FMIN "fmin")
3311 (UNSPEC_FMINNMV "fminnm")
3312 (UNSPEC_FMINV "fmin")
3313 (UNSPEC_FMAXNM "fmaxnm")
3314 (UNSPEC_FMINNM "fminnm")])
3316 (define_code_attr binqops_op [(ss_plus "sqadd")
3319 (us_minus "uqsub")])
3321 (define_code_attr binqops_op_rev [(ss_plus "sqsub")
3322 (ss_minus "sqadd")])
3324 ;; The SVE logical instruction that implements an unspec.
3325 (define_int_attr logicalf_op [(UNSPEC_ANDF "and")
3327 (UNSPEC_XORF "eor")])
3329 (define_int_attr last_op [(UNSPEC_CLASTA "after_last")
3330 (UNSPEC_CLASTB "last")
3331 (UNSPEC_LASTA "after_last")
3332 (UNSPEC_LASTB "last")])
3334 ;; "s" for signed operations and "u" for unsigned ones.
3335 (define_int_attr su [(UNSPEC_SADDV "s")
3341 (UNSPEC_UNPACKSHI "s")
3342 (UNSPEC_UNPACKUHI "u")
3343 (UNSPEC_UNPACKSLO "s")
3344 (UNSPEC_UNPACKULO "u")
3345 (UNSPEC_SMUL_HIGHPART "s")
3346 (UNSPEC_UMUL_HIGHPART "u")
3347 (UNSPEC_COND_FCVTZS "s")
3348 (UNSPEC_COND_FCVTZU "u")
3349 (UNSPEC_COND_SCVTF "s")
3350 (UNSPEC_COND_UCVTF "u")
3351 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u")
3352 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")])
3354 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
3355 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
3356 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
3357 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
3358 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
3359 (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
3360 (UNSPEC_SABDL "s") (UNSPEC_UABDL "u")
3361 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
3362 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
3363 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
3364 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
3365 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
3366 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
3367 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
3368 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
3369 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
3370 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
3372 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
3373 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
3374 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
3375 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
3376 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
3377 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
3378 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
3379 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
3380 (UNSPEC_USDOT "us") (UNSPEC_SUDOT "su")
3381 (UNSPEC_SMATMUL "s") (UNSPEC_UMATMUL "u")
3382 (UNSPEC_USMATMUL "us")
3385 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
3386 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
3387 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
3388 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
3389 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
3390 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
3391 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "")
3392 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r")
3395 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
3396 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")
3397 (UNSPEC_SQSHL "l") (UNSPEC_UQSHL "l")
3399 (UNSPEC_SRSHR "r") (UNSPEC_URSHR "r")
3401 (UNSPEC_SLI "l") (UNSPEC_SRI "r")])
3403 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
3404 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
3405 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
3406 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
3407 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
3408 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
3410 (define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")])
3412 (define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b")
3413 (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")])
3415 (define_int_attr bt [(UNSPEC_BFMLALB "b") (UNSPEC_BFMLALT "t")])
3417 (define_int_attr addsub [(UNSPEC_SHADD "add")
3418 (UNSPEC_UHADD "add")
3419 (UNSPEC_SRHADD "add")
3420 (UNSPEC_URHADD "add")
3421 (UNSPEC_SHSUB "sub")
3422 (UNSPEC_UHSUB "sub")
3423 (UNSPEC_ADDHN "add")
3424 (UNSPEC_SUBHN "sub")
3425 (UNSPEC_RADDHN "add")
3426 (UNSPEC_RSUBHN "sub")])
3428 ;; BSL variants: first commutative operand.
3429 (define_int_attr bsl_1st [(1 "w") (2 "0")])
3431 ;; BSL variants: second commutative operand.
3432 (define_int_attr bsl_2nd [(1 "0") (2 "w")])
3434 ;; BSL variants: duplicated input operand.
3435 (define_int_attr bsl_dup [(1 "1") (2 "2")])
3437 ;; BSL variants: operand which requires preserving via movprfx.
3438 (define_int_attr bsl_mov [(1 "2") (2 "1")])
3440 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
3441 (UNSPEC_SSRI "offset_")
3442 (UNSPEC_USRI "offset_")])
3444 ;; Standard pattern names for floating-point rounding instructions.
3445 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
3446 (UNSPEC_FRINTP "ceil")
3447 (UNSPEC_FRINTM "floor")
3448 (UNSPEC_FRINTI "nearbyint")
3449 (UNSPEC_FRINTX "rint")
3450 (UNSPEC_FRINTA "round")
3451 (UNSPEC_FRINTN "roundeven")])
3453 ;; frint suffix for floating-point rounding instructions.
3454 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
3455 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
3456 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
3457 (UNSPEC_FRINTN "n")])
3459 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
3460 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
3461 (UNSPEC_FRINTN "frintn")])
3463 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
3464 (UNSPEC_UCVTF "ucvtf")
3465 (UNSPEC_FCVTZS "fcvtzs")
3466 (UNSPEC_FCVTZU "fcvtzu")])
3468 ;; Pointer authentication mnemonic prefix.
3469 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
3470 (UNSPEC_PACIBSP "pacib")
3471 (UNSPEC_PACIA1716 "pacia")
3472 (UNSPEC_PACIB1716 "pacib")
3473 (UNSPEC_AUTIASP "autia")
3474 (UNSPEC_AUTIBSP "autib")
3475 (UNSPEC_AUTIA1716 "autia")
3476 (UNSPEC_AUTIB1716 "autib")])
3478 (define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
3479 (UNSPEC_PACIBSP "AARCH64_KEY_B")
3480 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
3481 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
3482 (UNSPEC_AUTIASP "AARCH64_KEY_A")
3483 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
3484 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
3485 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
3487 ;; Pointer authentication HINT number for NOP space instructions using A and
3489 (define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
3490 (UNSPEC_PACIBSP "27")
3491 (UNSPEC_AUTIASP "29")
3492 (UNSPEC_AUTIBSP "31")
3493 (UNSPEC_PACIA1716 "8")
3494 (UNSPEC_PACIB1716 "10")
3495 (UNSPEC_AUTIA1716 "12")
3496 (UNSPEC_AUTIB1716 "14")])
3498 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
3499 (UNSPEC_ZIP1Q "zip1") (UNSPEC_ZIP2Q "zip2")
3500 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
3501 (UNSPEC_TRN1Q "trn1") (UNSPEC_TRN2Q "trn2")
3502 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")
3503 (UNSPEC_UZP1Q "uzp1") (UNSPEC_UZP2Q "uzp2")])
3505 ; op code for REV instructions (size within which elements are reversed).
3506 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
3507 (UNSPEC_REV16 "16")])
3509 (define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
3510 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
3512 ;; Return true if the associated optab refers to the high-numbered lanes,
3513 ;; false if it refers to the low-numbered lanes. The convention is for
3514 ;; "hi" to refer to the low-numbered lanes (the first ones in memory)
3516 (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
3517 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
3518 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
3519 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
3521 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
3522 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
3523 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
3524 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
3526 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
3527 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
3528 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
3529 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
3531 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
3532 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
3534 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
3535 (UNSPEC_SHA1M "m")])
3537 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
3539 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
3541 (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
3543 (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
3544 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
3546 (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
3548 (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
3549 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
3551 (define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x")
3552 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")])
3554 ;; The condition associated with an UNSPEC_COND_<xx>.
3555 (define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq")
3556 (UNSPEC_COND_CMPGE_WIDE "ge")
3557 (UNSPEC_COND_CMPGT_WIDE "gt")
3558 (UNSPEC_COND_CMPHI_WIDE "hi")
3559 (UNSPEC_COND_CMPHS_WIDE "hs")
3560 (UNSPEC_COND_CMPLE_WIDE "le")
3561 (UNSPEC_COND_CMPLO_WIDE "lo")
3562 (UNSPEC_COND_CMPLS_WIDE "ls")
3563 (UNSPEC_COND_CMPLT_WIDE "lt")
3564 (UNSPEC_COND_CMPNE_WIDE "ne")
3565 (UNSPEC_COND_FCMEQ "eq")
3566 (UNSPEC_COND_FCMGE "ge")
3567 (UNSPEC_COND_FCMGT "gt")
3568 (UNSPEC_COND_FCMLE "le")
3569 (UNSPEC_COND_FCMLT "lt")
3570 (UNSPEC_COND_FCMNE "ne")
3571 (UNSPEC_WHILEGE "ge")
3572 (UNSPEC_WHILEGT "gt")
3573 (UNSPEC_WHILEHI "hi")
3574 (UNSPEC_WHILEHS "hs")
3575 (UNSPEC_WHILELE "le")
3576 (UNSPEC_WHILELO "lo")
3577 (UNSPEC_WHILELS "ls")
3578 (UNSPEC_WHILELT "lt")
3579 (UNSPEC_WHILERW "rw")
3580 (UNSPEC_WHILEWR "wr")])
3582 (define_int_attr while_optab_cmp [(UNSPEC_WHILEGE "ge")
3583 (UNSPEC_WHILEGT "gt")
3584 (UNSPEC_WHILEHI "ugt")
3585 (UNSPEC_WHILEHS "uge")
3586 (UNSPEC_WHILELE "le")
3587 (UNSPEC_WHILELO "ult")
3588 (UNSPEC_WHILELS "ule")
3589 (UNSPEC_WHILELT "lt")
3590 (UNSPEC_WHILERW "rw")
3591 (UNSPEC_WHILEWR "wr")])
3593 (define_int_attr raw_war [(UNSPEC_WHILERW "raw")
3594 (UNSPEC_WHILEWR "war")])
3596 (define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b")
3598 (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")])
3600 (define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")])
3602 (define_int_attr sve_int_op [(UNSPEC_ADCLB "adclb")
3603 (UNSPEC_ADCLT "adclt")
3604 (UNSPEC_ADDHNB "addhnb")
3605 (UNSPEC_ADDHNT "addhnt")
3606 (UNSPEC_ADDP "addp")
3607 (UNSPEC_ANDV "andv")
3608 (UNSPEC_ASHIFTRT_WIDE "asr")
3609 (UNSPEC_ASHIFT_WIDE "lsl")
3610 (UNSPEC_ASRD "asrd")
3611 (UNSPEC_BDEP "bdep")
3612 (UNSPEC_BEXT "bext")
3613 (UNSPEC_BGRP "bgrp")
3614 (UNSPEC_CADD90 "cadd")
3615 (UNSPEC_CADD270 "cadd")
3616 (UNSPEC_CDOT "cdot")
3617 (UNSPEC_CDOT90 "cdot")
3618 (UNSPEC_CDOT180 "cdot")
3619 (UNSPEC_CDOT270 "cdot")
3620 (UNSPEC_CMLA "cmla")
3621 (UNSPEC_CMLA90 "cmla")
3622 (UNSPEC_CMLA180 "cmla")
3623 (UNSPEC_CMLA270 "cmla")
3624 (UNSPEC_EORBT "eorbt")
3625 (UNSPEC_EORTB "eortb")
3627 (UNSPEC_LSHIFTRT_WIDE "lsr")
3628 (UNSPEC_MATCH "match")
3629 (UNSPEC_NMATCH "nmatch")
3630 (UNSPEC_PMULLB "pmullb")
3631 (UNSPEC_PMULLB_PAIR "pmullb")
3632 (UNSPEC_PMULLT "pmullt")
3633 (UNSPEC_PMULLT_PAIR "pmullt")
3634 (UNSPEC_RADDHNB "raddhnb")
3635 (UNSPEC_RADDHNT "raddhnt")
3636 (UNSPEC_RBIT "rbit")
3637 (UNSPEC_REVB "revb")
3638 (UNSPEC_REVH "revh")
3639 (UNSPEC_REVW "revw")
3640 (UNSPEC_RSHRNB "rshrnb")
3641 (UNSPEC_RSHRNT "rshrnt")
3642 (UNSPEC_RSQRTE "ursqrte")
3643 (UNSPEC_RSUBHNB "rsubhnb")
3644 (UNSPEC_RSUBHNT "rsubhnt")
3645 (UNSPEC_SABDLB "sabdlb")
3646 (UNSPEC_SABDLT "sabdlt")
3647 (UNSPEC_SADALP "sadalp")
3648 (UNSPEC_SADDLB "saddlb")
3649 (UNSPEC_SADDLBT "saddlbt")
3650 (UNSPEC_SADDLT "saddlt")
3651 (UNSPEC_SADDWB "saddwb")
3652 (UNSPEC_SADDWT "saddwt")
3653 (UNSPEC_SBCLB "sbclb")
3654 (UNSPEC_SBCLT "sbclt")
3655 (UNSPEC_SHADD "shadd")
3656 (UNSPEC_SHRNB "shrnb")
3657 (UNSPEC_SHRNT "shrnt")
3658 (UNSPEC_SHSUB "shsub")
3660 (UNSPEC_SMAXP "smaxp")
3661 (UNSPEC_SMAXV "smaxv")
3662 (UNSPEC_SMINP "sminp")
3663 (UNSPEC_SMINV "sminv")
3664 (UNSPEC_SMUL_HIGHPART "smulh")
3665 (UNSPEC_SMULLB "smullb")
3666 (UNSPEC_SMULLT "smullt")
3667 (UNSPEC_SQCADD90 "sqcadd")
3668 (UNSPEC_SQCADD270 "sqcadd")
3669 (UNSPEC_SQDMULH "sqdmulh")
3670 (UNSPEC_SQDMULLB "sqdmullb")
3671 (UNSPEC_SQDMULLBT "sqdmullbt")
3672 (UNSPEC_SQDMULLT "sqdmullt")
3673 (UNSPEC_SQRDCMLAH "sqrdcmlah")
3674 (UNSPEC_SQRDCMLAH90 "sqrdcmlah")
3675 (UNSPEC_SQRDCMLAH180 "sqrdcmlah")
3676 (UNSPEC_SQRDCMLAH270 "sqrdcmlah")
3677 (UNSPEC_SQRDMLAH "sqrdmlah")
3678 (UNSPEC_SQRDMLSH "sqrdmlsh")
3679 (UNSPEC_SQRDMULH "sqrdmulh")
3680 (UNSPEC_SQRSHL "sqrshl")
3681 (UNSPEC_SQRSHRNB "sqrshrnb")
3682 (UNSPEC_SQRSHRNT "sqrshrnt")
3683 (UNSPEC_SQRSHRUNB "sqrshrunb")
3684 (UNSPEC_SQRSHRUNT "sqrshrunt")
3685 (UNSPEC_SQSHL "sqshl")
3686 (UNSPEC_SQSHLU "sqshlu")
3687 (UNSPEC_SQSHRNB "sqshrnb")
3688 (UNSPEC_SQSHRNT "sqshrnt")
3689 (UNSPEC_SQSHRUNB "sqshrunb")
3690 (UNSPEC_SQSHRUNT "sqshrunt")
3691 (UNSPEC_SQXTNB "sqxtnb")
3692 (UNSPEC_SQXTNT "sqxtnt")
3693 (UNSPEC_SQXTUNB "sqxtunb")
3694 (UNSPEC_SQXTUNT "sqxtunt")
3695 (UNSPEC_SRHADD "srhadd")
3697 (UNSPEC_SRSHL "srshl")
3698 (UNSPEC_SRSHR "srshr")
3699 (UNSPEC_SSHLLB "sshllb")
3700 (UNSPEC_SSHLLT "sshllt")
3701 (UNSPEC_SSUBLB "ssublb")
3702 (UNSPEC_SSUBLBT "ssublbt")
3703 (UNSPEC_SSUBLT "ssublt")
3704 (UNSPEC_SSUBLTB "ssubltb")
3705 (UNSPEC_SSUBWB "ssubwb")
3706 (UNSPEC_SSUBWT "ssubwt")
3707 (UNSPEC_SUBHNB "subhnb")
3708 (UNSPEC_SUBHNT "subhnt")
3709 (UNSPEC_SUQADD "suqadd")
3710 (UNSPEC_UABDLB "uabdlb")
3711 (UNSPEC_UABDLT "uabdlt")
3712 (UNSPEC_UADALP "uadalp")
3713 (UNSPEC_UADDLB "uaddlb")
3714 (UNSPEC_UADDLT "uaddlt")
3715 (UNSPEC_UADDWB "uaddwb")
3716 (UNSPEC_UADDWT "uaddwt")
3717 (UNSPEC_UHADD "uhadd")
3718 (UNSPEC_UHSUB "uhsub")
3719 (UNSPEC_UMAXP "umaxp")
3720 (UNSPEC_UMAXV "umaxv")
3721 (UNSPEC_UMINP "uminp")
3722 (UNSPEC_UMINV "uminv")
3723 (UNSPEC_UMUL_HIGHPART "umulh")
3724 (UNSPEC_UMULLB "umullb")
3725 (UNSPEC_UMULLT "umullt")
3726 (UNSPEC_UQRSHL "uqrshl")
3727 (UNSPEC_UQRSHRNB "uqrshrnb")
3728 (UNSPEC_UQRSHRNT "uqrshrnt")
3729 (UNSPEC_UQSHL "uqshl")
3730 (UNSPEC_UQSHRNB "uqshrnb")
3731 (UNSPEC_UQSHRNT "uqshrnt")
3732 (UNSPEC_UQXTNB "uqxtnb")
3733 (UNSPEC_UQXTNT "uqxtnt")
3734 (UNSPEC_URECPE "urecpe")
3735 (UNSPEC_URHADD "urhadd")
3736 (UNSPEC_URSHL "urshl")
3737 (UNSPEC_URSHR "urshr")
3738 (UNSPEC_USHLLB "ushllb")
3739 (UNSPEC_USHLLT "ushllt")
3740 (UNSPEC_USQADD "usqadd")
3741 (UNSPEC_USUBLB "usublb")
3742 (UNSPEC_USUBLT "usublt")
3743 (UNSPEC_USUBWB "usubwb")
3744 (UNSPEC_USUBWT "usubwt")
3745 (UNSPEC_XORV "eorv")])
3747 (define_int_attr sve_int_op_rev [(UNSPEC_SHADD "shadd")
3748 (UNSPEC_SHSUB "shsubr")
3749 (UNSPEC_SQRSHL "sqrshlr")
3750 (UNSPEC_SRHADD "srhadd")
3751 (UNSPEC_SRSHL "srshlr")
3752 (UNSPEC_UHADD "uhadd")
3753 (UNSPEC_UHSUB "uhsubr")
3754 (UNSPEC_UQRSHL "uqrshlr")
3755 (UNSPEC_URHADD "urhadd")
3756 (UNSPEC_URSHL "urshlr")])
3758 (define_int_attr sve_int_add_op [(UNSPEC_SABDLB "sabalb")
3759 (UNSPEC_SABDLT "sabalt")
3760 (UNSPEC_SMULLB "smlalb")
3761 (UNSPEC_SMULLT "smlalt")
3762 (UNSPEC_UABDLB "uabalb")
3763 (UNSPEC_UABDLT "uabalt")
3764 (UNSPEC_UMULLB "umlalb")
3765 (UNSPEC_UMULLT "umlalt")])
3767 (define_int_attr sve_int_qadd_op [(UNSPEC_SQDMULLB "sqdmlalb")
3768 (UNSPEC_SQDMULLBT "sqdmlalbt")
3769 (UNSPEC_SQDMULLT "sqdmlalt")])
3771 (define_int_attr sve_int_sub_op [(UNSPEC_SMULLB "smlslb")
3772 (UNSPEC_SMULLT "smlslt")
3773 (UNSPEC_UMULLB "umlslb")
3774 (UNSPEC_UMULLT "umlslt")])
3776 (define_int_attr sve_int_qsub_op [(UNSPEC_SQDMULLB "sqdmlslb")
3777 (UNSPEC_SQDMULLBT "sqdmlslbt")
3778 (UNSPEC_SQDMULLT "sqdmlslt")])
3780 (define_int_attr sve_fp_op [(UNSPEC_BFDOT "bfdot")
3781 (UNSPEC_BFMLALB "bfmlalb")
3782 (UNSPEC_BFMLALT "bfmlalt")
3783 (UNSPEC_BFMMLA "bfmmla")
3784 (UNSPEC_FRECPE "frecpe")
3785 (UNSPEC_FRECPS "frecps")
3786 (UNSPEC_RSQRTE "frsqrte")
3787 (UNSPEC_RSQRTS "frsqrts")
3788 (UNSPEC_FADDP "faddp")
3789 (UNSPEC_FADDV "faddv")
3790 (UNSPEC_FEXPA "fexpa")
3791 (UNSPEC_FMAXNMP "fmaxnmp")
3792 (UNSPEC_FMAXNMV "fmaxnmv")
3793 (UNSPEC_FMAXP "fmaxp")
3794 (UNSPEC_FMAXV "fmaxv")
3795 (UNSPEC_FMINNMP "fminnmp")
3796 (UNSPEC_FMINNMV "fminnmv")
3797 (UNSPEC_FMINP "fminp")
3798 (UNSPEC_FMINV "fminv")
3799 (UNSPEC_FMLA "fmla")
3800 (UNSPEC_FMLALB "fmlalb")
3801 (UNSPEC_FMLALT "fmlalt")
3802 (UNSPEC_FMLS "fmls")
3803 (UNSPEC_FMLSLB "fmlslb")
3804 (UNSPEC_FMLSLT "fmlslt")
3805 (UNSPEC_FMMLA "fmmla")
3806 (UNSPEC_FTSMUL "ftsmul")
3807 (UNSPEC_FTSSEL "ftssel")
3808 (UNSPEC_COND_FABS "fabs")
3809 (UNSPEC_COND_FADD "fadd")
3810 (UNSPEC_COND_FCVTLT "fcvtlt")
3811 (UNSPEC_COND_FCVTX "fcvtx")
3812 (UNSPEC_COND_FDIV "fdiv")
3813 (UNSPEC_COND_FLOGB "flogb")
3814 (UNSPEC_COND_FMAX "fmax")
3815 (UNSPEC_COND_FMAXNM "fmaxnm")
3816 (UNSPEC_COND_FMIN "fmin")
3817 (UNSPEC_COND_FMINNM "fminnm")
3818 (UNSPEC_COND_FMUL "fmul")
3819 (UNSPEC_COND_FMULX "fmulx")
3820 (UNSPEC_COND_FNEG "fneg")
3821 (UNSPEC_COND_FRECPX "frecpx")
3822 (UNSPEC_COND_FRINTA "frinta")
3823 (UNSPEC_COND_FRINTI "frinti")
3824 (UNSPEC_COND_FRINTM "frintm")
3825 (UNSPEC_COND_FRINTN "frintn")
3826 (UNSPEC_COND_FRINTP "frintp")
3827 (UNSPEC_COND_FRINTX "frintx")
3828 (UNSPEC_COND_FRINTZ "frintz")
3829 (UNSPEC_COND_FSCALE "fscale")
3830 (UNSPEC_COND_FSQRT "fsqrt")
3831 (UNSPEC_COND_FSUB "fsub")])
3833 (define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
3834 (UNSPEC_COND_FDIV "fdivr")
3835 (UNSPEC_COND_FMAX "fmax")
3836 (UNSPEC_COND_FMAXNM "fmaxnm")
3837 (UNSPEC_COND_FMIN "fmin")
3838 (UNSPEC_COND_FMINNM "fminnm")
3839 (UNSPEC_COND_FMUL "fmul")
3840 (UNSPEC_COND_FMULX "fmulx")
3841 (UNSPEC_COND_FSUB "fsubr")])
3843 (define_int_attr rot [(UNSPEC_CADD90 "90")
3844 (UNSPEC_CADD270 "270")
3846 (UNSPEC_CDOT90 "90")
3847 (UNSPEC_CDOT180 "180")
3848 (UNSPEC_CDOT270 "270")
3850 (UNSPEC_CMLA90 "90")
3851 (UNSPEC_CMLA180 "180")
3852 (UNSPEC_CMLA270 "270")
3853 (UNSPEC_FCADD90 "90")
3854 (UNSPEC_FCADD270 "270")
3856 (UNSPEC_FCMLA90 "90")
3857 (UNSPEC_FCMLA180 "180")
3858 (UNSPEC_FCMLA270 "270")
3859 (UNSPEC_SQCADD90 "90")
3860 (UNSPEC_SQCADD270 "270")
3861 (UNSPEC_SQRDCMLAH "0")
3862 (UNSPEC_SQRDCMLAH90 "90")
3863 (UNSPEC_SQRDCMLAH180 "180")
3864 (UNSPEC_SQRDCMLAH270 "270")
3865 (UNSPEC_COND_FCADD90 "90")
3866 (UNSPEC_COND_FCADD270 "270")
3867 (UNSPEC_COND_FCMLA "0")
3868 (UNSPEC_COND_FCMLA90 "90")
3869 (UNSPEC_COND_FCMLA180 "180")
3870 (UNSPEC_COND_FCMLA270 "270")
3872 (UNSPEC_FCMUL_CONJ "180")])
3874 ;; A conjucate is a negation of the imaginary component
3875 ;; The number in the unspecs are the rotation component of the instruction, e.g
3876 ;; FCMLA180 means use the instruction with #180.
3877 ;; The iterator is used to produce the right name mangling for the function.
3878 (define_int_attr conj_op [(UNSPEC_FCMLA180 "")
3879 (UNSPEC_FCMLA180_CONJ "_conj")
3881 (UNSPEC_FCMLA_CONJ "_conj")
3883 (UNSPEC_FCMUL_CONJ "_conj")
3886 (UNSPEC_CMLA180_CONJ "_conj")
3887 (UNSPEC_CMLA_CONJ "_conj")
3889 (UNSPEC_CMUL_CONJ "_conj")])
3891 ;; The complex operations when performed on a real complex number require two
3892 ;; instructions to perform the operation. e.g. complex multiplication requires
3893 ;; two FCMUL with a particular rotation value.
3895 ;; These values can be looked up in rotsplit1 and rotsplit2. as an example
3896 ;; FCMUL needs the first instruction to use #0 and the second #90.
3897 (define_int_attr rotsplit1 [(UNSPEC_FCMLA "0")
3898 (UNSPEC_FCMLA_CONJ "0")
3900 (UNSPEC_FCMUL_CONJ "0")
3901 (UNSPEC_FCMLA180 "180")
3902 (UNSPEC_FCMLA180_CONJ "180")])
3904 (define_int_attr rotsplit2 [(UNSPEC_FCMLA "90")
3905 (UNSPEC_FCMLA_CONJ "270")
3907 (UNSPEC_FCMUL_CONJ "270")
3908 (UNSPEC_FCMLA180 "270")
3909 (UNSPEC_FCMLA180_CONJ "90")])
3911 ;; SVE has slightly different namings from NEON so we have to split these
3913 (define_int_attr sve_rot1 [(UNSPEC_FCMLA "")
3914 (UNSPEC_FCMLA_CONJ "")
3916 (UNSPEC_FCMUL_CONJ "")
3917 (UNSPEC_FCMLA180 "180")
3918 (UNSPEC_FCMLA180_CONJ "180")
3920 (UNSPEC_CMLA_CONJ "")
3922 (UNSPEC_CMUL_CONJ "")
3923 (UNSPEC_CMLA180 "180")
3924 (UNSPEC_CMLA180_CONJ "180")])
3926 (define_int_attr sve_rot2 [(UNSPEC_FCMLA "90")
3927 (UNSPEC_FCMLA_CONJ "270")
3929 (UNSPEC_FCMUL_CONJ "270")
3930 (UNSPEC_FCMLA180 "270")
3931 (UNSPEC_FCMLA180_CONJ "90")
3933 (UNSPEC_CMLA_CONJ "270")
3935 (UNSPEC_CMUL_CONJ "270")
3936 (UNSPEC_CMLA180 "270")
3937 (UNSPEC_CMLA180_CONJ "90")])
3940 (define_int_attr fcmac1 [(UNSPEC_FCMLA "a") (UNSPEC_FCMLA_CONJ "a")
3941 (UNSPEC_FCMLA180 "s") (UNSPEC_FCMLA180_CONJ "s")
3942 (UNSPEC_CMLA "a") (UNSPEC_CMLA_CONJ "a")
3943 (UNSPEC_CMLA180 "s") (UNSPEC_CMLA180_CONJ "s")])
3945 (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
3946 (UNSPEC_COND_FMLS "fmls")
3947 (UNSPEC_COND_FNMLA "fnmla")
3948 (UNSPEC_COND_FNMLS "fnmls")])
3950 (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
3951 (UNSPEC_COND_FMLS "fmsb")
3952 (UNSPEC_COND_FNMLA "fnmad")
3953 (UNSPEC_COND_FNMLS "fnmsb")])
3955 ;; The register constraint to use for the final operand in a binary BRK.
3956 (define_int_attr brk_reg_con [(UNSPEC_BRKN "0")
3957 (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")])
3959 ;; The register number to print for the above.
3960 (define_int_attr brk_reg_opno [(UNSPEC_BRKN "0")
3961 (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")])
3963 ;; The predicate to use for the first input operand in a floating-point
3964 ;; <optab><mode>3 pattern.
3965 (define_int_attr sve_pred_fp_rhs1_operand
3966 [(UNSPEC_COND_FADD "register_operand")
3967 (UNSPEC_COND_FDIV "register_operand")
3968 (UNSPEC_COND_FMAX "register_operand")
3969 (UNSPEC_COND_FMAXNM "register_operand")
3970 (UNSPEC_COND_FMIN "register_operand")
3971 (UNSPEC_COND_FMINNM "register_operand")
3972 (UNSPEC_COND_FMUL "register_operand")
3973 (UNSPEC_COND_FMULX "register_operand")
3974 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
3976 ;; The predicate to use for the second input operand in a floating-point
3977 ;; <optab><mode>3 pattern.
3978 (define_int_attr sve_pred_fp_rhs2_operand
3979 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
3980 (UNSPEC_COND_FDIV "register_operand")
3981 (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand")
3982 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
3983 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand")
3984 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
3985 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
3986 (UNSPEC_COND_FMULX "register_operand")
3987 (UNSPEC_COND_FSUB "register_operand")])
3989 ;; Likewise for immediates only.
3990 (define_int_attr sve_pred_fp_rhs2_immediate
3991 [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate")
3992 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate")
3993 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate")
3994 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate")
3995 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")])
3997 ;; The maximum number of element bits that an instruction can handle.
3998 (define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32")
3999 (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")])
4001 ;; The minimum number of element bits that an instruction can handle.
4002 (define_int_attr min_elem_bits [(UNSPEC_RBIT "8")
4005 (UNSPEC_REVW "64")])
4007 (define_int_attr unspec [(UNSPEC_WHILERW "UNSPEC_WHILERW")
4008 (UNSPEC_WHILEWR "UNSPEC_WHILEWR")])
4010 ;; Iterators and attributes for fpcr fpsr getter setters
4012 (define_int_iterator GET_FPSCR
4013 [UNSPECV_GET_FPSR UNSPECV_GET_FPCR])
4015 (define_int_iterator SET_FPSCR
4016 [UNSPECV_SET_FPSR UNSPECV_SET_FPCR])
4018 (define_int_attr fpscr_name
4019 [(UNSPECV_GET_FPSR "fpsr")
4020 (UNSPECV_SET_FPSR "fpsr")
4021 (UNSPECV_GET_FPCR "fpcr")
4022 (UNSPECV_SET_FPCR "fpcr")])