1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode
;
57 typedef struct minipool_fixup Mfix
;
59 const struct attribute_spec arm_attribute_table
[];
61 /* Forward function declarations. */
62 static arm_stack_offsets
*arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
65 HOST_WIDE_INT
, rtx
, rtx
, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx
, int);
68 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
69 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
70 inline static int thumb_index_register_rtx_p (rtx
, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
73 static rtx
emit_multi_reg_push (int);
74 static rtx
emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx
, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
79 static arm_cc
get_arm_condition_code (rtx
);
80 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
81 static rtx
is_jump_table (rtx
);
82 static const char *output_multi_immediate (rtx
*, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
86 static struct machine_function
*arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree
, rtx
, rtx
);
89 static void thumb_exit (FILE *, int, rtx
);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx
is_jump_table (rtx
);
92 static HOST_WIDE_INT
get_jump_table_size (rtx
);
93 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_forward_ref (Mfix
*);
95 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
96 static Mnode
*add_minipool_backward_ref (Mfix
*);
97 static void assign_minipool_offsets (Mfix
*);
98 static void arm_print_value (FILE *, rtx
);
99 static void dump_minipool (rtx
);
100 static int arm_barrier_cost (rtx
);
101 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
102 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
103 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
107 static int current_file_function_operand (rtx
);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree
);
111 static unsigned long arm_compute_func_type (void);
112 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
113 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static int arm_comp_type_attributes (tree
, tree
);
118 static void arm_set_default_type_attributes (tree
);
119 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
132 static int arm_address_cost (rtx
);
133 static bool arm_memory_load_p (rtx
);
134 static bool arm_cirrus_insn_p (rtx
);
135 static void cirrus_reorg (rtx
);
136 static void arm_init_builtins (void);
137 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
140 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
141 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
142 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
143 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree
, rtx
, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx
arm_struct_value_rtx (tree
, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
161 static bool arm_promote_prototypes (tree
);
164 /* Initialize the GCC target structure. */
165 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
166 #undef TARGET_MERGE_DECL_ATTRIBUTES
167 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
170 #undef TARGET_ATTRIBUTE_TABLE
171 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
174 #undef TARGET_ASM_BYTE_OP
175 #define TARGET_ASM_BYTE_OP "\tDCB\t"
176 #undef TARGET_ASM_ALIGNED_HI_OP
177 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
180 #undef TARGET_ASM_GLOBALIZE_LABEL
181 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
182 #undef TARGET_ASM_FILE_START
183 #define TARGET_ASM_FILE_START aof_file_start
184 #undef TARGET_ASM_FILE_END
185 #define TARGET_ASM_FILE_END aof_file_end
187 #undef TARGET_ASM_ALIGNED_SI_OP
188 #define TARGET_ASM_ALIGNED_SI_OP NULL
189 #undef TARGET_ASM_INTEGER
190 #define TARGET_ASM_INTEGER arm_assemble_integer
193 #undef TARGET_ASM_FUNCTION_PROLOGUE
194 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
196 #undef TARGET_ASM_FUNCTION_EPILOGUE
197 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
199 #undef TARGET_COMP_TYPE_ATTRIBUTES
200 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
202 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
203 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
205 #undef TARGET_SCHED_ADJUST_COST
206 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
208 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
209 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
211 #undef TARGET_ENCODE_SECTION_INFO
213 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
215 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
218 #undef TARGET_STRIP_NAME_ENCODING
219 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
221 #undef TARGET_ASM_INTERNAL_LABEL
222 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
224 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
225 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
227 #undef TARGET_ASM_OUTPUT_MI_THUNK
228 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
229 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
230 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
232 /* This will be overridden in arm_override_options. */
233 #undef TARGET_RTX_COSTS
234 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
235 #undef TARGET_ADDRESS_COST
236 #define TARGET_ADDRESS_COST arm_address_cost
238 #undef TARGET_MACHINE_DEPENDENT_REORG
239 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
241 #undef TARGET_INIT_BUILTINS
242 #define TARGET_INIT_BUILTINS arm_init_builtins
243 #undef TARGET_EXPAND_BUILTIN
244 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
246 #undef TARGET_PROMOTE_FUNCTION_ARGS
247 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
248 #undef TARGET_PROMOTE_FUNCTION_RETURN
249 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
250 #undef TARGET_PROMOTE_PROTOTYPES
251 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
253 #undef TARGET_STRUCT_VALUE_RTX
254 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
256 #undef TARGET_SETUP_INCOMING_VARARGS
257 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
259 struct gcc_target targetm
= TARGET_INITIALIZER
;
261 /* Obstack for minipool constant handling. */
262 static struct obstack minipool_obstack
;
263 static char * minipool_startobj
;
265 /* The maximum number of insns skipped which
266 will be conditionalised if possible. */
267 static int max_insns_skipped
= 5;
269 extern FILE * asm_out_file
;
271 /* True if we are currently building a constant table. */
272 int making_const_table
;
274 /* Define the information needed to generate branch insns. This is
275 stored from the compare operation. */
276 rtx arm_compare_op0
, arm_compare_op1
;
278 /* The processor for which instructions should be scheduled. */
279 enum processor_type arm_tune
= arm_none
;
281 /* Which floating point model to use. */
282 enum arm_fp_model arm_fp_model
;
284 /* Which floating point hardware is available. */
285 enum fputype arm_fpu_arch
;
287 /* Which floating point hardware to schedule for. */
288 enum fputype arm_fpu_tune
;
290 /* Whether to use floating point hardware. */
291 enum float_abi_type arm_float_abi
;
293 /* Which ABI to use. */
294 enum arm_abi_type arm_abi
;
296 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
297 enum prog_mode_type arm_prgmode
;
299 /* Set by the -mfpu=... option. */
300 const char * target_fpu_name
= NULL
;
302 /* Set by the -mfpe=... option. */
303 const char * target_fpe_name
= NULL
;
305 /* Set by the -mfloat-abi=... option. */
306 const char * target_float_abi_name
= NULL
;
308 /* Set by the -mabi=... option. */
309 const char * target_abi_name
= NULL
;
311 /* Used to parse -mstructure_size_boundary command line option. */
312 const char * structure_size_string
= NULL
;
313 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
315 /* Bit values used to identify processor capabilities. */
316 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
317 #define FL_ARCH3M (1 << 1) /* Extended multiply */
318 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
319 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
320 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
321 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
322 #define FL_THUMB (1 << 6) /* Thumb aware */
323 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
324 #define FL_STRONG (1 << 8) /* StrongARM */
325 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
326 #define FL_XSCALE (1 << 10) /* XScale */
327 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
328 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
329 media instructions. */
330 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
332 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
334 #define FL_FOR_ARCH2 0
335 #define FL_FOR_ARCH3 FL_MODE32
336 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
337 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
338 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
339 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
340 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
341 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
342 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
343 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
344 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
345 #define FL_FOR_ARCH6J FL_FOR_ARCH6
347 /* The bits in this mask specify which
348 instructions we are allowed to generate. */
349 static unsigned long insn_flags
= 0;
351 /* The bits in this mask specify which instruction scheduling options should
353 static unsigned long tune_flags
= 0;
355 /* The following are used in the arm.md file as equivalents to bits
356 in the above two flag variables. */
358 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
361 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
364 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
367 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
370 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
373 /* Nonzero if this chip can benefit from load scheduling. */
374 int arm_ld_sched
= 0;
376 /* Nonzero if this chip is a StrongARM. */
377 int arm_is_strong
= 0;
379 /* Nonzero if this chip is a Cirrus variant. */
380 int arm_arch_cirrus
= 0;
382 /* Nonzero if this chip supports Intel Wireless MMX technology. */
383 int arm_arch_iwmmxt
= 0;
385 /* Nonzero if this chip is an XScale. */
386 int arm_arch_xscale
= 0;
388 /* Nonzero if tuning for XScale */
389 int arm_tune_xscale
= 0;
391 /* Nonzero if this chip is an ARM6 or an ARM7. */
392 int arm_is_6_or_7
= 0;
394 /* Nonzero if generating Thumb instructions. */
397 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
398 must report the mode of the memory reference from PRINT_OPERAND to
399 PRINT_OPERAND_ADDRESS. */
400 enum machine_mode output_memory_reference_mode
;
402 /* The register number to be used for the PIC offset register. */
403 const char * arm_pic_register_string
= NULL
;
404 int arm_pic_register
= INVALID_REGNUM
;
406 /* Set to 1 when a return insn is output, this means that the epilogue
408 int return_used_this_function
;
410 /* Set to 1 after arm_reorg has started. Reset to start at the start of
411 the next function. */
412 static int after_arm_reorg
= 0;
414 /* The maximum number of insns to be used when loading a constant. */
415 static int arm_constant_limit
= 3;
417 /* For an explanation of these variables, see final_prescan_insn below. */
419 enum arm_cond_code arm_current_cc
;
421 int arm_target_label
;
423 /* The condition codes of the ARM, and the inverse function. */
424 static const char * const arm_condition_codes
[] =
426 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
427 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
430 #define streq(string1, string2) (strcmp (string1, string2) == 0)
432 /* Initialization code. */
436 const char *const name
;
437 enum processor_type core
;
439 const unsigned long flags
;
440 bool (* rtx_costs
) (rtx
, int, int, int *);
443 /* Not all of these give usefully different compilation alternatives,
444 but there is no simple way of generalizing them. */
445 static const struct processors all_cores
[] =
448 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
449 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
450 #include "arm-cores.def"
452 {NULL
, arm_none
, NULL
, 0, NULL
}
455 static const struct processors all_architectures
[] =
457 /* ARM Architectures */
458 /* We don't specify rtx_costs here as it will be figured out
461 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
462 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
463 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
464 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
465 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
466 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
467 implementations that support it, so we will leave it out for now. */
468 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
469 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
470 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
471 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
472 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
473 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
474 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
475 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
476 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
477 {NULL
, arm_none
, NULL
, 0 , NULL
}
480 /* This is a magic structure. The 'string' field is magically filled in
481 with a pointer to the value specified by the user on the command line
482 assuming that the user has specified such a value. */
484 struct arm_cpu_select arm_select
[] =
486 /* string name processors */
487 { NULL
, "-mcpu=", all_cores
},
488 { NULL
, "-march=", all_architectures
},
489 { NULL
, "-mtune=", all_cores
}
493 /* The name of the proprocessor macro to define for this architecture. */
495 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
504 /* Available values for for -mfpu=. */
506 static const struct fpu_desc all_fpus
[] =
508 {"fpa", FPUTYPE_FPA
},
509 {"fpe2", FPUTYPE_FPA_EMU2
},
510 {"fpe3", FPUTYPE_FPA_EMU2
},
511 {"maverick", FPUTYPE_MAVERICK
},
516 /* Floating point models used by the different hardware.
517 See fputype in arm.h. */
519 static const enum fputype fp_model_for_fpu
[] =
521 /* No FP hardware. */
522 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
523 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
524 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
525 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
526 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
527 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
534 enum float_abi_type abi_type
;
538 /* Available values for -mfloat-abi=. */
540 static const struct float_abi all_float_abis
[] =
542 {"soft", ARM_FLOAT_ABI_SOFT
},
543 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
544 {"hard", ARM_FLOAT_ABI_HARD
}
551 enum arm_abi_type abi_type
;
555 /* Available values for -mabi=. */
557 static const struct abi_name arm_all_abis
[] =
559 {"apcs-gnu", ARM_ABI_APCS
},
560 {"atpcs", ARM_ABI_ATPCS
},
561 {"aapcs", ARM_ABI_AAPCS
},
562 {"iwmmxt", ARM_ABI_IWMMXT
}
565 /* Return the number of bits set in VALUE. */
567 bit_count (unsigned long value
)
569 unsigned long count
= 0;
574 value
&= value
- 1; /* Clear the least-significant set bit. */
580 /* Fix up any incompatible options that the user has specified.
581 This has now turned into a maze. */
583 arm_override_options (void)
587 /* Set up the flags based on the cpu/architecture selected by the user. */
588 for (i
= ARRAY_SIZE (arm_select
); i
--;)
590 struct arm_cpu_select
* ptr
= arm_select
+ i
;
592 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
594 const struct processors
* sel
;
596 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
597 if (streq (ptr
->string
, sel
->name
))
599 /* Set the architecture define. */
601 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
603 /* Determine the processor core for which we should
604 tune code-generation. */
605 if (/* -mcpu= is a sensible default. */
607 /* If -march= is used, and -mcpu= has not been used,
608 assume that we should tune for a representative
609 CPU from that architecture. */
611 /* -mtune= overrides -mcpu= and -march=. */
613 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
617 /* If we have been given an architecture and a processor
618 make sure that they are compatible. We only generate
619 a warning though, and we prefer the CPU over the
621 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
622 warning ("switch -mcpu=%s conflicts with -march= switch",
625 insn_flags
= sel
->flags
;
631 if (sel
->name
== NULL
)
632 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
636 /* If the user did not specify a processor, choose one for them. */
639 const struct processors
* sel
;
641 enum processor_type cpu
;
643 cpu
= TARGET_CPU_DEFAULT
;
646 #ifdef SUBTARGET_CPU_DEFAULT
647 /* Use the subtarget default CPU if none was specified by
649 cpu
= SUBTARGET_CPU_DEFAULT
;
651 /* Default to ARM6. */
655 sel
= &all_cores
[cpu
];
657 insn_flags
= sel
->flags
;
659 /* Now check to see if the user has specified some command line
660 switch that require certain abilities from the cpu. */
663 if (TARGET_INTERWORK
|| TARGET_THUMB
)
665 sought
|= (FL_THUMB
| FL_MODE32
);
667 /* Force apcs-32 to be used for interworking. */
668 target_flags
|= ARM_FLAG_APCS_32
;
670 /* There are no ARM processors that support both APCS-26 and
671 interworking. Therefore we force FL_MODE26 to be removed
672 from insn_flags here (if it was set), so that the search
673 below will always be able to find a compatible processor. */
674 insn_flags
&= ~FL_MODE26
;
676 else if (!TARGET_APCS_32
)
679 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
681 /* Try to locate a CPU type that supports all of the abilities
682 of the default CPU, plus the extra abilities requested by
684 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
685 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
688 if (sel
->name
== NULL
)
690 unsigned current_bit_count
= 0;
691 const struct processors
* best_fit
= NULL
;
693 /* Ideally we would like to issue an error message here
694 saying that it was not possible to find a CPU compatible
695 with the default CPU, but which also supports the command
696 line options specified by the programmer, and so they
697 ought to use the -mcpu=<name> command line option to
698 override the default CPU type.
700 Unfortunately this does not work with multilibing. We
701 need to be able to support multilibs for -mapcs-26 and for
702 -mthumb-interwork and there is no CPU that can support both
703 options. Instead if we cannot find a cpu that has both the
704 characteristics of the default cpu and the given command line
705 options we scan the array again looking for a best match. */
706 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
707 if ((sel
->flags
& sought
) == sought
)
711 count
= bit_count (sel
->flags
& insn_flags
);
713 if (count
>= current_bit_count
)
716 current_bit_count
= count
;
720 if (best_fit
== NULL
)
726 insn_flags
= sel
->flags
;
728 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
729 if (arm_tune
== arm_none
)
730 arm_tune
= (enum processor_type
) (sel
- all_cores
);
733 /* The processor for which we should tune should now have been
735 if (arm_tune
== arm_none
)
738 tune_flags
= all_cores
[(int)arm_tune
].flags
;
739 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
741 /* Make sure that the processor choice does not conflict with any of the
742 other command line choices. */
743 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
745 /* If APCS-32 was not the default then it must have been set by the
746 user, so issue a warning message. If the user has specified
747 "-mapcs-32 -mcpu=arm2" then we loose here. */
748 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
749 warning ("target CPU does not support APCS-32" );
750 target_flags
&= ~ARM_FLAG_APCS_32
;
752 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
754 warning ("target CPU does not support APCS-26" );
755 target_flags
|= ARM_FLAG_APCS_32
;
758 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
760 warning ("target CPU does not support interworking" );
761 target_flags
&= ~ARM_FLAG_INTERWORK
;
764 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
766 warning ("target CPU does not support THUMB instructions");
767 target_flags
&= ~ARM_FLAG_THUMB
;
770 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
772 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
773 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
776 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
777 from here where no function is being compiled currently. */
778 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
780 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
782 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
783 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
785 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
786 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
788 /* If interworking is enabled then APCS-32 must be selected as well. */
789 if (TARGET_INTERWORK
)
792 warning ("interworking forces APCS-32 to be used" );
793 target_flags
|= ARM_FLAG_APCS_32
;
796 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
798 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
799 target_flags
|= ARM_FLAG_APCS_FRAME
;
802 if (TARGET_POKE_FUNCTION_NAME
)
803 target_flags
|= ARM_FLAG_APCS_FRAME
;
805 if (TARGET_APCS_REENT
&& flag_pic
)
806 error ("-fpic and -mapcs-reent are incompatible");
808 if (TARGET_APCS_REENT
)
809 warning ("APCS reentrant code not supported. Ignored");
811 /* If this target is normally configured to use APCS frames, warn if they
812 are turned off and debugging is turned on. */
814 && write_symbols
!= NO_DEBUG
815 && !TARGET_APCS_FRAME
816 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
817 warning ("-g with -mno-apcs-frame may not give sensible debugging");
819 /* If stack checking is disabled, we can use r10 as the PIC register,
820 which keeps r9 available. */
822 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
824 if (TARGET_APCS_FLOAT
)
825 warning ("passing floating point arguments in fp regs not yet supported");
827 /* Initialize boolean versions of the flags, for use in the arm.md file. */
828 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
829 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
830 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
831 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
832 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
833 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
834 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
836 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
837 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
838 thumb_code
= (TARGET_ARM
== 0);
839 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
840 && !(tune_flags
& FL_ARCH4
))) != 0;
841 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
842 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
846 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
848 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
850 arm_abi
= arm_all_abis
[i
].abi_type
;
854 if (i
== ARRAY_SIZE (arm_all_abis
))
855 error ("invalid ABI option: -mabi=%s", target_abi_name
);
858 arm_abi
= ARM_DEFAULT_ABI
;
860 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
861 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
863 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
864 error ("iwmmxt abi requires an iwmmxt capable cpu");
866 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
867 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
869 if (streq (target_fpe_name
, "2"))
870 target_fpu_name
= "fpe2";
871 else if (streq (target_fpe_name
, "3"))
872 target_fpu_name
= "fpe3";
874 error ("invalid floating point emulation option: -mfpe=%s",
877 if (target_fpu_name
!= NULL
)
879 /* The user specified a FPU. */
880 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
882 if (streq (all_fpus
[i
].name
, target_fpu_name
))
884 arm_fpu_arch
= all_fpus
[i
].fpu
;
885 arm_fpu_tune
= arm_fpu_arch
;
886 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
890 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
891 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
895 #ifdef FPUTYPE_DEFAULT
896 /* Use the default if it is specified for this platform. */
897 arm_fpu_arch
= FPUTYPE_DEFAULT
;
898 arm_fpu_tune
= FPUTYPE_DEFAULT
;
900 /* Pick one based on CPU type. */
901 /* ??? Some targets assume FPA is the default.
902 if ((insn_flags & FL_VFP) != 0)
903 arm_fpu_arch = FPUTYPE_VFP;
907 arm_fpu_arch
= FPUTYPE_MAVERICK
;
909 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
911 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
912 arm_fpu_tune
= FPUTYPE_FPA
;
914 arm_fpu_tune
= arm_fpu_arch
;
915 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
916 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
920 if (target_float_abi_name
!= NULL
)
922 /* The user specified a FP ABI. */
923 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
925 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
927 arm_float_abi
= all_float_abis
[i
].abi_type
;
931 if (i
== ARRAY_SIZE (all_float_abis
))
932 error ("invalid floating point abi: -mfloat-abi=%s",
933 target_float_abi_name
);
937 /* Use soft-float target flag. */
938 if (target_flags
& ARM_FLAG_SOFT_FLOAT
)
939 arm_float_abi
= ARM_FLOAT_ABI_SOFT
;
941 arm_float_abi
= ARM_FLOAT_ABI_HARD
;
944 if (arm_float_abi
== ARM_FLOAT_ABI_SOFTFP
)
945 sorry ("-mfloat-abi=softfp");
946 /* If soft-float is specified then don't use FPU. */
947 if (TARGET_SOFT_FLOAT
)
948 arm_fpu_arch
= FPUTYPE_NONE
;
950 /* For arm2/3 there is no need to do any scheduling if there is only
951 a floating point emulator, or we are doing software floating-point. */
952 if ((TARGET_SOFT_FLOAT
953 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
954 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
955 && (tune_flags
& FL_MODE32
) == 0)
956 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
958 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
960 /* Override the default structure alignment for AAPCS ABI. */
961 if (arm_abi
== ARM_ABI_AAPCS
)
962 arm_structure_size_boundary
= 8;
964 if (structure_size_string
!= NULL
)
966 int size
= strtol (structure_size_string
, NULL
, 0);
968 if (size
== 8 || size
== 32
969 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
970 arm_structure_size_boundary
= size
;
972 warning ("structure size boundary can only be set to %s",
973 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
976 if (arm_pic_register_string
!= NULL
)
978 int pic_register
= decode_reg_name (arm_pic_register_string
);
981 warning ("-mpic-register= is useless without -fpic");
983 /* Prevent the user from choosing an obviously stupid PIC register. */
984 else if (pic_register
< 0 || call_used_regs
[pic_register
]
985 || pic_register
== HARD_FRAME_POINTER_REGNUM
986 || pic_register
== STACK_POINTER_REGNUM
987 || pic_register
>= PC_REGNUM
)
988 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
990 arm_pic_register
= pic_register
;
993 if (TARGET_THUMB
&& flag_schedule_insns
)
995 /* Don't warn since it's on by default in -O2. */
996 flag_schedule_insns
= 0;
1001 /* There's some dispute as to whether this should be 1 or 2. However,
1002 experiments seem to show that in pathological cases a setting of
1003 1 degrades less severely than a setting of 2. This could change if
1004 other parts of the compiler change their behavior. */
1005 arm_constant_limit
= 1;
1007 /* If optimizing for size, bump the number of instructions that we
1008 are prepared to conditionally execute (even on a StrongARM). */
1009 max_insns_skipped
= 6;
1013 /* For processors with load scheduling, it never costs more than
1014 2 cycles to load a constant, and the load scheduler may well
1015 reduce that to 1. */
1016 if (tune_flags
& FL_LDSCHED
)
1017 arm_constant_limit
= 1;
1019 /* On XScale the longer latency of a load makes it more difficult
1020 to achieve a good schedule, so it's faster to synthesize
1021 constants that can be done in two insns. */
1022 if (arm_tune_xscale
)
1023 arm_constant_limit
= 2;
1025 /* StrongARM has early execution of branches, so a sequence
1026 that is worth skipping is shorter. */
1028 max_insns_skipped
= 3;
1031 /* Register global variables with the garbage collector. */
1032 arm_add_gc_roots ();
1036 arm_add_gc_roots (void)
1038 gcc_obstack_init(&minipool_obstack
);
1039 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1042 /* A table of known ARM exception types.
1043 For use with the interrupt function attribute. */
1047 const char *const arg
;
1048 const unsigned long return_value
;
1052 static const isr_attribute_arg isr_attribute_args
[] =
1054 { "IRQ", ARM_FT_ISR
},
1055 { "irq", ARM_FT_ISR
},
1056 { "FIQ", ARM_FT_FIQ
},
1057 { "fiq", ARM_FT_FIQ
},
1058 { "ABORT", ARM_FT_ISR
},
1059 { "abort", ARM_FT_ISR
},
1060 { "ABORT", ARM_FT_ISR
},
1061 { "abort", ARM_FT_ISR
},
1062 { "UNDEF", ARM_FT_EXCEPTION
},
1063 { "undef", ARM_FT_EXCEPTION
},
1064 { "SWI", ARM_FT_EXCEPTION
},
1065 { "swi", ARM_FT_EXCEPTION
},
1066 { NULL
, ARM_FT_NORMAL
}
1069 /* Returns the (interrupt) function type of the current
1070 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1072 static unsigned long
1073 arm_isr_value (tree argument
)
1075 const isr_attribute_arg
* ptr
;
1078 /* No argument - default to IRQ. */
1079 if (argument
== NULL_TREE
)
1082 /* Get the value of the argument. */
1083 if (TREE_VALUE (argument
) == NULL_TREE
1084 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1085 return ARM_FT_UNKNOWN
;
1087 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1089 /* Check it against the list of known arguments. */
1090 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1091 if (streq (arg
, ptr
->arg
))
1092 return ptr
->return_value
;
1094 /* An unrecognized interrupt type. */
1095 return ARM_FT_UNKNOWN
;
1098 /* Computes the type of the current function. */
1100 static unsigned long
1101 arm_compute_func_type (void)
1103 unsigned long type
= ARM_FT_UNKNOWN
;
1107 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
1110 /* Decide if the current function is volatile. Such functions
1111 never return, and many memory cycles can be saved by not storing
1112 register values that will never be needed again. This optimization
1113 was added to speed up context switching in a kernel application. */
1115 && current_function_nothrow
1116 && TREE_THIS_VOLATILE (current_function_decl
))
1117 type
|= ARM_FT_VOLATILE
;
1119 if (cfun
->static_chain_decl
!= NULL
)
1120 type
|= ARM_FT_NESTED
;
1122 attr
= DECL_ATTRIBUTES (current_function_decl
);
1124 a
= lookup_attribute ("naked", attr
);
1126 type
|= ARM_FT_NAKED
;
1128 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
1129 type
|= ARM_FT_EXCEPTION_HANDLER
;
1132 a
= lookup_attribute ("isr", attr
);
1134 a
= lookup_attribute ("interrupt", attr
);
1137 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1139 type
|= arm_isr_value (TREE_VALUE (a
));
1145 /* Returns the type of the current function. */
1148 arm_current_func_type (void)
1150 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1151 cfun
->machine
->func_type
= arm_compute_func_type ();
1153 return cfun
->machine
->func_type
;
1156 /* Return 1 if it is possible to return using a single instruction.
1157 If SIBLING is non-null, this is a test for a return before a sibling
1158 call. SIBLING is the call insn, so we can examine its register usage. */
1161 use_return_insn (int iscond
, rtx sibling
)
1164 unsigned int func_type
;
1165 unsigned long saved_int_regs
;
1166 unsigned HOST_WIDE_INT stack_adjust
;
1167 arm_stack_offsets
*offsets
;
1169 /* Never use a return instruction before reload has run. */
1170 if (!reload_completed
)
1173 func_type
= arm_current_func_type ();
1175 /* Naked functions and volatile functions need special
1177 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1180 /* So do interrupt functions that use the frame pointer. */
1181 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1184 offsets
= arm_get_frame_offsets ();
1185 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1187 /* As do variadic functions. */
1188 if (current_function_pretend_args_size
1189 || cfun
->machine
->uses_anonymous_args
1190 /* Or if the function calls __builtin_eh_return () */
1191 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
1192 /* Or if the function calls alloca */
1193 || current_function_calls_alloca
1194 /* Or if there is a stack adjustment. However, if the stack pointer
1195 is saved on the stack, we can use a pre-incrementing stack load. */
1196 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1199 saved_int_regs
= arm_compute_save_reg_mask ();
1201 /* Unfortunately, the insn
1203 ldmib sp, {..., sp, ...}
1205 triggers a bug on most SA-110 based devices, such that the stack
1206 pointer won't be correctly restored if the instruction takes a
1207 page fault. We work around this problem by popping r3 along with
1208 the other registers, since that is never slower than executing
1209 another instruction.
1211 We test for !arm_arch5 here, because code for any architecture
1212 less than this could potentially be run on one of the buggy
1214 if (stack_adjust
== 4 && !arm_arch5
)
1216 /* Validate that r3 is a call-clobbered register (always true in
1217 the default abi) ... */
1218 if (!call_used_regs
[3])
1221 /* ... that it isn't being used for a return value (always true
1222 until we implement return-in-regs), or for a tail-call
1226 if (GET_CODE (sibling
) != CALL_INSN
)
1229 if (find_regno_fusage (sibling
, USE
, 3))
1233 /* ... and that there are no call-saved registers in r0-r2
1234 (always true in the default ABI). */
1235 if (saved_int_regs
& 0x7)
1239 /* Can't be done if interworking with Thumb, and any registers have been
1241 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1244 /* On StrongARM, conditional returns are expensive if they aren't
1245 taken and multiple registers have been stacked. */
1246 if (iscond
&& arm_is_strong
)
1248 /* Conditional return when just the LR is stored is a simple
1249 conditional-load instruction, that's not expensive. */
1250 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1253 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1257 /* If there are saved registers but the LR isn't saved, then we need
1258 two instructions for the return. */
1259 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1262 /* Can't be done if any of the FPA regs are pushed,
1263 since this also requires an insn. */
1264 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1265 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1266 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1269 /* Likewise VFP regs. */
1270 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1271 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1272 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1275 if (TARGET_REALLY_IWMMXT
)
1276 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1277 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1283 /* Return TRUE if int I is a valid immediate ARM constant. */
1286 const_ok_for_arm (HOST_WIDE_INT i
)
1288 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1290 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1291 be all zero, or all one. */
1292 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1293 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1294 != ((~(unsigned HOST_WIDE_INT
) 0)
1295 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1298 /* Fast return for 0 and powers of 2 */
1299 if ((i
& (i
- 1)) == 0)
1304 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1307 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1308 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1310 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1315 /* Return true if I is a valid constant for the operation CODE. */
1317 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1319 if (const_ok_for_arm (i
))
1325 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1327 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1333 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1340 /* Emit a sequence of insns to handle a large constant.
1341 CODE is the code of the operation required, it can be any of SET, PLUS,
1342 IOR, AND, XOR, MINUS;
1343 MODE is the mode in which the operation is being performed;
1344 VAL is the integer to operate on;
1345 SOURCE is the other operand (a register, or a null-pointer for SET);
1346 SUBTARGETS means it is safe to create scratch registers if that will
1347 either produce a simpler sequence, or we will want to cse the values.
1348 Return value is the number of insns emitted. */
1351 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1352 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1356 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1357 cond
= COND_EXEC_TEST (PATTERN (insn
));
1361 if (subtargets
|| code
== SET
1362 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1363 && REGNO (target
) != REGNO (source
)))
1365 /* After arm_reorg has been called, we can't fix up expensive
1366 constants by pushing them into memory so we must synthesize
1367 them in-line, regardless of the cost. This is only likely to
1368 be more costly on chips that have load delay slots and we are
1369 compiling without running the scheduler (so no splitting
1370 occurred before the final instruction emission).
1372 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1374 if (!after_arm_reorg
1376 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1378 > arm_constant_limit
+ (code
!= SET
)))
1382 /* Currently SET is the only monadic value for CODE, all
1383 the rest are diadic. */
1384 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1389 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1391 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1392 /* For MINUS, the value is subtracted from, since we never
1393 have subtraction of a constant. */
1395 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1396 gen_rtx_MINUS (mode
, temp
, source
)));
1398 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1399 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1405 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1410 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1412 HOST_WIDE_INT temp1
;
1420 if (remainder
& (3 << (i
- 2)))
1425 temp1
= remainder
& ((0x0ff << end
)
1426 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1427 remainder
&= ~temp1
;
1432 } while (remainder
);
1436 /* Emit an instruction with the indicated PATTERN. If COND is
1437 non-NULL, conditionalize the execution of the instruction on COND
1441 emit_constant_insn (rtx cond
, rtx pattern
)
1444 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1445 emit_insn (pattern
);
1448 /* As above, but extra parameter GENERATE which, if clear, suppresses
1452 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1453 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1458 int can_negate_initial
= 0;
1461 int num_bits_set
= 0;
1462 int set_sign_bit_copies
= 0;
1463 int clear_sign_bit_copies
= 0;
1464 int clear_zero_bit_copies
= 0;
1465 int set_zero_bit_copies
= 0;
1467 unsigned HOST_WIDE_INT temp1
, temp2
;
1468 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1470 /* Find out which operations are safe for a given CODE. Also do a quick
1471 check for degenerate cases; these can occur when DImode operations
1483 can_negate_initial
= 1;
1487 if (remainder
== 0xffffffff)
1490 emit_constant_insn (cond
,
1491 gen_rtx_SET (VOIDmode
, target
,
1492 GEN_INT (ARM_SIGN_EXTEND (val
))));
1497 if (reload_completed
&& rtx_equal_p (target
, source
))
1500 emit_constant_insn (cond
,
1501 gen_rtx_SET (VOIDmode
, target
, source
));
1510 emit_constant_insn (cond
,
1511 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1514 if (remainder
== 0xffffffff)
1516 if (reload_completed
&& rtx_equal_p (target
, source
))
1519 emit_constant_insn (cond
,
1520 gen_rtx_SET (VOIDmode
, target
, source
));
1529 if (reload_completed
&& rtx_equal_p (target
, source
))
1532 emit_constant_insn (cond
,
1533 gen_rtx_SET (VOIDmode
, target
, source
));
1536 if (remainder
== 0xffffffff)
1539 emit_constant_insn (cond
,
1540 gen_rtx_SET (VOIDmode
, target
,
1541 gen_rtx_NOT (mode
, source
)));
1545 /* We don't know how to handle this yet below. */
1549 /* We treat MINUS as (val - source), since (source - val) is always
1550 passed as (source + (-val)). */
1554 emit_constant_insn (cond
,
1555 gen_rtx_SET (VOIDmode
, target
,
1556 gen_rtx_NEG (mode
, source
)));
1559 if (const_ok_for_arm (val
))
1562 emit_constant_insn (cond
,
1563 gen_rtx_SET (VOIDmode
, target
,
1564 gen_rtx_MINUS (mode
, GEN_INT (val
),
1576 /* If we can do it in one insn get out quickly. */
1577 if (const_ok_for_arm (val
)
1578 || (can_negate_initial
&& const_ok_for_arm (-val
))
1579 || (can_invert
&& const_ok_for_arm (~val
)))
1582 emit_constant_insn (cond
,
1583 gen_rtx_SET (VOIDmode
, target
,
1585 ? gen_rtx_fmt_ee (code
, mode
, source
,
1591 /* Calculate a few attributes that may be useful for specific
1593 for (i
= 31; i
>= 0; i
--)
1595 if ((remainder
& (1 << i
)) == 0)
1596 clear_sign_bit_copies
++;
1601 for (i
= 31; i
>= 0; i
--)
1603 if ((remainder
& (1 << i
)) != 0)
1604 set_sign_bit_copies
++;
1609 for (i
= 0; i
<= 31; i
++)
1611 if ((remainder
& (1 << i
)) == 0)
1612 clear_zero_bit_copies
++;
1617 for (i
= 0; i
<= 31; i
++)
1619 if ((remainder
& (1 << i
)) != 0)
1620 set_zero_bit_copies
++;
1628 /* See if we can do this by sign_extending a constant that is known
1629 to be negative. This is a good, way of doing it, since the shift
1630 may well merge into a subsequent insn. */
1631 if (set_sign_bit_copies
> 1)
1633 if (const_ok_for_arm
1634 (temp1
= ARM_SIGN_EXTEND (remainder
1635 << (set_sign_bit_copies
- 1))))
1639 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1640 emit_constant_insn (cond
,
1641 gen_rtx_SET (VOIDmode
, new_src
,
1643 emit_constant_insn (cond
,
1644 gen_ashrsi3 (target
, new_src
,
1645 GEN_INT (set_sign_bit_copies
- 1)));
1649 /* For an inverted constant, we will need to set the low bits,
1650 these will be shifted out of harm's way. */
1651 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1652 if (const_ok_for_arm (~temp1
))
1656 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1657 emit_constant_insn (cond
,
1658 gen_rtx_SET (VOIDmode
, new_src
,
1660 emit_constant_insn (cond
,
1661 gen_ashrsi3 (target
, new_src
,
1662 GEN_INT (set_sign_bit_copies
- 1)));
1668 /* See if we can generate this by setting the bottom (or the top)
1669 16 bits, and then shifting these into the other half of the
1670 word. We only look for the simplest cases, to do more would cost
1671 too much. Be careful, however, not to generate this when the
1672 alternative would take fewer insns. */
1673 if (val
& 0xffff0000)
1675 temp1
= remainder
& 0xffff0000;
1676 temp2
= remainder
& 0x0000ffff;
1678 /* Overlaps outside this range are best done using other methods. */
1679 for (i
= 9; i
< 24; i
++)
1681 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1682 && !const_ok_for_arm (temp2
))
1684 rtx new_src
= (subtargets
1685 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1687 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1688 source
, subtargets
, generate
);
1696 gen_rtx_ASHIFT (mode
, source
,
1703 /* Don't duplicate cases already considered. */
1704 for (i
= 17; i
< 24; i
++)
1706 if (((temp1
| (temp1
>> i
)) == remainder
)
1707 && !const_ok_for_arm (temp1
))
1709 rtx new_src
= (subtargets
1710 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1712 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1713 source
, subtargets
, generate
);
1718 gen_rtx_SET (VOIDmode
, target
,
1721 gen_rtx_LSHIFTRT (mode
, source
,
1732 /* If we have IOR or XOR, and the constant can be loaded in a
1733 single instruction, and we can find a temporary to put it in,
1734 then this can be done in two instructions instead of 3-4. */
1736 /* TARGET can't be NULL if SUBTARGETS is 0 */
1737 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1739 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1743 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1745 emit_constant_insn (cond
,
1746 gen_rtx_SET (VOIDmode
, sub
,
1748 emit_constant_insn (cond
,
1749 gen_rtx_SET (VOIDmode
, target
,
1750 gen_rtx_fmt_ee (code
, mode
,
1760 if (set_sign_bit_copies
> 8
1761 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1765 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1766 rtx shift
= GEN_INT (set_sign_bit_copies
);
1770 gen_rtx_SET (VOIDmode
, sub
,
1772 gen_rtx_ASHIFT (mode
,
1777 gen_rtx_SET (VOIDmode
, target
,
1779 gen_rtx_LSHIFTRT (mode
, sub
,
1785 if (set_zero_bit_copies
> 8
1786 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1790 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1791 rtx shift
= GEN_INT (set_zero_bit_copies
);
1795 gen_rtx_SET (VOIDmode
, sub
,
1797 gen_rtx_LSHIFTRT (mode
,
1802 gen_rtx_SET (VOIDmode
, target
,
1804 gen_rtx_ASHIFT (mode
, sub
,
1810 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1814 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1815 emit_constant_insn (cond
,
1816 gen_rtx_SET (VOIDmode
, sub
,
1817 gen_rtx_NOT (mode
, source
)));
1820 sub
= gen_reg_rtx (mode
);
1821 emit_constant_insn (cond
,
1822 gen_rtx_SET (VOIDmode
, sub
,
1823 gen_rtx_AND (mode
, source
,
1825 emit_constant_insn (cond
,
1826 gen_rtx_SET (VOIDmode
, target
,
1827 gen_rtx_NOT (mode
, sub
)));
1834 /* See if two shifts will do 2 or more insn's worth of work. */
1835 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1837 HOST_WIDE_INT shift_mask
= ((0xffffffff
1838 << (32 - clear_sign_bit_copies
))
1841 if ((remainder
| shift_mask
) != 0xffffffff)
1845 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1846 insns
= arm_gen_constant (AND
, mode
, cond
,
1847 remainder
| shift_mask
,
1848 new_src
, source
, subtargets
, 1);
1853 rtx targ
= subtargets
? NULL_RTX
: target
;
1854 insns
= arm_gen_constant (AND
, mode
, cond
,
1855 remainder
| shift_mask
,
1856 targ
, source
, subtargets
, 0);
1862 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1863 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1865 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1866 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1872 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1874 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1876 if ((remainder
| shift_mask
) != 0xffffffff)
1880 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1882 insns
= arm_gen_constant (AND
, mode
, cond
,
1883 remainder
| shift_mask
,
1884 new_src
, source
, subtargets
, 1);
1889 rtx targ
= subtargets
? NULL_RTX
: target
;
1891 insns
= arm_gen_constant (AND
, mode
, cond
,
1892 remainder
| shift_mask
,
1893 targ
, source
, subtargets
, 0);
1899 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1900 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1902 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1903 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1915 for (i
= 0; i
< 32; i
++)
1916 if (remainder
& (1 << i
))
1919 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1920 remainder
= (~remainder
) & 0xffffffff;
1921 else if (code
== PLUS
&& num_bits_set
> 16)
1922 remainder
= (-remainder
) & 0xffffffff;
1929 /* Now try and find a way of doing the job in either two or three
1931 We start by looking for the largest block of zeros that are aligned on
1932 a 2-bit boundary, we then fill up the temps, wrapping around to the
1933 top of the word when we drop off the bottom.
1934 In the worst case this code should produce no more than four insns. */
1937 int best_consecutive_zeros
= 0;
1939 for (i
= 0; i
< 32; i
+= 2)
1941 int consecutive_zeros
= 0;
1943 if (!(remainder
& (3 << i
)))
1945 while ((i
< 32) && !(remainder
& (3 << i
)))
1947 consecutive_zeros
+= 2;
1950 if (consecutive_zeros
> best_consecutive_zeros
)
1952 best_consecutive_zeros
= consecutive_zeros
;
1953 best_start
= i
- consecutive_zeros
;
1959 /* So long as it won't require any more insns to do so, it's
1960 desirable to emit a small constant (in bits 0...9) in the last
1961 insn. This way there is more chance that it can be combined with
1962 a later addressing insn to form a pre-indexed load or store
1963 operation. Consider:
1965 *((volatile int *)0xe0000100) = 1;
1966 *((volatile int *)0xe0000110) = 2;
1968 We want this to wind up as:
1972 str rB, [rA, #0x100]
1974 str rB, [rA, #0x110]
1976 rather than having to synthesize both large constants from scratch.
1978 Therefore, we calculate how many insns would be required to emit
1979 the constant starting from `best_start', and also starting from
1980 zero (ie with bit 31 first to be output). If `best_start' doesn't
1981 yield a shorter sequence, we may as well use zero. */
1983 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1984 && (count_insns_for_constant (remainder
, 0) <=
1985 count_insns_for_constant (remainder
, best_start
)))
1988 /* Now start emitting the insns. */
1996 if (remainder
& (3 << (i
- 2)))
2001 temp1
= remainder
& ((0x0ff << end
)
2002 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2003 remainder
&= ~temp1
;
2007 rtx new_src
, temp1_rtx
;
2009 if (code
== SET
|| code
== MINUS
)
2011 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2012 if (can_invert
&& code
!= MINUS
)
2017 if (remainder
&& subtargets
)
2018 new_src
= gen_reg_rtx (mode
);
2023 else if (can_negate
)
2027 temp1
= trunc_int_for_mode (temp1
, mode
);
2028 temp1_rtx
= GEN_INT (temp1
);
2032 else if (code
== MINUS
)
2033 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2035 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2037 emit_constant_insn (cond
,
2038 gen_rtx_SET (VOIDmode
, new_src
,
2048 else if (code
== MINUS
)
2062 /* Canonicalize a comparison so that we are more likely to recognize it.
2063 This can be done for a few constant compares, where we can make the
2064 immediate value easier to load. */
2067 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
2069 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2079 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
2080 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2082 *op1
= GEN_INT (i
+ 1);
2083 return code
== GT
? GE
: LT
;
2089 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
2090 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2092 *op1
= GEN_INT (i
- 1);
2093 return code
== GE
? GT
: LE
;
2099 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2100 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2102 *op1
= GEN_INT (i
+ 1);
2103 return code
== GTU
? GEU
: LTU
;
2110 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2112 *op1
= GEN_INT (i
- 1);
2113 return code
== GEU
? GTU
: LEU
;
2125 /* Define how to find the value returned by a function. */
2127 rtx
arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2129 enum machine_mode mode
;
2130 int unsignedp ATTRIBUTE_UNUSED
;
2131 rtx r ATTRIBUTE_UNUSED
;
2134 mode
= TYPE_MODE (type
);
2135 /* Promote integer types. */
2136 if (INTEGRAL_TYPE_P (type
))
2137 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2138 return LIBCALL_VALUE(mode
);
2142 /* Decide whether a type should be returned in memory (true)
2143 or in a register (false). This is called by the macro
2144 RETURN_IN_MEMORY. */
2146 arm_return_in_memory (tree type
)
2150 if (!AGGREGATE_TYPE_P (type
))
2151 /* All simple types are returned in registers. */
2154 size
= int_size_in_bytes (type
);
2156 if (arm_abi
!= ARM_ABI_APCS
)
2158 /* ATPCS and later return aggregate types in memory only if they are
2159 larger than a word (or are variable size). */
2160 return (size
< 0 || size
> UNITS_PER_WORD
);
2163 /* For the arm-wince targets we choose to be compatible with Microsoft's
2164 ARM and Thumb compilers, which always return aggregates in memory. */
2166 /* All structures/unions bigger than one word are returned in memory.
2167 Also catch the case where int_size_in_bytes returns -1. In this case
2168 the aggregate is either huge or of variable size, and in either case
2169 we will want to return it via memory and not in a register. */
2170 if (size
< 0 || size
> UNITS_PER_WORD
)
2173 if (TREE_CODE (type
) == RECORD_TYPE
)
2177 /* For a struct the APCS says that we only return in a register
2178 if the type is 'integer like' and every addressable element
2179 has an offset of zero. For practical purposes this means
2180 that the structure can have at most one non bit-field element
2181 and that this element must be the first one in the structure. */
2183 /* Find the first field, ignoring non FIELD_DECL things which will
2184 have been created by C++. */
2185 for (field
= TYPE_FIELDS (type
);
2186 field
&& TREE_CODE (field
) != FIELD_DECL
;
2187 field
= TREE_CHAIN (field
))
2191 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2193 /* Check that the first field is valid for returning in a register. */
2195 /* ... Floats are not allowed */
2196 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2199 /* ... Aggregates that are not themselves valid for returning in
2200 a register are not allowed. */
2201 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2204 /* Now check the remaining fields, if any. Only bitfields are allowed,
2205 since they are not addressable. */
2206 for (field
= TREE_CHAIN (field
);
2208 field
= TREE_CHAIN (field
))
2210 if (TREE_CODE (field
) != FIELD_DECL
)
2213 if (!DECL_BIT_FIELD_TYPE (field
))
2220 if (TREE_CODE (type
) == UNION_TYPE
)
2224 /* Unions can be returned in registers if every element is
2225 integral, or can be returned in an integer register. */
2226 for (field
= TYPE_FIELDS (type
);
2228 field
= TREE_CHAIN (field
))
2230 if (TREE_CODE (field
) != FIELD_DECL
)
2233 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2236 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2242 #endif /* not ARM_WINCE */
2244 /* Return all other types in memory. */
2248 /* Indicate whether or not words of a double are in big-endian order. */
2251 arm_float_words_big_endian (void)
2253 if (TARGET_MAVERICK
)
2256 /* For FPA, float words are always big-endian. For VFP, floats words
2257 follow the memory system mode. */
2265 return (TARGET_BIG_END
? 1 : 0);
2270 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2271 for a call to a function whose data type is FNTYPE.
2272 For a library call, FNTYPE is NULL. */
2274 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2275 rtx libname ATTRIBUTE_UNUSED
,
2276 tree fndecl ATTRIBUTE_UNUSED
)
2278 /* On the ARM, the offset starts at 0. */
2279 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2280 pcum
->iwmmxt_nregs
= 0;
2281 pcum
->can_split
= true;
2283 pcum
->call_cookie
= CALL_NORMAL
;
2285 if (TARGET_LONG_CALLS
)
2286 pcum
->call_cookie
= CALL_LONG
;
2288 /* Check for long call/short call attributes. The attributes
2289 override any command line option. */
2292 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2293 pcum
->call_cookie
= CALL_SHORT
;
2294 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2295 pcum
->call_cookie
= CALL_LONG
;
2298 /* Varargs vectors are treated the same as long long.
2299 named_count avoids having to change the way arm handles 'named' */
2300 pcum
->named_count
= 0;
2303 if (TARGET_REALLY_IWMMXT
&& fntype
)
2307 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2309 fn_arg
= TREE_CHAIN (fn_arg
))
2310 pcum
->named_count
+= 1;
2312 if (! pcum
->named_count
)
2313 pcum
->named_count
= INT_MAX
;
2318 /* Return true if mode/type need doubleword alignment. */
2320 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2322 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2323 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2327 /* Determine where to put an argument to a function.
2328 Value is zero to push the argument on the stack,
2329 or a hard register in which to store the argument.
2331 MODE is the argument's machine mode.
2332 TYPE is the data type of the argument (as a tree).
2333 This is null for libcalls where that information may
2335 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2336 the preceding args and about the function being called.
2337 NAMED is nonzero if this argument is a named parameter
2338 (otherwise it is an extra parameter matching an ellipsis). */
2341 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2342 tree type
, int named
)
2346 /* Varargs vectors are treated the same as long long.
2347 named_count avoids having to change the way arm handles 'named' */
2348 if (TARGET_IWMMXT_ABI
2349 && VECTOR_MODE_SUPPORTED_P (mode
)
2350 && pcum
->named_count
> pcum
->nargs
+ 1)
2352 if (pcum
->iwmmxt_nregs
<= 9)
2353 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2356 pcum
->can_split
= false;
2361 /* Put doubleword aligned quantities in even register pairs. */
2363 && ARM_DOUBLEWORD_ALIGN
2364 && arm_needs_doubleword_align (mode
, type
))
2367 if (mode
== VOIDmode
)
2368 /* Compute operand 2 of the call insn. */
2369 return GEN_INT (pcum
->call_cookie
);
2371 /* Only allow splitting an arg between regs and memory if all preceding
2372 args were allocated to regs. For args passed by reference we only count
2373 the reference pointer. */
2374 if (pcum
->can_split
)
2377 nregs
= ARM_NUM_REGS2 (mode
, type
);
2379 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2382 return gen_rtx_REG (mode
, pcum
->nregs
);
2385 /* Variable sized types are passed by reference. This is a GCC
2386 extension to the ARM ABI. */
2389 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2390 enum machine_mode mode ATTRIBUTE_UNUSED
,
2391 tree type
, int named ATTRIBUTE_UNUSED
)
2393 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2396 /* Implement va_arg. */
2399 arm_va_arg (tree valist
, tree type
)
2403 /* Variable sized types are passed by reference. */
2404 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2406 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2407 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2410 align
= FUNCTION_ARG_BOUNDARY (TYPE_MODE (type
), type
);
2411 if (align
> PARM_BOUNDARY
)
2416 /* Maintain 64-bit alignment of the valist pointer by
2417 constructing: valist = ((valist + (8 - 1)) & -8). */
2418 mask
= build_int_2 (- (align
/ BITS_PER_UNIT
), -1);
2419 t
= build_int_2 ((align
/ BITS_PER_UNIT
) - 1, 0);
2420 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
, t
);
2421 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, mask
);
2422 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
2423 TREE_SIDE_EFFECTS (t
) = 1;
2424 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2426 /* This is to stop the combine pass optimizing
2427 away the alignment adjustment. */
2428 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
2431 return std_expand_builtin_va_arg (valist
, type
);
2434 /* Encode the current state of the #pragma [no_]long_calls. */
2437 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2438 LONG
, /* #pragma long_calls is in effect. */
2439 SHORT
/* #pragma no_long_calls is in effect. */
2442 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2445 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2447 arm_pragma_long_calls
= LONG
;
2451 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2453 arm_pragma_long_calls
= SHORT
;
2457 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2459 arm_pragma_long_calls
= OFF
;
2462 /* Table of machine attributes. */
2463 const struct attribute_spec arm_attribute_table
[] =
2465 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2466 /* Function calls made to this symbol must be done indirectly, because
2467 it may lie outside of the 26 bit addressing range of a normal function
2469 { "long_call", 0, 0, false, true, true, NULL
},
2470 /* Whereas these functions are always known to reside within the 26 bit
2471 addressing range. */
2472 { "short_call", 0, 0, false, true, true, NULL
},
2473 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2474 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2475 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2476 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2478 /* ARM/PE has three new attributes:
2480 dllexport - for exporting a function/variable that will live in a dll
2481 dllimport - for importing a function/variable from a dll
2483 Microsoft allows multiple declspecs in one __declspec, separating
2484 them with spaces. We do NOT support this. Instead, use __declspec
2487 { "dllimport", 0, 0, true, false, false, NULL
},
2488 { "dllexport", 0, 0, true, false, false, NULL
},
2489 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2491 { NULL
, 0, 0, false, false, false, NULL
}
2494 /* Handle an attribute requiring a FUNCTION_DECL;
2495 arguments as in struct attribute_spec.handler. */
2497 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2498 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2500 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2502 warning ("`%s' attribute only applies to functions",
2503 IDENTIFIER_POINTER (name
));
2504 *no_add_attrs
= true;
2510 /* Handle an "interrupt" or "isr" attribute;
2511 arguments as in struct attribute_spec.handler. */
2513 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2518 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2520 warning ("`%s' attribute only applies to functions",
2521 IDENTIFIER_POINTER (name
));
2522 *no_add_attrs
= true;
2524 /* FIXME: the argument if any is checked for type attributes;
2525 should it be checked for decl ones? */
2529 if (TREE_CODE (*node
) == FUNCTION_TYPE
2530 || TREE_CODE (*node
) == METHOD_TYPE
)
2532 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2534 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2535 *no_add_attrs
= true;
2538 else if (TREE_CODE (*node
) == POINTER_TYPE
2539 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2540 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2541 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2543 *node
= build_type_copy (*node
);
2544 TREE_TYPE (*node
) = build_type_attribute_variant
2546 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2547 *no_add_attrs
= true;
2551 /* Possibly pass this attribute on from the type to a decl. */
2552 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2553 | (int) ATTR_FLAG_FUNCTION_NEXT
2554 | (int) ATTR_FLAG_ARRAY_NEXT
))
2556 *no_add_attrs
= true;
2557 return tree_cons (name
, args
, NULL_TREE
);
2561 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2569 /* Return 0 if the attributes for two types are incompatible, 1 if they
2570 are compatible, and 2 if they are nearly compatible (which causes a
2571 warning to be generated). */
2573 arm_comp_type_attributes (tree type1
, tree type2
)
2577 /* Check for mismatch of non-default calling convention. */
2578 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2581 /* Check for mismatched call attributes. */
2582 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2583 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2584 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2585 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2587 /* Only bother to check if an attribute is defined. */
2588 if (l1
| l2
| s1
| s2
)
2590 /* If one type has an attribute, the other must have the same attribute. */
2591 if ((l1
!= l2
) || (s1
!= s2
))
2594 /* Disallow mixed attributes. */
2595 if ((l1
& s2
) || (l2
& s1
))
2599 /* Check for mismatched ISR attribute. */
2600 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2602 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2603 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2605 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2612 /* Encode long_call or short_call attribute by prefixing
2613 symbol name in DECL with a special character FLAG. */
2615 arm_encode_call_attribute (tree decl
, int flag
)
2617 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2618 int len
= strlen (str
);
2621 /* Do not allow weak functions to be treated as short call. */
2622 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2625 newstr
= alloca (len
+ 2);
2627 strcpy (newstr
+ 1, str
);
2629 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2630 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2633 /* Assigns default attributes to newly defined type. This is used to
2634 set short_call/long_call attributes for function types of
2635 functions defined inside corresponding #pragma scopes. */
2637 arm_set_default_type_attributes (tree type
)
2639 /* Add __attribute__ ((long_call)) to all functions, when
2640 inside #pragma long_calls or __attribute__ ((short_call)),
2641 when inside #pragma no_long_calls. */
2642 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2644 tree type_attr_list
, attr_name
;
2645 type_attr_list
= TYPE_ATTRIBUTES (type
);
2647 if (arm_pragma_long_calls
== LONG
)
2648 attr_name
= get_identifier ("long_call");
2649 else if (arm_pragma_long_calls
== SHORT
)
2650 attr_name
= get_identifier ("short_call");
2654 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2655 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2659 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2660 defined within the current compilation unit. If this cannot be
2661 determined, then 0 is returned. */
2663 current_file_function_operand (rtx sym_ref
)
2665 /* This is a bit of a fib. A function will have a short call flag
2666 applied to its name if it has the short call attribute, or it has
2667 already been defined within the current compilation unit. */
2668 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2671 /* The current function is always defined within the current compilation
2672 unit. if it s a weak definition however, then this may not be the real
2673 definition of the function, and so we have to say no. */
2674 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2675 && !DECL_WEAK (current_function_decl
))
2678 /* We cannot make the determination - default to returning 0. */
2682 /* Return nonzero if a 32 bit "long_call" should be generated for
2683 this call. We generate a long_call if the function:
2685 a. has an __attribute__((long call))
2686 or b. is within the scope of a #pragma long_calls
2687 or c. the -mlong-calls command line switch has been specified
2689 However we do not generate a long call if the function:
2691 d. has an __attribute__ ((short_call))
2692 or e. is inside the scope of a #pragma no_long_calls
2693 or f. has an __attribute__ ((section))
2694 or g. is defined within the current compilation unit.
2696 This function will be called by C fragments contained in the machine
2697 description file. CALL_REF and CALL_COOKIE correspond to the matched
2698 rtl operands. CALL_SYMBOL is used to distinguish between
2699 two different callers of the function. It is set to 1 in the
2700 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2701 and "call_value" patterns. This is because of the difference in the
2702 SYM_REFs passed by these patterns. */
2704 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2708 if (GET_CODE (sym_ref
) != MEM
)
2711 sym_ref
= XEXP (sym_ref
, 0);
2714 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2717 if (call_cookie
& CALL_SHORT
)
2720 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2723 if (current_file_function_operand (sym_ref
))
2726 return (call_cookie
& CALL_LONG
)
2727 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2728 || TARGET_LONG_CALLS
;
2731 /* Return nonzero if it is ok to make a tail-call to DECL. */
2733 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2735 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2737 if (cfun
->machine
->sibcall_blocked
)
2740 /* Never tailcall something for which we have no decl, or if we
2741 are in Thumb mode. */
2742 if (decl
== NULL
|| TARGET_THUMB
)
2745 /* Get the calling method. */
2746 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2747 call_type
= CALL_SHORT
;
2748 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2749 call_type
= CALL_LONG
;
2751 /* Cannot tail-call to long calls, since these are out of range of
2752 a branch instruction. However, if not compiling PIC, we know
2753 we can reach the symbol if it is in this compilation unit. */
2754 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2757 /* If we are interworking and the function is not declared static
2758 then we can't tail-call it unless we know that it exists in this
2759 compilation unit (since it might be a Thumb routine). */
2760 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2763 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2764 if (IS_INTERRUPT (arm_current_func_type ()))
2767 /* Everything else is ok. */
2772 /* Addressing mode support functions. */
2774 /* Return nonzero if X is a legitimate immediate operand when compiling
2777 legitimate_pic_operand_p (rtx x
)
2781 && (GET_CODE (x
) == SYMBOL_REF
2782 || (GET_CODE (x
) == CONST
2783 && GET_CODE (XEXP (x
, 0)) == PLUS
2784 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2791 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2793 if (GET_CODE (orig
) == SYMBOL_REF
2794 || GET_CODE (orig
) == LABEL_REF
)
2796 #ifndef AOF_ASSEMBLER
2797 rtx pic_ref
, address
;
2807 reg
= gen_reg_rtx (Pmode
);
2812 #ifdef AOF_ASSEMBLER
2813 /* The AOF assembler can generate relocations for these directly, and
2814 understands that the PIC register has to be added into the offset. */
2815 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2818 address
= gen_reg_rtx (Pmode
);
2823 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2825 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2827 if ((GET_CODE (orig
) == LABEL_REF
2828 || (GET_CODE (orig
) == SYMBOL_REF
&&
2829 SYMBOL_REF_LOCAL_P (orig
)))
2831 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2834 pic_ref
= gen_rtx_MEM (Pmode
,
2835 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2837 RTX_UNCHANGING_P (pic_ref
) = 1;
2840 insn
= emit_move_insn (reg
, pic_ref
);
2842 current_function_uses_pic_offset_table
= 1;
2843 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2845 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2849 else if (GET_CODE (orig
) == CONST
)
2853 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2854 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2862 reg
= gen_reg_rtx (Pmode
);
2865 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2867 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2868 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2869 base
== reg
? 0 : reg
);
2874 if (GET_CODE (offset
) == CONST_INT
)
2876 /* The base register doesn't really matter, we only want to
2877 test the index for the appropriate mode. */
2878 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
2880 if (!no_new_pseudos
)
2881 offset
= force_reg (Pmode
, offset
);
2886 if (GET_CODE (offset
) == CONST_INT
)
2887 return plus_constant (base
, INTVAL (offset
));
2890 if (GET_MODE_SIZE (mode
) > 4
2891 && (GET_MODE_CLASS (mode
) == MODE_INT
2892 || TARGET_SOFT_FLOAT
))
2894 emit_insn (gen_addsi3 (reg
, base
, offset
));
2898 return gen_rtx_PLUS (Pmode
, base
, offset
);
2904 /* Generate code to load the PIC register. PROLOGUE is true if
2905 called from arm_expand_prologue (in which case we want the
2906 generated insns at the start of the function); false if called
2907 by an exception receiver that needs the PIC register reloaded
2908 (in which case the insns are just dumped at the current location). */
2910 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2912 #ifndef AOF_ASSEMBLER
2913 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2914 rtx global_offset_table
;
2916 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2923 l1
= gen_label_rtx ();
2925 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2926 /* On the ARM the PC register contains 'dot + 8' at the time of the
2927 addition, on the Thumb it is 'dot + 4'. */
2928 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2930 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2931 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2933 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2935 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2939 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2940 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2944 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2945 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2951 emit_insn_after (seq
, get_insns ());
2955 /* Need to emit this whether or not we obey regdecls,
2956 since setjmp/longjmp can cause life info to screw up. */
2957 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2958 #endif /* AOF_ASSEMBLER */
2961 /* Return nonzero if X is valid as an ARM state addressing register. */
2963 arm_address_register_rtx_p (rtx x
, int strict_p
)
2967 if (GET_CODE (x
) != REG
)
2973 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2975 return (regno
<= LAST_ARM_REGNUM
2976 || regno
>= FIRST_PSEUDO_REGISTER
2977 || regno
== FRAME_POINTER_REGNUM
2978 || regno
== ARG_POINTER_REGNUM
);
2981 /* Return nonzero if X is a valid ARM state address operand. */
2983 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
2987 enum rtx_code code
= GET_CODE (x
);
2989 if (arm_address_register_rtx_p (x
, strict_p
))
2992 use_ldrd
= (TARGET_LDRD
2994 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
2996 if (code
== POST_INC
|| code
== PRE_DEC
2997 || ((code
== PRE_INC
|| code
== POST_DEC
)
2998 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
2999 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3001 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3002 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3003 && GET_CODE (XEXP (x
, 1)) == PLUS
3004 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3006 rtx addend
= XEXP (XEXP (x
, 1), 1);
3008 /* Don't allow ldrd post increment by register becuase it's hard
3009 to fixup invalid register choices. */
3011 && GET_CODE (x
) == POST_MODIFY
3012 && GET_CODE (addend
) == REG
)
3015 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3016 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3019 /* After reload constants split into minipools will have addresses
3020 from a LABEL_REF. */
3021 else if (reload_completed
3022 && (code
== LABEL_REF
3024 && GET_CODE (XEXP (x
, 0)) == PLUS
3025 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3026 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3029 else if (mode
== TImode
)
3032 else if (code
== PLUS
)
3034 rtx xop0
= XEXP (x
, 0);
3035 rtx xop1
= XEXP (x
, 1);
3037 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3038 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3039 || (arm_address_register_rtx_p (xop1
, strict_p
)
3040 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3044 /* Reload currently can't handle MINUS, so disable this for now */
3045 else if (GET_CODE (x
) == MINUS
)
3047 rtx xop0
= XEXP (x
, 0);
3048 rtx xop1
= XEXP (x
, 1);
3050 return (arm_address_register_rtx_p (xop0
, strict_p
)
3051 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3055 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3056 && code
== SYMBOL_REF
3057 && CONSTANT_POOL_ADDRESS_P (x
)
3059 && symbol_mentioned_p (get_pool_constant (x
))))
3065 /* Return nonzero if INDEX is valid for an address index operand in
3068 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3071 HOST_WIDE_INT range
;
3072 enum rtx_code code
= GET_CODE (index
);
3074 /* Standard coprocessor addressing modes. */
3075 if (TARGET_HARD_FLOAT
3076 && (TARGET_FPA
|| TARGET_MAVERICK
)
3077 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3078 || (TARGET_MAVERICK
&& mode
== DImode
)))
3079 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3080 && INTVAL (index
) > -1024
3081 && (INTVAL (index
) & 3) == 0);
3083 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3084 return (code
== CONST_INT
3085 && INTVAL (index
) < 1024
3086 && INTVAL (index
) > -1024
3087 && (INTVAL (index
) & 3) == 0);
3089 if (arm_address_register_rtx_p (index
, strict_p
)
3090 && (GET_MODE_SIZE (mode
) <= 4))
3093 if (mode
== DImode
|| mode
== DFmode
)
3095 if (code
== CONST_INT
)
3097 HOST_WIDE_INT val
= INTVAL (index
);
3100 return val
> -256 && val
< 256;
3102 return val
== 4 || val
== -4 || val
== -8;
3105 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3108 if (GET_MODE_SIZE (mode
) <= 4
3111 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3115 rtx xiop0
= XEXP (index
, 0);
3116 rtx xiop1
= XEXP (index
, 1);
3118 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3119 && power_of_two_operand (xiop1
, SImode
))
3120 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3121 && power_of_two_operand (xiop0
, SImode
)));
3123 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3124 || code
== ASHIFT
|| code
== ROTATERT
)
3126 rtx op
= XEXP (index
, 1);
3128 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3129 && GET_CODE (op
) == CONST_INT
3131 && INTVAL (op
) <= 31);
3135 /* For ARM v4 we may be doing a sign-extend operation during the
3139 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3145 range
= (mode
== HImode
) ? 4095 : 4096;
3147 return (code
== CONST_INT
3148 && INTVAL (index
) < range
3149 && INTVAL (index
) > -range
);
3152 /* Return nonzero if X is valid as a Thumb state base register. */
3154 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3158 if (GET_CODE (x
) != REG
)
3164 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3166 return (regno
<= LAST_LO_REGNUM
3167 || regno
> LAST_VIRTUAL_REGISTER
3168 || regno
== FRAME_POINTER_REGNUM
3169 || (GET_MODE_SIZE (mode
) >= 4
3170 && (regno
== STACK_POINTER_REGNUM
3171 || regno
>= FIRST_PSEUDO_REGISTER
3172 || x
== hard_frame_pointer_rtx
3173 || x
== arg_pointer_rtx
)));
3176 /* Return nonzero if x is a legitimate index register. This is the case
3177 for any base register that can access a QImode object. */
3179 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3181 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3184 /* Return nonzero if x is a legitimate Thumb-state address.
3186 The AP may be eliminated to either the SP or the FP, so we use the
3187 least common denominator, e.g. SImode, and offsets from 0 to 64.
3189 ??? Verify whether the above is the right approach.
3191 ??? Also, the FP may be eliminated to the SP, so perhaps that
3192 needs special handling also.
3194 ??? Look at how the mips16 port solves this problem. It probably uses
3195 better ways to solve some of these problems.
3197 Although it is not incorrect, we don't accept QImode and HImode
3198 addresses based on the frame pointer or arg pointer until the
3199 reload pass starts. This is so that eliminating such addresses
3200 into stack based ones won't produce impossible code. */
3202 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3204 /* ??? Not clear if this is right. Experiment. */
3205 if (GET_MODE_SIZE (mode
) < 4
3206 && !(reload_in_progress
|| reload_completed
)
3207 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3208 || reg_mentioned_p (arg_pointer_rtx
, x
)
3209 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3210 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3211 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3212 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3215 /* Accept any base register. SP only in SImode or larger. */
3216 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3219 /* This is PC relative data before arm_reorg runs. */
3220 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3221 && GET_CODE (x
) == SYMBOL_REF
3222 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3225 /* This is PC relative data after arm_reorg runs. */
3226 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3227 && (GET_CODE (x
) == LABEL_REF
3228 || (GET_CODE (x
) == CONST
3229 && GET_CODE (XEXP (x
, 0)) == PLUS
3230 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3231 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3234 /* Post-inc indexing only supported for SImode and larger. */
3235 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3236 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3239 else if (GET_CODE (x
) == PLUS
)
3241 /* REG+REG address can be any two index registers. */
3242 /* We disallow FRAME+REG addressing since we know that FRAME
3243 will be replaced with STACK, and SP relative addressing only
3244 permits SP+OFFSET. */
3245 if (GET_MODE_SIZE (mode
) <= 4
3246 && XEXP (x
, 0) != frame_pointer_rtx
3247 && XEXP (x
, 1) != frame_pointer_rtx
3248 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3249 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3252 /* REG+const has 5-7 bit offset for non-SP registers. */
3253 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3254 || XEXP (x
, 0) == arg_pointer_rtx
)
3255 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3256 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3259 /* REG+const has 10 bit offset for SP, but only SImode and
3260 larger is supported. */
3261 /* ??? Should probably check for DI/DFmode overflow here
3262 just like GO_IF_LEGITIMATE_OFFSET does. */
3263 else if (GET_CODE (XEXP (x
, 0)) == REG
3264 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3265 && GET_MODE_SIZE (mode
) >= 4
3266 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3267 && INTVAL (XEXP (x
, 1)) >= 0
3268 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3269 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3272 else if (GET_CODE (XEXP (x
, 0)) == REG
3273 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3274 && GET_MODE_SIZE (mode
) >= 4
3275 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3276 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3280 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3281 && GET_MODE_SIZE (mode
) == 4
3282 && GET_CODE (x
) == SYMBOL_REF
3283 && CONSTANT_POOL_ADDRESS_P (x
)
3285 && symbol_mentioned_p (get_pool_constant (x
))))
3291 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3292 instruction of mode MODE. */
3294 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3296 switch (GET_MODE_SIZE (mode
))
3299 return val
>= 0 && val
< 32;
3302 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3306 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3311 /* Try machine-dependent ways of modifying an illegitimate address
3312 to be legitimate. If we find one, return the new, valid address. */
3314 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3316 if (GET_CODE (x
) == PLUS
)
3318 rtx xop0
= XEXP (x
, 0);
3319 rtx xop1
= XEXP (x
, 1);
3321 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3322 xop0
= force_reg (SImode
, xop0
);
3324 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3325 xop1
= force_reg (SImode
, xop1
);
3327 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3328 && GET_CODE (xop1
) == CONST_INT
)
3330 HOST_WIDE_INT n
, low_n
;
3334 /* VFP addressing modes actually allow greater offsets, but for
3335 now we just stick with the lowest common denominator. */
3337 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3349 low_n
= ((mode
) == TImode
? 0
3350 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3354 base_reg
= gen_reg_rtx (SImode
);
3355 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3356 GEN_INT (n
)), NULL_RTX
);
3357 emit_move_insn (base_reg
, val
);
3358 x
= (low_n
== 0 ? base_reg
3359 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3361 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3362 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3365 /* XXX We don't allow MINUS any more -- see comment in
3366 arm_legitimate_address_p (). */
3367 else if (GET_CODE (x
) == MINUS
)
3369 rtx xop0
= XEXP (x
, 0);
3370 rtx xop1
= XEXP (x
, 1);
3372 if (CONSTANT_P (xop0
))
3373 xop0
= force_reg (SImode
, xop0
);
3375 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3376 xop1
= force_reg (SImode
, xop1
);
3378 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3379 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3384 /* We need to find and carefully transform any SYMBOL and LABEL
3385 references; so go back to the original address expression. */
3386 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3388 if (new_x
!= orig_x
)
3396 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3397 to be legitimate. If we find one, return the new, valid address. */
3399 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3401 if (GET_CODE (x
) == PLUS
3402 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3403 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3404 || INTVAL (XEXP (x
, 1)) < 0))
3406 rtx xop0
= XEXP (x
, 0);
3407 rtx xop1
= XEXP (x
, 1);
3408 HOST_WIDE_INT offset
= INTVAL (xop1
);
3410 /* Try and fold the offset into a biasing of the base register and
3411 then offsetting that. Don't do this when optimizing for space
3412 since it can cause too many CSEs. */
3413 if (optimize_size
&& offset
>= 0
3414 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3416 HOST_WIDE_INT delta
;
3419 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3420 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3421 delta
= 31 * GET_MODE_SIZE (mode
);
3423 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3425 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3427 x
= plus_constant (xop0
, delta
);
3429 else if (offset
< 0 && offset
> -256)
3430 /* Small negative offsets are best done with a subtract before the
3431 dereference, forcing these into a register normally takes two
3433 x
= force_operand (x
, NULL_RTX
);
3436 /* For the remaining cases, force the constant into a register. */
3437 xop1
= force_reg (SImode
, xop1
);
3438 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3441 else if (GET_CODE (x
) == PLUS
3442 && s_register_operand (XEXP (x
, 1), SImode
)
3443 && !s_register_operand (XEXP (x
, 0), SImode
))
3445 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3447 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3452 /* We need to find and carefully transform any SYMBOL and LABEL
3453 references; so go back to the original address expression. */
3454 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3456 if (new_x
!= orig_x
)
3465 #define REG_OR_SUBREG_REG(X) \
3466 (GET_CODE (X) == REG \
3467 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3469 #define REG_OR_SUBREG_RTX(X) \
3470 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3472 #ifndef COSTS_N_INSNS
3473 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3476 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3478 enum machine_mode mode
= GET_MODE (x
);
3491 return COSTS_N_INSNS (1);
3494 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3497 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3504 return COSTS_N_INSNS (2) + cycles
;
3506 return COSTS_N_INSNS (1) + 16;
3509 return (COSTS_N_INSNS (1)
3510 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3511 + GET_CODE (SET_DEST (x
)) == MEM
));
3516 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3518 if (thumb_shiftable_const (INTVAL (x
)))
3519 return COSTS_N_INSNS (2);
3520 return COSTS_N_INSNS (3);
3522 else if ((outer
== PLUS
|| outer
== COMPARE
)
3523 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3525 else if (outer
== AND
3526 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3527 return COSTS_N_INSNS (1);
3528 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3529 || outer
== LSHIFTRT
)
3531 return COSTS_N_INSNS (2);
3537 return COSTS_N_INSNS (3);
3556 /* XXX another guess. */
3557 /* Memory costs quite a lot for the first word, but subsequent words
3558 load at the equivalent of a single insn each. */
3559 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3560 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3565 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3570 /* XXX still guessing. */
3571 switch (GET_MODE (XEXP (x
, 0)))
3574 return (1 + (mode
== DImode
? 4 : 0)
3575 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3578 return (4 + (mode
== DImode
? 4 : 0)
3579 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3582 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3594 /* Worker routine for arm_rtx_costs. */
3596 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3598 enum machine_mode mode
= GET_MODE (x
);
3599 enum rtx_code subcode
;
3605 /* Memory costs quite a lot for the first word, but subsequent words
3606 load at the equivalent of a single insn each. */
3607 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3608 + (GET_CODE (x
) == SYMBOL_REF
3609 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3615 return optimize_size
? COSTS_N_INSNS (2) : 100;
3618 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3625 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3627 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3628 + ((GET_CODE (XEXP (x
, 0)) == REG
3629 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3630 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3632 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3633 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3634 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3636 + ((GET_CODE (XEXP (x
, 1)) == REG
3637 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3638 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3639 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3644 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3645 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3646 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3647 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3650 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3651 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3652 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3653 && arm_const_double_rtx (XEXP (x
, 1))))
3655 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3656 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3657 && arm_const_double_rtx (XEXP (x
, 0))))
3660 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3661 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3662 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3663 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3664 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3665 || subcode
== ROTATE
|| subcode
== ROTATERT
3667 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3668 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3669 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3670 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3671 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3672 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3673 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3678 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3679 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3680 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3681 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3682 && arm_const_double_rtx (XEXP (x
, 1))))
3686 case AND
: case XOR
: case IOR
:
3689 /* Normally the frame registers will be spilt into reg+const during
3690 reload, so it is a bad idea to combine them with other instructions,
3691 since then they might not be moved outside of loops. As a compromise
3692 we allow integration with ops that have a constant as their second
3694 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3695 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3696 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3697 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3698 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3702 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3703 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3704 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3705 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3708 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3709 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3710 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3711 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3712 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3715 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3716 return (1 + extra_cost
3717 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3718 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3719 || subcode
== ROTATE
|| subcode
== ROTATERT
3721 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3722 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3723 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3724 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3725 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3726 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3732 /* This should have been handled by the CPU specific routines. */
3736 if (arm_arch3m
&& mode
== SImode
3737 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3738 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3739 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3740 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3741 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3742 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3747 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3748 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3752 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3754 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3757 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3765 return 4 + (mode
== DImode
? 4 : 0);
3768 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3769 return (4 + (mode
== DImode
? 4 : 0)
3770 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3773 switch (GET_MODE (XEXP (x
, 0)))
3776 return (1 + (mode
== DImode
? 4 : 0)
3777 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3780 return (4 + (mode
== DImode
? 4 : 0)
3781 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3784 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3799 if (const_ok_for_arm (INTVAL (x
)))
3800 return outer
== SET
? 2 : -1;
3801 else if (outer
== AND
3802 && const_ok_for_arm (~INTVAL (x
)))
3804 else if ((outer
== COMPARE
3805 || outer
== PLUS
|| outer
== MINUS
)
3806 && const_ok_for_arm (-INTVAL (x
)))
3817 if (arm_const_double_rtx (x
))
3818 return outer
== SET
? 2 : -1;
3819 else if ((outer
== COMPARE
|| outer
== PLUS
)
3820 && neg_const_double_rtx_ok_for_fpa (x
))
3829 /* RTX costs for cores with a slow MUL implementation. */
3832 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3834 enum machine_mode mode
= GET_MODE (x
);
3838 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3845 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3852 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3854 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3855 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3856 int cost
, const_ok
= const_ok_for_arm (i
);
3857 int j
, booth_unit_size
;
3859 /* Tune as appropriate. */
3860 cost
= const_ok
? 4 : 8;
3861 booth_unit_size
= 2;
3862 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3864 i
>>= booth_unit_size
;
3872 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3873 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3877 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3883 /* RTX cost for cores with a fast multiply unit (M variants). */
3886 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3888 enum machine_mode mode
= GET_MODE (x
);
3892 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3899 /* There is no point basing this on the tuning, since it is always the
3900 fast variant if it exists at all. */
3902 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3903 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3904 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3911 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3918 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3920 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3921 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3922 int cost
, const_ok
= const_ok_for_arm (i
);
3923 int j
, booth_unit_size
;
3925 /* Tune as appropriate. */
3926 cost
= const_ok
? 4 : 8;
3927 booth_unit_size
= 8;
3928 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3930 i
>>= booth_unit_size
;
3938 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3939 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3943 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3949 /* RTX cost for XScale CPUs. */
3952 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3954 enum machine_mode mode
= GET_MODE (x
);
3958 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3965 /* There is no point basing this on the tuning, since it is always the
3966 fast variant if it exists at all. */
3968 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3969 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3970 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3977 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3984 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3986 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3987 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3988 int cost
, const_ok
= const_ok_for_arm (i
);
3989 unsigned HOST_WIDE_INT masked_const
;
3991 /* The cost will be related to two insns.
3992 First a load of the constant (MOV or LDR), then a multiply. */
3995 cost
+= 1; /* LDR is probably more expensive because
3996 of longer result latency. */
3997 masked_const
= i
& 0xffff8000;
3998 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4000 masked_const
= i
& 0xf8000000;
4001 if (masked_const
== 0 || masked_const
== 0xf8000000)
4010 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4011 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4015 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4021 /* RTX costs for 9e (and later) cores. */
4024 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4026 enum machine_mode mode
= GET_MODE (x
);
4035 *total
= COSTS_N_INSNS (3);
4039 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4047 /* There is no point basing this on the tuning, since it is always the
4048 fast variant if it exists at all. */
4050 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4051 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4052 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4059 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4076 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4077 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4081 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4085 /* All address computations that can be done are free, but rtx cost returns
4086 the same for practically all of them. So we weight the different types
4087 of address here in the order (most pref first):
4088 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4090 arm_arm_address_cost (rtx x
)
4092 enum rtx_code c
= GET_CODE (x
);
4094 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4096 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4099 if (c
== PLUS
|| c
== MINUS
)
4101 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4104 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4114 arm_thumb_address_cost (rtx x
)
4116 enum rtx_code c
= GET_CODE (x
);
4121 && GET_CODE (XEXP (x
, 0)) == REG
4122 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4129 arm_address_cost (rtx x
)
4131 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4135 arm_use_dfa_pipeline_interface (void)
4141 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4145 /* Some true dependencies can have a higher cost depending
4146 on precisely how certain input operands are used. */
4148 && REG_NOTE_KIND (link
) == 0
4149 && recog_memoized (insn
) >= 0
4150 && recog_memoized (dep
) >= 0)
4152 int shift_opnum
= get_attr_shift (insn
);
4153 enum attr_type attr_type
= get_attr_type (dep
);
4155 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4156 operand for INSN. If we have a shifted input operand and the
4157 instruction we depend on is another ALU instruction, then we may
4158 have to account for an additional stall. */
4159 if (shift_opnum
!= 0
4160 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4162 rtx shifted_operand
;
4165 /* Get the shifted operand. */
4166 extract_insn (insn
);
4167 shifted_operand
= recog_data
.operand
[shift_opnum
];
4169 /* Iterate over all the operands in DEP. If we write an operand
4170 that overlaps with SHIFTED_OPERAND, then we have increase the
4171 cost of this dependency. */
4173 preprocess_constraints ();
4174 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4176 /* We can ignore strict inputs. */
4177 if (recog_data
.operand_type
[opno
] == OP_IN
)
4180 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4187 /* XXX This is not strictly true for the FPA. */
4188 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4189 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4192 /* Call insns don't incur a stall, even if they follow a load. */
4193 if (REG_NOTE_KIND (link
) == 0
4194 && GET_CODE (insn
) == CALL_INSN
)
4197 if ((i_pat
= single_set (insn
)) != NULL
4198 && GET_CODE (SET_SRC (i_pat
)) == MEM
4199 && (d_pat
= single_set (dep
)) != NULL
4200 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4202 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4203 /* This is a load after a store, there is no conflict if the load reads
4204 from a cached area. Assume that loads from the stack, and from the
4205 constant pool are cached, and that others will miss. This is a
4208 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4209 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4210 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4211 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4218 static int fp_consts_inited
= 0;
4220 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4221 static const char * const strings_fp
[8] =
4224 "4", "5", "0.5", "10"
4227 static REAL_VALUE_TYPE values_fp
[8];
4230 init_fp_table (void)
4236 fp_consts_inited
= 1;
4238 fp_consts_inited
= 8;
4240 for (i
= 0; i
< fp_consts_inited
; i
++)
4242 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4247 /* Return TRUE if rtx X is a valid immediate FP constant. */
4249 arm_const_double_rtx (rtx x
)
4254 if (!fp_consts_inited
)
4257 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4258 if (REAL_VALUE_MINUS_ZERO (r
))
4261 for (i
= 0; i
< fp_consts_inited
; i
++)
4262 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4268 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4270 neg_const_double_rtx_ok_for_fpa (rtx x
)
4275 if (!fp_consts_inited
)
4278 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4279 r
= REAL_VALUE_NEGATE (r
);
4280 if (REAL_VALUE_MINUS_ZERO (r
))
4283 for (i
= 0; i
< 8; i
++)
4284 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4290 /* Predicates for `match_operand' and `match_operator'. */
4292 /* s_register_operand is the same as register_operand, but it doesn't accept
4295 This function exists because at the time it was put in it led to better
4296 code. SUBREG(MEM) always needs a reload in the places where
4297 s_register_operand is used, and this seemed to lead to excessive
4300 s_register_operand (rtx op
, enum machine_mode mode
)
4302 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4305 if (GET_CODE (op
) == SUBREG
)
4306 op
= SUBREG_REG (op
);
4308 /* We don't consider registers whose class is NO_REGS
4309 to be a register operand. */
4310 /* XXX might have to check for lo regs only for thumb ??? */
4311 return (GET_CODE (op
) == REG
4312 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4313 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4316 /* A hard register operand (even before reload. */
4318 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
4320 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4323 return (GET_CODE (op
) == REG
4324 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
4327 /* An arm register operand. */
4329 arm_general_register_operand (rtx op
, enum machine_mode mode
)
4331 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4334 if (GET_CODE (op
) == SUBREG
)
4335 op
= SUBREG_REG (op
);
4337 return (GET_CODE (op
) == REG
4338 && (REGNO (op
) <= LAST_ARM_REGNUM
4339 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
4342 /* Only accept reg, subreg(reg), const_int. */
4344 reg_or_int_operand (rtx op
, enum machine_mode mode
)
4346 if (GET_CODE (op
) == CONST_INT
)
4349 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4352 if (GET_CODE (op
) == SUBREG
)
4353 op
= SUBREG_REG (op
);
4355 /* We don't consider registers whose class is NO_REGS
4356 to be a register operand. */
4357 return (GET_CODE (op
) == REG
4358 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4359 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4362 /* Return 1 if OP is an item in memory, given that we are in reload. */
4364 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4366 int regno
= true_regnum (op
);
4368 return (!CONSTANT_P (op
)
4370 || (GET_CODE (op
) == REG
4371 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
4374 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4376 arm_rhs_operand (rtx op
, enum machine_mode mode
)
4378 return (s_register_operand (op
, mode
)
4379 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
4382 /* Return TRUE for valid operands for the
4383 rhs of an ARM instruction, or a load. */
4385 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
4387 return (s_register_operand (op
, mode
)
4388 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
4389 || memory_operand (op
, mode
));
4392 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4393 constant that is valid when negated. */
4395 arm_add_operand (rtx op
, enum machine_mode mode
)
4398 return thumb_cmp_operand (op
, mode
);
4400 return (s_register_operand (op
, mode
)
4401 || (GET_CODE (op
) == CONST_INT
4402 && (const_ok_for_arm (INTVAL (op
))
4403 || const_ok_for_arm (-INTVAL (op
)))));
4406 /* Return TRUE for valid ARM constants (or when valid if negated). */
4408 arm_addimm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4410 return (GET_CODE (op
) == CONST_INT
4411 && (const_ok_for_arm (INTVAL (op
))
4412 || const_ok_for_arm (-INTVAL (op
))));
4416 arm_not_operand (rtx op
, enum machine_mode mode
)
4418 return (s_register_operand (op
, mode
)
4419 || (GET_CODE (op
) == CONST_INT
4420 && (const_ok_for_arm (INTVAL (op
))
4421 || const_ok_for_arm (~INTVAL (op
)))));
4424 /* Return TRUE if the operand is a memory reference which contains an
4425 offsettable address. */
4427 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
4429 if (mode
== VOIDmode
)
4430 mode
= GET_MODE (op
);
4432 return (mode
== GET_MODE (op
)
4433 && GET_CODE (op
) == MEM
4434 && offsettable_address_p (reload_completed
| reload_in_progress
,
4435 mode
, XEXP (op
, 0)));
4438 /* Return TRUE if the operand is a memory reference which is, or can be
4439 made word aligned by adjusting the offset. */
4441 alignable_memory_operand (rtx op
, enum machine_mode mode
)
4445 if (mode
== VOIDmode
)
4446 mode
= GET_MODE (op
);
4448 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
4453 return ((GET_CODE (reg
= op
) == REG
4454 || (GET_CODE (op
) == SUBREG
4455 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
4456 || (GET_CODE (op
) == PLUS
4457 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4458 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
4459 || (GET_CODE (XEXP (op
, 0)) == SUBREG
4460 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
4461 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
4464 /* Similar to s_register_operand, but does not allow hard integer
4467 f_register_operand (rtx op
, enum machine_mode mode
)
4469 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4472 if (GET_CODE (op
) == SUBREG
)
4473 op
= SUBREG_REG (op
);
4475 /* We don't consider registers whose class is NO_REGS
4476 to be a register operand. */
4477 return (GET_CODE (op
) == REG
4478 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4479 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
4482 /* Return TRUE for valid operands for the rhs of an floating point insns.
4483 Allows regs or certain consts on FPA, just regs for everything else. */
4485 arm_float_rhs_operand (rtx op
, enum machine_mode mode
)
4487 if (s_register_operand (op
, mode
))
4490 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4493 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4494 return arm_const_double_rtx (op
);
4500 arm_float_add_operand (rtx op
, enum machine_mode mode
)
4502 if (s_register_operand (op
, mode
))
4505 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4508 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4509 return (arm_const_double_rtx (op
)
4510 || neg_const_double_rtx_ok_for_fpa (op
));
4516 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4517 Depends which fpu we are targeting. */
4520 arm_float_compare_operand (rtx op
, enum machine_mode mode
)
4523 return vfp_compare_operand (op
, mode
);
4525 return arm_float_rhs_operand (op
, mode
);
4529 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4531 cirrus_memory_offset (rtx op
)
4533 /* Reject eliminable registers. */
4534 if (! (reload_in_progress
|| reload_completed
)
4535 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4536 || reg_mentioned_p (arg_pointer_rtx
, op
)
4537 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4538 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4539 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4540 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4543 if (GET_CODE (op
) == MEM
)
4549 /* Match: (mem (reg)). */
4550 if (GET_CODE (ind
) == REG
)
4556 if (GET_CODE (ind
) == PLUS
4557 && GET_CODE (XEXP (ind
, 0)) == REG
4558 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4559 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4567 arm_extendqisi_mem_op (rtx op
, enum machine_mode mode
)
4569 if (!memory_operand (op
, mode
))
4572 return arm_legitimate_address_p (mode
, XEXP (op
, 0), SIGN_EXTEND
, 0);
4575 /* Return nonzero if OP is a Cirrus or general register. */
4577 cirrus_register_operand (rtx op
, enum machine_mode mode
)
4579 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4582 if (GET_CODE (op
) == SUBREG
)
4583 op
= SUBREG_REG (op
);
4585 return (GET_CODE (op
) == REG
4586 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
4587 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
4590 /* Return nonzero if OP is a cirrus FP register. */
4592 cirrus_fp_register (rtx op
, enum machine_mode mode
)
4594 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4597 if (GET_CODE (op
) == SUBREG
)
4598 op
= SUBREG_REG (op
);
4600 return (GET_CODE (op
) == REG
4601 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4602 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
4605 /* Return nonzero if OP is a 6bit constant (0..63). */
4607 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4609 return (GET_CODE (op
) == CONST_INT
4611 && INTVAL (op
) < 64);
4615 /* Return TRUE if OP is a valid VFP memory address pattern.
4616 WB if true if writeback address modes are allowed. */
4619 arm_coproc_mem_operand (rtx op
, bool wb
)
4623 /* Reject eliminable registers. */
4624 if (! (reload_in_progress
|| reload_completed
)
4625 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4626 || reg_mentioned_p (arg_pointer_rtx
, op
)
4627 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4628 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4629 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4630 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4633 /* Constants are converted into offsets from labels. */
4634 if (GET_CODE (op
) != MEM
)
4639 if (reload_completed
4640 && (GET_CODE (ind
) == LABEL_REF
4641 || (GET_CODE (ind
) == CONST
4642 && GET_CODE (XEXP (ind
, 0)) == PLUS
4643 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4644 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4647 /* Match: (mem (reg)). */
4648 if (GET_CODE (ind
) == REG
)
4649 return arm_address_register_rtx_p (ind
, 0);
4651 /* Autoincremment addressing modes. */
4653 && (GET_CODE (ind
) == PRE_INC
4654 || GET_CODE (ind
) == POST_INC
4655 || GET_CODE (ind
) == PRE_DEC
4656 || GET_CODE (ind
) == POST_DEC
))
4657 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4660 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4661 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4662 && GET_CODE (XEXP (ind
, 1)) == PLUS
4663 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4664 ind
= XEXP (ind
, 1);
4669 if (GET_CODE (ind
) == PLUS
4670 && GET_CODE (XEXP (ind
, 0)) == REG
4671 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4672 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4673 && INTVAL (XEXP (ind
, 1)) > -1024
4674 && INTVAL (XEXP (ind
, 1)) < 1024
4675 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4682 /* Return TRUE if OP is a REG or constant zero. */
4684 vfp_compare_operand (rtx op
, enum machine_mode mode
)
4686 if (s_register_operand (op
, mode
))
4689 return (GET_CODE (op
) == CONST_DOUBLE
4690 && arm_const_double_rtx (op
));
4694 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4695 VFP registers. Otherwise return NO_REGS. */
4698 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
4700 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
4703 return GENERAL_REGS
;
4707 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4708 Use by the Cirrus Maverick code which has to workaround
4709 a hardware bug triggered by such instructions. */
4711 arm_memory_load_p (rtx insn
)
4713 rtx body
, lhs
, rhs
;;
4715 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4718 body
= PATTERN (insn
);
4720 if (GET_CODE (body
) != SET
)
4723 lhs
= XEXP (body
, 0);
4724 rhs
= XEXP (body
, 1);
4726 lhs
= REG_OR_SUBREG_RTX (lhs
);
4728 /* If the destination is not a general purpose
4729 register we do not have to worry. */
4730 if (GET_CODE (lhs
) != REG
4731 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4734 /* As well as loads from memory we also have to react
4735 to loads of invalid constants which will be turned
4736 into loads from the minipool. */
4737 return (GET_CODE (rhs
) == MEM
4738 || GET_CODE (rhs
) == SYMBOL_REF
4739 || note_invalid_constants (insn
, -1, false));
4742 /* Return TRUE if INSN is a Cirrus instruction. */
4744 arm_cirrus_insn_p (rtx insn
)
4746 enum attr_cirrus attr
;
4748 /* get_attr aborts on USE and CLOBBER. */
4750 || GET_CODE (insn
) != INSN
4751 || GET_CODE (PATTERN (insn
)) == USE
4752 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4755 attr
= get_attr_cirrus (insn
);
4757 return attr
!= CIRRUS_NOT
;
4760 /* Cirrus reorg for invalid instruction combinations. */
4762 cirrus_reorg (rtx first
)
4764 enum attr_cirrus attr
;
4765 rtx body
= PATTERN (first
);
4769 /* Any branch must be followed by 2 non Cirrus instructions. */
4770 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4773 t
= next_nonnote_insn (first
);
4775 if (arm_cirrus_insn_p (t
))
4778 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4782 emit_insn_after (gen_nop (), first
);
4787 /* (float (blah)) is in parallel with a clobber. */
4788 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4789 body
= XVECEXP (body
, 0, 0);
4791 if (GET_CODE (body
) == SET
)
4793 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4795 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4796 be followed by a non Cirrus insn. */
4797 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4799 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4800 emit_insn_after (gen_nop (), first
);
4804 else if (arm_memory_load_p (first
))
4806 unsigned int arm_regno
;
4808 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4809 ldr/cfmv64hr combination where the Rd field is the same
4810 in both instructions must be split with a non Cirrus
4817 /* Get Arm register number for ldr insn. */
4818 if (GET_CODE (lhs
) == REG
)
4819 arm_regno
= REGNO (lhs
);
4820 else if (GET_CODE (rhs
) == REG
)
4821 arm_regno
= REGNO (rhs
);
4826 first
= next_nonnote_insn (first
);
4828 if (! arm_cirrus_insn_p (first
))
4831 body
= PATTERN (first
);
4833 /* (float (blah)) is in parallel with a clobber. */
4834 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4835 body
= XVECEXP (body
, 0, 0);
4837 if (GET_CODE (body
) == FLOAT
)
4838 body
= XEXP (body
, 0);
4840 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4841 && GET_CODE (XEXP (body
, 1)) == REG
4842 && arm_regno
== REGNO (XEXP (body
, 1)))
4843 emit_insn_after (gen_nop (), first
);
4849 /* get_attr aborts on USE and CLOBBER. */
4851 || GET_CODE (first
) != INSN
4852 || GET_CODE (PATTERN (first
)) == USE
4853 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4856 attr
= get_attr_cirrus (first
);
4858 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4859 must be followed by a non-coprocessor instruction. */
4860 if (attr
== CIRRUS_COMPARE
)
4864 t
= next_nonnote_insn (first
);
4866 if (arm_cirrus_insn_p (t
))
4869 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4873 emit_insn_after (gen_nop (), first
);
4879 /* Return nonzero if OP is a constant power of two. */
4881 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4883 if (GET_CODE (op
) == CONST_INT
)
4885 HOST_WIDE_INT value
= INTVAL (op
);
4887 return value
!= 0 && (value
& (value
- 1)) == 0;
4893 /* Return TRUE for a valid operand of a DImode operation.
4894 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4895 Note that this disallows MEM(REG+REG), but allows
4896 MEM(PRE/POST_INC/DEC(REG)). */
4898 di_operand (rtx op
, enum machine_mode mode
)
4900 if (s_register_operand (op
, mode
))
4903 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4906 if (GET_CODE (op
) == SUBREG
)
4907 op
= SUBREG_REG (op
);
4909 switch (GET_CODE (op
))
4916 return memory_address_p (DImode
, XEXP (op
, 0));
4923 /* Like di_operand, but don't accept constants. */
4925 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4927 if (s_register_operand (op
, mode
))
4930 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4933 if (GET_CODE (op
) == SUBREG
)
4934 op
= SUBREG_REG (op
);
4936 if (GET_CODE (op
) == MEM
)
4937 return memory_address_p (DImode
, XEXP (op
, 0));
4942 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4943 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4944 Note that this disallows MEM(REG+REG), but allows
4945 MEM(PRE/POST_INC/DEC(REG)). */
4947 soft_df_operand (rtx op
, enum machine_mode mode
)
4949 if (s_register_operand (op
, mode
))
4952 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4955 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4958 if (GET_CODE (op
) == SUBREG
)
4959 op
= SUBREG_REG (op
);
4961 switch (GET_CODE (op
))
4967 return memory_address_p (DFmode
, XEXP (op
, 0));
4974 /* Like soft_df_operand, but don't accept constants. */
4976 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
4978 if (s_register_operand (op
, mode
))
4981 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4984 if (GET_CODE (op
) == SUBREG
)
4985 op
= SUBREG_REG (op
);
4987 if (GET_CODE (op
) == MEM
)
4988 return memory_address_p (DFmode
, XEXP (op
, 0));
4992 /* Return TRUE for valid index operands. */
4994 index_operand (rtx op
, enum machine_mode mode
)
4996 return (s_register_operand (op
, mode
)
4997 || (immediate_operand (op
, mode
)
4998 && (GET_CODE (op
) != CONST_INT
4999 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
5002 /* Return TRUE for valid shifts by a constant. This also accepts any
5003 power of two on the (somewhat overly relaxed) assumption that the
5004 shift operator in this case was a mult. */
5006 const_shift_operand (rtx op
, enum machine_mode mode
)
5008 return (power_of_two_operand (op
, mode
)
5009 || (immediate_operand (op
, mode
)
5010 && (GET_CODE (op
) != CONST_INT
5011 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
5014 /* Return TRUE for arithmetic operators which can be combined with a multiply
5017 shiftable_operator (rtx x
, enum machine_mode mode
)
5021 if (GET_MODE (x
) != mode
)
5024 code
= GET_CODE (x
);
5026 return (code
== PLUS
|| code
== MINUS
5027 || code
== IOR
|| code
== XOR
|| code
== AND
);
5030 /* Return TRUE for binary logical operators. */
5032 logical_binary_operator (rtx x
, enum machine_mode mode
)
5036 if (GET_MODE (x
) != mode
)
5039 code
= GET_CODE (x
);
5041 return (code
== IOR
|| code
== XOR
|| code
== AND
);
5044 /* Return TRUE for shift operators. */
5046 shift_operator (rtx x
,enum machine_mode mode
)
5050 if (GET_MODE (x
) != mode
)
5053 code
= GET_CODE (x
);
5056 return power_of_two_operand (XEXP (x
, 1), mode
);
5058 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
5059 || code
== ROTATERT
);
5062 /* Return TRUE if x is EQ or NE. */
5064 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5066 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
5069 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5071 arm_comparison_operator (rtx x
, enum machine_mode mode
)
5073 return (comparison_operator (x
, mode
)
5074 && GET_CODE (x
) != LTGT
5075 && GET_CODE (x
) != UNEQ
);
5078 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5080 minmax_operator (rtx x
, enum machine_mode mode
)
5082 enum rtx_code code
= GET_CODE (x
);
5084 if (GET_MODE (x
) != mode
)
5087 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
5090 /* Return TRUE if this is the condition code register, if we aren't given
5091 a mode, accept any class CCmode register. */
5093 cc_register (rtx x
, enum machine_mode mode
)
5095 if (mode
== VOIDmode
)
5097 mode
= GET_MODE (x
);
5099 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5103 if ( GET_MODE (x
) == mode
5104 && GET_CODE (x
) == REG
5105 && REGNO (x
) == CC_REGNUM
)
5111 /* Return TRUE if this is the condition code register, if we aren't given
5112 a mode, accept any class CCmode register which indicates a dominance
5115 dominant_cc_register (rtx x
, enum machine_mode mode
)
5117 if (mode
== VOIDmode
)
5119 mode
= GET_MODE (x
);
5121 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5125 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
5126 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
5127 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
5128 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
5129 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
5132 return cc_register (x
, mode
);
5135 /* Return TRUE if X references a SYMBOL_REF. */
5137 symbol_mentioned_p (rtx x
)
5142 if (GET_CODE (x
) == SYMBOL_REF
)
5145 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5147 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5153 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5154 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5157 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5164 /* Return TRUE if X references a LABEL_REF. */
5166 label_mentioned_p (rtx x
)
5171 if (GET_CODE (x
) == LABEL_REF
)
5174 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5175 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5181 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5182 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5185 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5195 enum rtx_code code
= GET_CODE (x
);
5199 else if (code
== SMIN
)
5201 else if (code
== UMIN
)
5203 else if (code
== UMAX
)
5209 /* Return 1 if memory locations are adjacent. */
5211 adjacent_mem_locations (rtx a
, rtx b
)
5213 if ((GET_CODE (XEXP (a
, 0)) == REG
5214 || (GET_CODE (XEXP (a
, 0)) == PLUS
5215 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5216 && (GET_CODE (XEXP (b
, 0)) == REG
5217 || (GET_CODE (XEXP (b
, 0)) == PLUS
5218 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5220 int val0
= 0, val1
= 0;
5223 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5225 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
5226 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5229 reg0
= REGNO (XEXP (a
, 0));
5231 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5233 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
5234 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5237 reg1
= REGNO (XEXP (b
, 0));
5239 /* Don't accept any offset that will require multiple
5240 instructions to handle, since this would cause the
5241 arith_adjacentmem pattern to output an overlong sequence. */
5242 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5245 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
5250 /* Return 1 if OP is a load multiple operation. It is known to be
5251 parallel and the first section will be tested. */
5253 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5255 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5258 HOST_WIDE_INT i
= 1, base
= 0;
5262 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5265 /* Check to see if this might be a write-back. */
5266 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5271 /* Now check it more carefully. */
5272 if (GET_CODE (SET_DEST (elt
)) != REG
5273 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5274 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5275 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5279 /* Perform a quick check so we don't blow up below. */
5281 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5282 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
5283 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
5286 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
5287 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
5289 for (; i
< count
; i
++)
5291 elt
= XVECEXP (op
, 0, i
);
5293 if (GET_CODE (elt
) != SET
5294 || GET_CODE (SET_DEST (elt
)) != REG
5295 || GET_MODE (SET_DEST (elt
)) != SImode
5296 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
5297 || GET_CODE (SET_SRC (elt
)) != MEM
5298 || GET_MODE (SET_SRC (elt
)) != SImode
5299 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
5300 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
5301 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
5302 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
5309 /* Return 1 if OP is a store multiple operation. It is known to be
5310 parallel and the first section will be tested. */
5312 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5314 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5317 HOST_WIDE_INT i
= 1, base
= 0;
5321 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5324 /* Check to see if this might be a write-back. */
5325 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5330 /* Now check it more carefully. */
5331 if (GET_CODE (SET_DEST (elt
)) != REG
5332 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5333 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5334 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5338 /* Perform a quick check so we don't blow up below. */
5340 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5341 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
5342 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
5345 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
5346 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
5348 for (; i
< count
; i
++)
5350 elt
= XVECEXP (op
, 0, i
);
5352 if (GET_CODE (elt
) != SET
5353 || GET_CODE (SET_SRC (elt
)) != REG
5354 || GET_MODE (SET_SRC (elt
)) != SImode
5355 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
5356 || GET_CODE (SET_DEST (elt
)) != MEM
5357 || GET_MODE (SET_DEST (elt
)) != SImode
5358 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
5359 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
5360 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
5361 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
5369 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5370 HOST_WIDE_INT
*load_offset
)
5372 int unsorted_regs
[4];
5373 HOST_WIDE_INT unsorted_offsets
[4];
5378 /* Can only handle 2, 3, or 4 insns at present,
5379 though could be easily extended if required. */
5380 if (nops
< 2 || nops
> 4)
5383 /* Loop over the operands and check that the memory references are
5384 suitable (ie immediate offsets from the same base register). At
5385 the same time, extract the target register, and the memory
5387 for (i
= 0; i
< nops
; i
++)
5392 /* Convert a subreg of a mem into the mem itself. */
5393 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5394 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5396 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5399 /* Don't reorder volatile memory references; it doesn't seem worth
5400 looking for the case where the order is ok anyway. */
5401 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5404 offset
= const0_rtx
;
5406 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5407 || (GET_CODE (reg
) == SUBREG
5408 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5409 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5410 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5412 || (GET_CODE (reg
) == SUBREG
5413 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5414 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5419 base_reg
= REGNO (reg
);
5420 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5421 ? REGNO (operands
[i
])
5422 : REGNO (SUBREG_REG (operands
[i
])));
5427 if (base_reg
!= (int) REGNO (reg
))
5428 /* Not addressed from the same base register. */
5431 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5432 ? REGNO (operands
[i
])
5433 : REGNO (SUBREG_REG (operands
[i
])));
5434 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5438 /* If it isn't an integer register, or if it overwrites the
5439 base register but isn't the last insn in the list, then
5440 we can't do this. */
5441 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5442 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5445 unsorted_offsets
[i
] = INTVAL (offset
);
5448 /* Not a suitable memory address. */
5452 /* All the useful information has now been extracted from the
5453 operands into unsorted_regs and unsorted_offsets; additionally,
5454 order[0] has been set to the lowest numbered register in the
5455 list. Sort the registers into order, and check that the memory
5456 offsets are ascending and adjacent. */
5458 for (i
= 1; i
< nops
; i
++)
5462 order
[i
] = order
[i
- 1];
5463 for (j
= 0; j
< nops
; j
++)
5464 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5465 && (order
[i
] == order
[i
- 1]
5466 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5469 /* Have we found a suitable register? if not, one must be used more
5471 if (order
[i
] == order
[i
- 1])
5474 /* Is the memory address adjacent and ascending? */
5475 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5483 for (i
= 0; i
< nops
; i
++)
5484 regs
[i
] = unsorted_regs
[order
[i
]];
5486 *load_offset
= unsorted_offsets
[order
[0]];
5489 if (unsorted_offsets
[order
[0]] == 0)
5490 return 1; /* ldmia */
5492 if (unsorted_offsets
[order
[0]] == 4)
5493 return 2; /* ldmib */
5495 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5496 return 3; /* ldmda */
5498 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5499 return 4; /* ldmdb */
5501 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5502 if the offset isn't small enough. The reason 2 ldrs are faster
5503 is because these ARMs are able to do more than one cache access
5504 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5505 whilst the ARM8 has a double bandwidth cache. This means that
5506 these cores can do both an instruction fetch and a data fetch in
5507 a single cycle, so the trick of calculating the address into a
5508 scratch register (one of the result regs) and then doing a load
5509 multiple actually becomes slower (and no smaller in code size).
5510 That is the transformation
5512 ldr rd1, [rbase + offset]
5513 ldr rd2, [rbase + offset + 4]
5517 add rd1, rbase, offset
5518 ldmia rd1, {rd1, rd2}
5520 produces worse code -- '3 cycles + any stalls on rd2' instead of
5521 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5522 access per cycle, the first sequence could never complete in less
5523 than 6 cycles, whereas the ldm sequence would only take 5 and
5524 would make better use of sequential accesses if not hitting the
5527 We cheat here and test 'arm_ld_sched' which we currently know to
5528 only be true for the ARM8, ARM9 and StrongARM. If this ever
5529 changes, then the test below needs to be reworked. */
5530 if (nops
== 2 && arm_ld_sched
)
5533 /* Can't do it without setting up the offset, only do this if it takes
5534 no more than one insn. */
5535 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5536 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5540 emit_ldm_seq (rtx
*operands
, int nops
)
5544 HOST_WIDE_INT offset
;
5548 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5551 strcpy (buf
, "ldm%?ia\t");
5555 strcpy (buf
, "ldm%?ib\t");
5559 strcpy (buf
, "ldm%?da\t");
5563 strcpy (buf
, "ldm%?db\t");
5568 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5569 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5572 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5573 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5575 output_asm_insn (buf
, operands
);
5577 strcpy (buf
, "ldm%?ia\t");
5584 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5585 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5587 for (i
= 1; i
< nops
; i
++)
5588 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5589 reg_names
[regs
[i
]]);
5591 strcat (buf
, "}\t%@ phole ldm");
5593 output_asm_insn (buf
, operands
);
5598 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5599 HOST_WIDE_INT
* load_offset
)
5601 int unsorted_regs
[4];
5602 HOST_WIDE_INT unsorted_offsets
[4];
5607 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5608 extended if required. */
5609 if (nops
< 2 || nops
> 4)
5612 /* Loop over the operands and check that the memory references are
5613 suitable (ie immediate offsets from the same base register). At
5614 the same time, extract the target register, and the memory
5616 for (i
= 0; i
< nops
; i
++)
5621 /* Convert a subreg of a mem into the mem itself. */
5622 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5623 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5625 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5628 /* Don't reorder volatile memory references; it doesn't seem worth
5629 looking for the case where the order is ok anyway. */
5630 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5633 offset
= const0_rtx
;
5635 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5636 || (GET_CODE (reg
) == SUBREG
5637 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5638 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5639 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5641 || (GET_CODE (reg
) == SUBREG
5642 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5643 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5648 base_reg
= REGNO (reg
);
5649 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5650 ? REGNO (operands
[i
])
5651 : REGNO (SUBREG_REG (operands
[i
])));
5656 if (base_reg
!= (int) REGNO (reg
))
5657 /* Not addressed from the same base register. */
5660 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5661 ? REGNO (operands
[i
])
5662 : REGNO (SUBREG_REG (operands
[i
])));
5663 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5667 /* If it isn't an integer register, then we can't do this. */
5668 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5671 unsorted_offsets
[i
] = INTVAL (offset
);
5674 /* Not a suitable memory address. */
5678 /* All the useful information has now been extracted from the
5679 operands into unsorted_regs and unsorted_offsets; additionally,
5680 order[0] has been set to the lowest numbered register in the
5681 list. Sort the registers into order, and check that the memory
5682 offsets are ascending and adjacent. */
5684 for (i
= 1; i
< nops
; i
++)
5688 order
[i
] = order
[i
- 1];
5689 for (j
= 0; j
< nops
; j
++)
5690 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5691 && (order
[i
] == order
[i
- 1]
5692 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5695 /* Have we found a suitable register? if not, one must be used more
5697 if (order
[i
] == order
[i
- 1])
5700 /* Is the memory address adjacent and ascending? */
5701 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5709 for (i
= 0; i
< nops
; i
++)
5710 regs
[i
] = unsorted_regs
[order
[i
]];
5712 *load_offset
= unsorted_offsets
[order
[0]];
5715 if (unsorted_offsets
[order
[0]] == 0)
5716 return 1; /* stmia */
5718 if (unsorted_offsets
[order
[0]] == 4)
5719 return 2; /* stmib */
5721 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5722 return 3; /* stmda */
5724 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5725 return 4; /* stmdb */
5731 emit_stm_seq (rtx
*operands
, int nops
)
5735 HOST_WIDE_INT offset
;
5739 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5742 strcpy (buf
, "stm%?ia\t");
5746 strcpy (buf
, "stm%?ib\t");
5750 strcpy (buf
, "stm%?da\t");
5754 strcpy (buf
, "stm%?db\t");
5761 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5762 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5764 for (i
= 1; i
< nops
; i
++)
5765 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5766 reg_names
[regs
[i
]]);
5768 strcat (buf
, "}\t%@ phole stm");
5770 output_asm_insn (buf
, operands
);
5775 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5777 if (GET_CODE (op
) != PARALLEL
5778 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5779 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5780 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5786 /* Routines for use in generating RTL. */
5789 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5790 int write_back
, int unchanging_p
, int in_struct_p
,
5795 int sign
= up
? 1 : -1;
5798 /* XScale has load-store double instructions, but they have stricter
5799 alignment requirements than load-store multiple, so we can not
5802 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5803 the pipeline until completion.
5811 An ldr instruction takes 1-3 cycles, but does not block the
5820 Best case ldr will always win. However, the more ldr instructions
5821 we issue, the less likely we are to be able to schedule them well.
5822 Using ldr instructions also increases code size.
5824 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5825 for counts of 3 or 4 regs. */
5826 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5832 for (i
= 0; i
< count
; i
++)
5834 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5835 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5836 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5837 MEM_SCALAR_P (mem
) = scalar_p
;
5838 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5842 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5850 result
= gen_rtx_PARALLEL (VOIDmode
,
5851 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5854 XVECEXP (result
, 0, 0)
5855 = gen_rtx_SET (GET_MODE (from
), from
,
5856 plus_constant (from
, count
* 4 * sign
));
5861 for (j
= 0; i
< count
; i
++, j
++)
5863 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5864 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5865 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5866 MEM_SCALAR_P (mem
) = scalar_p
;
5867 XVECEXP (result
, 0, i
)
5868 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5875 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5876 int write_back
, int unchanging_p
, int in_struct_p
,
5881 int sign
= up
? 1 : -1;
5884 /* See arm_gen_load_multiple for discussion of
5885 the pros/cons of ldm/stm usage for XScale. */
5886 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5892 for (i
= 0; i
< count
; i
++)
5894 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5895 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5896 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5897 MEM_SCALAR_P (mem
) = scalar_p
;
5898 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5902 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5910 result
= gen_rtx_PARALLEL (VOIDmode
,
5911 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5914 XVECEXP (result
, 0, 0)
5915 = gen_rtx_SET (GET_MODE (to
), to
,
5916 plus_constant (to
, count
* 4 * sign
));
5921 for (j
= 0; i
< count
; i
++, j
++)
5923 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5924 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5925 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5926 MEM_SCALAR_P (mem
) = scalar_p
;
5928 XVECEXP (result
, 0, i
)
5929 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5936 arm_gen_movstrqi (rtx
*operands
)
5938 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5941 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5942 rtx part_bytes_reg
= NULL
;
5944 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5945 int dst_scalar_p
, src_scalar_p
;
5947 if (GET_CODE (operands
[2]) != CONST_INT
5948 || GET_CODE (operands
[3]) != CONST_INT
5949 || INTVAL (operands
[2]) > 64
5950 || INTVAL (operands
[3]) & 3)
5953 st_dst
= XEXP (operands
[0], 0);
5954 st_src
= XEXP (operands
[1], 0);
5956 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5957 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5958 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5959 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5960 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5961 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5963 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5964 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5966 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5967 out_words_to_go
= INTVAL (operands
[2]) / 4;
5968 last_bytes
= INTVAL (operands
[2]) & 3;
5970 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5971 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5973 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5975 if (in_words_to_go
> 4)
5976 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5981 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5982 FALSE
, src_unchanging_p
,
5983 src_in_struct_p
, src_scalar_p
));
5985 if (out_words_to_go
)
5987 if (out_words_to_go
> 4)
5988 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5992 else if (out_words_to_go
!= 1)
5993 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6002 mem
= gen_rtx_MEM (SImode
, dst
);
6003 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6004 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6005 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6006 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6007 if (last_bytes
!= 0)
6008 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6012 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6013 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6016 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6017 if (out_words_to_go
)
6021 mem
= gen_rtx_MEM (SImode
, src
);
6022 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6023 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6024 MEM_SCALAR_P (mem
) = src_scalar_p
;
6025 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
6026 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
6028 mem
= gen_rtx_MEM (SImode
, dst
);
6029 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6030 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6031 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6032 emit_move_insn (mem
, sreg
);
6033 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
6036 if (in_words_to_go
) /* Sanity check */
6042 if (in_words_to_go
< 0)
6045 mem
= gen_rtx_MEM (SImode
, src
);
6046 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6047 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6048 MEM_SCALAR_P (mem
) = src_scalar_p
;
6049 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6052 if (last_bytes
&& part_bytes_reg
== NULL
)
6055 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6057 rtx tmp
= gen_reg_rtx (SImode
);
6059 /* The bytes we want are in the top end of the word. */
6060 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6061 GEN_INT (8 * (4 - last_bytes
))));
6062 part_bytes_reg
= tmp
;
6066 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
6067 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6068 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6069 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6070 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6074 tmp
= gen_reg_rtx (SImode
);
6075 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6076 part_bytes_reg
= tmp
;
6085 mem
= gen_rtx_MEM (HImode
, dst
);
6086 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6087 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6088 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6089 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6093 rtx tmp
= gen_reg_rtx (SImode
);
6095 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6096 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6097 part_bytes_reg
= tmp
;
6103 mem
= gen_rtx_MEM (QImode
, dst
);
6104 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6105 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6106 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6107 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6114 /* Generate a memory reference for a half word, such that it will be loaded
6115 into the top 16 bits of the word. We can assume that the address is
6116 known to be alignable and of the form reg, or plus (reg, const). */
6119 arm_gen_rotated_half_load (rtx memref
)
6121 HOST_WIDE_INT offset
= 0;
6122 rtx base
= XEXP (memref
, 0);
6124 if (GET_CODE (base
) == PLUS
)
6126 offset
= INTVAL (XEXP (base
, 1));
6127 base
= XEXP (base
, 0);
6130 /* If we aren't allowed to generate unaligned addresses, then fail. */
6131 if (TARGET_MMU_TRAPS
6132 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
6135 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
6137 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
6140 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
6143 /* Select a dominance comparison mode if possible for a test of the general
6144 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6145 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6146 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6147 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6148 In all cases OP will be either EQ or NE, but we don't need to know which
6149 here. If we are unable to support a dominance comparison we return
6150 CC mode. This will then fail to match for the RTL expressions that
6151 generate this call. */
6153 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6155 enum rtx_code cond1
, cond2
;
6158 /* Currently we will probably get the wrong result if the individual
6159 comparisons are not simple. This also ensures that it is safe to
6160 reverse a comparison if necessary. */
6161 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6163 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6167 /* The if_then_else variant of this tests the second condition if the
6168 first passes, but is true if the first fails. Reverse the first
6169 condition to get a true "inclusive-or" expression. */
6170 if (cond_or
== DOM_CC_NX_OR_Y
)
6171 cond1
= reverse_condition (cond1
);
6173 /* If the comparisons are not equal, and one doesn't dominate the other,
6174 then we can't do this. */
6176 && !comparison_dominates_p (cond1
, cond2
)
6177 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6182 enum rtx_code temp
= cond1
;
6190 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
6195 case LE
: return CC_DLEmode
;
6196 case LEU
: return CC_DLEUmode
;
6197 case GE
: return CC_DGEmode
;
6198 case GEU
: return CC_DGEUmode
;
6205 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
6214 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
6223 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
6232 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
6240 /* The remaining cases only occur when both comparisons are the
6265 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6267 /* All floating point compares return CCFP if it is an equality
6268 comparison, and CCFPE otherwise. */
6269 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6289 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6298 /* A compare with a shifted operand. Because of canonicalization, the
6299 comparison will have to be swapped when we emit the assembler. */
6300 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6301 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6302 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6303 || GET_CODE (x
) == ROTATERT
))
6306 /* This is a special case that is used by combine to allow a
6307 comparison of a shifted byte load to be split into a zero-extend
6308 followed by a comparison of the shifted integer (only valid for
6309 equalities and unsigned inequalities). */
6310 if (GET_MODE (x
) == SImode
6311 && GET_CODE (x
) == ASHIFT
6312 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6313 && GET_CODE (XEXP (x
, 0)) == SUBREG
6314 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6315 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6316 && (op
== EQ
|| op
== NE
6317 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6318 && GET_CODE (y
) == CONST_INT
)
6321 /* A construct for a conditional compare, if the false arm contains
6322 0, then both conditions must be true, otherwise either condition
6323 must be true. Not all conditions are possible, so CCmode is
6324 returned if it can't be done. */
6325 if (GET_CODE (x
) == IF_THEN_ELSE
6326 && (XEXP (x
, 2) == const0_rtx
6327 || XEXP (x
, 2) == const1_rtx
)
6328 && COMPARISON_P (XEXP (x
, 0))
6329 && COMPARISON_P (XEXP (x
, 1)))
6330 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6331 INTVAL (XEXP (x
, 2)));
6333 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6334 if (GET_CODE (x
) == AND
6335 && COMPARISON_P (XEXP (x
, 0))
6336 && COMPARISON_P (XEXP (x
, 1)))
6337 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6340 if (GET_CODE (x
) == IOR
6341 && COMPARISON_P (XEXP (x
, 0))
6342 && COMPARISON_P (XEXP (x
, 1)))
6343 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6346 /* An operation (on Thumb) where we want to test for a single bit.
6347 This is done by shifting that bit up into the top bit of a
6348 scratch register; we can then branch on the sign bit. */
6350 && GET_MODE (x
) == SImode
6351 && (op
== EQ
|| op
== NE
)
6352 && (GET_CODE (x
) == ZERO_EXTRACT
))
6355 /* An operation that sets the condition codes as a side-effect, the
6356 V flag is not set correctly, so we can only use comparisons where
6357 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6359 if (GET_MODE (x
) == SImode
6361 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6362 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6363 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6364 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6365 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6366 || GET_CODE (x
) == LSHIFTRT
6367 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6368 || GET_CODE (x
) == ROTATERT
6369 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6372 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6375 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6376 && GET_CODE (x
) == PLUS
6377 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6383 /* X and Y are two things to compare using CODE. Emit the compare insn and
6384 return the rtx for register 0 in the proper mode. FP means this is a
6385 floating point compare: I don't think that it is needed on the arm. */
6387 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6389 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6390 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6392 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6393 gen_rtx_COMPARE (mode
, x
, y
)));
6398 /* Generate a sequence of insns that will generate the correct return
6399 address mask depending on the physical architecture that the program
6402 arm_gen_return_addr_mask (void)
6404 rtx reg
= gen_reg_rtx (Pmode
);
6406 emit_insn (gen_return_addr_mask (reg
));
6411 arm_reload_in_hi (rtx
*operands
)
6413 rtx ref
= operands
[1];
6415 HOST_WIDE_INT offset
= 0;
6417 if (GET_CODE (ref
) == SUBREG
)
6419 offset
= SUBREG_BYTE (ref
);
6420 ref
= SUBREG_REG (ref
);
6423 if (GET_CODE (ref
) == REG
)
6425 /* We have a pseudo which has been spilt onto the stack; there
6426 are two cases here: the first where there is a simple
6427 stack-slot replacement and a second where the stack-slot is
6428 out of range, or is used as a subreg. */
6429 if (reg_equiv_mem
[REGNO (ref
)])
6431 ref
= reg_equiv_mem
[REGNO (ref
)];
6432 base
= find_replacement (&XEXP (ref
, 0));
6435 /* The slot is out of range, or was dressed up in a SUBREG. */
6436 base
= reg_equiv_address
[REGNO (ref
)];
6439 base
= find_replacement (&XEXP (ref
, 0));
6441 /* Handle the case where the address is too complex to be offset by 1. */
6442 if (GET_CODE (base
) == MINUS
6443 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6445 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6447 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6450 else if (GET_CODE (base
) == PLUS
)
6452 /* The addend must be CONST_INT, or we would have dealt with it above. */
6453 HOST_WIDE_INT hi
, lo
;
6455 offset
+= INTVAL (XEXP (base
, 1));
6456 base
= XEXP (base
, 0);
6458 /* Rework the address into a legal sequence of insns. */
6459 /* Valid range for lo is -4095 -> 4095 */
6462 : -((-offset
) & 0xfff));
6464 /* Corner case, if lo is the max offset then we would be out of range
6465 once we have added the additional 1 below, so bump the msb into the
6466 pre-loading insn(s). */
6470 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6471 ^ (HOST_WIDE_INT
) 0x80000000)
6472 - (HOST_WIDE_INT
) 0x80000000);
6474 if (hi
+ lo
!= offset
)
6479 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6481 /* Get the base address; addsi3 knows how to handle constants
6482 that require more than one insn. */
6483 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6489 /* Operands[2] may overlap operands[0] (though it won't overlap
6490 operands[1]), that's why we asked for a DImode reg -- so we can
6491 use the bit that does not overlap. */
6492 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6493 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6495 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6497 emit_insn (gen_zero_extendqisi2 (scratch
,
6498 gen_rtx_MEM (QImode
,
6499 plus_constant (base
,
6501 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6502 gen_rtx_MEM (QImode
,
6503 plus_constant (base
,
6505 if (!BYTES_BIG_ENDIAN
)
6506 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6507 gen_rtx_IOR (SImode
,
6510 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6514 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6515 gen_rtx_IOR (SImode
,
6516 gen_rtx_ASHIFT (SImode
, scratch
,
6518 gen_rtx_SUBREG (SImode
, operands
[0],
6522 /* Handle storing a half-word to memory during reload by synthesizing as two
6523 byte stores. Take care not to clobber the input values until after we
6524 have moved them somewhere safe. This code assumes that if the DImode
6525 scratch in operands[2] overlaps either the input value or output address
6526 in some way, then that value must die in this insn (we absolutely need
6527 two scratch registers for some corner cases). */
6529 arm_reload_out_hi (rtx
*operands
)
6531 rtx ref
= operands
[0];
6532 rtx outval
= operands
[1];
6534 HOST_WIDE_INT offset
= 0;
6536 if (GET_CODE (ref
) == SUBREG
)
6538 offset
= SUBREG_BYTE (ref
);
6539 ref
= SUBREG_REG (ref
);
6542 if (GET_CODE (ref
) == REG
)
6544 /* We have a pseudo which has been spilt onto the stack; there
6545 are two cases here: the first where there is a simple
6546 stack-slot replacement and a second where the stack-slot is
6547 out of range, or is used as a subreg. */
6548 if (reg_equiv_mem
[REGNO (ref
)])
6550 ref
= reg_equiv_mem
[REGNO (ref
)];
6551 base
= find_replacement (&XEXP (ref
, 0));
6554 /* The slot is out of range, or was dressed up in a SUBREG. */
6555 base
= reg_equiv_address
[REGNO (ref
)];
6558 base
= find_replacement (&XEXP (ref
, 0));
6560 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6562 /* Handle the case where the address is too complex to be offset by 1. */
6563 if (GET_CODE (base
) == MINUS
6564 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6566 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6568 /* Be careful not to destroy OUTVAL. */
6569 if (reg_overlap_mentioned_p (base_plus
, outval
))
6571 /* Updating base_plus might destroy outval, see if we can
6572 swap the scratch and base_plus. */
6573 if (!reg_overlap_mentioned_p (scratch
, outval
))
6576 scratch
= base_plus
;
6581 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6583 /* Be conservative and copy OUTVAL into the scratch now,
6584 this should only be necessary if outval is a subreg
6585 of something larger than a word. */
6586 /* XXX Might this clobber base? I can't see how it can,
6587 since scratch is known to overlap with OUTVAL, and
6588 must be wider than a word. */
6589 emit_insn (gen_movhi (scratch_hi
, outval
));
6590 outval
= scratch_hi
;
6594 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6597 else if (GET_CODE (base
) == PLUS
)
6599 /* The addend must be CONST_INT, or we would have dealt with it above. */
6600 HOST_WIDE_INT hi
, lo
;
6602 offset
+= INTVAL (XEXP (base
, 1));
6603 base
= XEXP (base
, 0);
6605 /* Rework the address into a legal sequence of insns. */
6606 /* Valid range for lo is -4095 -> 4095 */
6609 : -((-offset
) & 0xfff));
6611 /* Corner case, if lo is the max offset then we would be out of range
6612 once we have added the additional 1 below, so bump the msb into the
6613 pre-loading insn(s). */
6617 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6618 ^ (HOST_WIDE_INT
) 0x80000000)
6619 - (HOST_WIDE_INT
) 0x80000000);
6621 if (hi
+ lo
!= offset
)
6626 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6628 /* Be careful not to destroy OUTVAL. */
6629 if (reg_overlap_mentioned_p (base_plus
, outval
))
6631 /* Updating base_plus might destroy outval, see if we
6632 can swap the scratch and base_plus. */
6633 if (!reg_overlap_mentioned_p (scratch
, outval
))
6636 scratch
= base_plus
;
6641 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6643 /* Be conservative and copy outval into scratch now,
6644 this should only be necessary if outval is a
6645 subreg of something larger than a word. */
6646 /* XXX Might this clobber base? I can't see how it
6647 can, since scratch is known to overlap with
6649 emit_insn (gen_movhi (scratch_hi
, outval
));
6650 outval
= scratch_hi
;
6654 /* Get the base address; addsi3 knows how to handle constants
6655 that require more than one insn. */
6656 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6662 if (BYTES_BIG_ENDIAN
)
6664 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6665 plus_constant (base
, offset
+ 1)),
6666 gen_lowpart (QImode
, outval
)));
6667 emit_insn (gen_lshrsi3 (scratch
,
6668 gen_rtx_SUBREG (SImode
, outval
, 0),
6670 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6671 gen_lowpart (QImode
, scratch
)));
6675 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6676 gen_lowpart (QImode
, outval
)));
6677 emit_insn (gen_lshrsi3 (scratch
,
6678 gen_rtx_SUBREG (SImode
, outval
, 0),
6680 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6681 plus_constant (base
, offset
+ 1)),
6682 gen_lowpart (QImode
, scratch
)));
6686 /* Print a symbolic form of X to the debug file, F. */
6688 arm_print_value (FILE *f
, rtx x
)
6690 switch (GET_CODE (x
))
6693 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6697 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6705 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6707 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6708 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6716 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6720 fprintf (f
, "`%s'", XSTR (x
, 0));
6724 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6728 arm_print_value (f
, XEXP (x
, 0));
6732 arm_print_value (f
, XEXP (x
, 0));
6734 arm_print_value (f
, XEXP (x
, 1));
6742 fprintf (f
, "????");
6747 /* Routines for manipulation of the constant pool. */
6749 /* Arm instructions cannot load a large constant directly into a
6750 register; they have to come from a pc relative load. The constant
6751 must therefore be placed in the addressable range of the pc
6752 relative load. Depending on the precise pc relative load
6753 instruction the range is somewhere between 256 bytes and 4k. This
6754 means that we often have to dump a constant inside a function, and
6755 generate code to branch around it.
6757 It is important to minimize this, since the branches will slow
6758 things down and make the code larger.
6760 Normally we can hide the table after an existing unconditional
6761 branch so that there is no interruption of the flow, but in the
6762 worst case the code looks like this:
6780 We fix this by performing a scan after scheduling, which notices
6781 which instructions need to have their operands fetched from the
6782 constant table and builds the table.
6784 The algorithm starts by building a table of all the constants that
6785 need fixing up and all the natural barriers in the function (places
6786 where a constant table can be dropped without breaking the flow).
6787 For each fixup we note how far the pc-relative replacement will be
6788 able to reach and the offset of the instruction into the function.
6790 Having built the table we then group the fixes together to form
6791 tables that are as large as possible (subject to addressing
6792 constraints) and emit each table of constants after the last
6793 barrier that is within range of all the instructions in the group.
6794 If a group does not contain a barrier, then we forcibly create one
6795 by inserting a jump instruction into the flow. Once the table has
6796 been inserted, the insns are then modified to reference the
6797 relevant entry in the pool.
6799 Possible enhancements to the algorithm (not implemented) are:
6801 1) For some processors and object formats, there may be benefit in
6802 aligning the pools to the start of cache lines; this alignment
6803 would need to be taken into account when calculating addressability
6806 /* These typedefs are located at the start of this file, so that
6807 they can be used in the prototypes there. This comment is to
6808 remind readers of that fact so that the following structures
6809 can be understood more easily.
6811 typedef struct minipool_node Mnode;
6812 typedef struct minipool_fixup Mfix; */
6814 struct minipool_node
6816 /* Doubly linked chain of entries. */
6819 /* The maximum offset into the code that this entry can be placed. While
6820 pushing fixes for forward references, all entries are sorted in order
6821 of increasing max_address. */
6822 HOST_WIDE_INT max_address
;
6823 /* Similarly for an entry inserted for a backwards ref. */
6824 HOST_WIDE_INT min_address
;
6825 /* The number of fixes referencing this entry. This can become zero
6826 if we "unpush" an entry. In this case we ignore the entry when we
6827 come to emit the code. */
6829 /* The offset from the start of the minipool. */
6830 HOST_WIDE_INT offset
;
6831 /* The value in table. */
6833 /* The mode of value. */
6834 enum machine_mode mode
;
6835 /* The size of the value. With iWMMXt enabled
6836 sizes > 4 also imply an alignment of 8-bytes. */
6840 struct minipool_fixup
6844 HOST_WIDE_INT address
;
6846 enum machine_mode mode
;
6850 HOST_WIDE_INT forwards
;
6851 HOST_WIDE_INT backwards
;
6854 /* Fixes less than a word need padding out to a word boundary. */
6855 #define MINIPOOL_FIX_SIZE(mode) \
6856 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6858 static Mnode
* minipool_vector_head
;
6859 static Mnode
* minipool_vector_tail
;
6860 static rtx minipool_vector_label
;
6862 /* The linked list of all minipool fixes required for this function. */
6863 Mfix
* minipool_fix_head
;
6864 Mfix
* minipool_fix_tail
;
6865 /* The fix entry for the current minipool, once it has been placed. */
6866 Mfix
* minipool_barrier
;
6868 /* Determines if INSN is the start of a jump table. Returns the end
6869 of the TABLE or NULL_RTX. */
6871 is_jump_table (rtx insn
)
6875 if (GET_CODE (insn
) == JUMP_INSN
6876 && JUMP_LABEL (insn
) != NULL
6877 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6878 == next_real_insn (insn
))
6880 && GET_CODE (table
) == JUMP_INSN
6881 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6882 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6888 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6889 #define JUMP_TABLES_IN_TEXT_SECTION 0
6892 static HOST_WIDE_INT
6893 get_jump_table_size (rtx insn
)
6895 /* ADDR_VECs only take room if read-only data does into the text
6897 if (JUMP_TABLES_IN_TEXT_SECTION
6898 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6903 rtx body
= PATTERN (insn
);
6904 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6906 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6912 /* Move a minipool fix MP from its current location to before MAX_MP.
6913 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6914 constraints may need updating. */
6916 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6917 HOST_WIDE_INT max_address
)
6919 /* This should never be true and the code below assumes these are
6926 if (max_address
< mp
->max_address
)
6927 mp
->max_address
= max_address
;
6931 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6932 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6934 mp
->max_address
= max_address
;
6936 /* Unlink MP from its current position. Since max_mp is non-null,
6937 mp->prev must be non-null. */
6938 mp
->prev
->next
= mp
->next
;
6939 if (mp
->next
!= NULL
)
6940 mp
->next
->prev
= mp
->prev
;
6942 minipool_vector_tail
= mp
->prev
;
6944 /* Re-insert it before MAX_MP. */
6946 mp
->prev
= max_mp
->prev
;
6949 if (mp
->prev
!= NULL
)
6950 mp
->prev
->next
= mp
;
6952 minipool_vector_head
= mp
;
6955 /* Save the new entry. */
6958 /* Scan over the preceding entries and adjust their addresses as
6960 while (mp
->prev
!= NULL
6961 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6963 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6970 /* Add a constant to the minipool for a forward reference. Returns the
6971 node added or NULL if the constant will not fit in this pool. */
6973 add_minipool_forward_ref (Mfix
*fix
)
6975 /* If set, max_mp is the first pool_entry that has a lower
6976 constraint than the one we are trying to add. */
6977 Mnode
* max_mp
= NULL
;
6978 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6981 /* If this fix's address is greater than the address of the first
6982 entry, then we can't put the fix in this pool. We subtract the
6983 size of the current fix to ensure that if the table is fully
6984 packed we still have enough room to insert this value by suffling
6985 the other fixes forwards. */
6986 if (minipool_vector_head
&&
6987 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6990 /* Scan the pool to see if a constant with the same value has
6991 already been added. While we are doing this, also note the
6992 location where we must insert the constant if it doesn't already
6994 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6996 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6997 && fix
->mode
== mp
->mode
6998 && (GET_CODE (fix
->value
) != CODE_LABEL
6999 || (CODE_LABEL_NUMBER (fix
->value
)
7000 == CODE_LABEL_NUMBER (mp
->value
)))
7001 && rtx_equal_p (fix
->value
, mp
->value
))
7003 /* More than one fix references this entry. */
7005 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7008 /* Note the insertion point if necessary. */
7010 && mp
->max_address
> max_address
)
7013 /* If we are inserting an 8-bytes aligned quantity and
7014 we have not already found an insertion point, then
7015 make sure that all such 8-byte aligned quantities are
7016 placed at the start of the pool. */
7017 if (ARM_DOUBLEWORD_ALIGN
7019 && fix
->fix_size
== 8
7020 && mp
->fix_size
!= 8)
7023 max_address
= mp
->max_address
;
7027 /* The value is not currently in the minipool, so we need to create
7028 a new entry for it. If MAX_MP is NULL, the entry will be put on
7029 the end of the list since the placement is less constrained than
7030 any existing entry. Otherwise, we insert the new fix before
7031 MAX_MP and, if necessary, adjust the constraints on the other
7033 mp
= xmalloc (sizeof (* mp
));
7034 mp
->fix_size
= fix
->fix_size
;
7035 mp
->mode
= fix
->mode
;
7036 mp
->value
= fix
->value
;
7038 /* Not yet required for a backwards ref. */
7039 mp
->min_address
= -65536;
7043 mp
->max_address
= max_address
;
7045 mp
->prev
= minipool_vector_tail
;
7047 if (mp
->prev
== NULL
)
7049 minipool_vector_head
= mp
;
7050 minipool_vector_label
= gen_label_rtx ();
7053 mp
->prev
->next
= mp
;
7055 minipool_vector_tail
= mp
;
7059 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7060 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7062 mp
->max_address
= max_address
;
7065 mp
->prev
= max_mp
->prev
;
7067 if (mp
->prev
!= NULL
)
7068 mp
->prev
->next
= mp
;
7070 minipool_vector_head
= mp
;
7073 /* Save the new entry. */
7076 /* Scan over the preceding entries and adjust their addresses as
7078 while (mp
->prev
!= NULL
7079 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7081 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7089 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7090 HOST_WIDE_INT min_address
)
7092 HOST_WIDE_INT offset
;
7094 /* This should never be true, and the code below assumes these are
7101 if (min_address
> mp
->min_address
)
7102 mp
->min_address
= min_address
;
7106 /* We will adjust this below if it is too loose. */
7107 mp
->min_address
= min_address
;
7109 /* Unlink MP from its current position. Since min_mp is non-null,
7110 mp->next must be non-null. */
7111 mp
->next
->prev
= mp
->prev
;
7112 if (mp
->prev
!= NULL
)
7113 mp
->prev
->next
= mp
->next
;
7115 minipool_vector_head
= mp
->next
;
7117 /* Reinsert it after MIN_MP. */
7119 mp
->next
= min_mp
->next
;
7121 if (mp
->next
!= NULL
)
7122 mp
->next
->prev
= mp
;
7124 minipool_vector_tail
= mp
;
7130 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7132 mp
->offset
= offset
;
7133 if (mp
->refcount
> 0)
7134 offset
+= mp
->fix_size
;
7136 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7137 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7143 /* Add a constant to the minipool for a backward reference. Returns the
7144 node added or NULL if the constant will not fit in this pool.
7146 Note that the code for insertion for a backwards reference can be
7147 somewhat confusing because the calculated offsets for each fix do
7148 not take into account the size of the pool (which is still under
7151 add_minipool_backward_ref (Mfix
*fix
)
7153 /* If set, min_mp is the last pool_entry that has a lower constraint
7154 than the one we are trying to add. */
7155 Mnode
*min_mp
= NULL
;
7156 /* This can be negative, since it is only a constraint. */
7157 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7160 /* If we can't reach the current pool from this insn, or if we can't
7161 insert this entry at the end of the pool without pushing other
7162 fixes out of range, then we don't try. This ensures that we
7163 can't fail later on. */
7164 if (min_address
>= minipool_barrier
->address
7165 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7166 >= minipool_barrier
->address
))
7169 /* Scan the pool to see if a constant with the same value has
7170 already been added. While we are doing this, also note the
7171 location where we must insert the constant if it doesn't already
7173 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7175 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7176 && fix
->mode
== mp
->mode
7177 && (GET_CODE (fix
->value
) != CODE_LABEL
7178 || (CODE_LABEL_NUMBER (fix
->value
)
7179 == CODE_LABEL_NUMBER (mp
->value
)))
7180 && rtx_equal_p (fix
->value
, mp
->value
)
7181 /* Check that there is enough slack to move this entry to the
7182 end of the table (this is conservative). */
7184 > (minipool_barrier
->address
7185 + minipool_vector_tail
->offset
7186 + minipool_vector_tail
->fix_size
)))
7189 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7193 mp
->min_address
+= fix
->fix_size
;
7196 /* Note the insertion point if necessary. */
7197 if (mp
->min_address
< min_address
)
7199 /* For now, we do not allow the insertion of 8-byte alignment
7200 requiring nodes anywhere but at the start of the pool. */
7201 if (ARM_DOUBLEWORD_ALIGN
7202 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7207 else if (mp
->max_address
7208 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7210 /* Inserting before this entry would push the fix beyond
7211 its maximum address (which can happen if we have
7212 re-located a forwards fix); force the new fix to come
7215 min_address
= mp
->min_address
+ fix
->fix_size
;
7217 /* If we are inserting an 8-bytes aligned quantity and
7218 we have not already found an insertion point, then
7219 make sure that all such 8-byte aligned quantities are
7220 placed at the start of the pool. */
7221 else if (ARM_DOUBLEWORD_ALIGN
7223 && fix
->fix_size
== 8
7224 && mp
->fix_size
< 8)
7227 min_address
= mp
->min_address
+ fix
->fix_size
;
7232 /* We need to create a new entry. */
7233 mp
= xmalloc (sizeof (* mp
));
7234 mp
->fix_size
= fix
->fix_size
;
7235 mp
->mode
= fix
->mode
;
7236 mp
->value
= fix
->value
;
7238 mp
->max_address
= minipool_barrier
->address
+ 65536;
7240 mp
->min_address
= min_address
;
7245 mp
->next
= minipool_vector_head
;
7247 if (mp
->next
== NULL
)
7249 minipool_vector_tail
= mp
;
7250 minipool_vector_label
= gen_label_rtx ();
7253 mp
->next
->prev
= mp
;
7255 minipool_vector_head
= mp
;
7259 mp
->next
= min_mp
->next
;
7263 if (mp
->next
!= NULL
)
7264 mp
->next
->prev
= mp
;
7266 minipool_vector_tail
= mp
;
7269 /* Save the new entry. */
7277 /* Scan over the following entries and adjust their offsets. */
7278 while (mp
->next
!= NULL
)
7280 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7281 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7284 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7286 mp
->next
->offset
= mp
->offset
;
7295 assign_minipool_offsets (Mfix
*barrier
)
7297 HOST_WIDE_INT offset
= 0;
7300 minipool_barrier
= barrier
;
7302 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7304 mp
->offset
= offset
;
7306 if (mp
->refcount
> 0)
7307 offset
+= mp
->fix_size
;
7311 /* Output the literal table */
7313 dump_minipool (rtx scan
)
7319 if (ARM_DOUBLEWORD_ALIGN
)
7320 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7321 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7329 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7330 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7332 scan
= emit_label_after (gen_label_rtx (), scan
);
7333 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7334 scan
= emit_label_after (minipool_vector_label
, scan
);
7336 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7338 if (mp
->refcount
> 0)
7343 ";; Offset %u, min %ld, max %ld ",
7344 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7345 (unsigned long) mp
->max_address
);
7346 arm_print_value (dump_file
, mp
->value
);
7347 fputc ('\n', dump_file
);
7350 switch (mp
->fix_size
)
7352 #ifdef HAVE_consttable_1
7354 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7358 #ifdef HAVE_consttable_2
7360 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7364 #ifdef HAVE_consttable_4
7366 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7370 #ifdef HAVE_consttable_8
7372 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7386 minipool_vector_head
= minipool_vector_tail
= NULL
;
7387 scan
= emit_insn_after (gen_consttable_end (), scan
);
7388 scan
= emit_barrier_after (scan
);
7391 /* Return the cost of forcibly inserting a barrier after INSN. */
7393 arm_barrier_cost (rtx insn
)
7395 /* Basing the location of the pool on the loop depth is preferable,
7396 but at the moment, the basic block information seems to be
7397 corrupt by this stage of the compilation. */
7399 rtx next
= next_nonnote_insn (insn
);
7401 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7404 switch (GET_CODE (insn
))
7407 /* It will always be better to place the table before the label, rather
7416 return base_cost
- 10;
7419 return base_cost
+ 10;
7423 /* Find the best place in the insn stream in the range
7424 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7425 Create the barrier by inserting a jump and add a new fix entry for
7428 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7430 HOST_WIDE_INT count
= 0;
7432 rtx from
= fix
->insn
;
7433 rtx selected
= from
;
7435 HOST_WIDE_INT selected_address
;
7437 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7438 rtx label
= gen_label_rtx ();
7440 selected_cost
= arm_barrier_cost (from
);
7441 selected_address
= fix
->address
;
7443 while (from
&& count
< max_count
)
7448 /* This code shouldn't have been called if there was a natural barrier
7450 if (GET_CODE (from
) == BARRIER
)
7453 /* Count the length of this insn. */
7454 count
+= get_attr_length (from
);
7456 /* If there is a jump table, add its length. */
7457 tmp
= is_jump_table (from
);
7460 count
+= get_jump_table_size (tmp
);
7462 /* Jump tables aren't in a basic block, so base the cost on
7463 the dispatch insn. If we select this location, we will
7464 still put the pool after the table. */
7465 new_cost
= arm_barrier_cost (from
);
7467 if (count
< max_count
&& new_cost
<= selected_cost
)
7470 selected_cost
= new_cost
;
7471 selected_address
= fix
->address
+ count
;
7474 /* Continue after the dispatch table. */
7475 from
= NEXT_INSN (tmp
);
7479 new_cost
= arm_barrier_cost (from
);
7481 if (count
< max_count
&& new_cost
<= selected_cost
)
7484 selected_cost
= new_cost
;
7485 selected_address
= fix
->address
+ count
;
7488 from
= NEXT_INSN (from
);
7491 /* Create a new JUMP_INSN that branches around a barrier. */
7492 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7493 JUMP_LABEL (from
) = label
;
7494 barrier
= emit_barrier_after (from
);
7495 emit_label_after (label
, barrier
);
7497 /* Create a minipool barrier entry for the new barrier. */
7498 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7499 new_fix
->insn
= barrier
;
7500 new_fix
->address
= selected_address
;
7501 new_fix
->next
= fix
->next
;
7502 fix
->next
= new_fix
;
7507 /* Record that there is a natural barrier in the insn stream at
7510 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7512 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7515 fix
->address
= address
;
7518 if (minipool_fix_head
!= NULL
)
7519 minipool_fix_tail
->next
= fix
;
7521 minipool_fix_head
= fix
;
7523 minipool_fix_tail
= fix
;
7526 /* Record INSN, which will need fixing up to load a value from the
7527 minipool. ADDRESS is the offset of the insn since the start of the
7528 function; LOC is a pointer to the part of the insn which requires
7529 fixing; VALUE is the constant that must be loaded, which is of type
7532 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7533 enum machine_mode mode
, rtx value
)
7535 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7537 #ifdef AOF_ASSEMBLER
7538 /* PIC symbol references need to be converted into offsets into the
7540 /* XXX This shouldn't be done here. */
7541 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7542 value
= aof_pic_entry (value
);
7543 #endif /* AOF_ASSEMBLER */
7546 fix
->address
= address
;
7549 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7551 fix
->forwards
= get_attr_pool_range (insn
);
7552 fix
->backwards
= get_attr_neg_pool_range (insn
);
7553 fix
->minipool
= NULL
;
7555 /* If an insn doesn't have a range defined for it, then it isn't
7556 expecting to be reworked by this code. Better to abort now than
7557 to generate duff assembly code. */
7558 if (fix
->forwards
== 0 && fix
->backwards
== 0)
7561 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7562 So there might be an empty word before the start of the pool.
7563 Hence we reduce the forward range by 4 to allow for this
7565 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7571 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7572 GET_MODE_NAME (mode
),
7573 INSN_UID (insn
), (unsigned long) address
,
7574 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7575 arm_print_value (dump_file
, fix
->value
);
7576 fprintf (dump_file
, "\n");
7579 /* Add it to the chain of fixes. */
7582 if (minipool_fix_head
!= NULL
)
7583 minipool_fix_tail
->next
= fix
;
7585 minipool_fix_head
= fix
;
7587 minipool_fix_tail
= fix
;
7590 /* Scan INSN and note any of its operands that need fixing.
7591 If DO_PUSHES is false we do not actually push any of the fixups
7592 needed. The function returns TRUE is any fixups were needed/pushed.
7593 This is used by arm_memory_load_p() which needs to know about loads
7594 of constants that will be converted into minipool loads. */
7596 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7598 bool result
= false;
7601 extract_insn (insn
);
7603 if (!constrain_operands (1))
7604 fatal_insn_not_found (insn
);
7606 if (recog_data
.n_alternatives
== 0)
7609 /* Fill in recog_op_alt with information about the constraints of this insn. */
7610 preprocess_constraints ();
7612 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7614 /* Things we need to fix can only occur in inputs. */
7615 if (recog_data
.operand_type
[opno
] != OP_IN
)
7618 /* If this alternative is a memory reference, then any mention
7619 of constants in this alternative is really to fool reload
7620 into allowing us to accept one there. We need to fix them up
7621 now so that we output the right code. */
7622 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7624 rtx op
= recog_data
.operand
[opno
];
7626 if (CONSTANT_P (op
))
7629 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7630 recog_data
.operand_mode
[opno
], op
);
7633 else if (GET_CODE (op
) == MEM
7634 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7635 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7639 rtx cop
= avoid_constant_pool_reference (op
);
7641 /* Casting the address of something to a mode narrower
7642 than a word can cause avoid_constant_pool_reference()
7643 to return the pool reference itself. That's no good to
7644 us here. Lets just hope that we can use the
7645 constant pool value directly. */
7647 cop
= get_pool_constant (XEXP (op
, 0));
7649 push_minipool_fix (insn
, address
,
7650 recog_data
.operand_loc
[opno
],
7651 recog_data
.operand_mode
[opno
], cop
);
7662 /* Gcc puts the pool in the wrong place for ARM, since we can only
7663 load addresses a limited distance around the pc. We do some
7664 special munging to move the constant pool values to the correct
7665 point in the code. */
7670 HOST_WIDE_INT address
= 0;
7673 minipool_fix_head
= minipool_fix_tail
= NULL
;
7675 /* The first insn must always be a note, or the code below won't
7676 scan it properly. */
7677 insn
= get_insns ();
7678 if (GET_CODE (insn
) != NOTE
)
7681 /* Scan all the insns and record the operands that will need fixing. */
7682 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7684 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7685 && (arm_cirrus_insn_p (insn
)
7686 || GET_CODE (insn
) == JUMP_INSN
7687 || arm_memory_load_p (insn
)))
7688 cirrus_reorg (insn
);
7690 if (GET_CODE (insn
) == BARRIER
)
7691 push_minipool_barrier (insn
, address
);
7692 else if (INSN_P (insn
))
7696 note_invalid_constants (insn
, address
, true);
7697 address
+= get_attr_length (insn
);
7699 /* If the insn is a vector jump, add the size of the table
7700 and skip the table. */
7701 if ((table
= is_jump_table (insn
)) != NULL
)
7703 address
+= get_jump_table_size (table
);
7709 fix
= minipool_fix_head
;
7711 /* Now scan the fixups and perform the required changes. */
7716 Mfix
* last_added_fix
;
7717 Mfix
* last_barrier
= NULL
;
7720 /* Skip any further barriers before the next fix. */
7721 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7724 /* No more fixes. */
7728 last_added_fix
= NULL
;
7730 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7732 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7734 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7737 last_barrier
= ftmp
;
7739 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7742 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7745 /* If we found a barrier, drop back to that; any fixes that we
7746 could have reached but come after the barrier will now go in
7747 the next mini-pool. */
7748 if (last_barrier
!= NULL
)
7750 /* Reduce the refcount for those fixes that won't go into this
7752 for (fdel
= last_barrier
->next
;
7753 fdel
&& fdel
!= ftmp
;
7756 fdel
->minipool
->refcount
--;
7757 fdel
->minipool
= NULL
;
7760 ftmp
= last_barrier
;
7764 /* ftmp is first fix that we can't fit into this pool and
7765 there no natural barriers that we could use. Insert a
7766 new barrier in the code somewhere between the previous
7767 fix and this one, and arrange to jump around it. */
7768 HOST_WIDE_INT max_address
;
7770 /* The last item on the list of fixes must be a barrier, so
7771 we can never run off the end of the list of fixes without
7772 last_barrier being set. */
7776 max_address
= minipool_vector_head
->max_address
;
7777 /* Check that there isn't another fix that is in range that
7778 we couldn't fit into this pool because the pool was
7779 already too large: we need to put the pool before such an
7781 if (ftmp
->address
< max_address
)
7782 max_address
= ftmp
->address
;
7784 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7787 assign_minipool_offsets (last_barrier
);
7791 if (GET_CODE (ftmp
->insn
) != BARRIER
7792 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7799 /* Scan over the fixes we have identified for this pool, fixing them
7800 up and adding the constants to the pool itself. */
7801 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7802 this_fix
= this_fix
->next
)
7803 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7806 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7807 minipool_vector_label
),
7808 this_fix
->minipool
->offset
);
7809 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7812 dump_minipool (last_barrier
->insn
);
7816 /* From now on we must synthesize any constants that we can't handle
7817 directly. This can happen if the RTL gets split during final
7818 instruction generation. */
7819 after_arm_reorg
= 1;
7821 /* Free the minipool memory. */
7822 obstack_free (&minipool_obstack
, minipool_startobj
);
7825 /* Routines to output assembly language. */
7827 /* If the rtx is the correct value then return the string of the number.
7828 In this way we can ensure that valid double constants are generated even
7829 when cross compiling. */
7831 fp_immediate_constant (rtx x
)
7836 if (!fp_consts_inited
)
7839 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7840 for (i
= 0; i
< 8; i
++)
7841 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7842 return strings_fp
[i
];
7847 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7849 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7853 if (!fp_consts_inited
)
7856 for (i
= 0; i
< 8; i
++)
7857 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7858 return strings_fp
[i
];
7863 /* Output the operands of a LDM/STM instruction to STREAM.
7864 MASK is the ARM register set mask of which only bits 0-15 are important.
7865 REG is the base register, either the frame pointer or the stack pointer,
7866 INSTR is the possibly suffixed load or store instruction. */
7868 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7871 int not_first
= FALSE
;
7873 fputc ('\t', stream
);
7874 asm_fprintf (stream
, instr
, reg
);
7875 fputs (", {", stream
);
7877 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7878 if (mask
& (1 << i
))
7881 fprintf (stream
, ", ");
7883 asm_fprintf (stream
, "%r", i
);
7887 fprintf (stream
, "}");
7889 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7890 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7891 Strictly speaking the instruction would be unpredictable only if
7892 we were writing back the base register as well, but since we never
7893 want to generate an LDM type 2 instruction (register bank switching)
7894 which is what you get if the PC is not being loaded, we do not need
7895 to check for writeback. */
7896 if (! TARGET_APCS_32
7897 && ((mask
& (1 << PC_REGNUM
)) != 0))
7898 fprintf (stream
, "^");
7900 fprintf (stream
, "\n");
7904 /* Output a FLDMX instruction to STREAM.
7905 BASE if the register containing the address.
7906 REG and COUNT specify the register range.
7907 Extra registers may be added to avoid hardware bugs. */
7910 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
7914 /* Workaround ARM10 VFPr1 bug. */
7915 if (count
== 2 && !arm_arch6
)
7922 fputc ('\t', stream
);
7923 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
7925 for (i
= reg
; i
< reg
+ count
; i
++)
7928 fputs (", ", stream
);
7929 asm_fprintf (stream
, "d%d", i
);
7931 fputs ("}\n", stream
);
7936 /* Output the assembly for a store multiple. */
7939 vfp_output_fstmx (rtx
* operands
)
7946 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
7947 p
= strlen (pattern
);
7949 if (GET_CODE (operands
[1]) != REG
)
7952 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
7953 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
7955 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
7957 strcpy (&pattern
[p
], "}");
7959 output_asm_insn (pattern
, operands
);
7964 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7965 number of bytes pushed. */
7968 vfp_emit_fstmx (int base_reg
, int count
)
7975 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7976 register pairs are stored by a store multiple insn. We avoid this
7977 by pushing an extra pair. */
7978 if (count
== 2 && !arm_arch6
)
7980 if (base_reg
== LAST_VFP_REGNUM
- 3)
7985 /* ??? The frame layout is implementation defined. We describe
7986 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7987 We really need some way of representing the whole block so that the
7988 unwinder can figure it out at runtime. */
7989 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7990 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
7992 reg
= gen_rtx_REG (DFmode
, base_reg
);
7996 = gen_rtx_SET (VOIDmode
,
7997 gen_rtx_MEM (BLKmode
,
7998 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7999 gen_rtx_UNSPEC (BLKmode
,
8003 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8004 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8005 GEN_INT (-(count
* 8 + 4))));
8006 RTX_FRAME_RELATED_P (tmp
) = 1;
8007 XVECEXP (dwarf
, 0, 0) = tmp
;
8009 tmp
= gen_rtx_SET (VOIDmode
,
8010 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
8012 RTX_FRAME_RELATED_P (tmp
) = 1;
8013 XVECEXP (dwarf
, 0, 1) = tmp
;
8015 for (i
= 1; i
< count
; i
++)
8017 reg
= gen_rtx_REG (DFmode
, base_reg
);
8019 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8021 tmp
= gen_rtx_SET (VOIDmode
,
8022 gen_rtx_MEM (DFmode
,
8023 gen_rtx_PLUS (SImode
,
8027 RTX_FRAME_RELATED_P (tmp
) = 1;
8028 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8031 par
= emit_insn (par
);
8032 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8034 RTX_FRAME_RELATED_P (par
) = 1;
8036 return count
* 8 + 4;
8040 /* Output a 'call' insn. */
8042 output_call (rtx
*operands
)
8044 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8046 if (REGNO (operands
[0]) == LR_REGNUM
)
8048 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8049 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8052 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8054 if (TARGET_INTERWORK
)
8055 output_asm_insn ("bx%?\t%0", operands
);
8057 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8062 /* Output a 'call' insn that is a reference in memory. */
8064 output_call_mem (rtx
*operands
)
8066 if (TARGET_INTERWORK
)
8068 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8069 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8070 output_asm_insn ("bx%?\t%|ip", operands
);
8072 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8074 /* LR is used in the memory address. We load the address in the
8075 first instruction. It's safe to use IP as the target of the
8076 load since the call will kill it anyway. */
8077 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8078 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8079 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8083 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8084 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8091 /* Output a move from arm registers to an fpa registers.
8092 OPERANDS[0] is an fpa register.
8093 OPERANDS[1] is the first registers of an arm register pair. */
8095 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8097 int arm_reg0
= REGNO (operands
[1]);
8100 if (arm_reg0
== IP_REGNUM
)
8103 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8104 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8105 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8107 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8108 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8113 /* Output a move from an fpa register to arm registers.
8114 OPERANDS[0] is the first registers of an arm register pair.
8115 OPERANDS[1] is an fpa register. */
8117 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8119 int arm_reg0
= REGNO (operands
[0]);
8122 if (arm_reg0
== IP_REGNUM
)
8125 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8126 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8127 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8129 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8130 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8134 /* Output a move from arm registers to arm registers of a long double
8135 OPERANDS[0] is the destination.
8136 OPERANDS[1] is the source. */
8138 output_mov_long_double_arm_from_arm (rtx
*operands
)
8140 /* We have to be careful here because the two might overlap. */
8141 int dest_start
= REGNO (operands
[0]);
8142 int src_start
= REGNO (operands
[1]);
8146 if (dest_start
< src_start
)
8148 for (i
= 0; i
< 3; i
++)
8150 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8151 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8152 output_asm_insn ("mov%?\t%0, %1", ops
);
8157 for (i
= 2; i
>= 0; i
--)
8159 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8160 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8161 output_asm_insn ("mov%?\t%0, %1", ops
);
8169 /* Output a move from arm registers to an fpa registers.
8170 OPERANDS[0] is an fpa register.
8171 OPERANDS[1] is the first registers of an arm register pair. */
8173 output_mov_double_fpa_from_arm (rtx
*operands
)
8175 int arm_reg0
= REGNO (operands
[1]);
8178 if (arm_reg0
== IP_REGNUM
)
8181 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8182 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8183 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8184 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8188 /* Output a move from an fpa register to arm registers.
8189 OPERANDS[0] is the first registers of an arm register pair.
8190 OPERANDS[1] is an fpa register. */
8192 output_mov_double_arm_from_fpa (rtx
*operands
)
8194 int arm_reg0
= REGNO (operands
[0]);
8197 if (arm_reg0
== IP_REGNUM
)
8200 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8201 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8202 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8203 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8207 /* Output a move between double words.
8208 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8209 or MEM<-REG and all MEMs must be offsettable addresses. */
8211 output_move_double (rtx
*operands
)
8213 enum rtx_code code0
= GET_CODE (operands
[0]);
8214 enum rtx_code code1
= GET_CODE (operands
[1]);
8219 int reg0
= REGNO (operands
[0]);
8221 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8225 int reg1
= REGNO (operands
[1]);
8226 if (reg1
== IP_REGNUM
)
8229 /* Ensure the second source is not overwritten. */
8230 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
8231 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
8233 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
8235 else if (code1
== CONST_VECTOR
)
8237 HOST_WIDE_INT hint
= 0;
8239 switch (GET_MODE (operands
[1]))
8242 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
8243 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
8247 if (BYTES_BIG_ENDIAN
)
8249 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8251 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8255 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8257 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8260 otherops
[1] = GEN_INT (hint
);
8263 if (BYTES_BIG_ENDIAN
)
8265 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8267 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8271 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8273 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8276 operands
[1] = GEN_INT (hint
);
8280 if (BYTES_BIG_ENDIAN
)
8282 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8284 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8286 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8288 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8292 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8294 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8296 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8298 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8301 otherops
[1] = GEN_INT (hint
);
8304 if (BYTES_BIG_ENDIAN
)
8306 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8308 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8310 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8312 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8316 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8318 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8320 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8322 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8325 operands
[1] = GEN_INT (hint
);
8331 output_mov_immediate (operands
);
8332 output_mov_immediate (otherops
);
8334 else if (code1
== CONST_DOUBLE
)
8336 if (GET_MODE (operands
[1]) == DFmode
)
8341 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
8342 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
8343 otherops
[1] = GEN_INT (l
[1]);
8344 operands
[1] = GEN_INT (l
[0]);
8346 else if (GET_MODE (operands
[1]) != VOIDmode
)
8348 else if (WORDS_BIG_ENDIAN
)
8350 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8351 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8355 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8356 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8359 output_mov_immediate (operands
);
8360 output_mov_immediate (otherops
);
8362 else if (code1
== CONST_INT
)
8364 #if HOST_BITS_PER_WIDE_INT > 32
8365 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8366 what the upper word is. */
8367 if (WORDS_BIG_ENDIAN
)
8369 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8370 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8374 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8375 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8378 /* Sign extend the intval into the high-order word. */
8379 if (WORDS_BIG_ENDIAN
)
8381 otherops
[1] = operands
[1];
8382 operands
[1] = (INTVAL (operands
[1]) < 0
8383 ? constm1_rtx
: const0_rtx
);
8386 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
8388 output_mov_immediate (otherops
);
8389 output_mov_immediate (operands
);
8391 else if (code1
== MEM
)
8393 switch (GET_CODE (XEXP (operands
[1], 0)))
8396 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8401 abort (); /* Should never happen now. */
8402 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8406 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8410 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8415 abort (); /* Should never happen now. */
8416 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8421 otherops
[0] = operands
[0];
8422 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8423 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8425 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8427 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8429 /* Registers overlap so split out the increment. */
8430 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8431 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8434 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8438 /* We only allow constant increments, so this is safe. */
8439 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8445 output_asm_insn ("adr%?\t%0, %1", operands
);
8446 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8450 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8451 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8453 otherops
[0] = operands
[0];
8454 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8455 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8457 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8459 if (GET_CODE (otherops
[2]) == CONST_INT
)
8461 switch ((int) INTVAL (otherops
[2]))
8464 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8467 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8470 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8475 && (GET_CODE (otherops
[2]) == REG
8476 || (GET_CODE (otherops
[2]) == CONST_INT
8477 && INTVAL (otherops
[2]) > -256
8478 && INTVAL (otherops
[2]) < 256)))
8480 if (reg_overlap_mentioned_p (otherops
[0],
8483 /* Swap base and index registers over to
8484 avoid a conflict. */
8485 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8486 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8489 /* If both registers conflict, it will usually
8490 have been fixed by a splitter. */
8491 if (reg_overlap_mentioned_p (otherops
[0],
8494 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8495 output_asm_insn ("ldr%?d\t%0, [%1]",
8501 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8506 if (GET_CODE (otherops
[2]) == CONST_INT
)
8508 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8509 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8511 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8514 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8517 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8519 return "ldm%?ia\t%0, %M0";
8523 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8524 /* Take care of overlapping base/data reg. */
8525 if (reg_mentioned_p (operands
[0], operands
[1]))
8527 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8528 output_asm_insn ("ldr%?\t%0, %1", operands
);
8532 output_asm_insn ("ldr%?\t%0, %1", operands
);
8533 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8539 abort (); /* Constraints should prevent this. */
8541 else if (code0
== MEM
&& code1
== REG
)
8543 if (REGNO (operands
[1]) == IP_REGNUM
)
8546 switch (GET_CODE (XEXP (operands
[0], 0)))
8549 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8554 abort (); /* Should never happen now. */
8555 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8559 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8563 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8568 abort (); /* Should never happen now. */
8569 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8574 otherops
[0] = operands
[1];
8575 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8576 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8578 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8579 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8581 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8585 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8586 if (GET_CODE (otherops
[2]) == CONST_INT
)
8588 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8591 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8595 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8599 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8604 && (GET_CODE (otherops
[2]) == REG
8605 || (GET_CODE (otherops
[2]) == CONST_INT
8606 && INTVAL (otherops
[2]) > -256
8607 && INTVAL (otherops
[2]) < 256)))
8609 otherops
[0] = operands
[1];
8610 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8611 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8617 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8618 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8619 output_asm_insn ("str%?\t%1, %0", operands
);
8620 output_asm_insn ("str%?\t%1, %0", otherops
);
8624 /* Constraints should prevent this. */
8631 /* Output an arbitrary MOV reg, #n.
8632 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8634 output_mov_immediate (rtx
*operands
)
8636 HOST_WIDE_INT n
= INTVAL (operands
[1]);
8638 /* Try to use one MOV. */
8639 if (const_ok_for_arm (n
))
8640 output_asm_insn ("mov%?\t%0, %1", operands
);
8642 /* Try to use one MVN. */
8643 else if (const_ok_for_arm (~n
))
8645 operands
[1] = GEN_INT (~n
);
8646 output_asm_insn ("mvn%?\t%0, %1", operands
);
8653 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8654 for (i
= 0; i
< 32; i
++)
8658 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
8659 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
8661 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
8667 /* Output an ADD r, s, #n where n may be too big for one instruction.
8668 If adding zero to one register, output nothing. */
8670 output_add_immediate (rtx
*operands
)
8672 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8674 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8677 output_multi_immediate (operands
,
8678 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8681 output_multi_immediate (operands
,
8682 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8689 /* Output a multiple immediate operation.
8690 OPERANDS is the vector of operands referred to in the output patterns.
8691 INSTR1 is the output pattern to use for the first constant.
8692 INSTR2 is the output pattern to use for subsequent constants.
8693 IMMED_OP is the index of the constant slot in OPERANDS.
8694 N is the constant value. */
8696 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8697 int immed_op
, HOST_WIDE_INT n
)
8699 #if HOST_BITS_PER_WIDE_INT > 32
8705 /* Quick and easy output. */
8706 operands
[immed_op
] = const0_rtx
;
8707 output_asm_insn (instr1
, operands
);
8712 const char * instr
= instr1
;
8714 /* Note that n is never zero here (which would give no output). */
8715 for (i
= 0; i
< 32; i
+= 2)
8719 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8720 output_asm_insn (instr
, operands
);
8730 /* Return the appropriate ARM instruction for the operation code.
8731 The returned result should not be overwritten. OP is the rtx of the
8732 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8735 arithmetic_instr (rtx op
, int shift_first_arg
)
8737 switch (GET_CODE (op
))
8743 return shift_first_arg
? "rsb" : "sub";
8759 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8760 for the operation code. The returned result should not be overwritten.
8761 OP is the rtx code of the shift.
8762 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8765 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8768 enum rtx_code code
= GET_CODE (op
);
8770 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
8772 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8773 *amountp
= INTVAL (XEXP (op
, 1));
8796 /* We never have to worry about the amount being other than a
8797 power of 2, since this case can never be reloaded from a reg. */
8799 *amountp
= int_log2 (*amountp
);
8810 /* This is not 100% correct, but follows from the desire to merge
8811 multiplication by a power of 2 with the recognizer for a
8812 shift. >=32 is not a valid shift for "asl", so we must try and
8813 output a shift that produces the correct arithmetical result.
8814 Using lsr #32 is identical except for the fact that the carry bit
8815 is not set correctly if we set the flags; but we never use the
8816 carry bit from such an operation, so we can ignore that. */
8817 if (code
== ROTATERT
)
8818 /* Rotate is just modulo 32. */
8820 else if (*amountp
!= (*amountp
& 31))
8827 /* Shifts of 0 are no-ops. */
8835 /* Obtain the shift from the POWER of two. */
8837 static HOST_WIDE_INT
8838 int_log2 (HOST_WIDE_INT power
)
8840 HOST_WIDE_INT shift
= 0;
8842 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8852 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8853 /bin/as is horribly restrictive. */
8854 #define MAX_ASCII_LEN 51
8857 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8862 fputs ("\t.ascii\t\"", stream
);
8864 for (i
= 0; i
< len
; i
++)
8868 if (len_so_far
>= MAX_ASCII_LEN
)
8870 fputs ("\"\n\t.ascii\t\"", stream
);
8877 fputs ("\\t", stream
);
8882 fputs ("\\f", stream
);
8887 fputs ("\\b", stream
);
8892 fputs ("\\r", stream
);
8896 case TARGET_NEWLINE
:
8897 fputs ("\\n", stream
);
8899 if ((c
>= ' ' && c
<= '~')
8901 /* This is a good place for a line break. */
8902 len_so_far
= MAX_ASCII_LEN
;
8909 putc ('\\', stream
);
8914 if (c
>= ' ' && c
<= '~')
8921 fprintf (stream
, "\\%03o", c
);
8928 fputs ("\"\n", stream
);
8931 /* Compute the register sabe mask for registers 0 through 12
8932 inclusive. This code is used by arm_compute_save_reg_mask. */
8933 static unsigned long
8934 arm_compute_save_reg0_reg12_mask (void)
8936 unsigned long func_type
= arm_current_func_type ();
8937 unsigned int save_reg_mask
= 0;
8940 if (IS_INTERRUPT (func_type
))
8942 unsigned int max_reg
;
8943 /* Interrupt functions must not corrupt any registers,
8944 even call clobbered ones. If this is a leaf function
8945 we can just examine the registers used by the RTL, but
8946 otherwise we have to assume that whatever function is
8947 called might clobber anything, and so we have to save
8948 all the call-clobbered registers as well. */
8949 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8950 /* FIQ handlers have registers r8 - r12 banked, so
8951 we only need to check r0 - r7, Normal ISRs only
8952 bank r14 and r15, so we must check up to r12.
8953 r13 is the stack pointer which is always preserved,
8954 so we do not need to consider it here. */
8959 for (reg
= 0; reg
<= max_reg
; reg
++)
8960 if (regs_ever_live
[reg
]
8961 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8962 save_reg_mask
|= (1 << reg
);
8966 /* In the normal case we only need to save those registers
8967 which are call saved and which are used by this function. */
8968 for (reg
= 0; reg
<= 10; reg
++)
8969 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8970 save_reg_mask
|= (1 << reg
);
8972 /* Handle the frame pointer as a special case. */
8973 if (! TARGET_APCS_FRAME
8974 && ! frame_pointer_needed
8975 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8976 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8977 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8979 /* If we aren't loading the PIC register,
8980 don't stack it even though it may be live. */
8982 && ! TARGET_SINGLE_PIC_BASE
8983 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
8984 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8987 return save_reg_mask
;
8990 /* Compute a bit mask of which registers need to be
8991 saved on the stack for the current function. */
8993 static unsigned long
8994 arm_compute_save_reg_mask (void)
8996 unsigned int save_reg_mask
= 0;
8997 unsigned long func_type
= arm_current_func_type ();
8999 if (IS_NAKED (func_type
))
9000 /* This should never really happen. */
9003 /* If we are creating a stack frame, then we must save the frame pointer,
9004 IP (which will hold the old stack pointer), LR and the PC. */
9005 if (frame_pointer_needed
)
9007 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9012 /* Volatile functions do not return, so there
9013 is no need to save any other registers. */
9014 if (IS_VOLATILE (func_type
))
9015 return save_reg_mask
;
9017 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9019 /* Decide if we need to save the link register.
9020 Interrupt routines have their own banked link register,
9021 so they never need to save it.
9022 Otherwise if we do not use the link register we do not need to save
9023 it. If we are pushing other registers onto the stack however, we
9024 can save an instruction in the epilogue by pushing the link register
9025 now and then popping it back into the PC. This incurs extra memory
9026 accesses though, so we only do it when optimizing for size, and only
9027 if we know that we will not need a fancy return sequence. */
9028 if (regs_ever_live
[LR_REGNUM
]
9031 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
9032 save_reg_mask
|= 1 << LR_REGNUM
;
9034 if (cfun
->machine
->lr_save_eliminated
)
9035 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9037 if (TARGET_REALLY_IWMMXT
9038 && ((bit_count (save_reg_mask
)
9039 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9043 /* The total number of registers that are going to be pushed
9044 onto the stack is odd. We need to ensure that the stack
9045 is 64-bit aligned before we start to save iWMMXt registers,
9046 and also before we start to create locals. (A local variable
9047 might be a double or long long which we will load/store using
9048 an iWMMXt instruction). Therefore we need to push another
9049 ARM register, so that the stack will be 64-bit aligned. We
9050 try to avoid using the arg registers (r0 -r3) as they might be
9051 used to pass values in a tail call. */
9052 for (reg
= 4; reg
<= 12; reg
++)
9053 if ((save_reg_mask
& (1 << reg
)) == 0)
9057 save_reg_mask
|= (1 << reg
);
9060 cfun
->machine
->sibcall_blocked
= 1;
9061 save_reg_mask
|= (1 << 3);
9065 return save_reg_mask
;
9069 /* Return the number of bytes required to save VFP registers. */
9071 arm_get_vfp_saved_size (void)
9078 /* Space for saved VFP registers. */
9079 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9082 for (regno
= FIRST_VFP_REGNUM
;
9083 regno
< LAST_VFP_REGNUM
;
9086 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9087 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9091 /* Workaround ARM10 VFPr1 bug. */
9092 if (count
== 2 && !arm_arch6
)
9094 saved
+= count
* 8 + 4;
9103 if (count
== 2 && !arm_arch6
)
9105 saved
+= count
* 8 + 4;
9112 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9113 everything bar the final return instruction. */
9115 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9117 char conditional
[10];
9120 unsigned long live_regs_mask
;
9121 unsigned long func_type
;
9122 arm_stack_offsets
*offsets
;
9124 func_type
= arm_current_func_type ();
9126 if (IS_NAKED (func_type
))
9129 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9131 /* If this function was declared non-returning, and we have
9132 found a tail call, then we have to trust that the called
9133 function won't return. */
9138 /* Otherwise, trap an attempted return by aborting. */
9140 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9142 assemble_external_libcall (ops
[1]);
9143 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9149 if (current_function_calls_alloca
&& !really_return
)
9152 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9154 return_used_this_function
= 1;
9156 live_regs_mask
= arm_compute_save_reg_mask ();
9160 const char * return_reg
;
9162 /* If we do not have any special requirements for function exit
9163 (eg interworking, or ISR) then we can load the return address
9164 directly into the PC. Otherwise we must load it into LR. */
9166 && ! TARGET_INTERWORK
)
9167 return_reg
= reg_names
[PC_REGNUM
];
9169 return_reg
= reg_names
[LR_REGNUM
];
9171 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9173 /* There are three possible reasons for the IP register
9174 being saved. 1) a stack frame was created, in which case
9175 IP contains the old stack pointer, or 2) an ISR routine
9176 corrupted it, or 3) it was saved to align the stack on
9177 iWMMXt. In case 1, restore IP into SP, otherwise just
9179 if (frame_pointer_needed
)
9181 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9182 live_regs_mask
|= (1 << SP_REGNUM
);
9186 if (! IS_INTERRUPT (func_type
)
9187 && ! TARGET_REALLY_IWMMXT
)
9192 /* On some ARM architectures it is faster to use LDR rather than
9193 LDM to load a single register. On other architectures, the
9194 cost is the same. In 26 bit mode, or for exception handlers,
9195 we have to use LDM to load the PC so that the CPSR is also
9197 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9199 if (live_regs_mask
== (unsigned int)(1 << reg
))
9202 if (reg
<= LAST_ARM_REGNUM
9203 && (reg
!= LR_REGNUM
9205 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
9207 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9208 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9215 /* Generate the load multiple instruction to restore the
9216 registers. Note we can get here, even if
9217 frame_pointer_needed is true, but only if sp already
9218 points to the base of the saved core registers. */
9219 if (live_regs_mask
& (1 << SP_REGNUM
))
9221 unsigned HOST_WIDE_INT stack_adjust
;
9223 offsets
= arm_get_frame_offsets ();
9224 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9225 if (stack_adjust
!= 0 && stack_adjust
!= 4)
9228 if (stack_adjust
&& arm_arch5
)
9229 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9232 /* If we can't use ldmib (SA110 bug), then try to pop r3
9235 live_regs_mask
|= 1 << 3;
9236 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9240 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9242 p
= instr
+ strlen (instr
);
9244 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9245 if (live_regs_mask
& (1 << reg
))
9247 int l
= strlen (reg_names
[reg
]);
9253 memcpy (p
, ", ", 2);
9257 memcpy (p
, "%|", 2);
9258 memcpy (p
+ 2, reg_names
[reg
], l
);
9262 if (live_regs_mask
& (1 << LR_REGNUM
))
9264 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9265 /* Decide if we need to add the ^ symbol to the end of the
9266 register list. This causes the saved condition codes
9267 register to be copied into the current condition codes
9268 register. We do the copy if we are conforming to the 32-bit
9269 ABI and this is an interrupt function, or if we are
9270 conforming to the 26-bit ABI. There is a special case for
9271 the 26-bit ABI however, which is if we are writing back the
9272 stack pointer but not loading the PC. In this case adding
9273 the ^ symbol would create a type 2 LDM instruction, where
9274 writeback is UNPREDICTABLE. We are safe in leaving the ^
9275 character off in this case however, since the actual return
9276 instruction will be a MOVS which will restore the CPSR. */
9277 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
9278 || (! TARGET_APCS_32
&& really_return
))
9285 output_asm_insn (instr
, & operand
);
9287 /* See if we need to generate an extra instruction to
9288 perform the actual function return. */
9290 && func_type
!= ARM_FT_INTERWORKED
9291 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9293 /* The return has already been handled
9294 by loading the LR into the PC. */
9301 switch ((int) ARM_FUNC_TYPE (func_type
))
9305 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9308 case ARM_FT_INTERWORKED
:
9309 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9312 case ARM_FT_EXCEPTION
:
9313 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9317 /* ARMv5 implementations always provide BX, so interworking
9318 is the default unless APCS-26 is in use. */
9319 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
9320 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9322 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
9323 conditional
, TARGET_APCS_32
? "" : "s");
9327 output_asm_insn (instr
, & operand
);
9333 /* Write the function name into the code section, directly preceding
9334 the function prologue.
9336 Code will be output similar to this:
9338 .ascii "arm_poke_function_name", 0
9341 .word 0xff000000 + (t1 - t0)
9342 arm_poke_function_name
9344 stmfd sp!, {fp, ip, lr, pc}
9347 When performing a stack backtrace, code can inspect the value
9348 of 'pc' stored at 'fp' + 0. If the trace function then looks
9349 at location pc - 12 and the top 8 bits are set, then we know
9350 that there is a function name embedded immediately preceding this
9351 location and has length ((pc[-3]) & 0xff000000).
9353 We assume that pc is declared as a pointer to an unsigned long.
9355 It is of no benefit to output the function name if we are assembling
9356 a leaf function. These function types will not contain a stack
9357 backtrace structure, therefore it is not possible to determine the
9360 arm_poke_function_name (FILE *stream
, const char *name
)
9362 unsigned long alignlength
;
9363 unsigned long length
;
9366 length
= strlen (name
) + 1;
9367 alignlength
= ROUND_UP_WORD (length
);
9369 ASM_OUTPUT_ASCII (stream
, name
, length
);
9370 ASM_OUTPUT_ALIGN (stream
, 2);
9371 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9372 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9375 /* Place some comments into the assembler stream
9376 describing the current function. */
9378 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9380 unsigned long func_type
;
9384 thumb_output_function_prologue (f
, frame_size
);
9389 if (arm_ccfsm_state
|| arm_target_insn
)
9392 func_type
= arm_current_func_type ();
9394 switch ((int) ARM_FUNC_TYPE (func_type
))
9399 case ARM_FT_INTERWORKED
:
9400 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9402 case ARM_FT_EXCEPTION_HANDLER
:
9403 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
9406 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9409 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9411 case ARM_FT_EXCEPTION
:
9412 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9416 if (IS_NAKED (func_type
))
9417 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9419 if (IS_VOLATILE (func_type
))
9420 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9422 if (IS_NESTED (func_type
))
9423 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9425 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9426 current_function_args_size
,
9427 current_function_pretend_args_size
, frame_size
);
9429 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9430 frame_pointer_needed
,
9431 cfun
->machine
->uses_anonymous_args
);
9433 if (cfun
->machine
->lr_save_eliminated
)
9434 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9436 #ifdef AOF_ASSEMBLER
9438 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9441 return_used_this_function
= 0;
9445 arm_output_epilogue (rtx sibling
)
9448 unsigned long saved_regs_mask
;
9449 unsigned long func_type
;
9450 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9451 frame that is $fp + 4 for a non-variadic function. */
9452 int floats_offset
= 0;
9454 FILE * f
= asm_out_file
;
9455 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9456 unsigned int lrm_count
= 0;
9457 int really_return
= (sibling
== NULL
);
9459 arm_stack_offsets
*offsets
;
9461 /* If we have already generated the return instruction
9462 then it is futile to generate anything else. */
9463 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9466 func_type
= arm_current_func_type ();
9468 if (IS_NAKED (func_type
))
9469 /* Naked functions don't have epilogues. */
9472 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9476 /* A volatile function should never return. Call abort. */
9477 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9478 assemble_external_libcall (op
);
9479 output_asm_insn ("bl\t%a0", &op
);
9484 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
9486 /* If we are throwing an exception, then we really must
9487 be doing a return, so we can't tail-call. */
9490 offsets
= arm_get_frame_offsets ();
9491 saved_regs_mask
= arm_compute_save_reg_mask ();
9494 lrm_count
= bit_count (saved_regs_mask
);
9496 floats_offset
= offsets
->saved_args
;
9497 /* Compute how far away the floats will be. */
9498 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9499 if (saved_regs_mask
& (1 << reg
))
9502 if (frame_pointer_needed
)
9504 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9505 int vfp_offset
= offsets
->frame
;
9507 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9509 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9510 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9512 floats_offset
+= 12;
9513 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9514 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9519 start_reg
= LAST_FPA_REGNUM
;
9521 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9523 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9525 floats_offset
+= 12;
9527 /* We can't unstack more than four registers at once. */
9528 if (start_reg
- reg
== 3)
9530 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9531 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9532 start_reg
= reg
- 1;
9537 if (reg
!= start_reg
)
9538 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9539 reg
+ 1, start_reg
- reg
,
9540 FP_REGNUM
, floats_offset
- vfp_offset
);
9541 start_reg
= reg
- 1;
9545 /* Just in case the last register checked also needs unstacking. */
9546 if (reg
!= start_reg
)
9547 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9548 reg
+ 1, start_reg
- reg
,
9549 FP_REGNUM
, floats_offset
- vfp_offset
);
9552 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9556 /* The fldmx insn does not have base+offset addressing modes,
9557 so we use IP to hold the address. */
9558 saved_size
= arm_get_vfp_saved_size ();
9562 floats_offset
+= saved_size
;
9563 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9564 FP_REGNUM
, floats_offset
- vfp_offset
);
9566 start_reg
= FIRST_VFP_REGNUM
;
9567 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9569 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9570 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9572 if (start_reg
!= reg
)
9573 arm_output_fldmx (f
, IP_REGNUM
,
9574 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9575 (reg
- start_reg
) / 2);
9576 start_reg
= reg
+ 2;
9579 if (start_reg
!= reg
)
9580 arm_output_fldmx (f
, IP_REGNUM
,
9581 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9582 (reg
- start_reg
) / 2);
9587 /* The frame pointer is guaranteed to be non-double-word aligned.
9588 This is because it is set to (old_stack_pointer - 4) and the
9589 old_stack_pointer was double word aligned. Thus the offset to
9590 the iWMMXt registers to be loaded must also be non-double-word
9591 sized, so that the resultant address *is* double-word aligned.
9592 We can ignore floats_offset since that was already included in
9593 the live_regs_mask. */
9594 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9596 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9597 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9599 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9600 reg
, FP_REGNUM
, lrm_count
* 4);
9605 /* saved_regs_mask should contain the IP, which at the time of stack
9606 frame generation actually contains the old stack pointer. So a
9607 quick way to unwind the stack is just pop the IP register directly
9608 into the stack pointer. */
9609 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
9611 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9612 saved_regs_mask
|= (1 << SP_REGNUM
);
9614 /* There are two registers left in saved_regs_mask - LR and PC. We
9615 only need to restore the LR register (the return address), but to
9616 save time we can load it directly into the PC, unless we need a
9617 special function exit sequence, or we are not really returning. */
9618 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
9619 /* Delete the LR from the register mask, so that the LR on
9620 the stack is loaded into the PC in the register mask. */
9621 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9623 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9625 /* We must use SP as the base register, because SP is one of the
9626 registers being restored. If an interrupt or page fault
9627 happens in the ldm instruction, the SP might or might not
9628 have been restored. That would be bad, as then SP will no
9629 longer indicate the safe area of stack, and we can get stack
9630 corruption. Using SP as the base register means that it will
9631 be reset correctly to the original value, should an interrupt
9632 occur. If the stack pointer already points at the right
9633 place, then omit the subtraction. */
9634 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9635 || current_function_calls_alloca
)
9636 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9637 4 * bit_count (saved_regs_mask
));
9638 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9640 if (IS_INTERRUPT (func_type
))
9641 /* Interrupt handlers will have pushed the
9642 IP onto the stack, so restore it now. */
9643 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9647 /* Restore stack pointer if necessary. */
9648 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9650 operands
[0] = operands
[1] = stack_pointer_rtx
;
9651 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9652 output_add_immediate (operands
);
9655 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9657 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9658 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9659 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9664 start_reg
= FIRST_FPA_REGNUM
;
9666 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9668 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9670 if (reg
- start_reg
== 3)
9672 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9673 start_reg
, SP_REGNUM
);
9674 start_reg
= reg
+ 1;
9679 if (reg
!= start_reg
)
9680 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9681 start_reg
, reg
- start_reg
,
9684 start_reg
= reg
+ 1;
9688 /* Just in case the last register checked also needs unstacking. */
9689 if (reg
!= start_reg
)
9690 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9691 start_reg
, reg
- start_reg
, SP_REGNUM
);
9694 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9696 start_reg
= FIRST_VFP_REGNUM
;
9697 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9699 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9700 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9702 if (start_reg
!= reg
)
9703 arm_output_fldmx (f
, SP_REGNUM
,
9704 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9705 (reg
- start_reg
) / 2);
9706 start_reg
= reg
+ 2;
9709 if (start_reg
!= reg
)
9710 arm_output_fldmx (f
, SP_REGNUM
,
9711 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9712 (reg
- start_reg
) / 2);
9715 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9716 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9717 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9719 /* If we can, restore the LR into the PC. */
9720 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9722 && current_function_pretend_args_size
== 0
9723 && saved_regs_mask
& (1 << LR_REGNUM
))
9725 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9726 saved_regs_mask
|= (1 << PC_REGNUM
);
9729 /* Load the registers off the stack. If we only have one register
9730 to load use the LDR instruction - it is faster. */
9731 if (saved_regs_mask
== (1 << LR_REGNUM
))
9733 /* The exception handler ignores the LR, so we do
9734 not really need to load it off the stack. */
9736 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
9738 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9740 else if (saved_regs_mask
)
9742 if (saved_regs_mask
& (1 << SP_REGNUM
))
9743 /* Note - write back to the stack register is not enabled
9744 (ie "ldmfd sp!..."). We know that the stack pointer is
9745 in the list of registers and if we add writeback the
9746 instruction becomes UNPREDICTABLE. */
9747 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9749 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9752 if (current_function_pretend_args_size
)
9754 /* Unwind the pre-pushed regs. */
9755 operands
[0] = operands
[1] = stack_pointer_rtx
;
9756 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9757 output_add_immediate (operands
);
9762 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9763 && current_function_pretend_args_size
== 0
9764 && saved_regs_mask
& (1 << PC_REGNUM
)))
9767 /* Generate the return instruction. */
9768 switch ((int) ARM_FUNC_TYPE (func_type
))
9770 case ARM_FT_EXCEPTION_HANDLER
:
9771 /* Even in 26-bit mode we do a mov (rather than a movs)
9772 because we don't have the PSR bits set in the address. */
9773 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
9778 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9781 case ARM_FT_EXCEPTION
:
9782 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9785 case ARM_FT_INTERWORKED
:
9786 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9790 if (frame_pointer_needed
)
9791 /* If we used the frame pointer then the return address
9792 will have been loaded off the stack directly into the
9793 PC, so there is no need to issue a MOV instruction
9796 else if (current_function_pretend_args_size
== 0
9797 && (saved_regs_mask
& (1 << LR_REGNUM
)))
9798 /* Similarly we may have been able to load LR into the PC
9799 even if we did not create a stack frame. */
9801 else if (TARGET_APCS_32
)
9802 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9804 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9812 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9813 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9815 arm_stack_offsets
*offsets
;
9819 /* ??? Probably not safe to set this here, since it assumes that a
9820 function will be emitted as assembly immediately after we generate
9821 RTL for it. This does not happen for inline functions. */
9822 return_used_this_function
= 0;
9826 /* We need to take into account any stack-frame rounding. */
9827 offsets
= arm_get_frame_offsets ();
9829 if (use_return_insn (FALSE
, NULL
)
9830 && return_used_this_function
9831 && offsets
->saved_regs
!= offsets
->outgoing_args
9832 && !frame_pointer_needed
)
9835 /* Reset the ARM-specific per-function variables. */
9836 after_arm_reorg
= 0;
9840 /* Generate and emit an insn that we will recognize as a push_multi.
9841 Unfortunately, since this insn does not reflect very well the actual
9842 semantics of the operation, we need to annotate the insn for the benefit
9843 of DWARF2 frame unwind information. */
9845 emit_multi_reg_push (int mask
)
9852 int dwarf_par_index
;
9855 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9856 if (mask
& (1 << i
))
9859 if (num_regs
== 0 || num_regs
> 16)
9862 /* We don't record the PC in the dwarf frame information. */
9863 num_dwarf_regs
= num_regs
;
9864 if (mask
& (1 << PC_REGNUM
))
9867 /* For the body of the insn we are going to generate an UNSPEC in
9868 parallel with several USEs. This allows the insn to be recognized
9869 by the push_multi pattern in the arm.md file. The insn looks
9870 something like this:
9873 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9874 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9875 (use (reg:SI 11 fp))
9876 (use (reg:SI 12 ip))
9877 (use (reg:SI 14 lr))
9878 (use (reg:SI 15 pc))
9881 For the frame note however, we try to be more explicit and actually
9882 show each register being stored into the stack frame, plus a (single)
9883 decrement of the stack pointer. We do it this way in order to be
9884 friendly to the stack unwinding code, which only wants to see a single
9885 stack decrement per instruction. The RTL we generate for the note looks
9886 something like this:
9889 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9890 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9891 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9892 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9893 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9896 This sequence is used both by the code to support stack unwinding for
9897 exceptions handlers and the code to generate dwarf2 frame debugging. */
9899 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9900 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9901 dwarf_par_index
= 1;
9903 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9905 if (mask
& (1 << i
))
9907 reg
= gen_rtx_REG (SImode
, i
);
9910 = gen_rtx_SET (VOIDmode
,
9911 gen_rtx_MEM (BLKmode
,
9912 gen_rtx_PRE_DEC (BLKmode
,
9913 stack_pointer_rtx
)),
9914 gen_rtx_UNSPEC (BLKmode
,
9920 tmp
= gen_rtx_SET (VOIDmode
,
9921 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
9923 RTX_FRAME_RELATED_P (tmp
) = 1;
9924 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9932 for (j
= 1, i
++; j
< num_regs
; i
++)
9934 if (mask
& (1 << i
))
9936 reg
= gen_rtx_REG (SImode
, i
);
9938 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9942 tmp
= gen_rtx_SET (VOIDmode
,
9943 gen_rtx_MEM (SImode
,
9944 plus_constant (stack_pointer_rtx
,
9947 RTX_FRAME_RELATED_P (tmp
) = 1;
9948 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
9955 par
= emit_insn (par
);
9957 tmp
= gen_rtx_SET (SImode
,
9959 gen_rtx_PLUS (SImode
,
9961 GEN_INT (-4 * num_regs
)));
9962 RTX_FRAME_RELATED_P (tmp
) = 1;
9963 XVECEXP (dwarf
, 0, 0) = tmp
;
9965 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9971 emit_sfm (int base_reg
, int count
)
9978 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9979 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
9981 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9984 = gen_rtx_SET (VOIDmode
,
9985 gen_rtx_MEM (BLKmode
,
9986 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9987 gen_rtx_UNSPEC (BLKmode
,
9991 = gen_rtx_SET (VOIDmode
,
9992 gen_rtx_MEM (XFmode
,
9993 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9995 RTX_FRAME_RELATED_P (tmp
) = 1;
9996 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
9998 for (i
= 1; i
< count
; i
++)
10000 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10001 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10003 tmp
= gen_rtx_SET (VOIDmode
,
10004 gen_rtx_MEM (XFmode
,
10005 gen_rtx_PRE_DEC (BLKmode
,
10006 stack_pointer_rtx
)),
10008 RTX_FRAME_RELATED_P (tmp
) = 1;
10009 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
10012 par
= emit_insn (par
);
10013 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10019 /* Compute the distance from register FROM to register TO.
10020 These can be the arg pointer (26), the soft frame pointer (25),
10021 the stack pointer (13) or the hard frame pointer (11).
10022 Typical stack layout looks like this:
10024 old stack pointer -> | |
10027 | | saved arguments for
10028 | | vararg functions
10031 hard FP & arg pointer -> | | \
10039 soft frame pointer -> | | /
10049 current stack pointer -> | | /
10052 For a given function some or all of these stack components
10053 may not be needed, giving rise to the possibility of
10054 eliminating some of the registers.
10056 The values returned by this function must reflect the behavior
10057 of arm_expand_prologue() and arm_compute_save_reg_mask().
10059 The sign of the number returned reflects the direction of stack
10060 growth, so the values are positive for all eliminations except
10061 from the soft frame pointer to the hard frame pointer.
10063 SFP may point just inside the local variables block to ensure correct
10067 /* Calculate stack offsets. These are used to calculate register elimination
10068 offsets and in prologue/epilogue code. */
10070 static arm_stack_offsets
*
10071 arm_get_frame_offsets (void)
10073 struct arm_stack_offsets
*offsets
;
10074 unsigned long func_type
;
10077 HOST_WIDE_INT frame_size
;
10079 offsets
= &cfun
->machine
->stack_offsets
;
10081 /* We need to know if we are a leaf function. Unfortunately, it
10082 is possible to be called after start_sequence has been called,
10083 which causes get_insns to return the insns for the sequence,
10084 not the function, which will cause leaf_function_p to return
10085 the incorrect result.
10087 to know about leaf functions once reload has completed, and the
10088 frame size cannot be changed after that time, so we can safely
10089 use the cached value. */
10091 if (reload_completed
)
10094 /* Initially this is the size of the local variables. It will translated
10095 into an offset once we have determined the size of preceding data. */
10096 frame_size
= ROUND_UP_WORD (get_frame_size ());
10098 leaf
= leaf_function_p ();
10100 /* Space for variadic functions. */
10101 offsets
->saved_args
= current_function_pretend_args_size
;
10103 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10107 unsigned int regno
;
10109 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10111 /* We know that SP will be doubleword aligned on entry, and we must
10112 preserve that condition at any subroutine call. We also require the
10113 soft frame pointer to be doubleword aligned. */
10115 if (TARGET_REALLY_IWMMXT
)
10117 /* Check for the call-saved iWMMXt registers. */
10118 for (regno
= FIRST_IWMMXT_REGNUM
;
10119 regno
<= LAST_IWMMXT_REGNUM
;
10121 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10125 func_type
= arm_current_func_type ();
10126 if (! IS_VOLATILE (func_type
))
10128 /* Space for saved FPA registers. */
10129 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10130 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10133 /* Space for saved VFP registers. */
10134 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10135 saved
+= arm_get_vfp_saved_size ();
10138 else /* TARGET_THUMB */
10145 for (reg
= 8; reg
< 13; reg
++)
10146 if (THUMB_REG_PUSHED_P (reg
))
10149 saved
+= 4 * count_regs
;
10151 for (reg
= 0; reg
<= LAST_LO_REGNUM
; reg
++)
10152 if (THUMB_REG_PUSHED_P (reg
))
10154 if (count_regs
|| ! leaf_function_p ()
10155 || thumb_far_jump_used_p ())
10156 saved
+= 4 * (count_regs
+ 1);
10157 if (TARGET_BACKTRACE
)
10159 if ((count_regs
& 0xFF) == 0 && (regs_ever_live
[3] != 0))
10166 /* Saved registers include the stack frame. */
10167 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10168 offsets
->soft_frame
= offsets
->saved_regs
;
10169 /* A leaf function does not need any stack alignment if it has nothing
10171 if (leaf
&& frame_size
== 0)
10173 offsets
->outgoing_args
= offsets
->soft_frame
;
10177 /* Ensure SFP has the correct alignment. */
10178 if (ARM_DOUBLEWORD_ALIGN
10179 && (offsets
->soft_frame
& 7))
10180 offsets
->soft_frame
+= 4;
10182 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
10183 + current_function_outgoing_args_size
;
10185 if (ARM_DOUBLEWORD_ALIGN
)
10187 /* Ensure SP remains doubleword aligned. */
10188 if (offsets
->outgoing_args
& 7)
10189 offsets
->outgoing_args
+= 4;
10190 if (offsets
->outgoing_args
& 7)
10198 /* Calculate the relative offsets for the different stack pointers. Positive
10199 offsets are in the direction of stack growth. */
10202 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10204 arm_stack_offsets
*offsets
;
10206 offsets
= arm_get_frame_offsets ();
10208 /* OK, now we have enough information to compute the distances.
10209 There must be an entry in these switch tables for each pair
10210 of registers in ELIMINABLE_REGS, even if some of the entries
10211 seem to be redundant or useless. */
10214 case ARG_POINTER_REGNUM
:
10217 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10220 case FRAME_POINTER_REGNUM
:
10221 /* This is the reverse of the soft frame pointer
10222 to hard frame pointer elimination below. */
10223 return offsets
->soft_frame
- offsets
->saved_args
;
10225 case ARM_HARD_FRAME_POINTER_REGNUM
:
10226 /* If there is no stack frame then the hard
10227 frame pointer and the arg pointer coincide. */
10228 if (offsets
->frame
== offsets
->saved_regs
)
10230 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10231 return (frame_pointer_needed
10232 && cfun
->static_chain_decl
!= NULL
10233 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10235 case STACK_POINTER_REGNUM
:
10236 /* If nothing has been pushed on the stack at all
10237 then this will return -4. This *is* correct! */
10238 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10245 case FRAME_POINTER_REGNUM
:
10248 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10251 case ARM_HARD_FRAME_POINTER_REGNUM
:
10252 /* The hard frame pointer points to the top entry in the
10253 stack frame. The soft frame pointer to the bottom entry
10254 in the stack frame. If there is no stack frame at all,
10255 then they are identical. */
10257 return offsets
->frame
- offsets
->soft_frame
;
10259 case STACK_POINTER_REGNUM
:
10260 return offsets
->outgoing_args
- offsets
->soft_frame
;
10268 /* You cannot eliminate from the stack pointer.
10269 In theory you could eliminate from the hard frame
10270 pointer to the stack pointer, but this will never
10271 happen, since if a stack frame is not needed the
10272 hard frame pointer will never be used. */
10278 /* Generate the prologue instructions for entry into an ARM function. */
10280 arm_expand_prologue (void)
10286 unsigned long live_regs_mask
;
10287 unsigned long func_type
;
10289 int saved_pretend_args
= 0;
10290 int saved_regs
= 0;
10291 unsigned int args_to_push
;
10292 arm_stack_offsets
*offsets
;
10294 func_type
= arm_current_func_type ();
10296 /* Naked functions don't have prologues. */
10297 if (IS_NAKED (func_type
))
10300 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10301 args_to_push
= current_function_pretend_args_size
;
10303 /* Compute which register we will have to save onto the stack. */
10304 live_regs_mask
= arm_compute_save_reg_mask ();
10306 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10308 if (frame_pointer_needed
)
10310 if (IS_INTERRUPT (func_type
))
10312 /* Interrupt functions must not corrupt any registers.
10313 Creating a frame pointer however, corrupts the IP
10314 register, so we must push it first. */
10315 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10317 /* Do not set RTX_FRAME_RELATED_P on this insn.
10318 The dwarf stack unwinding code only wants to see one
10319 stack decrement per function, and this is not it. If
10320 this instruction is labeled as being part of the frame
10321 creation sequence then dwarf2out_frame_debug_expr will
10322 abort when it encounters the assignment of IP to FP
10323 later on, since the use of SP here establishes SP as
10324 the CFA register and not IP.
10326 Anyway this instruction is not really part of the stack
10327 frame creation although it is part of the prologue. */
10329 else if (IS_NESTED (func_type
))
10331 /* The Static chain register is the same as the IP register
10332 used as a scratch register during stack frame creation.
10333 To get around this need to find somewhere to store IP
10334 whilst the frame is being created. We try the following
10337 1. The last argument register.
10338 2. A slot on the stack above the frame. (This only
10339 works if the function is not a varargs function).
10340 3. Register r3, after pushing the argument registers
10343 Note - we only need to tell the dwarf2 backend about the SP
10344 adjustment in the second variant; the static chain register
10345 doesn't need to be unwound, as it doesn't contain a value
10346 inherited from the caller. */
10348 if (regs_ever_live
[3] == 0)
10350 insn
= gen_rtx_REG (SImode
, 3);
10351 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10352 insn
= emit_insn (insn
);
10354 else if (args_to_push
== 0)
10357 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10358 insn
= gen_rtx_MEM (SImode
, insn
);
10359 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10360 insn
= emit_insn (insn
);
10364 /* Just tell the dwarf backend that we adjusted SP. */
10365 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10366 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10367 GEN_INT (-fp_offset
)));
10368 RTX_FRAME_RELATED_P (insn
) = 1;
10369 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10370 dwarf
, REG_NOTES (insn
));
10374 /* Store the args on the stack. */
10375 if (cfun
->machine
->uses_anonymous_args
)
10376 insn
= emit_multi_reg_push
10377 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10380 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10381 GEN_INT (- args_to_push
)));
10383 RTX_FRAME_RELATED_P (insn
) = 1;
10385 saved_pretend_args
= 1;
10386 fp_offset
= args_to_push
;
10389 /* Now reuse r3 to preserve IP. */
10390 insn
= gen_rtx_REG (SImode
, 3);
10391 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10392 (void) emit_insn (insn
);
10398 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10399 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10402 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10404 insn
= emit_insn (insn
);
10405 RTX_FRAME_RELATED_P (insn
) = 1;
10410 /* Push the argument registers, or reserve space for them. */
10411 if (cfun
->machine
->uses_anonymous_args
)
10412 insn
= emit_multi_reg_push
10413 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10416 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10417 GEN_INT (- args_to_push
)));
10418 RTX_FRAME_RELATED_P (insn
) = 1;
10421 /* If this is an interrupt service routine, and the link register
10422 is going to be pushed, and we are not creating a stack frame,
10423 (which would involve an extra push of IP and a pop in the epilogue)
10424 subtracting four from LR now will mean that the function return
10425 can be done with a single instruction. */
10426 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10427 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10428 && ! frame_pointer_needed
)
10429 emit_insn (gen_rtx_SET (SImode
,
10430 gen_rtx_REG (SImode
, LR_REGNUM
),
10431 gen_rtx_PLUS (SImode
,
10432 gen_rtx_REG (SImode
, LR_REGNUM
),
10435 if (live_regs_mask
)
10437 insn
= emit_multi_reg_push (live_regs_mask
);
10438 saved_regs
+= bit_count (live_regs_mask
) * 4;
10439 RTX_FRAME_RELATED_P (insn
) = 1;
10443 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10444 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10446 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10447 insn
= gen_rtx_MEM (V2SImode
, insn
);
10448 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10449 gen_rtx_REG (V2SImode
, reg
)));
10450 RTX_FRAME_RELATED_P (insn
) = 1;
10454 if (! IS_VOLATILE (func_type
))
10458 /* Save any floating point call-saved registers used by this
10460 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10462 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10463 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10465 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10466 insn
= gen_rtx_MEM (XFmode
, insn
);
10467 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10468 gen_rtx_REG (XFmode
, reg
)));
10469 RTX_FRAME_RELATED_P (insn
) = 1;
10475 start_reg
= LAST_FPA_REGNUM
;
10477 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10479 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10481 if (start_reg
- reg
== 3)
10483 insn
= emit_sfm (reg
, 4);
10484 RTX_FRAME_RELATED_P (insn
) = 1;
10486 start_reg
= reg
- 1;
10491 if (start_reg
!= reg
)
10493 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10494 RTX_FRAME_RELATED_P (insn
) = 1;
10495 saved_regs
+= (start_reg
- reg
) * 12;
10497 start_reg
= reg
- 1;
10501 if (start_reg
!= reg
)
10503 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10504 saved_regs
+= (start_reg
- reg
) * 12;
10505 RTX_FRAME_RELATED_P (insn
) = 1;
10508 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10510 start_reg
= FIRST_VFP_REGNUM
;
10512 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10514 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10515 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10517 if (start_reg
!= reg
)
10518 saved_regs
+= vfp_emit_fstmx (start_reg
,
10519 (reg
- start_reg
) / 2);
10520 start_reg
= reg
+ 2;
10523 if (start_reg
!= reg
)
10524 saved_regs
+= vfp_emit_fstmx (start_reg
,
10525 (reg
- start_reg
) / 2);
10529 if (frame_pointer_needed
)
10531 /* Create the new frame pointer. */
10532 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10533 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10534 RTX_FRAME_RELATED_P (insn
) = 1;
10536 if (IS_NESTED (func_type
))
10538 /* Recover the static chain register. */
10539 if (regs_ever_live
[3] == 0
10540 || saved_pretend_args
)
10541 insn
= gen_rtx_REG (SImode
, 3);
10542 else /* if (current_function_pretend_args_size == 0) */
10544 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10546 insn
= gen_rtx_MEM (SImode
, insn
);
10549 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10550 /* Add a USE to stop propagate_one_insn() from barfing. */
10551 emit_insn (gen_prologue_use (ip_rtx
));
10555 offsets
= arm_get_frame_offsets ();
10556 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10558 /* This add can produce multiple insns for a large constant, so we
10559 need to get tricky. */
10560 rtx last
= get_last_insn ();
10562 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10563 - offsets
->outgoing_args
);
10565 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10569 last
= last
? NEXT_INSN (last
) : get_insns ();
10570 RTX_FRAME_RELATED_P (last
) = 1;
10572 while (last
!= insn
);
10574 /* If the frame pointer is needed, emit a special barrier that
10575 will prevent the scheduler from moving stores to the frame
10576 before the stack adjustment. */
10577 if (frame_pointer_needed
)
10578 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10579 hard_frame_pointer_rtx
));
10582 /* If we are profiling, make sure no instructions are scheduled before
10583 the call to mcount. Similarly if the user has requested no
10584 scheduling in the prolog. */
10585 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10586 emit_insn (gen_blockage ());
10588 /* If the link register is being kept alive, with the return address in it,
10589 then make sure that it does not get reused by the ce2 pass. */
10590 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10592 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10593 cfun
->machine
->lr_save_eliminated
= 1;
10597 /* If CODE is 'd', then the X is a condition operand and the instruction
10598 should only be executed if the condition is true.
10599 if CODE is 'D', then the X is a condition operand and the instruction
10600 should only be executed if the condition is false: however, if the mode
10601 of the comparison is CCFPEmode, then always execute the instruction -- we
10602 do this because in these circumstances !GE does not necessarily imply LT;
10603 in these cases the instruction pattern will take care to make sure that
10604 an instruction containing %d will follow, thereby undoing the effects of
10605 doing this instruction unconditionally.
10606 If CODE is 'N' then X is a floating point operand that must be negated
10608 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10609 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10611 arm_print_operand (FILE *stream
, rtx x
, int code
)
10616 fputs (ASM_COMMENT_START
, stream
);
10620 fputs (user_label_prefix
, stream
);
10624 fputs (REGISTER_PREFIX
, stream
);
10628 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10630 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
10633 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10635 else if (current_insn_predicate
)
10637 enum arm_cond_code code
;
10642 code
= get_arm_condition_code (current_insn_predicate
);
10643 fputs (arm_condition_codes
[code
], stream
);
10650 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10651 r
= REAL_VALUE_NEGATE (r
);
10652 fprintf (stream
, "%s", fp_const_from_val (&r
));
10657 if (GET_CODE (x
) == CONST_INT
)
10660 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10661 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10665 putc ('~', stream
);
10666 output_addr_const (stream
, x
);
10671 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10674 /* Truncate Cirrus shift counts. */
10676 if (GET_CODE (x
) == CONST_INT
)
10678 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10681 arm_print_operand (stream
, x
, 0);
10685 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10691 const char * shift
= shift_op (x
, &val
);
10695 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10697 arm_print_operand (stream
, XEXP (x
, 1), 0);
10699 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10704 /* An explanation of the 'Q', 'R' and 'H' register operands:
10706 In a pair of registers containing a DI or DF value the 'Q'
10707 operand returns the register number of the register containing
10708 the least significant part of the value. The 'R' operand returns
10709 the register number of the register containing the most
10710 significant part of the value.
10712 The 'H' operand returns the higher of the two register numbers.
10713 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10714 same as the 'Q' operand, since the most significant part of the
10715 value is held in the lower number register. The reverse is true
10716 on systems where WORDS_BIG_ENDIAN is false.
10718 The purpose of these operands is to distinguish between cases
10719 where the endian-ness of the values is important (for example
10720 when they are added together), and cases where the endian-ness
10721 is irrelevant, but the order of register operations is important.
10722 For example when loading a value from memory into a register
10723 pair, the endian-ness does not matter. Provided that the value
10724 from the lower memory address is put into the lower numbered
10725 register, and the value from the higher address is put into the
10726 higher numbered register, the load will work regardless of whether
10727 the value being loaded is big-wordian or little-wordian. The
10728 order of the two register loads can matter however, if the address
10729 of the memory location is actually held in one of the registers
10730 being overwritten by the load. */
10732 if (REGNO (x
) > LAST_ARM_REGNUM
)
10734 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10738 if (REGNO (x
) > LAST_ARM_REGNUM
)
10740 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10744 if (REGNO (x
) > LAST_ARM_REGNUM
)
10746 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10750 asm_fprintf (stream
, "%r",
10751 GET_CODE (XEXP (x
, 0)) == REG
10752 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10756 asm_fprintf (stream
, "{%r-%r}",
10758 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10762 /* CONST_TRUE_RTX means always -- that's the default. */
10763 if (x
== const_true_rtx
)
10766 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10771 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10772 want to do that. */
10773 if (x
== const_true_rtx
)
10776 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10777 (get_arm_condition_code (x
))],
10781 /* Cirrus registers can be accessed in a variety of ways:
10782 single floating point (f)
10783 double floating point (d)
10785 64bit integer (dx). */
10786 case 'W': /* Cirrus register in F mode. */
10787 case 'X': /* Cirrus register in D mode. */
10788 case 'Y': /* Cirrus register in FX mode. */
10789 case 'Z': /* Cirrus register in DX mode. */
10790 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10793 fprintf (stream
, "mv%s%s",
10795 : code
== 'X' ? "d"
10796 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10800 /* Print cirrus register in the mode specified by the register's mode. */
10803 int mode
= GET_MODE (x
);
10805 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10808 fprintf (stream
, "mv%s%s",
10809 mode
== DFmode
? "d"
10810 : mode
== SImode
? "fx"
10811 : mode
== DImode
? "dx"
10812 : "f", reg_names
[REGNO (x
)] + 2);
10818 if (GET_CODE (x
) != REG
10819 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10820 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10821 /* Bad value for wCG register number. */
10824 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10827 /* Print an iWMMXt control register name. */
10829 if (GET_CODE (x
) != CONST_INT
10831 || INTVAL (x
) >= 16)
10832 /* Bad value for wC register number. */
10836 static const char * wc_reg_names
[16] =
10838 "wCID", "wCon", "wCSSF", "wCASF",
10839 "wC4", "wC5", "wC6", "wC7",
10840 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10841 "wC12", "wC13", "wC14", "wC15"
10844 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10848 /* Print a VFP double precision register name. */
10851 int mode
= GET_MODE (x
);
10854 if (mode
!= DImode
&& mode
!= DFmode
)
10857 if (GET_CODE (x
) != REG
10858 || !IS_VFP_REGNUM (REGNO (x
)))
10861 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10865 fprintf (stream
, "d%d", num
>> 1);
10873 if (GET_CODE (x
) == REG
)
10874 asm_fprintf (stream
, "%r", REGNO (x
));
10875 else if (GET_CODE (x
) == MEM
)
10877 output_memory_reference_mode
= GET_MODE (x
);
10878 output_address (XEXP (x
, 0));
10880 else if (GET_CODE (x
) == CONST_DOUBLE
)
10881 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10882 else if (GET_CODE (x
) == NEG
)
10883 abort (); /* This should never happen now. */
10886 fputc ('#', stream
);
10887 output_addr_const (stream
, x
);
10892 #ifndef AOF_ASSEMBLER
10893 /* Target hook for assembling integer objects. The ARM version needs to
10894 handle word-sized values specially. */
10896 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10898 if (size
== UNITS_PER_WORD
&& aligned_p
)
10900 fputs ("\t.word\t", asm_out_file
);
10901 output_addr_const (asm_out_file
, x
);
10903 /* Mark symbols as position independent. We only do this in the
10904 .text segment, not in the .data segment. */
10905 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10906 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10908 if (GET_CODE (x
) == SYMBOL_REF
10909 && (CONSTANT_POOL_ADDRESS_P (x
)
10910 || SYMBOL_REF_LOCAL_P (x
)))
10911 fputs ("(GOTOFF)", asm_out_file
);
10912 else if (GET_CODE (x
) == LABEL_REF
)
10913 fputs ("(GOTOFF)", asm_out_file
);
10915 fputs ("(GOT)", asm_out_file
);
10917 fputc ('\n', asm_out_file
);
10921 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
10925 if (GET_CODE (x
) != CONST_VECTOR
)
10928 units
= CONST_VECTOR_NUNITS (x
);
10930 switch (GET_MODE (x
))
10932 case V2SImode
: size
= 4; break;
10933 case V4HImode
: size
= 2; break;
10934 case V8QImode
: size
= 1; break;
10939 for (i
= 0; i
< units
; i
++)
10943 elt
= CONST_VECTOR_ELT (x
, i
);
10945 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
10951 return default_assemble_integer (x
, size
, aligned_p
);
10955 /* A finite state machine takes care of noticing whether or not instructions
10956 can be conditionally executed, and thus decrease execution time and code
10957 size by deleting branch instructions. The fsm is controlled by
10958 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10960 /* The state of the fsm controlling condition codes are:
10961 0: normal, do nothing special
10962 1: make ASM_OUTPUT_OPCODE not output this instruction
10963 2: make ASM_OUTPUT_OPCODE not output this instruction
10964 3: make instructions conditional
10965 4: make instructions conditional
10967 State transitions (state->state by whom under condition):
10968 0 -> 1 final_prescan_insn if the `target' is a label
10969 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10970 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10971 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10972 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10973 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10974 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10975 (the target insn is arm_target_insn).
10977 If the jump clobbers the conditions then we use states 2 and 4.
10979 A similar thing can be done with conditional return insns.
10981 XXX In case the `target' is an unconditional branch, this conditionalising
10982 of the instructions always reduces code size, but not always execution
10983 time. But then, I want to reduce the code size to somewhere near what
10984 /bin/cc produces. */
10986 /* Returns the index of the ARM condition code string in
10987 `arm_condition_codes'. COMPARISON should be an rtx like
10988 `(eq (...) (...))'. */
10989 static enum arm_cond_code
10990 get_arm_condition_code (rtx comparison
)
10992 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
10994 enum rtx_code comp_code
= GET_CODE (comparison
);
10996 if (GET_MODE_CLASS (mode
) != MODE_CC
)
10997 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
10998 XEXP (comparison
, 1));
11002 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11003 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11004 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11005 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11006 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11007 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11008 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11009 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11010 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11011 case CC_DLTUmode
: code
= ARM_CC
;
11014 if (comp_code
!= EQ
&& comp_code
!= NE
)
11017 if (comp_code
== EQ
)
11018 return ARM_INVERSE_CONDITION_CODE (code
);
11024 case NE
: return ARM_NE
;
11025 case EQ
: return ARM_EQ
;
11026 case GE
: return ARM_PL
;
11027 case LT
: return ARM_MI
;
11034 case NE
: return ARM_NE
;
11035 case EQ
: return ARM_EQ
;
11042 case NE
: return ARM_MI
;
11043 case EQ
: return ARM_PL
;
11049 /* These encodings assume that AC=1 in the FPA system control
11050 byte. This allows us to handle all cases except UNEQ and
11054 case GE
: return ARM_GE
;
11055 case GT
: return ARM_GT
;
11056 case LE
: return ARM_LS
;
11057 case LT
: return ARM_MI
;
11058 case NE
: return ARM_NE
;
11059 case EQ
: return ARM_EQ
;
11060 case ORDERED
: return ARM_VC
;
11061 case UNORDERED
: return ARM_VS
;
11062 case UNLT
: return ARM_LT
;
11063 case UNLE
: return ARM_LE
;
11064 case UNGT
: return ARM_HI
;
11065 case UNGE
: return ARM_PL
;
11066 /* UNEQ and LTGT do not have a representation. */
11067 case UNEQ
: /* Fall through. */
11068 case LTGT
: /* Fall through. */
11075 case NE
: return ARM_NE
;
11076 case EQ
: return ARM_EQ
;
11077 case GE
: return ARM_LE
;
11078 case GT
: return ARM_LT
;
11079 case LE
: return ARM_GE
;
11080 case LT
: return ARM_GT
;
11081 case GEU
: return ARM_LS
;
11082 case GTU
: return ARM_CC
;
11083 case LEU
: return ARM_CS
;
11084 case LTU
: return ARM_HI
;
11091 case LTU
: return ARM_CS
;
11092 case GEU
: return ARM_CC
;
11099 case NE
: return ARM_NE
;
11100 case EQ
: return ARM_EQ
;
11101 case GE
: return ARM_GE
;
11102 case GT
: return ARM_GT
;
11103 case LE
: return ARM_LE
;
11104 case LT
: return ARM_LT
;
11105 case GEU
: return ARM_CS
;
11106 case GTU
: return ARM_HI
;
11107 case LEU
: return ARM_LS
;
11108 case LTU
: return ARM_CC
;
11119 arm_final_prescan_insn (rtx insn
)
11121 /* BODY will hold the body of INSN. */
11122 rtx body
= PATTERN (insn
);
11124 /* This will be 1 if trying to repeat the trick, and things need to be
11125 reversed if it appears to fail. */
11128 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11129 taken are clobbered, even if the rtl suggests otherwise. It also
11130 means that we have to grub around within the jump expression to find
11131 out what the conditions are when the jump isn't taken. */
11132 int jump_clobbers
= 0;
11134 /* If we start with a return insn, we only succeed if we find another one. */
11135 int seeking_return
= 0;
11137 /* START_INSN will hold the insn from where we start looking. This is the
11138 first insn after the following code_label if REVERSE is true. */
11139 rtx start_insn
= insn
;
11141 /* If in state 4, check if the target branch is reached, in order to
11142 change back to state 0. */
11143 if (arm_ccfsm_state
== 4)
11145 if (insn
== arm_target_insn
)
11147 arm_target_insn
= NULL
;
11148 arm_ccfsm_state
= 0;
11153 /* If in state 3, it is possible to repeat the trick, if this insn is an
11154 unconditional branch to a label, and immediately following this branch
11155 is the previous target label which is only used once, and the label this
11156 branch jumps to is not too far off. */
11157 if (arm_ccfsm_state
== 3)
11159 if (simplejump_p (insn
))
11161 start_insn
= next_nonnote_insn (start_insn
);
11162 if (GET_CODE (start_insn
) == BARRIER
)
11164 /* XXX Isn't this always a barrier? */
11165 start_insn
= next_nonnote_insn (start_insn
);
11167 if (GET_CODE (start_insn
) == CODE_LABEL
11168 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11169 && LABEL_NUSES (start_insn
) == 1)
11174 else if (GET_CODE (body
) == RETURN
)
11176 start_insn
= next_nonnote_insn (start_insn
);
11177 if (GET_CODE (start_insn
) == BARRIER
)
11178 start_insn
= next_nonnote_insn (start_insn
);
11179 if (GET_CODE (start_insn
) == CODE_LABEL
11180 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11181 && LABEL_NUSES (start_insn
) == 1)
11184 seeking_return
= 1;
11193 if (arm_ccfsm_state
!= 0 && !reverse
)
11195 if (GET_CODE (insn
) != JUMP_INSN
)
11198 /* This jump might be paralleled with a clobber of the condition codes
11199 the jump should always come first */
11200 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11201 body
= XVECEXP (body
, 0, 0);
11204 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11205 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11208 int fail
= FALSE
, succeed
= FALSE
;
11209 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11210 int then_not_else
= TRUE
;
11211 rtx this_insn
= start_insn
, label
= 0;
11213 /* If the jump cannot be done with one instruction, we cannot
11214 conditionally execute the instruction in the inverse case. */
11215 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11221 /* Register the insn jumped to. */
11224 if (!seeking_return
)
11225 label
= XEXP (SET_SRC (body
), 0);
11227 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11228 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11229 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11231 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11232 then_not_else
= FALSE
;
11234 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11235 seeking_return
= 1;
11236 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11238 seeking_return
= 1;
11239 then_not_else
= FALSE
;
11244 /* See how many insns this branch skips, and what kind of insns. If all
11245 insns are okay, and the label or unconditional branch to the same
11246 label is not too far away, succeed. */
11247 for (insns_skipped
= 0;
11248 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11252 this_insn
= next_nonnote_insn (this_insn
);
11256 switch (GET_CODE (this_insn
))
11259 /* Succeed if it is the target label, otherwise fail since
11260 control falls in from somewhere else. */
11261 if (this_insn
== label
)
11265 arm_ccfsm_state
= 2;
11266 this_insn
= next_nonnote_insn (this_insn
);
11269 arm_ccfsm_state
= 1;
11277 /* Succeed if the following insn is the target label.
11279 If return insns are used then the last insn in a function
11280 will be a barrier. */
11281 this_insn
= next_nonnote_insn (this_insn
);
11282 if (this_insn
&& this_insn
== label
)
11286 arm_ccfsm_state
= 2;
11287 this_insn
= next_nonnote_insn (this_insn
);
11290 arm_ccfsm_state
= 1;
11298 /* If using 32-bit addresses the cc is not preserved over
11300 if (TARGET_APCS_32
)
11302 /* Succeed if the following insn is the target label,
11303 or if the following two insns are a barrier and
11304 the target label. */
11305 this_insn
= next_nonnote_insn (this_insn
);
11306 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11307 this_insn
= next_nonnote_insn (this_insn
);
11309 if (this_insn
&& this_insn
== label
11310 && insns_skipped
< max_insns_skipped
)
11314 arm_ccfsm_state
= 2;
11315 this_insn
= next_nonnote_insn (this_insn
);
11318 arm_ccfsm_state
= 1;
11327 /* If this is an unconditional branch to the same label, succeed.
11328 If it is to another label, do nothing. If it is conditional,
11330 /* XXX Probably, the tests for SET and the PC are
11333 scanbody
= PATTERN (this_insn
);
11334 if (GET_CODE (scanbody
) == SET
11335 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11337 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11338 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11340 arm_ccfsm_state
= 2;
11343 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11346 /* Fail if a conditional return is undesirable (eg on a
11347 StrongARM), but still allow this if optimizing for size. */
11348 else if (GET_CODE (scanbody
) == RETURN
11349 && !use_return_insn (TRUE
, NULL
)
11352 else if (GET_CODE (scanbody
) == RETURN
11355 arm_ccfsm_state
= 2;
11358 else if (GET_CODE (scanbody
) == PARALLEL
)
11360 switch (get_attr_conds (this_insn
))
11370 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
11375 /* Instructions using or affecting the condition codes make it
11377 scanbody
= PATTERN (this_insn
);
11378 if (!(GET_CODE (scanbody
) == SET
11379 || GET_CODE (scanbody
) == PARALLEL
)
11380 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11383 /* A conditional cirrus instruction must be followed by
11384 a non Cirrus instruction. However, since we
11385 conditionalize instructions in this function and by
11386 the time we get here we can't add instructions
11387 (nops), because shorten_branches() has already been
11388 called, we will disable conditionalizing Cirrus
11389 instructions to be safe. */
11390 if (GET_CODE (scanbody
) != USE
11391 && GET_CODE (scanbody
) != CLOBBER
11392 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11402 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11403 arm_target_label
= CODE_LABEL_NUMBER (label
);
11404 else if (seeking_return
|| arm_ccfsm_state
== 2)
11406 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11408 this_insn
= next_nonnote_insn (this_insn
);
11409 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
11410 || GET_CODE (this_insn
) == CODE_LABEL
))
11415 /* Oh, dear! we ran off the end.. give up. */
11416 recog (PATTERN (insn
), insn
, NULL
);
11417 arm_ccfsm_state
= 0;
11418 arm_target_insn
= NULL
;
11421 arm_target_insn
= this_insn
;
11430 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11432 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11433 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11434 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11435 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11439 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11442 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11446 if (reverse
|| then_not_else
)
11447 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11450 /* Restore recog_data (getting the attributes of other insns can
11451 destroy this array, but final.c assumes that it remains intact
11452 across this call; since the insn has been recognized already we
11453 call recog direct). */
11454 recog (PATTERN (insn
), insn
, NULL
);
11458 /* Returns true if REGNO is a valid register
11459 for holding a quantity of tyoe MODE. */
11461 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11463 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11464 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11467 /* For the Thumb we only allow values bigger than SImode in
11468 registers 0 - 6, so that there is always a second low
11469 register available to hold the upper part of the value.
11470 We probably we ought to ensure that the register is the
11471 start of an even numbered register pair. */
11472 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11474 if (IS_CIRRUS_REGNUM (regno
))
11475 /* We have outlawed SI values in Cirrus registers because they
11476 reside in the lower 32 bits, but SF values reside in the
11477 upper 32 bits. This causes gcc all sorts of grief. We can't
11478 even split the registers into pairs because Cirrus SI values
11479 get sign extended to 64bits-- aldyh. */
11480 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11482 if (IS_VFP_REGNUM (regno
))
11484 if (mode
== SFmode
|| mode
== SImode
)
11487 /* DFmode values are only valid in even register pairs. */
11488 if (mode
== DFmode
)
11489 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11493 if (IS_IWMMXT_GR_REGNUM (regno
))
11494 return mode
== SImode
;
11496 if (IS_IWMMXT_REGNUM (regno
))
11497 return VALID_IWMMXT_REG_MODE (mode
);
11499 /* We allow any value to be stored in the general registers.
11500 Restrict doubleword quantities to even register pairs so that we can
11502 if (regno
<= LAST_ARM_REGNUM
)
11503 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11505 if ( regno
== FRAME_POINTER_REGNUM
11506 || regno
== ARG_POINTER_REGNUM
)
11507 /* We only allow integers in the fake hard registers. */
11508 return GET_MODE_CLASS (mode
) == MODE_INT
;
11510 /* The only registers left are the FPA registers
11511 which we only allow to hold FP values. */
11512 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11513 && regno
>= FIRST_FPA_REGNUM
11514 && regno
<= LAST_FPA_REGNUM
;
11518 arm_regno_class (int regno
)
11522 if (regno
== STACK_POINTER_REGNUM
)
11524 if (regno
== CC_REGNUM
)
11531 if ( regno
<= LAST_ARM_REGNUM
11532 || regno
== FRAME_POINTER_REGNUM
11533 || regno
== ARG_POINTER_REGNUM
)
11534 return GENERAL_REGS
;
11536 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11539 if (IS_CIRRUS_REGNUM (regno
))
11540 return CIRRUS_REGS
;
11542 if (IS_VFP_REGNUM (regno
))
11545 if (IS_IWMMXT_REGNUM (regno
))
11546 return IWMMXT_REGS
;
11548 if (IS_IWMMXT_GR_REGNUM (regno
))
11549 return IWMMXT_GR_REGS
;
11554 /* Handle a special case when computing the offset
11555 of an argument from the frame pointer. */
11557 arm_debugger_arg_offset (int value
, rtx addr
)
11561 /* We are only interested if dbxout_parms() failed to compute the offset. */
11565 /* We can only cope with the case where the address is held in a register. */
11566 if (GET_CODE (addr
) != REG
)
11569 /* If we are using the frame pointer to point at the argument, then
11570 an offset of 0 is correct. */
11571 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11574 /* If we are using the stack pointer to point at the
11575 argument, then an offset of 0 is correct. */
11576 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11577 && REGNO (addr
) == SP_REGNUM
)
11580 /* Oh dear. The argument is pointed to by a register rather
11581 than being held in a register, or being stored at a known
11582 offset from the frame pointer. Since GDB only understands
11583 those two kinds of argument we must translate the address
11584 held in the register into an offset from the frame pointer.
11585 We do this by searching through the insns for the function
11586 looking to see where this register gets its value. If the
11587 register is initialized from the frame pointer plus an offset
11588 then we are in luck and we can continue, otherwise we give up.
11590 This code is exercised by producing debugging information
11591 for a function with arguments like this:
11593 double func (double a, double b, int c, double d) {return d;}
11595 Without this code the stab for parameter 'd' will be set to
11596 an offset of 0 from the frame pointer, rather than 8. */
11598 /* The if() statement says:
11600 If the insn is a normal instruction
11601 and if the insn is setting the value in a register
11602 and if the register being set is the register holding the address of the argument
11603 and if the address is computing by an addition
11604 that involves adding to a register
11605 which is the frame pointer
11610 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11612 if ( GET_CODE (insn
) == INSN
11613 && GET_CODE (PATTERN (insn
)) == SET
11614 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11615 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11616 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11617 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11618 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11621 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11630 warning ("unable to compute real location of stacked parameter");
11631 value
= 8; /* XXX magic hack */
11637 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11640 if ((MASK) & insn_flags) \
11641 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11645 struct builtin_description
11647 const unsigned int mask
;
11648 const enum insn_code icode
;
11649 const char * const name
;
11650 const enum arm_builtins code
;
11651 const enum rtx_code comparison
;
11652 const unsigned int flag
;
11655 static const struct builtin_description bdesc_2arg
[] =
11657 #define IWMMXT_BUILTIN(code, string, builtin) \
11658 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11659 ARM_BUILTIN_##builtin, 0, 0 },
11661 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11662 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11663 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11664 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11665 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11666 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11667 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11668 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11669 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11670 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11671 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11672 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11673 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11674 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11675 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11676 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11677 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11678 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11679 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11680 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11681 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11682 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11683 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11684 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11685 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11686 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11687 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11688 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11689 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11690 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11691 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11692 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11693 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11694 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11695 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11696 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11697 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11698 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11699 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11700 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11701 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11702 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11703 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11704 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11705 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11706 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11707 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11708 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11709 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11710 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11711 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11712 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11713 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11714 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11715 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11716 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11717 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11718 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11720 #define IWMMXT_BUILTIN2(code, builtin) \
11721 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11723 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11724 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11725 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11726 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11727 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11728 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11729 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11730 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11731 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11732 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11733 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11734 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11735 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11736 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11737 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11738 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11739 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11740 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11741 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11742 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11743 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11744 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11745 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11746 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11747 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11748 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11749 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11750 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11751 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11752 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11753 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11754 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11757 static const struct builtin_description bdesc_1arg
[] =
11759 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11760 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11761 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11762 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11763 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11764 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11765 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11766 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11767 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11768 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11769 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11770 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11771 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11772 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11773 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11774 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11775 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11776 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11779 /* Set up all the iWMMXt builtins. This is
11780 not called if TARGET_IWMMXT is zero. */
11783 arm_init_iwmmxt_builtins (void)
11785 const struct builtin_description
* d
;
11787 tree endlink
= void_list_node
;
11789 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11790 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11791 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11794 = build_function_type (integer_type_node
,
11795 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11796 tree v8qi_ftype_v8qi_v8qi_int
11797 = build_function_type (V8QI_type_node
,
11798 tree_cons (NULL_TREE
, V8QI_type_node
,
11799 tree_cons (NULL_TREE
, V8QI_type_node
,
11800 tree_cons (NULL_TREE
,
11803 tree v4hi_ftype_v4hi_int
11804 = build_function_type (V4HI_type_node
,
11805 tree_cons (NULL_TREE
, V4HI_type_node
,
11806 tree_cons (NULL_TREE
, integer_type_node
,
11808 tree v2si_ftype_v2si_int
11809 = build_function_type (V2SI_type_node
,
11810 tree_cons (NULL_TREE
, V2SI_type_node
,
11811 tree_cons (NULL_TREE
, integer_type_node
,
11813 tree v2si_ftype_di_di
11814 = build_function_type (V2SI_type_node
,
11815 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11816 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11818 tree di_ftype_di_int
11819 = build_function_type (long_long_integer_type_node
,
11820 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11821 tree_cons (NULL_TREE
, integer_type_node
,
11823 tree di_ftype_di_int_int
11824 = build_function_type (long_long_integer_type_node
,
11825 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11826 tree_cons (NULL_TREE
, integer_type_node
,
11827 tree_cons (NULL_TREE
,
11830 tree int_ftype_v8qi
11831 = build_function_type (integer_type_node
,
11832 tree_cons (NULL_TREE
, V8QI_type_node
,
11834 tree int_ftype_v4hi
11835 = build_function_type (integer_type_node
,
11836 tree_cons (NULL_TREE
, V4HI_type_node
,
11838 tree int_ftype_v2si
11839 = build_function_type (integer_type_node
,
11840 tree_cons (NULL_TREE
, V2SI_type_node
,
11842 tree int_ftype_v8qi_int
11843 = build_function_type (integer_type_node
,
11844 tree_cons (NULL_TREE
, V8QI_type_node
,
11845 tree_cons (NULL_TREE
, integer_type_node
,
11847 tree int_ftype_v4hi_int
11848 = build_function_type (integer_type_node
,
11849 tree_cons (NULL_TREE
, V4HI_type_node
,
11850 tree_cons (NULL_TREE
, integer_type_node
,
11852 tree int_ftype_v2si_int
11853 = build_function_type (integer_type_node
,
11854 tree_cons (NULL_TREE
, V2SI_type_node
,
11855 tree_cons (NULL_TREE
, integer_type_node
,
11857 tree v8qi_ftype_v8qi_int_int
11858 = build_function_type (V8QI_type_node
,
11859 tree_cons (NULL_TREE
, V8QI_type_node
,
11860 tree_cons (NULL_TREE
, integer_type_node
,
11861 tree_cons (NULL_TREE
,
11864 tree v4hi_ftype_v4hi_int_int
11865 = build_function_type (V4HI_type_node
,
11866 tree_cons (NULL_TREE
, V4HI_type_node
,
11867 tree_cons (NULL_TREE
, integer_type_node
,
11868 tree_cons (NULL_TREE
,
11871 tree v2si_ftype_v2si_int_int
11872 = build_function_type (V2SI_type_node
,
11873 tree_cons (NULL_TREE
, V2SI_type_node
,
11874 tree_cons (NULL_TREE
, integer_type_node
,
11875 tree_cons (NULL_TREE
,
11878 /* Miscellaneous. */
11879 tree v8qi_ftype_v4hi_v4hi
11880 = build_function_type (V8QI_type_node
,
11881 tree_cons (NULL_TREE
, V4HI_type_node
,
11882 tree_cons (NULL_TREE
, V4HI_type_node
,
11884 tree v4hi_ftype_v2si_v2si
11885 = build_function_type (V4HI_type_node
,
11886 tree_cons (NULL_TREE
, V2SI_type_node
,
11887 tree_cons (NULL_TREE
, V2SI_type_node
,
11889 tree v2si_ftype_v4hi_v4hi
11890 = build_function_type (V2SI_type_node
,
11891 tree_cons (NULL_TREE
, V4HI_type_node
,
11892 tree_cons (NULL_TREE
, V4HI_type_node
,
11894 tree v2si_ftype_v8qi_v8qi
11895 = build_function_type (V2SI_type_node
,
11896 tree_cons (NULL_TREE
, V8QI_type_node
,
11897 tree_cons (NULL_TREE
, V8QI_type_node
,
11899 tree v4hi_ftype_v4hi_di
11900 = build_function_type (V4HI_type_node
,
11901 tree_cons (NULL_TREE
, V4HI_type_node
,
11902 tree_cons (NULL_TREE
,
11903 long_long_integer_type_node
,
11905 tree v2si_ftype_v2si_di
11906 = build_function_type (V2SI_type_node
,
11907 tree_cons (NULL_TREE
, V2SI_type_node
,
11908 tree_cons (NULL_TREE
,
11909 long_long_integer_type_node
,
11911 tree void_ftype_int_int
11912 = build_function_type (void_type_node
,
11913 tree_cons (NULL_TREE
, integer_type_node
,
11914 tree_cons (NULL_TREE
, integer_type_node
,
11917 = build_function_type (long_long_unsigned_type_node
, endlink
);
11919 = build_function_type (long_long_integer_type_node
,
11920 tree_cons (NULL_TREE
, V8QI_type_node
,
11923 = build_function_type (long_long_integer_type_node
,
11924 tree_cons (NULL_TREE
, V4HI_type_node
,
11927 = build_function_type (long_long_integer_type_node
,
11928 tree_cons (NULL_TREE
, V2SI_type_node
,
11930 tree v2si_ftype_v4hi
11931 = build_function_type (V2SI_type_node
,
11932 tree_cons (NULL_TREE
, V4HI_type_node
,
11934 tree v4hi_ftype_v8qi
11935 = build_function_type (V4HI_type_node
,
11936 tree_cons (NULL_TREE
, V8QI_type_node
,
11939 tree di_ftype_di_v4hi_v4hi
11940 = build_function_type (long_long_unsigned_type_node
,
11941 tree_cons (NULL_TREE
,
11942 long_long_unsigned_type_node
,
11943 tree_cons (NULL_TREE
, V4HI_type_node
,
11944 tree_cons (NULL_TREE
,
11948 tree di_ftype_v4hi_v4hi
11949 = build_function_type (long_long_unsigned_type_node
,
11950 tree_cons (NULL_TREE
, V4HI_type_node
,
11951 tree_cons (NULL_TREE
, V4HI_type_node
,
11954 /* Normal vector binops. */
11955 tree v8qi_ftype_v8qi_v8qi
11956 = build_function_type (V8QI_type_node
,
11957 tree_cons (NULL_TREE
, V8QI_type_node
,
11958 tree_cons (NULL_TREE
, V8QI_type_node
,
11960 tree v4hi_ftype_v4hi_v4hi
11961 = build_function_type (V4HI_type_node
,
11962 tree_cons (NULL_TREE
, V4HI_type_node
,
11963 tree_cons (NULL_TREE
, V4HI_type_node
,
11965 tree v2si_ftype_v2si_v2si
11966 = build_function_type (V2SI_type_node
,
11967 tree_cons (NULL_TREE
, V2SI_type_node
,
11968 tree_cons (NULL_TREE
, V2SI_type_node
,
11970 tree di_ftype_di_di
11971 = build_function_type (long_long_unsigned_type_node
,
11972 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11973 tree_cons (NULL_TREE
,
11974 long_long_unsigned_type_node
,
11977 /* Add all builtins that are more or less simple operations on two
11979 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11981 /* Use one of the operands; the target can have a different mode for
11982 mask-generating compares. */
11983 enum machine_mode mode
;
11989 mode
= insn_data
[d
->icode
].operand
[1].mode
;
11994 type
= v8qi_ftype_v8qi_v8qi
;
11997 type
= v4hi_ftype_v4hi_v4hi
;
12000 type
= v2si_ftype_v2si_v2si
;
12003 type
= di_ftype_di_di
;
12010 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12013 /* Add the remaining MMX insns with somewhat more complicated types. */
12014 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12015 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12016 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12018 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12019 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12020 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12021 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12022 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12023 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12025 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12026 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12027 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12028 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12029 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12030 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12032 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12033 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12034 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12035 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12036 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12037 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12039 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12040 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12041 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12042 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12043 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12044 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12046 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12048 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12049 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12050 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12051 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12053 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12054 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12055 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12056 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12057 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12058 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12059 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12060 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12061 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12063 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12064 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12065 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12067 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12068 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12069 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12071 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12072 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12073 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12074 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12075 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12076 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12078 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12079 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12080 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12081 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12082 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12083 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12084 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12085 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12086 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12087 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12088 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12089 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12091 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12092 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12093 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12094 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12096 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12097 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12098 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12099 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12100 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12101 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12102 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12106 arm_init_builtins (void)
12108 if (TARGET_REALLY_IWMMXT
)
12109 arm_init_iwmmxt_builtins ();
12112 /* Errors in the source file can cause expand_expr to return const0_rtx
12113 where we expect a vector. To avoid crashing, use one of the vector
12114 clear instructions. */
12117 safe_vector_operand (rtx x
, enum machine_mode mode
)
12119 if (x
!= const0_rtx
)
12121 x
= gen_reg_rtx (mode
);
12123 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12124 : gen_rtx_SUBREG (DImode
, x
, 0)));
12128 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12131 arm_expand_binop_builtin (enum insn_code icode
,
12132 tree arglist
, rtx target
)
12135 tree arg0
= TREE_VALUE (arglist
);
12136 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12137 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12138 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12139 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12140 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12141 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12143 if (VECTOR_MODE_P (mode0
))
12144 op0
= safe_vector_operand (op0
, mode0
);
12145 if (VECTOR_MODE_P (mode1
))
12146 op1
= safe_vector_operand (op1
, mode1
);
12149 || GET_MODE (target
) != tmode
12150 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12151 target
= gen_reg_rtx (tmode
);
12153 /* In case the insn wants input operands in modes different from
12154 the result, abort. */
12155 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
12158 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12159 op0
= copy_to_mode_reg (mode0
, op0
);
12160 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12161 op1
= copy_to_mode_reg (mode1
, op1
);
12163 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12170 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12173 arm_expand_unop_builtin (enum insn_code icode
,
12174 tree arglist
, rtx target
, int do_load
)
12177 tree arg0
= TREE_VALUE (arglist
);
12178 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12179 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12180 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12183 || GET_MODE (target
) != tmode
12184 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12185 target
= gen_reg_rtx (tmode
);
12187 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12190 if (VECTOR_MODE_P (mode0
))
12191 op0
= safe_vector_operand (op0
, mode0
);
12193 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12194 op0
= copy_to_mode_reg (mode0
, op0
);
12197 pat
= GEN_FCN (icode
) (target
, op0
);
12204 /* Expand an expression EXP that calls a built-in function,
12205 with result going to TARGET if that's convenient
12206 (and in mode MODE if that's convenient).
12207 SUBTARGET may be used as the target for computing one of EXP's operands.
12208 IGNORE is nonzero if the value is to be ignored. */
12211 arm_expand_builtin (tree exp
,
12213 rtx subtarget ATTRIBUTE_UNUSED
,
12214 enum machine_mode mode ATTRIBUTE_UNUSED
,
12215 int ignore ATTRIBUTE_UNUSED
)
12217 const struct builtin_description
* d
;
12218 enum insn_code icode
;
12219 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12220 tree arglist
= TREE_OPERAND (exp
, 1);
12228 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12230 enum machine_mode tmode
;
12231 enum machine_mode mode0
;
12232 enum machine_mode mode1
;
12233 enum machine_mode mode2
;
12237 case ARM_BUILTIN_TEXTRMSB
:
12238 case ARM_BUILTIN_TEXTRMUB
:
12239 case ARM_BUILTIN_TEXTRMSH
:
12240 case ARM_BUILTIN_TEXTRMUH
:
12241 case ARM_BUILTIN_TEXTRMSW
:
12242 case ARM_BUILTIN_TEXTRMUW
:
12243 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12244 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12245 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12246 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12247 : CODE_FOR_iwmmxt_textrmw
);
12249 arg0
= TREE_VALUE (arglist
);
12250 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12251 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12252 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12253 tmode
= insn_data
[icode
].operand
[0].mode
;
12254 mode0
= insn_data
[icode
].operand
[1].mode
;
12255 mode1
= insn_data
[icode
].operand
[2].mode
;
12257 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12258 op0
= copy_to_mode_reg (mode0
, op0
);
12259 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12261 /* @@@ better error message */
12262 error ("selector must be an immediate");
12263 return gen_reg_rtx (tmode
);
12266 || GET_MODE (target
) != tmode
12267 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12268 target
= gen_reg_rtx (tmode
);
12269 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12275 case ARM_BUILTIN_TINSRB
:
12276 case ARM_BUILTIN_TINSRH
:
12277 case ARM_BUILTIN_TINSRW
:
12278 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12279 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12280 : CODE_FOR_iwmmxt_tinsrw
);
12281 arg0
= TREE_VALUE (arglist
);
12282 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12283 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12284 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12285 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12286 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12287 tmode
= insn_data
[icode
].operand
[0].mode
;
12288 mode0
= insn_data
[icode
].operand
[1].mode
;
12289 mode1
= insn_data
[icode
].operand
[2].mode
;
12290 mode2
= insn_data
[icode
].operand
[3].mode
;
12292 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12293 op0
= copy_to_mode_reg (mode0
, op0
);
12294 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12295 op1
= copy_to_mode_reg (mode1
, op1
);
12296 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12298 /* @@@ better error message */
12299 error ("selector must be an immediate");
12303 || GET_MODE (target
) != tmode
12304 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12305 target
= gen_reg_rtx (tmode
);
12306 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12312 case ARM_BUILTIN_SETWCX
:
12313 arg0
= TREE_VALUE (arglist
);
12314 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12315 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12316 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12317 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12320 case ARM_BUILTIN_GETWCX
:
12321 arg0
= TREE_VALUE (arglist
);
12322 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12323 target
= gen_reg_rtx (SImode
);
12324 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12327 case ARM_BUILTIN_WSHUFH
:
12328 icode
= CODE_FOR_iwmmxt_wshufh
;
12329 arg0
= TREE_VALUE (arglist
);
12330 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12331 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12332 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12333 tmode
= insn_data
[icode
].operand
[0].mode
;
12334 mode1
= insn_data
[icode
].operand
[1].mode
;
12335 mode2
= insn_data
[icode
].operand
[2].mode
;
12337 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12338 op0
= copy_to_mode_reg (mode1
, op0
);
12339 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12341 /* @@@ better error message */
12342 error ("mask must be an immediate");
12346 || GET_MODE (target
) != tmode
12347 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12348 target
= gen_reg_rtx (tmode
);
12349 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12355 case ARM_BUILTIN_WSADB
:
12356 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12357 case ARM_BUILTIN_WSADH
:
12358 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12359 case ARM_BUILTIN_WSADBZ
:
12360 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12361 case ARM_BUILTIN_WSADHZ
:
12362 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12364 /* Several three-argument builtins. */
12365 case ARM_BUILTIN_WMACS
:
12366 case ARM_BUILTIN_WMACU
:
12367 case ARM_BUILTIN_WALIGN
:
12368 case ARM_BUILTIN_TMIA
:
12369 case ARM_BUILTIN_TMIAPH
:
12370 case ARM_BUILTIN_TMIATT
:
12371 case ARM_BUILTIN_TMIATB
:
12372 case ARM_BUILTIN_TMIABT
:
12373 case ARM_BUILTIN_TMIABB
:
12374 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12375 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12376 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12377 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12378 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12379 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12380 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12381 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12382 : CODE_FOR_iwmmxt_walign
);
12383 arg0
= TREE_VALUE (arglist
);
12384 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12385 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12386 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12387 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12388 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12389 tmode
= insn_data
[icode
].operand
[0].mode
;
12390 mode0
= insn_data
[icode
].operand
[1].mode
;
12391 mode1
= insn_data
[icode
].operand
[2].mode
;
12392 mode2
= insn_data
[icode
].operand
[3].mode
;
12394 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12395 op0
= copy_to_mode_reg (mode0
, op0
);
12396 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12397 op1
= copy_to_mode_reg (mode1
, op1
);
12398 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12399 op2
= copy_to_mode_reg (mode2
, op2
);
12401 || GET_MODE (target
) != tmode
12402 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12403 target
= gen_reg_rtx (tmode
);
12404 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12410 case ARM_BUILTIN_WZERO
:
12411 target
= gen_reg_rtx (DImode
);
12412 emit_insn (gen_iwmmxt_clrdi (target
));
12419 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12420 if (d
->code
== (const enum arm_builtins
) fcode
)
12421 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12423 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12424 if (d
->code
== (const enum arm_builtins
) fcode
)
12425 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12427 /* @@@ Should really do something sensible here. */
12431 /* Recursively search through all of the blocks in a function
12432 checking to see if any of the variables created in that
12433 function match the RTX called 'orig'. If they do then
12434 replace them with the RTX called 'new'. */
12436 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
12438 for (; block
; block
= BLOCK_CHAIN (block
))
12442 if (!TREE_USED (block
))
12445 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
12447 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
12448 || DECL_IGNORED_P (sym
)
12449 || TREE_CODE (sym
) != VAR_DECL
12450 || DECL_EXTERNAL (sym
)
12451 || !rtx_equal_p (DECL_RTL (sym
), orig
)
12455 SET_DECL_RTL (sym
, new);
12458 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
12462 /* Return the number (counting from 0) of
12463 the least significant set bit in MASK. */
12466 number_of_first_bit_set (int mask
)
12471 (mask
& (1 << bit
)) == 0;
12478 /* Generate code to return from a thumb function.
12479 If 'reg_containing_return_addr' is -1, then the return address is
12480 actually on the stack, at the stack pointer. */
12482 thumb_exit (FILE *f
, int reg_containing_return_addr
, rtx eh_ofs
)
12484 unsigned regs_available_for_popping
;
12485 unsigned regs_to_pop
;
12487 unsigned available
;
12491 int restore_a4
= FALSE
;
12493 /* Compute the registers we need to pop. */
12497 /* There is an assumption here, that if eh_ofs is not NULL, the
12498 normal return address will have been pushed. */
12499 if (reg_containing_return_addr
== -1 || eh_ofs
)
12501 /* When we are generating a return for __builtin_eh_return,
12502 reg_containing_return_addr must specify the return regno. */
12503 if (eh_ofs
&& reg_containing_return_addr
== -1)
12506 regs_to_pop
|= 1 << LR_REGNUM
;
12510 if (TARGET_BACKTRACE
)
12512 /* Restore the (ARM) frame pointer and stack pointer. */
12513 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12517 /* If there is nothing to pop then just emit the BX instruction and
12519 if (pops_needed
== 0)
12522 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12524 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12527 /* Otherwise if we are not supporting interworking and we have not created
12528 a backtrace structure and the function was not entered in ARM mode then
12529 just pop the return address straight into the PC. */
12530 else if (!TARGET_INTERWORK
12531 && !TARGET_BACKTRACE
12532 && !is_called_in_ARM_mode (current_function_decl
))
12536 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
12537 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12538 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12541 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12546 /* Find out how many of the (return) argument registers we can corrupt. */
12547 regs_available_for_popping
= 0;
12549 /* If returning via __builtin_eh_return, the bottom three registers
12550 all contain information needed for the return. */
12556 /* If we can deduce the registers used from the function's
12557 return value. This is more reliable that examining
12558 regs_ever_live[] because that will be set if the register is
12559 ever used in the function, not just if the register is used
12560 to hold a return value. */
12562 if (current_function_return_rtx
!= 0)
12563 mode
= GET_MODE (current_function_return_rtx
);
12566 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12568 size
= GET_MODE_SIZE (mode
);
12572 /* In a void function we can use any argument register.
12573 In a function that returns a structure on the stack
12574 we can use the second and third argument registers. */
12575 if (mode
== VOIDmode
)
12576 regs_available_for_popping
=
12577 (1 << ARG_REGISTER (1))
12578 | (1 << ARG_REGISTER (2))
12579 | (1 << ARG_REGISTER (3));
12581 regs_available_for_popping
=
12582 (1 << ARG_REGISTER (2))
12583 | (1 << ARG_REGISTER (3));
12585 else if (size
<= 4)
12586 regs_available_for_popping
=
12587 (1 << ARG_REGISTER (2))
12588 | (1 << ARG_REGISTER (3));
12589 else if (size
<= 8)
12590 regs_available_for_popping
=
12591 (1 << ARG_REGISTER (3));
12594 /* Match registers to be popped with registers into which we pop them. */
12595 for (available
= regs_available_for_popping
,
12596 required
= regs_to_pop
;
12597 required
!= 0 && available
!= 0;
12598 available
&= ~(available
& - available
),
12599 required
&= ~(required
& - required
))
12602 /* If we have any popping registers left over, remove them. */
12604 regs_available_for_popping
&= ~available
;
12606 /* Otherwise if we need another popping register we can use
12607 the fourth argument register. */
12608 else if (pops_needed
)
12610 /* If we have not found any free argument registers and
12611 reg a4 contains the return address, we must move it. */
12612 if (regs_available_for_popping
== 0
12613 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12615 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12616 reg_containing_return_addr
= LR_REGNUM
;
12618 else if (size
> 12)
12620 /* Register a4 is being used to hold part of the return value,
12621 but we have dire need of a free, low register. */
12624 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12627 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12629 /* The fourth argument register is available. */
12630 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12636 /* Pop as many registers as we can. */
12637 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12638 regs_available_for_popping
);
12640 /* Process the registers we popped. */
12641 if (reg_containing_return_addr
== -1)
12643 /* The return address was popped into the lowest numbered register. */
12644 regs_to_pop
&= ~(1 << LR_REGNUM
);
12646 reg_containing_return_addr
=
12647 number_of_first_bit_set (regs_available_for_popping
);
12649 /* Remove this register for the mask of available registers, so that
12650 the return address will not be corrupted by further pops. */
12651 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12654 /* If we popped other registers then handle them here. */
12655 if (regs_available_for_popping
)
12659 /* Work out which register currently contains the frame pointer. */
12660 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12662 /* Move it into the correct place. */
12663 asm_fprintf (f
, "\tmov\t%r, %r\n",
12664 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12666 /* (Temporarily) remove it from the mask of popped registers. */
12667 regs_available_for_popping
&= ~(1 << frame_pointer
);
12668 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12670 if (regs_available_for_popping
)
12674 /* We popped the stack pointer as well,
12675 find the register that contains it. */
12676 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12678 /* Move it into the stack register. */
12679 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12681 /* At this point we have popped all necessary registers, so
12682 do not worry about restoring regs_available_for_popping
12683 to its correct value:
12685 assert (pops_needed == 0)
12686 assert (regs_available_for_popping == (1 << frame_pointer))
12687 assert (regs_to_pop == (1 << STACK_POINTER)) */
12691 /* Since we have just move the popped value into the frame
12692 pointer, the popping register is available for reuse, and
12693 we know that we still have the stack pointer left to pop. */
12694 regs_available_for_popping
|= (1 << frame_pointer
);
12698 /* If we still have registers left on the stack, but we no longer have
12699 any registers into which we can pop them, then we must move the return
12700 address into the link register and make available the register that
12702 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12704 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12706 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12707 reg_containing_return_addr
);
12709 reg_containing_return_addr
= LR_REGNUM
;
12712 /* If we have registers left on the stack then pop some more.
12713 We know that at most we will want to pop FP and SP. */
12714 if (pops_needed
> 0)
12719 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12720 regs_available_for_popping
);
12722 /* We have popped either FP or SP.
12723 Move whichever one it is into the correct register. */
12724 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12725 move_to
= number_of_first_bit_set (regs_to_pop
);
12727 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12729 regs_to_pop
&= ~(1 << move_to
);
12734 /* If we still have not popped everything then we must have only
12735 had one register available to us and we are now popping the SP. */
12736 if (pops_needed
> 0)
12740 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12741 regs_available_for_popping
);
12743 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12745 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12747 assert (regs_to_pop == (1 << STACK_POINTER))
12748 assert (pops_needed == 1)
12752 /* If necessary restore the a4 register. */
12755 if (reg_containing_return_addr
!= LR_REGNUM
)
12757 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12758 reg_containing_return_addr
= LR_REGNUM
;
12761 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12765 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
12767 /* Return to caller. */
12768 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12771 /* Emit code to push or pop registers to or from the stack. F is the
12772 assembly file. MASK is the registers to push or pop. PUSH is
12773 nonzero if we should push, and zero if we should pop. For debugging
12774 output, if pushing, adjust CFA_OFFSET by the amount of space added
12775 to the stack. REAL_REGS should have the same number of bits set as
12776 MASK, and will be used instead (in the same order) to describe which
12777 registers were saved - this is used to mark the save slots when we
12778 push high registers after moving them to low registers. */
12780 thumb_pushpop (FILE *f
, int mask
, int push
, int *cfa_offset
, int real_regs
)
12783 int lo_mask
= mask
& 0xFF;
12784 int pushed_words
= 0;
12786 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
12788 /* Special case. Do not generate a POP PC statement here, do it in
12790 thumb_exit (f
, -1, NULL_RTX
);
12794 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12796 /* Look at the low registers first. */
12797 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12801 asm_fprintf (f
, "%r", regno
);
12803 if ((lo_mask
& ~1) != 0)
12810 if (push
&& (mask
& (1 << LR_REGNUM
)))
12812 /* Catch pushing the LR. */
12816 asm_fprintf (f
, "%r", LR_REGNUM
);
12820 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12822 /* Catch popping the PC. */
12823 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
12825 /* The PC is never poped directly, instead
12826 it is popped into r3 and then BX is used. */
12827 fprintf (f
, "}\n");
12829 thumb_exit (f
, -1, NULL_RTX
);
12838 asm_fprintf (f
, "%r", PC_REGNUM
);
12842 fprintf (f
, "}\n");
12844 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12846 char *l
= dwarf2out_cfi_label ();
12847 int pushed_mask
= real_regs
;
12849 *cfa_offset
+= pushed_words
* 4;
12850 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12853 pushed_mask
= real_regs
;
12854 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12856 if (pushed_mask
& 1)
12857 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12863 thumb_final_prescan_insn (rtx insn
)
12865 if (flag_print_asm_name
)
12866 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12867 INSN_ADDRESSES (INSN_UID (insn
)));
12871 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12873 unsigned HOST_WIDE_INT mask
= 0xff;
12876 if (val
== 0) /* XXX */
12879 for (i
= 0; i
< 25; i
++)
12880 if ((val
& (mask
<< i
)) == val
)
12886 /* Returns nonzero if the current function contains,
12887 or might contain a far jump. */
12889 thumb_far_jump_used_p (void)
12893 /* This test is only important for leaf functions. */
12894 /* assert (!leaf_function_p ()); */
12896 /* If we have already decided that far jumps may be used,
12897 do not bother checking again, and always return true even if
12898 it turns out that they are not being used. Once we have made
12899 the decision that far jumps are present (and that hence the link
12900 register will be pushed onto the stack) we cannot go back on it. */
12901 if (cfun
->machine
->far_jump_used
)
12904 /* If this function is not being called from the prologue/epilogue
12905 generation code then it must be being called from the
12906 INITIAL_ELIMINATION_OFFSET macro. */
12907 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12909 /* In this case we know that we are being asked about the elimination
12910 of the arg pointer register. If that register is not being used,
12911 then there are no arguments on the stack, and we do not have to
12912 worry that a far jump might force the prologue to push the link
12913 register, changing the stack offsets. In this case we can just
12914 return false, since the presence of far jumps in the function will
12915 not affect stack offsets.
12917 If the arg pointer is live (or if it was live, but has now been
12918 eliminated and so set to dead) then we do have to test to see if
12919 the function might contain a far jump. This test can lead to some
12920 false negatives, since before reload is completed, then length of
12921 branch instructions is not known, so gcc defaults to returning their
12922 longest length, which in turn sets the far jump attribute to true.
12924 A false negative will not result in bad code being generated, but it
12925 will result in a needless push and pop of the link register. We
12926 hope that this does not occur too often.
12928 If we need doubleword stack alignment this could affect the other
12929 elimination offsets so we can't risk getting it wrong. */
12930 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12931 cfun
->machine
->arg_pointer_live
= 1;
12932 else if (!cfun
->machine
->arg_pointer_live
)
12936 /* Check to see if the function contains a branch
12937 insn with the far jump attribute set. */
12938 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12940 if (GET_CODE (insn
) == JUMP_INSN
12941 /* Ignore tablejump patterns. */
12942 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
12943 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
12944 && get_attr_far_jump (insn
) == FAR_JUMP_YES
12947 /* Record the fact that we have decided that
12948 the function does use far jumps. */
12949 cfun
->machine
->far_jump_used
= 1;
12957 /* Return nonzero if FUNC must be entered in ARM mode. */
12959 is_called_in_ARM_mode (tree func
)
12961 if (TREE_CODE (func
) != FUNCTION_DECL
)
12964 /* Ignore the problem about functions whoes address is taken. */
12965 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
12969 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
12975 /* The bits which aren't usefully expanded as rtl. */
12977 thumb_unexpanded_epilogue (void)
12980 int live_regs_mask
= 0;
12981 int high_regs_pushed
= 0;
12982 int leaf_function
= leaf_function_p ();
12983 int had_to_push_lr
;
12984 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
12986 if (return_used_this_function
)
12989 if (IS_NAKED (arm_current_func_type ()))
12992 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12993 if (THUMB_REG_PUSHED_P (regno
))
12994 live_regs_mask
|= 1 << regno
;
12996 for (regno
= 8; regno
< 13; regno
++)
12997 if (THUMB_REG_PUSHED_P (regno
))
12998 high_regs_pushed
++;
13000 /* The prolog may have pushed some high registers to use as
13001 work registers. eg the testsuite file:
13002 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13003 compiles to produce:
13004 push {r4, r5, r6, r7, lr}
13008 as part of the prolog. We have to undo that pushing here. */
13010 if (high_regs_pushed
)
13012 int mask
= live_regs_mask
;
13018 /* If we can deduce the registers used from the function's return value.
13019 This is more reliable that examining regs_ever_live[] because that
13020 will be set if the register is ever used in the function, not just if
13021 the register is used to hold a return value. */
13023 if (current_function_return_rtx
!= 0)
13024 mode
= GET_MODE (current_function_return_rtx
);
13027 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13029 size
= GET_MODE_SIZE (mode
);
13031 /* Unless we are returning a type of size > 12 register r3 is
13037 /* Oh dear! We have no low registers into which we can pop
13040 ("no low registers available for popping high registers");
13042 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13043 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13046 while (high_regs_pushed
)
13048 /* Find lo register(s) into which the high register(s) can
13050 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13052 if (mask
& (1 << regno
))
13053 high_regs_pushed
--;
13054 if (high_regs_pushed
== 0)
13058 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13060 /* Pop the values into the low register(s). */
13061 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13063 /* Move the value(s) into the high registers. */
13064 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13066 if (mask
& (1 << regno
))
13068 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13071 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13072 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13079 had_to_push_lr
= (live_regs_mask
|| !leaf_function
13080 || thumb_far_jump_used_p ());
13082 if (TARGET_BACKTRACE
13083 && ((live_regs_mask
& 0xFF) == 0)
13084 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
13086 /* The stack backtrace structure creation code had to
13087 push R7 in order to get a work register, so we pop
13089 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13092 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13095 && !is_called_in_ARM_mode (current_function_decl
)
13097 live_regs_mask
|= 1 << PC_REGNUM
;
13099 /* Either no argument registers were pushed or a backtrace
13100 structure was created which includes an adjusted stack
13101 pointer, so just pop everything. */
13102 if (live_regs_mask
)
13103 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13107 thumb_exit (asm_out_file
, 2, eh_ofs
);
13108 /* We have either just popped the return address into the
13109 PC or it is was kept in LR for the entire function or
13110 it is still on the stack because we do not want to
13111 return by doing a pop {pc}. */
13112 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
13113 thumb_exit (asm_out_file
,
13115 && is_called_in_ARM_mode (current_function_decl
)) ?
13116 -1 : LR_REGNUM
, NULL_RTX
);
13120 /* Pop everything but the return address. */
13121 live_regs_mask
&= ~(1 << PC_REGNUM
);
13123 if (live_regs_mask
)
13124 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13127 if (had_to_push_lr
)
13128 /* Get the return address into a temporary register. */
13129 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13130 1 << LAST_ARG_REGNUM
);
13132 /* Remove the argument registers that were pushed onto the stack. */
13133 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13134 SP_REGNUM
, SP_REGNUM
,
13135 current_function_pretend_args_size
);
13138 thumb_exit (asm_out_file
, 2, eh_ofs
);
13140 thumb_exit (asm_out_file
,
13141 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
13147 /* Functions to save and restore machine-specific function data. */
13148 static struct machine_function
*
13149 arm_init_machine_status (void)
13151 struct machine_function
*machine
;
13152 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13154 #if ARM_FT_UNKNOWN != 0
13155 machine
->func_type
= ARM_FT_UNKNOWN
;
13160 /* Return an RTX indicating where the return address to the
13161 calling function can be found. */
13163 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13168 if (TARGET_APCS_32
)
13169 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13172 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
13173 GEN_INT (RETURN_ADDR_MASK26
));
13174 return get_func_hard_reg_initial_val (cfun
, lr
);
13178 /* Do anything needed before RTL is emitted for each function. */
13180 arm_init_expanders (void)
13182 /* Arrange to initialize and mark the machine per-function status. */
13183 init_machine_status
= arm_init_machine_status
;
13187 /* Like arm_compute_initial_elimination offset. Simpler because
13188 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13191 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13193 arm_stack_offsets
*offsets
;
13195 offsets
= arm_get_frame_offsets ();
13199 case ARG_POINTER_REGNUM
:
13202 case STACK_POINTER_REGNUM
:
13203 return offsets
->outgoing_args
- offsets
->saved_args
;
13205 case FRAME_POINTER_REGNUM
:
13206 return offsets
->soft_frame
- offsets
->saved_args
;
13208 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13209 case ARM_HARD_FRAME_POINTER_REGNUM
:
13210 return offsets
->saved_regs
- offsets
->saved_args
;
13217 case FRAME_POINTER_REGNUM
:
13220 case STACK_POINTER_REGNUM
:
13221 return offsets
->outgoing_args
- offsets
->soft_frame
;
13223 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13224 case ARM_HARD_FRAME_POINTER_REGNUM
:
13225 return offsets
->saved_regs
- offsets
->soft_frame
;
13238 /* Generate the rest of a function's prologue. */
13240 thumb_expand_prologue (void)
13244 HOST_WIDE_INT amount
;
13245 arm_stack_offsets
*offsets
;
13246 unsigned long func_type
;
13248 func_type
= arm_current_func_type ();
13250 /* Naked functions don't have prologues. */
13251 if (IS_NAKED (func_type
))
13254 if (IS_INTERRUPT (func_type
))
13256 error ("interrupt Service Routines cannot be coded in Thumb mode");
13260 offsets
= arm_get_frame_offsets ();
13262 if (frame_pointer_needed
)
13264 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
13265 stack_pointer_rtx
));
13266 RTX_FRAME_RELATED_P (insn
) = 1;
13269 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13274 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13275 GEN_INT (- amount
)));
13276 RTX_FRAME_RELATED_P (insn
) = 1;
13283 /* The stack decrement is too big for an immediate value in a single
13284 insn. In theory we could issue multiple subtracts, but after
13285 three of them it becomes more space efficient to place the full
13286 value in the constant pool and load into a register. (Also the
13287 ARM debugger really likes to see only one stack decrement per
13288 function). So instead we look for a scratch register into which
13289 we can load the decrement, and then we subtract this from the
13290 stack pointer. Unfortunately on the thumb the only available
13291 scratch registers are the argument registers, and we cannot use
13292 these as they may hold arguments to the function. Instead we
13293 attempt to locate a call preserved register which is used by this
13294 function. If we can find one, then we know that it will have
13295 been pushed at the start of the prologue and so we can corrupt
13297 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13298 if (THUMB_REG_PUSHED_P (regno
)
13299 && !(frame_pointer_needed
13300 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13303 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13305 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13307 /* Choose an arbitrary, non-argument low register. */
13308 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13310 /* Save it by copying it into a high, scratch register. */
13311 emit_insn (gen_movsi (spare
, reg
));
13312 /* Add a USE to stop propagate_one_insn() from barfing. */
13313 emit_insn (gen_prologue_use (spare
));
13315 /* Decrement the stack. */
13316 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13317 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13318 stack_pointer_rtx
, reg
));
13319 RTX_FRAME_RELATED_P (insn
) = 1;
13320 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13321 plus_constant (stack_pointer_rtx
,
13322 GEN_INT (- amount
)));
13323 RTX_FRAME_RELATED_P (dwarf
) = 1;
13325 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13328 /* Restore the low register's original value. */
13329 emit_insn (gen_movsi (reg
, spare
));
13331 /* Emit a USE of the restored scratch register, so that flow
13332 analysis will not consider the restore redundant. The
13333 register won't be used again in this function and isn't
13334 restored by the epilogue. */
13335 emit_insn (gen_prologue_use (reg
));
13339 reg
= gen_rtx_REG (SImode
, regno
);
13341 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13343 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13344 stack_pointer_rtx
, reg
));
13345 RTX_FRAME_RELATED_P (insn
) = 1;
13346 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13347 plus_constant (stack_pointer_rtx
,
13348 GEN_INT (- amount
)));
13349 RTX_FRAME_RELATED_P (dwarf
) = 1;
13351 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13355 /* If the frame pointer is needed, emit a special barrier that
13356 will prevent the scheduler from moving stores to the frame
13357 before the stack adjustment. */
13358 if (frame_pointer_needed
)
13359 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13360 hard_frame_pointer_rtx
));
13363 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13364 emit_insn (gen_blockage ());
13368 thumb_expand_epilogue (void)
13370 HOST_WIDE_INT amount
;
13371 arm_stack_offsets
*offsets
;
13374 /* Naked functions don't have prologues. */
13375 if (IS_NAKED (arm_current_func_type ()))
13378 offsets
= arm_get_frame_offsets ();
13379 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13381 if (frame_pointer_needed
)
13382 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13386 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13387 GEN_INT (amount
)));
13390 /* r3 is always free in the epilogue. */
13391 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13393 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13394 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13398 /* Emit a USE (stack_pointer_rtx), so that
13399 the stack adjustment will not be deleted. */
13400 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13402 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13403 emit_insn (gen_blockage ());
13405 /* Emit a clobber for each insn that will be restored in the epilogue,
13406 so that flow2 will get register lifetimes correct. */
13407 for (regno
= 0; regno
< 13; regno
++)
13408 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13409 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13411 if (! regs_ever_live
[LR_REGNUM
])
13412 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13416 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13418 int live_regs_mask
= 0;
13419 int high_regs_pushed
= 0;
13420 int cfa_offset
= 0;
13423 if (IS_NAKED (arm_current_func_type ()))
13426 if (is_called_in_ARM_mode (current_function_decl
))
13430 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
13432 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
13434 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13436 /* Generate code sequence to switch us into Thumb mode. */
13437 /* The .code 32 directive has already been emitted by
13438 ASM_DECLARE_FUNCTION_NAME. */
13439 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13440 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13442 /* Generate a label, so that the debugger will notice the
13443 change in instruction sets. This label is also used by
13444 the assembler to bypass the ARM code when this function
13445 is called from a Thumb encoded function elsewhere in the
13446 same file. Hence the definition of STUB_NAME here must
13447 agree with the definition in gas/config/tc-arm.c. */
13449 #define STUB_NAME ".real_start_of"
13451 fprintf (f
, "\t.code\t16\n");
13453 if (arm_dllexport_name_p (name
))
13454 name
= arm_strip_name_encoding (name
);
13456 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13457 fprintf (f
, "\t.thumb_func\n");
13458 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13461 if (current_function_pretend_args_size
)
13463 if (cfun
->machine
->uses_anonymous_args
)
13467 fprintf (f
, "\tpush\t{");
13469 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13471 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13472 regno
<= LAST_ARG_REGNUM
;
13474 asm_fprintf (f
, "%r%s", regno
,
13475 regno
== LAST_ARG_REGNUM
? "" : ", ");
13477 fprintf (f
, "}\n");
13480 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13481 SP_REGNUM
, SP_REGNUM
,
13482 current_function_pretend_args_size
);
13484 /* We don't need to record the stores for unwinding (would it
13485 help the debugger any if we did?), but record the change in
13486 the stack pointer. */
13487 if (dwarf2out_do_frame ())
13489 char *l
= dwarf2out_cfi_label ();
13490 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13491 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13495 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13496 if (THUMB_REG_PUSHED_P (regno
))
13497 live_regs_mask
|= 1 << regno
;
13499 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p ())
13500 live_regs_mask
|= 1 << LR_REGNUM
;
13502 if (TARGET_BACKTRACE
)
13505 int work_register
= 0;
13508 /* We have been asked to create a stack backtrace structure.
13509 The code looks like this:
13513 0 sub SP, #16 Reserve space for 4 registers.
13514 2 push {R7} Get a work register.
13515 4 add R7, SP, #20 Get the stack pointer before the push.
13516 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13517 8 mov R7, PC Get hold of the start of this code plus 12.
13518 10 str R7, [SP, #16] Store it.
13519 12 mov R7, FP Get hold of the current frame pointer.
13520 14 str R7, [SP, #4] Store it.
13521 16 mov R7, LR Get hold of the current return address.
13522 18 str R7, [SP, #12] Store it.
13523 20 add R7, SP, #16 Point at the start of the backtrace structure.
13524 22 mov FP, R7 Put this value into the frame pointer. */
13526 if ((live_regs_mask
& 0xFF) == 0)
13528 /* See if the a4 register is free. */
13530 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
13531 work_register
= LAST_ARG_REGNUM
;
13532 else /* We must push a register of our own. */
13533 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13536 if (work_register
== 0)
13538 /* Select a register from the list that will be pushed to
13539 use as our work register. */
13540 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
13541 if ((1 << work_register
) & live_regs_mask
)
13546 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13547 SP_REGNUM
, SP_REGNUM
);
13549 if (dwarf2out_do_frame ())
13551 char *l
= dwarf2out_cfi_label ();
13552 cfa_offset
= cfa_offset
+ 16;
13553 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13556 if (live_regs_mask
)
13557 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13559 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
13560 if (wr
& live_regs_mask
)
13563 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13564 offset
+ 16 + current_function_pretend_args_size
);
13566 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13569 /* Make sure that the instruction fetching the PC is in the right place
13570 to calculate "start of backtrace creation code + 12". */
13571 if (live_regs_mask
)
13573 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13574 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13576 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13577 ARM_HARD_FRAME_POINTER_REGNUM
);
13578 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13583 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13584 ARM_HARD_FRAME_POINTER_REGNUM
);
13585 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13587 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13588 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13592 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13593 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13595 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13597 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13598 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13600 else if (live_regs_mask
)
13601 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13603 for (regno
= 8; regno
< 13; regno
++)
13604 if (THUMB_REG_PUSHED_P (regno
))
13605 high_regs_pushed
++;
13607 if (high_regs_pushed
)
13609 int pushable_regs
= 0;
13610 int mask
= live_regs_mask
& 0xff;
13613 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13614 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13617 pushable_regs
= mask
;
13619 if (pushable_regs
== 0)
13621 /* Desperation time -- this probably will never happen. */
13622 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
13623 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
13624 mask
= 1 << LAST_ARG_REGNUM
;
13627 while (high_regs_pushed
> 0)
13629 int real_regs_mask
= 0;
13631 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13633 if (mask
& (1 << regno
))
13635 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13637 high_regs_pushed
--;
13638 real_regs_mask
|= (1 << next_hi_reg
);
13640 if (high_regs_pushed
)
13642 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13644 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13649 mask
&= ~((1 << regno
) - 1);
13655 thumb_pushpop (f
, mask
, 1, &cfa_offset
, real_regs_mask
);
13658 if (pushable_regs
== 0
13659 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
13660 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13664 /* Handle the case of a double word load into a low register from
13665 a computed memory address. The computed address may involve a
13666 register which is overwritten by the load. */
13668 thumb_load_double_from_address (rtx
*operands
)
13676 if (GET_CODE (operands
[0]) != REG
)
13679 if (GET_CODE (operands
[1]) != MEM
)
13682 /* Get the memory address. */
13683 addr
= XEXP (operands
[1], 0);
13685 /* Work out how the memory address is computed. */
13686 switch (GET_CODE (addr
))
13689 operands
[2] = gen_rtx_MEM (SImode
,
13690 plus_constant (XEXP (operands
[1], 0), 4));
13692 if (REGNO (operands
[0]) == REGNO (addr
))
13694 output_asm_insn ("ldr\t%H0, %2", operands
);
13695 output_asm_insn ("ldr\t%0, %1", operands
);
13699 output_asm_insn ("ldr\t%0, %1", operands
);
13700 output_asm_insn ("ldr\t%H0, %2", operands
);
13705 /* Compute <address> + 4 for the high order load. */
13706 operands
[2] = gen_rtx_MEM (SImode
,
13707 plus_constant (XEXP (operands
[1], 0), 4));
13709 output_asm_insn ("ldr\t%0, %1", operands
);
13710 output_asm_insn ("ldr\t%H0, %2", operands
);
13714 arg1
= XEXP (addr
, 0);
13715 arg2
= XEXP (addr
, 1);
13717 if (CONSTANT_P (arg1
))
13718 base
= arg2
, offset
= arg1
;
13720 base
= arg1
, offset
= arg2
;
13722 if (GET_CODE (base
) != REG
)
13725 /* Catch the case of <address> = <reg> + <reg> */
13726 if (GET_CODE (offset
) == REG
)
13728 int reg_offset
= REGNO (offset
);
13729 int reg_base
= REGNO (base
);
13730 int reg_dest
= REGNO (operands
[0]);
13732 /* Add the base and offset registers together into the
13733 higher destination register. */
13734 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13735 reg_dest
+ 1, reg_base
, reg_offset
);
13737 /* Load the lower destination register from the address in
13738 the higher destination register. */
13739 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13740 reg_dest
, reg_dest
+ 1);
13742 /* Load the higher destination register from its own address
13744 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13745 reg_dest
+ 1, reg_dest
+ 1);
13749 /* Compute <address> + 4 for the high order load. */
13750 operands
[2] = gen_rtx_MEM (SImode
,
13751 plus_constant (XEXP (operands
[1], 0), 4));
13753 /* If the computed address is held in the low order register
13754 then load the high order register first, otherwise always
13755 load the low order register first. */
13756 if (REGNO (operands
[0]) == REGNO (base
))
13758 output_asm_insn ("ldr\t%H0, %2", operands
);
13759 output_asm_insn ("ldr\t%0, %1", operands
);
13763 output_asm_insn ("ldr\t%0, %1", operands
);
13764 output_asm_insn ("ldr\t%H0, %2", operands
);
13770 /* With no registers to worry about we can just load the value
13772 operands
[2] = gen_rtx_MEM (SImode
,
13773 plus_constant (XEXP (operands
[1], 0), 4));
13775 output_asm_insn ("ldr\t%H0, %2", operands
);
13776 output_asm_insn ("ldr\t%0, %1", operands
);
13788 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13795 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13798 operands
[4] = operands
[5];
13801 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13802 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13806 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13809 operands
[4] = operands
[5];
13812 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13815 operands
[5] = operands
[6];
13818 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13821 operands
[4] = operands
[5];
13825 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13826 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13836 /* Routines for generating rtl. */
13838 thumb_expand_movstrqi (rtx
*operands
)
13840 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13841 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13842 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13843 HOST_WIDE_INT offset
= 0;
13847 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13853 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13859 rtx reg
= gen_reg_rtx (SImode
);
13860 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13861 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13868 rtx reg
= gen_reg_rtx (HImode
);
13869 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13870 plus_constant (in
, offset
))));
13871 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13879 rtx reg
= gen_reg_rtx (QImode
);
13880 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13881 plus_constant (in
, offset
))));
13882 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13888 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
13890 return ((GET_CODE (op
) == CONST_INT
13891 && INTVAL (op
) < 256
13892 && INTVAL (op
) >= 0)
13893 || s_register_operand (op
, mode
));
13897 thumb_cmpneg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
13899 return (GET_CODE (op
) == CONST_INT
13901 && INTVAL (op
) > -256);
13904 /* Return TRUE if a result can be stored in OP without clobbering the
13905 condition code register. Prior to reload we only accept a
13906 register. After reload we have to be able to handle memory as
13907 well, since a pseudo may not get a hard reg and reload cannot
13908 handle output-reloads on jump insns.
13910 We could possibly handle mem before reload as well, but that might
13911 complicate things with the need to handle increment
13915 thumb_cbrch_target_operand (rtx op
, enum machine_mode mode
)
13917 return (s_register_operand (op
, mode
)
13918 || ((reload_in_progress
|| reload_completed
)
13919 && memory_operand (op
, mode
)));
13922 /* Handle storing a half-word to memory during reload. */
13924 thumb_reload_out_hi (rtx
*operands
)
13926 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13929 /* Handle reading a half-word from memory during reload. */
13931 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13936 /* Return the length of a function name prefix
13937 that starts with the character 'c'. */
13939 arm_get_strip_length (int c
)
13943 ARM_NAME_ENCODING_LENGTHS
13948 /* Return a pointer to a function's name with any
13949 and all prefix encodings stripped from it. */
13951 arm_strip_name_encoding (const char *name
)
13955 while ((skip
= arm_get_strip_length (* name
)))
13961 /* If there is a '*' anywhere in the name's prefix, then
13962 emit the stripped name verbatim, otherwise prepend an
13963 underscore if leading underscores are being used. */
13965 arm_asm_output_labelref (FILE *stream
, const char *name
)
13970 while ((skip
= arm_get_strip_length (* name
)))
13972 verbatim
|= (*name
== '*');
13977 fputs (name
, stream
);
13979 asm_fprintf (stream
, "%U%s", name
);
13984 #ifdef AOF_ASSEMBLER
13985 /* Special functions only needed when producing AOF syntax assembler. */
13989 struct pic_chain
* next
;
13990 const char * symname
;
13993 static struct pic_chain
* aof_pic_chain
= NULL
;
13996 aof_pic_entry (rtx x
)
13998 struct pic_chain
** chainp
;
14001 if (aof_pic_label
== NULL_RTX
)
14003 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14006 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14007 offset
+= 4, chainp
= &(*chainp
)->next
)
14008 if ((*chainp
)->symname
== XSTR (x
, 0))
14009 return plus_constant (aof_pic_label
, offset
);
14011 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14012 (*chainp
)->next
= NULL
;
14013 (*chainp
)->symname
= XSTR (x
, 0);
14014 return plus_constant (aof_pic_label
, offset
);
14018 aof_dump_pic_table (FILE *f
)
14020 struct pic_chain
* chain
;
14022 if (aof_pic_chain
== NULL
)
14025 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14026 PIC_OFFSET_TABLE_REGNUM
,
14027 PIC_OFFSET_TABLE_REGNUM
);
14028 fputs ("|x$adcons|\n", f
);
14030 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14032 fputs ("\tDCD\t", f
);
14033 assemble_name (f
, chain
->symname
);
14038 int arm_text_section_count
= 1;
14041 aof_text_section (void )
14043 static char buf
[100];
14044 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14045 arm_text_section_count
++);
14047 strcat (buf
, ", PIC, REENTRANT");
14051 static int arm_data_section_count
= 1;
14054 aof_data_section (void)
14056 static char buf
[100];
14057 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14061 /* The AOF assembler is religiously strict about declarations of
14062 imported and exported symbols, so that it is impossible to declare
14063 a function as imported near the beginning of the file, and then to
14064 export it later on. It is, however, possible to delay the decision
14065 until all the functions in the file have been compiled. To get
14066 around this, we maintain a list of the imports and exports, and
14067 delete from it any that are subsequently defined. At the end of
14068 compilation we spit the remainder of the list out before the END
14073 struct import
* next
;
14077 static struct import
* imports_list
= NULL
;
14080 aof_add_import (const char *name
)
14082 struct import
* new;
14084 for (new = imports_list
; new; new = new->next
)
14085 if (new->name
== name
)
14088 new = (struct import
*) xmalloc (sizeof (struct import
));
14089 new->next
= imports_list
;
14090 imports_list
= new;
14095 aof_delete_import (const char *name
)
14097 struct import
** old
;
14099 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14101 if ((*old
)->name
== name
)
14103 *old
= (*old
)->next
;
14109 int arm_main_function
= 0;
14112 aof_dump_imports (FILE *f
)
14114 /* The AOF assembler needs this to cause the startup code to be extracted
14115 from the library. Brining in __main causes the whole thing to work
14117 if (arm_main_function
)
14120 fputs ("\tIMPORT __main\n", f
);
14121 fputs ("\tDCD __main\n", f
);
14124 /* Now dump the remaining imports. */
14125 while (imports_list
)
14127 fprintf (f
, "\tIMPORT\t");
14128 assemble_name (f
, imports_list
->name
);
14130 imports_list
= imports_list
->next
;
14135 aof_globalize_label (FILE *stream
, const char *name
)
14137 default_globalize_label (stream
, name
);
14138 if (! strcmp (name
, "main"))
14139 arm_main_function
= 1;
14143 aof_file_start (void)
14145 fputs ("__r0\tRN\t0\n", asm_out_file
);
14146 fputs ("__a1\tRN\t0\n", asm_out_file
);
14147 fputs ("__a2\tRN\t1\n", asm_out_file
);
14148 fputs ("__a3\tRN\t2\n", asm_out_file
);
14149 fputs ("__a4\tRN\t3\n", asm_out_file
);
14150 fputs ("__v1\tRN\t4\n", asm_out_file
);
14151 fputs ("__v2\tRN\t5\n", asm_out_file
);
14152 fputs ("__v3\tRN\t6\n", asm_out_file
);
14153 fputs ("__v4\tRN\t7\n", asm_out_file
);
14154 fputs ("__v5\tRN\t8\n", asm_out_file
);
14155 fputs ("__v6\tRN\t9\n", asm_out_file
);
14156 fputs ("__sl\tRN\t10\n", asm_out_file
);
14157 fputs ("__fp\tRN\t11\n", asm_out_file
);
14158 fputs ("__ip\tRN\t12\n", asm_out_file
);
14159 fputs ("__sp\tRN\t13\n", asm_out_file
);
14160 fputs ("__lr\tRN\t14\n", asm_out_file
);
14161 fputs ("__pc\tRN\t15\n", asm_out_file
);
14162 fputs ("__f0\tFN\t0\n", asm_out_file
);
14163 fputs ("__f1\tFN\t1\n", asm_out_file
);
14164 fputs ("__f2\tFN\t2\n", asm_out_file
);
14165 fputs ("__f3\tFN\t3\n", asm_out_file
);
14166 fputs ("__f4\tFN\t4\n", asm_out_file
);
14167 fputs ("__f5\tFN\t5\n", asm_out_file
);
14168 fputs ("__f6\tFN\t6\n", asm_out_file
);
14169 fputs ("__f7\tFN\t7\n", asm_out_file
);
14174 aof_file_end (void)
14177 aof_dump_pic_table (asm_out_file
);
14178 aof_dump_imports (asm_out_file
);
14179 fputs ("\tEND\n", asm_out_file
);
14181 #endif /* AOF_ASSEMBLER */
14183 #ifdef OBJECT_FORMAT_ELF
14184 /* Switch to an arbitrary section NAME with attributes as specified
14185 by FLAGS. ALIGN specifies any known alignment requirements for
14186 the section; 0 if the default should be used.
14188 Differs from the default elf version only in the prefix character
14189 used before the section type. */
14192 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
14194 char flagchars
[10], *f
= flagchars
;
14196 if (! named_section_first_declaration (name
))
14198 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
14202 if (!(flags
& SECTION_DEBUG
))
14204 if (flags
& SECTION_WRITE
)
14206 if (flags
& SECTION_CODE
)
14208 if (flags
& SECTION_SMALL
)
14210 if (flags
& SECTION_MERGE
)
14212 if (flags
& SECTION_STRINGS
)
14214 if (flags
& SECTION_TLS
)
14218 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
14220 if (!(flags
& SECTION_NOTYPE
))
14224 if (flags
& SECTION_BSS
)
14229 fprintf (asm_out_file
, ",%%%s", type
);
14231 if (flags
& SECTION_ENTSIZE
)
14232 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
14235 putc ('\n', asm_out_file
);
14240 /* Symbols in the text segment can be accessed without indirecting via the
14241 constant pool; it may take an extra binary operation, but this is still
14242 faster than indirecting via memory. Don't do this when not optimizing,
14243 since we won't be calculating al of the offsets necessary to do this
14247 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14249 /* This doesn't work with AOF syntax, since the string table may be in
14250 a different AREA. */
14251 #ifndef AOF_ASSEMBLER
14252 if (optimize
> 0 && TREE_CONSTANT (decl
))
14253 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14256 /* If we are referencing a function that is weak then encode a long call
14257 flag in the function name, otherwise if the function is static or
14258 or known to be defined in this file then encode a short call flag. */
14259 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
14261 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14262 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14263 else if (! TREE_PUBLIC (decl
))
14264 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14267 #endif /* !ARM_PE */
14270 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14272 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14273 && !strcmp (prefix
, "L"))
14275 arm_ccfsm_state
= 0;
14276 arm_target_insn
= NULL
;
14278 default_internal_label (stream
, prefix
, labelno
);
14281 /* Output code to add DELTA to the first argument, and then jump
14282 to FUNCTION. Used for C++ multiple inheritance. */
14284 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14285 HOST_WIDE_INT delta
,
14286 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14289 static int thunk_label
= 0;
14291 int mi_delta
= delta
;
14292 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14294 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14297 mi_delta
= - mi_delta
;
14300 int labelno
= thunk_label
++;
14301 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14302 fputs ("\tldr\tr12, ", file
);
14303 assemble_name (file
, label
);
14304 fputc ('\n', file
);
14306 while (mi_delta
!= 0)
14308 if ((mi_delta
& (3 << shift
)) == 0)
14312 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14313 mi_op
, this_regno
, this_regno
,
14314 mi_delta
& (0xff << shift
));
14315 mi_delta
&= ~(0xff << shift
);
14321 fprintf (file
, "\tbx\tr12\n");
14322 ASM_OUTPUT_ALIGN (file
, 2);
14323 assemble_name (file
, label
);
14324 fputs (":\n", file
);
14325 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14329 fputs ("\tb\t", file
);
14330 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14331 if (NEED_PLT_RELOC
)
14332 fputs ("(PLT)", file
);
14333 fputc ('\n', file
);
14338 arm_emit_vector_const (FILE *file
, rtx x
)
14341 const char * pattern
;
14343 if (GET_CODE (x
) != CONST_VECTOR
)
14346 switch (GET_MODE (x
))
14348 case V2SImode
: pattern
= "%08x"; break;
14349 case V4HImode
: pattern
= "%04x"; break;
14350 case V8QImode
: pattern
= "%02x"; break;
14354 fprintf (file
, "0x");
14355 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14359 element
= CONST_VECTOR_ELT (x
, i
);
14360 fprintf (file
, pattern
, INTVAL (element
));
14367 arm_output_load_gr (rtx
*operands
)
14374 if (GET_CODE (operands
[1]) != MEM
14375 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14376 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14377 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14378 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14379 return "wldrw%?\t%0, %1";
14381 /* Fix up an out-of-range load of a GR register. */
14382 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14383 wcgr
= operands
[0];
14385 output_asm_insn ("ldr%?\t%0, %1", operands
);
14387 operands
[0] = wcgr
;
14389 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14390 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14396 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14397 int incoming ATTRIBUTE_UNUSED
)
14400 /* FIXME: The ARM backend has special code to handle structure
14401 returns, and will reserve its own hidden first argument. So
14402 if this macro is enabled a *second* hidden argument will be
14403 reserved, which will break binary compatibility with old
14404 toolchains and also thunk handling. One day this should be
14408 /* Register in which address to store a structure value
14409 is passed to a function. */
14410 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14414 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14416 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14417 named arg and all anonymous args onto the stack.
14418 XXX I know the prologue shouldn't be pushing registers, but it is faster
14422 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14423 enum machine_mode mode ATTRIBUTE_UNUSED
,
14424 tree type ATTRIBUTE_UNUSED
,
14426 int second_time ATTRIBUTE_UNUSED
)
14428 cfun
->machine
->uses_anonymous_args
= 1;
14429 if (cum
->nregs
< NUM_ARG_REGS
)
14430 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14433 /* Return nonzero if the CONSUMER instruction (a store) does not need
14434 PRODUCER's value to calculate the address. */
14437 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14439 rtx value
= PATTERN (producer
);
14440 rtx addr
= PATTERN (consumer
);
14442 if (GET_CODE (value
) == COND_EXEC
)
14443 value
= COND_EXEC_CODE (value
);
14444 if (GET_CODE (value
) == PARALLEL
)
14445 value
= XVECEXP (value
, 0, 0);
14446 value
= XEXP (value
, 0);
14447 if (GET_CODE (addr
) == COND_EXEC
)
14448 addr
= COND_EXEC_CODE (addr
);
14449 if (GET_CODE (addr
) == PARALLEL
)
14450 addr
= XVECEXP (addr
, 0, 0);
14451 addr
= XEXP (addr
, 0);
14453 return !reg_overlap_mentioned_p (value
, addr
);
14456 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14457 have an early register shift value or amount dependency on the
14458 result of PRODUCER. */
14461 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14463 rtx value
= PATTERN (producer
);
14464 rtx op
= PATTERN (consumer
);
14467 if (GET_CODE (value
) == COND_EXEC
)
14468 value
= COND_EXEC_CODE (value
);
14469 if (GET_CODE (value
) == PARALLEL
)
14470 value
= XVECEXP (value
, 0, 0);
14471 value
= XEXP (value
, 0);
14472 if (GET_CODE (op
) == COND_EXEC
)
14473 op
= COND_EXEC_CODE (op
);
14474 if (GET_CODE (op
) == PARALLEL
)
14475 op
= XVECEXP (op
, 0, 0);
14478 early_op
= XEXP (op
, 0);
14479 /* This is either an actual independent shift, or a shift applied to
14480 the first operand of another operation. We want the whole shift
14482 if (GET_CODE (early_op
) == REG
)
14485 return !reg_overlap_mentioned_p (value
, early_op
);
14488 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14489 have an early register shift value dependency on the result of
14493 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14495 rtx value
= PATTERN (producer
);
14496 rtx op
= PATTERN (consumer
);
14499 if (GET_CODE (value
) == COND_EXEC
)
14500 value
= COND_EXEC_CODE (value
);
14501 if (GET_CODE (value
) == PARALLEL
)
14502 value
= XVECEXP (value
, 0, 0);
14503 value
= XEXP (value
, 0);
14504 if (GET_CODE (op
) == COND_EXEC
)
14505 op
= COND_EXEC_CODE (op
);
14506 if (GET_CODE (op
) == PARALLEL
)
14507 op
= XVECEXP (op
, 0, 0);
14510 early_op
= XEXP (op
, 0);
14512 /* This is either an actual independent shift, or a shift applied to
14513 the first operand of another operation. We want the value being
14514 shifted, in either case. */
14515 if (GET_CODE (early_op
) != REG
)
14516 early_op
= XEXP (early_op
, 0);
14518 return !reg_overlap_mentioned_p (value
, early_op
);
14521 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14522 have an early register mult dependency on the result of
14526 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14528 rtx value
= PATTERN (producer
);
14529 rtx op
= PATTERN (consumer
);
14531 if (GET_CODE (value
) == COND_EXEC
)
14532 value
= COND_EXEC_CODE (value
);
14533 if (GET_CODE (value
) == PARALLEL
)
14534 value
= XVECEXP (value
, 0, 0);
14535 value
= XEXP (value
, 0);
14536 if (GET_CODE (op
) == COND_EXEC
)
14537 op
= COND_EXEC_CODE (op
);
14538 if (GET_CODE (op
) == PARALLEL
)
14539 op
= XVECEXP (op
, 0, 0);
14542 return (GET_CODE (op
) == PLUS
14543 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14547 /* We can't rely on the caller doing the proper promotion when
14548 using APCS or ATPCS. */
14551 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14553 return !TARGET_AAPCS_BASED
;