gcc/config/arm/constraints.md

   1 ;; Constraint definitions for ARM and Thumb
   2 ;; Copyright (C) 2006-2024 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; The following register constraints have been used:
  22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
  23 ;; - in Thumb state: h, b
  24 ;; - in both states: l, c, k, q, Cs, Ts, US
  25 ;; In ARM state, 'l' is an alias for 'r'
  26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
  27
  28 ;; The following normal constraints have been used:
  29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
  30 ;; in Thumb-1 state: I, J, K, L, M, N, O
  31 ;; 'H' was previously used for FPA.
  32
  33 ;; The following multi-letter normal constraints have been used:
  34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
  35 ;;                       Dj, Ds, Dt, Dp, Dz, Tu, Te
  36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
  37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, Rb, Ra,
  38 ;;                   Rg, Ri
  39 ;; in all states: Pg
  40
  41 ;; The following memory constraints have been used:
  42 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf, Ux, Ul
  43 ;; in ARM state: Uq
  44 ;; in Thumb state: Uu, Uw
  45 ;; in all states: Q
  46
  47 (define_register_constraint "Up" "TARGET_HAVE_MVE ? VPR_REG : NO_REGS"
  48   "MVE VPR register")
  49
  50 (define_memory_constraint "Ul"
  51  "@internal
  52   In ARM/Thumb-2 state a valid address for load instruction with XEXP (op, 0)
  53   being label of the literal data item to be loaded."
  54  (and (match_code "mem")
  55       (match_test "TARGET_HAVE_MVE && reload_completed
  56                    && (GET_CODE (XEXP (op, 0)) == LABEL_REF
  57                        || (GET_CODE (XEXP (op, 0)) == CONST
  58                            && GET_CODE (XEXP (XEXP (op, 0), 0)) == PLUS
  59                            && GET_CODE (XEXP (XEXP (XEXP (op, 0), 0), 0)) == LABEL_REF
  60                            && CONST_INT_P (XEXP (XEXP (XEXP (op, 0), 0), 1))))")))
  61
  62 (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS"
  63   "MVE FPCCR register")
  64
  65 (define_register_constraint "Te" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS"
  66   "EVEN core registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8},
  67    @code{r10}, @code{r12}, @code{r14}")
  68
  69 (define_constraint "Rd"
  70   "@internal In Thumb-2 state a constant in range 1 to 16"
  71   (and (match_code "const_int")
  72        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 16")))
  73
  74 (define_constraint "Ra"
  75   "@internal In Thumb-2 state a constant in range 0 to 7"
  76   (and (match_code "const_int")
  77        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 7")))
  78
  79 (define_constraint "Rb"
  80   "@internal In Thumb-2 state a constant in range 1 to 8"
  81   (and (match_code "const_int")
  82        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 8")))
  83
  84 (define_constraint "Rc"
  85   "@internal In Thumb-2 state a constant in range 0 to 15"
  86   (and (match_code "const_int")
  87        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 15")))
  88
  89 (define_constraint "Re"
  90   "@internal In Thumb-2 state a constant in range 0 to 31"
  91   (and (match_code "const_int")
  92        (match_test "TARGET_HAVE_MVE && ival >= 0 && ival <= 31")))
  93
  94 (define_constraint "Rf"
  95   "@internal In Thumb-2 state a constant in range 1 to 32"
  96   (and (match_code "const_int")
  97        (match_test "TARGET_HAVE_MVE && ival >= 1 && ival <= 32")))
  98
  99 (define_constraint "Rg"
 100   "@internal In Thumb-2 state a constant is one among 1, 2, 4 and 8"
 101   (and (match_code "const_int")
 102        (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
 103                                        || (ival == 4) || (ival == 8))")))
 104
 105 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
 106  "The VFP registers @code{s0}-@code{s31}.")
 107
 108 (define_register_constraint "w"
 109   "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
 110  "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
 111
 112 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
 113  "The VFP registers @code{d0}-@code{d7}.")
 114
 115 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
 116  "The Intel iWMMX co-processor registers.")
 117
 118 (define_register_constraint "z"
 119  "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
 120  "The Intel iWMMX GR registers.")
 121
 122 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
 123  "In Thumb state the core registers @code{r0}-@code{r7}.")
 124
 125 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
 126  "In Thumb state the core registers @code{r8}-@code{r15}.")
 127
 128 (define_constraint "j"
 129  "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
 130  (and (match_test "TARGET_HAVE_MOVT")
 131       (ior (and (match_code "high")
 132                 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
 133            (and (match_code "const_int")
 134                 (match_test "(ival & 0xffff0000) == 0")))))
 135
 136 (define_constraint "Pj"
 137  "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
 138  (and (match_code "const_int")
 139       (and (match_test "TARGET_THUMB2")
 140            (match_test "(ival & 0xfffff000) == 0"))))
 141
 142 (define_constraint "PJ"
 143  "@internal A constant that satisfies the Pj constrant if negated."
 144  (and (match_code "const_int")
 145       (and (match_test "TARGET_THUMB2")
 146            (match_test "((-ival) & 0xfffff000) == 0"))))
 147
 148 (define_register_constraint "k" "STACK_REG"
 149  "@internal The stack register.")
 150
 151 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
 152  "@internal
 153   Thumb only.  The union of the low registers and the stack register.")
 154
 155 (define_constraint "c"
 156  "@internal The condition code register."
 157  (match_operand 0 "cc_register"))
 158
 159 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
 160  "@internal The caller save registers.  Useful for sibcalls.")
 161
 162 (define_constraint "I"
 163  "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
 164   Data Processing instruction.  In Thumb-1 state a constant in the range
 165   0-255."
 166  (and (match_code "const_int")
 167       (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
 168                    : ival >= 0 && ival <= 255")))
 169
 170 (define_constraint "J"
 171  "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095.  In Thumb-1
 172   state a constant in the range @minus{}255-@minus{}1."
 173  (and (match_code "const_int")
 174       (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
 175                    : (ival >= -255 && ival <= -1)")))
 176
 177 (define_constraint "K"
 178  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 179   inverted.  In Thumb-1 state a constant that satisfies the @code{I}
 180   constraint multiplied by any power of 2."
 181  (and (match_code "const_int")
 182       (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
 183                    : thumb_shiftable_const (ival)")))
 184
 185 (define_constraint "L"
 186  "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
 187   negated.  In Thumb-1 state a constant in the range @minus{}7-7."
 188  (and (match_code "const_int")
 189       (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
 190                    : (ival >= -7 && ival <= 7)")))
 191
 192 ;; The ARM state version is internal...
 193 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
 194 ;; power of 2.
 195 (define_constraint "M"
 196  "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
 197  (and (match_code "const_int")
 198       (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
 199                                  || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
 200                    : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
 201
 202 (define_constraint "N"
 203  "Thumb-1 state a constant in the range 0-31."
 204  (and (match_code "const_int")
 205       (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
 206
 207 (define_constraint "O"
 208  "In Thumb-1 state a constant that is a multiple of 4 in the range
 209   @minus{}508-508."
 210  (and (match_code "const_int")
 211       (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
 212                    && ((ival & 3) == 0)")))
 213
 214 (define_constraint "Pa"
 215   "@internal In Thumb-1 state a constant in the range -510 to +510"
 216   (and (match_code "const_int")
 217        (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
 218                     && (ival > 255 || ival < -255)")))
 219
 220 (define_constraint "Pb"
 221   "@internal In Thumb-1 state a constant in the range -262 to +262"
 222   (and (match_code "const_int")
 223        (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
 224                     && (ival > 255 || ival < -255)")))
 225
 226 (define_constraint "Pc"
 227   "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
 228   (and (match_code "const_int")
 229        (match_test "TARGET_THUMB1
 230                     && ival > 1020 && ival <= 1275")))
 231
 232 (define_constraint "Pd"
 233   "@internal In Thumb state a constant in the range 0 to 7"
 234   (and (match_code "const_int")
 235        (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
 236
 237 (define_constraint "Pe"
 238   "@internal In Thumb-1 state a constant in the range 256 to +510"
 239   (and (match_code "const_int")
 240        (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
 241
 242 (define_constraint "Pg"
 243   "@internal In Thumb-2 state a constant in range 1 to 32"
 244   (and (match_code "const_int")
 245        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
 246
 247 (define_constraint "Ps"
 248   "@internal In Thumb-2 state a constant in the range -255 to +255"
 249   (and (match_code "const_int")
 250        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
 251
 252 (define_constraint "Pt"
 253   "@internal In Thumb-2 state a constant in the range -7 to +7"
 254   (and (match_code "const_int")
 255        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
 256
 257 (define_constraint "Pu"
 258   "@internal In Thumb-2 state a constant in the range +1 to +8"
 259   (and (match_code "const_int")
 260        (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
 261
 262 (define_constraint "Pv"
 263   "@internal In Thumb-2 state a constant in the range -255 to 0"
 264   (and (match_code "const_int")
 265        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
 266
 267 (define_constraint "Pw"
 268   "@internal In Thumb-2 state a constant in the range -255 to -1"
 269   (and (match_code "const_int")
 270        (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
 271
 272 (define_constraint "Px"
 273   "@internal In Thumb-2 state a constant in the range -7 to -1"
 274   (and (match_code "const_int")
 275        (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
 276
 277 (define_constraint "Py"
 278   "@internal In Thumb-2 state a constant in the range 0 to 255"
 279   (and (match_code "const_int")
 280        (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
 281
 282 (define_constraint "Pz"
 283   "@internal In Thumb-2 state the constant 0"
 284   (and (match_code "const_int")
 285        (match_test "TARGET_THUMB2 && (ival == 0)")))
 286
 287 (define_constraint "G"
 288  "In ARM/Thumb-2 state the floating-point constant 0."
 289  (and (match_code "const_double")
 290       (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
 291
 292 (define_constraint "Ha"
 293   "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
 294   (and (match_code "const_double")
 295        (match_test "satisfies_constraint_E (op)")
 296        (match_test "!arm_disable_literal_pool")))
 297
 298 (define_constraint "Dz"
 299  "@internal
 300   In ARM/Thumb-2 state a vector of constant zeros."
 301  (and (match_code "const_vector")
 302       (match_test "(TARGET_NEON || TARGET_HAVE_MVE) && op == CONST0_RTX (mode)")))
 303
 304 (define_constraint "DB"
 305  "@internal
 306   In ARM/Thumb-2 state with MVE a constant vector of booleans."
 307  (and (match_code "const_vector")
 308       (match_test "TARGET_HAVE_MVE && VALID_MVE_PRED_MODE (mode)")))
 309
 310 (define_constraint "Da"
 311  "@internal
 312   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 313   be generated with two Data Processing insns."
 314  (and (match_code "const_double,const_int,const_vector")
 315       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
 316
 317 (define_constraint "Db"
 318  "@internal
 319   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 320   be generated with three Data Processing insns."
 321  (and (match_code "const_double,const_int,const_vector")
 322       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
 323
 324 (define_constraint "Dc"
 325  "@internal
 326   In ARM/Thumb-2 state a const_int, const_double or const_vector that can
 327   be generated with four Data Processing insns.  This pattern is disabled
 328   if optimizing for space or when we have load-delay slots to fill."
 329  (and (match_code "const_double,const_int,const_vector")
 330       (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
 331                    && !(optimize_size || arm_ld_sched)")))
 332
 333 (define_constraint "Dd"
 334  "@internal
 335   In ARM/Thumb-2 state a const_int that can be used by insn adddi."
 336  (and (match_code "const_int")
 337       (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
 338
 339 (define_constraint "Di"
 340  "@internal
 341   In ARM/Thumb-2 state a const_int or const_double where both the high
 342   and low SImode words can be generated as immediates in 32-bit instructions."
 343  (and (match_code "const_double,const_int")
 344       (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
 345
 346 (define_constraint "Dj"
 347   "@internal
 348    In cores with the v6t2 ISA, a constant with exactly one consecutive
 349    string of zero bits."
 350   (and (match_code "const_int")
 351        (match_test "arm_arch_thumb2
 352                     && exact_log2 (~ival + (~ival & -~ival)) >= 0")))
 353
 354 (define_constraint "Dm"
 355  "@internal
 356   In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
 357   immediate instruction."
 358  (and (match_code "const_vector")
 359       (match_test "TARGET_32BIT
 360                    && imm_for_neon_mov_operand (op, GET_MODE (op))")))
 361
 362 (define_constraint "Dn"
 363  "@internal
 364   In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
 365   immediate instruction."
 366  (and (match_code "const_int")
 367       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
 368
 369 (define_constraint "DN"
 370  "@internal
 371   In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
 372   immediate instruction."
 373  (and (match_code "const_int")
 374       (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
 375
 376 (define_constraint "Dl"
 377  "@internal
 378   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
 379   vbic instruction."
 380  (and (match_code "const_vector")
 381       (match_test "TARGET_32BIT
 382                    && imm_for_neon_logic_operand (op, GET_MODE (op))")))
 383
 384 (define_constraint "DL"
 385  "@internal
 386   In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
 387   vand instruction."
 388  (and (match_code "const_vector")
 389       (match_test "TARGET_32BIT
 390                    && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
 391
 392 (define_constraint "Do"
 393  "@internal
 394   In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
 395  (and (match_code "const_int")
 396       (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
 397
 398 (define_constraint "Dv"
 399  "@internal
 400   In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
 401   instruction."
 402  (and (match_code "const_double")
 403       (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
 404
 405 (define_constraint "Dy"
 406  "@internal
 407   In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
 408   instruction."
 409  (and (match_code "const_double")
 410       (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
 411
 412 (define_constraint "Dt"
 413  "@internal
 414   In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
 415   (and (match_code "const_double")
 416        (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
 417
 418 (define_constraint "Ds"
 419  "@internal
 420   In ARM/Thumb-2 state a const_vector which can be used as immediate
 421   in vshl instruction."
 422  (and (match_code "const_vector")
 423       (match_test "TARGET_32BIT
 424                    && imm_for_neon_lshift_operand (op, GET_MODE (op))")))
 425
 426 (define_constraint "Dp"
 427  "@internal
 428   In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
 429   (and (match_code "const_double")
 430        (match_test "TARGET_32BIT
 431                     && vfp3_const_double_for_bits (op) > 0")))
 432
 433 (define_constraint "Tu"
 434   "@internal In ARM / Thumb-2 an integer constant iff literal pools are
 435    allowed."
 436   (and (match_test "CONSTANT_P (op)")
 437        (match_test "!arm_disable_literal_pool")))
 438
 439 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
 440  "For arm_restrict_it the core registers @code{r0}-@code{r7}.  GENERAL_REGS otherwise.")
 441
 442 (define_memory_constraint "Ua"
 443  "@internal
 444   An address valid for loading/storing register exclusive"
 445  (match_operand 0 "mem_noofs_operand"))
 446
 447 (define_memory_constraint "Uh"
 448  "@internal
 449   An address suitable for byte and half-word loads which does not point inside a constant pool"
 450  (and (match_code "mem")
 451       (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
 452
 453 (define_memory_constraint "Ut"
 454  "@internal
 455   In ARM/Thumb-2 state an address valid for loading/storing opaque structure
 456   types wider than TImode."
 457  (and (match_code "mem")
 458       (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
 459
 460 (define_memory_constraint "Uv"
 461  "@internal
 462   In ARM/Thumb-2 state a valid VFP load/store address."
 463  (and (match_code "mem")
 464       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
 465
 466 (define_memory_constraint "Ug"
 467  "@internal
 468   In Thumb-2 state a valid MVE struct load/store address."
 469  (match_operand 0 "mve_struct_operand"))
 470
 471 (define_memory_constraint "Uj"
 472  "@internal
 473   In ARM/Thumb-2 state a VFP load/store address that supports writeback
 474   for Neon but not for MVE"
 475  (and (match_code "mem")
 476       (match_test "TARGET_32BIT")
 477       (match_test "TARGET_HAVE_MVE
 478                    ? arm_coproc_mem_operand_no_writeback (op)
 479                    : neon_vector_mem_operand (op, 2, true)")))
 480
 481 (define_memory_constraint "Uy"
 482  "@internal
 483   In ARM/Thumb-2 state a valid iWMMX load/store address."
 484  (and (match_code "mem")
 485       (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
 486
 487 (define_memory_constraint "Un"
 488  "@internal
 489   In ARM/Thumb-2 state a valid address for Neon doubleword vector
 490   load/store instructions."
 491  (and (match_code "mem")
 492       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
 493
 494 (define_memory_constraint "Um"
 495  "@internal
 496   In ARM/Thumb-2 state a valid address for Neon element and structure
 497   load/store instructions."
 498  (and (match_code "mem")
 499       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 500
 501 (define_memory_constraint "Us"
 502  "@internal
 503   In ARM/Thumb-2 state a valid address for non-offset loads/stores of
 504   quad-word values in four ARM registers."
 505  (and (match_code "mem")
 506       (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
 507
 508 (define_memory_constraint "Ux"
 509  "@internal
 510   In ARM/Thumb-2 state a valid address and load into CORE regs or only to
 511   LO_REGS based on mode of op."
 512  (and (match_code "mem")
 513       (match_test "(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT)
 514                    && mve_vector_mem_operand (GET_MODE (op),
 515                                               XEXP (op, 0), true)")))
 516
 517 (define_constraint "Ui"
 518   "@internal
 519    Match a constant (as per the 'i' constraint) provided that we have the
 520    literal pool available.  This is useful for load insns that would need
 521    to move such constants to the literal pool after RA."
 522  (match_test "!arm_disable_literal_pool && satisfies_constraint_i (op)"))
 523
 524 (define_memory_constraint "Uq"
 525  "@internal
 526   In ARM state an address valid in ldrsb instructions."
 527  (and (match_code "mem")
 528       (match_test "TARGET_ARM
 529                    && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
 530                                                       SIGN_EXTEND, 0)
 531                    && !arm_is_constant_pool_ref (op)")))
 532
 533 (define_memory_constraint "Q"
 534  "@internal
 535   An address that is a single base register."
 536  (and (match_code "mem")
 537       (match_test "REG_P (XEXP (op, 0))")))
 538
 539 (define_memory_constraint "Uu"
 540  "@internal
 541   In Thumb state an address that is valid in 16bit encoding."
 542  (and (match_code "mem")
 543       (match_test "TARGET_THUMB
 544                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 545                                                    0)")))
 546
 547 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
 548 ; are actually LDM/STM instructions, so cannot be used to access unaligned
 549 ; data.
 550 (define_memory_constraint "Uw"
 551  "@internal
 552   In Thumb state an address that is valid in 16bit encoding, and that can be
 553   used for unaligned accesses."
 554  (and (match_code "mem")
 555       (match_test "TARGET_THUMB
 556                    && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 557                                                    0)
 558                    && GET_CODE (XEXP (op, 0)) != POST_INC")))
 559
 560 (define_constraint "US"
 561  "@internal
 562   US is a symbol reference."
 563  (match_code "symbol_ref")
 564 )
 565
 566 ;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
 567 (define_constraint "Ri"
 568   "@internal In Thumb-2 state a constant is multiple of 8 and in range
 569    of -/+ 1016 for MVE"
 570   (and (match_code "const_int")
 571        (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
 572                     && ((ival % 8) == 0)")))
 573
 574 ;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
 575 (define_constraint "Rl"
 576   "@internal In Thumb-2 state a constant is multiple of 2 and in range
 577    of -/+ 252 for MVE"
 578   (and (match_code "const_int")
 579        (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
 580                     && ((ival % 2) == 0)")))
 581
 582 (define_memory_constraint "Uz"
 583  "@internal
 584   A memory access that is accessible as an LDC/STC operand"
 585  (and (match_code "mem")
 586       (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
 587
 588 ;; We used to have constraint letters for S and R in ARM state, but
 589 ;; all uses of these now appear to have been removed.
 590
 591 ;; Additionally, we used to have a Q constraint in Thumb state, but
 592 ;; this wasn't really a valid memory constraint.  Again, all uses of
 593 ;; this now seem to have been removed.
 594