1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008, 2010
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ::::::::::::::::::::
29 ;; ::::::::::::::::::::
31 ;; GOT constants must go 12/HI/LO for the splitter to work
37 (UNSPEC_PIC_PROLOGUE 3)
39 (UNSPEC_STACK_ADJUST 5)
40 (UNSPEC_EH_RETURN_EPILOGUE 6)
43 (UNSPEC_OPTIONAL_MEMBAR 9)
45 (UNSPEC_GETTLSOFF 200)
46 (UNSPEC_TLS_LOAD_GOTTLSOFF12 201)
47 (UNSPEC_TLS_INDIRECT_CALL 202)
48 (UNSPEC_TLS_TLSDESC_LDD 203)
49 (UNSPEC_TLS_TLSDESC_LDD_AUX 204)
50 (UNSPEC_TLS_TLSOFF_LD 205)
52 (UNSPEC_TLSOFF_HILO 207)
58 (R_FRV_FUNCDESC_GOT12 15)
59 (R_FRV_FUNCDESC_GOTHI 16)
60 (R_FRV_FUNCDESC_GOTLO 17)
61 (R_FRV_FUNCDESC_VALUE 18)
62 (R_FRV_FUNCDESC_GOTOFF12 19)
63 (R_FRV_FUNCDESC_GOTOFFHI 20)
64 (R_FRV_FUNCDESC_GOTOFFLO 21)
71 (R_FRV_GOTTLSOFF_HI 28)
72 (R_FRV_GOTTLSOFF_LO 29)
78 (R_FRV_GOTTLSDESCHI 35)
79 (R_FRV_GOTTLSDESCLO 36)
84 ;; LR_REG conflicts with definition in frv.h
89 (define_mode_iterator IMODE [QI HI SI DI])
90 (define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])
91 (define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])
93 ;; ::::::::::::::::::::
97 ;; ::::::::::::::::::::
99 ;; Standard Constraints
101 ;; `m' A memory operand is allowed, with any kind of address that the
102 ;; machine supports in general.
104 ;; `o' A memory operand is allowed, but only if the address is
105 ;; "offsettable". This means that adding a small integer (actually, the
106 ;; width in bytes of the operand, as determined by its machine mode) may be
107 ;; added to the address and the result is also a valid memory address.
109 ;; `V' A memory operand that is not offsettable. In other words,
110 ;; anything that would fit the `m' constraint but not the `o' constraint.
112 ;; `<' A memory operand with autodecrement addressing (either
113 ;; predecrement or postdecrement) is allowed.
115 ;; `>' A memory operand with autoincrement addressing (either
116 ;; preincrement or postincrement) is allowed.
118 ;; `r' A register operand is allowed provided that it is in a general
121 ;; `d', `a', `f', ...
122 ;; Other letters can be defined in machine-dependent fashion to stand for
123 ;; particular classes of registers. `d', `a' and `f' are defined on the
124 ;; 68000/68020 to stand for data, address and floating point registers.
126 ;; `i' An immediate integer operand (one with constant value) is allowed.
127 ;; This includes symbolic constants whose values will be known only at
130 ;; `n' An immediate integer operand with a known numeric value is allowed.
131 ;; Many systems cannot support assembly-time constants for operands less
132 ;; than a word wide. Constraints for these operands should use `n' rather
135 ;; 'I' First machine-dependent integer constant (6-bit signed ints).
136 ;; 'J' Second machine-dependent integer constant (10-bit signed ints).
137 ;; 'K' Third machine-dependent integer constant (-2048).
138 ;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
139 ;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
140 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
141 ;; 'O' Seventh machine-dependent integer constant (zero).
142 ;; 'P' Eighth machine-dependent integer constant (1..2047).
144 ;; Other letters in the range `I' through `P' may be defined in a
145 ;; machine-dependent fashion to permit immediate integer operands with
146 ;; explicit integer values in specified ranges. For example, on the 68000,
147 ;; `I' is defined to stand for the range of values 1 to 8. This is the
148 ;; range permitted as a shift count in the shift instructions.
150 ;; `E' An immediate floating operand (expression code `const_double') is
151 ;; allowed, but only if the target floating point format is the same as
152 ;; that of the host machine (on which the compiler is running).
154 ;; `F' An immediate floating operand (expression code `const_double') is
157 ;; 'G' First machine-dependent const_double.
158 ;; 'H' Second machine-dependent const_double.
160 ;; `s' An immediate integer operand whose value is not an explicit
161 ;; integer is allowed.
163 ;; This might appear strange; if an insn allows a constant operand with a
164 ;; value not known at compile time, it certainly must allow any known
165 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
168 ;; For example, on the 68000 in a fullword instruction it is possible to
169 ;; use an immediate operand; but if the immediate value is between -128 and
170 ;; 127, better code results from loading the value into a register and
171 ;; using the register. This is because the load into the register can be
172 ;; done with a `moveq' instruction. We arrange for this to happen by
173 ;; defining the letter `K' to mean "any integer outside the range -128 to
174 ;; 127", and then specifying `Ks' in the operand constraints.
176 ;; `g' Any register, memory or immediate integer operand is allowed,
177 ;; except for registers that are not general registers.
179 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
180 ;; `general_operand'. This is normally used in the constraint of a
181 ;; `match_scratch' when certain alternatives will not actually require a
184 ;; `0' Match operand 0.
185 ;; `1' Match operand 1.
186 ;; `2' Match operand 2.
187 ;; `3' Match operand 3.
188 ;; `4' Match operand 4.
189 ;; `5' Match operand 5.
190 ;; `6' Match operand 6.
191 ;; `7' Match operand 7.
192 ;; `8' Match operand 8.
193 ;; `9' Match operand 9.
195 ;; An operand that matches the specified operand number is allowed. If a
196 ;; digit is used together with letters within the same alternative, the
197 ;; digit should come last.
199 ;; This is called a "matching constraint" and what it really means is that
200 ;; the assembler has only a single operand that fills two roles considered
201 ;; separate in the RTL insn. For example, an add insn has two input
202 ;; operands and one output operand in the RTL, but on most CISC machines an
203 ;; add instruction really has only two operands, one of them an
204 ;; input-output operand:
208 ;; Matching constraints are used in these circumstances. More precisely,
209 ;; the two operands that match must include one input-only operand and one
210 ;; output-only operand. Moreover, the digit must be a smaller number than
211 ;; the number of the operand that uses it in the constraint.
213 ;; For operands to match in a particular case usually means that they are
214 ;; identical-looking RTL expressions. But in a few special cases specific
215 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
216 ;; operand will match `*x++' as an output operand. For proper results in
217 ;; such cases, the output template should always use the output-operand's
218 ;; number when printing the operand.
220 ;; `p' An operand that is a valid memory address is allowed. This is for
221 ;; "load address" and "push address" instructions.
223 ;; `p' in the constraint must be accompanied by `address_operand' as the
224 ;; predicate in the `match_operand'. This predicate interprets the mode
225 ;; specified in the `match_operand' as the mode of the memory reference for
226 ;; which the address would be valid.
228 ;; `Q` First non constant, non register machine-dependent insns
229 ;; `R` Second non constant, non register machine-dependent insns
230 ;; `S` Third non constant, non register machine-dependent insns
231 ;; `T` Fourth non constant, non register machine-dependent insns
232 ;; `U` Fifth non constant, non register machine-dependent insns
234 ;; Letters in the range `Q' through `U' may be defined in a
235 ;; machine-dependent fashion to stand for arbitrary operand types. The
236 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
237 ;; its first argument and the constraint letter as its second operand.
239 ;; A typical use for this would be to distinguish certain types of memory
240 ;; references that affect other insn operands.
242 ;; Do not define these constraint letters to accept register references
243 ;; (`reg'); the reload pass does not expect this and would not handle it
246 ;; Multiple Alternative Constraints
247 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
248 ;; choice when no alternative applies exactly. The compiler regards this
249 ;; alternative as one unit more costly for each `?' that appears in it.
251 ;; `!' Disparage severely the alternative that the `!' appears in. This
252 ;; alternative can still be used if it fits without reloading, but if
253 ;; reloading is needed, some other alternative will be used.
255 ;; Constraint modifiers
256 ;; `=' Means that this operand is write-only for this instruction: the
257 ;; previous value is discarded and replaced by output data.
259 ;; `+' Means that this operand is both read and written by the
262 ;; When the compiler fixes up the operands to satisfy the constraints, it
263 ;; needs to know which operands are inputs to the instruction and which are
264 ;; outputs from it. `=' identifies an output; `+' identifies an operand
265 ;; that is both input and output; all other operands are assumed to be
268 ;; `&' Means (in a particular alternative) that this operand is written
269 ;; before the instruction is finished using the input operands. Therefore,
270 ;; this operand may not lie in a register that is used as an input operand
271 ;; or as part of any memory address.
273 ;; `&' applies only to the alternative in which it is written. In
274 ;; constraints with multiple alternatives, sometimes one alternative
275 ;; requires `&' while others do not.
277 ;; `&' does not obviate the need to write `='.
279 ;; `%' Declares the instruction to be commutative for this operand and the
280 ;; following operand. This means that the compiler may interchange the two
281 ;; operands if that is the cheapest way to make all operands fit the
282 ;; constraints. This is often used in patterns for addition instructions
283 ;; that really have only two operands: the result must go in one of the
286 ;; `#' Says that all following characters, up to the next comma, are to be
287 ;; ignored as a constraint. They are significant only for choosing
288 ;; register preferences.
290 ;; `*' Says that the following character should be ignored when choosing
291 ;; register preferences. `*' has no effect on the meaning of the
292 ;; constraint as a constraint, and no effect on reloading.
295 ;; ::::::::::::::::::::
299 ;; ::::::::::::::::::::
301 ;; The `define_attr' expression is used to define each attribute required by
302 ;; the target machine. It looks like:
304 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
306 ;; NAME is a string specifying the name of the attribute being defined.
308 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
309 ;; values that can be assigned to the attribute, or a null string to indicate
310 ;; that the attribute takes numeric values.
312 ;; DEFAULT is an attribute expression that gives the value of this attribute
313 ;; for insns that match patterns whose definition does not include an explicit
314 ;; value for this attribute.
316 ;; For each defined attribute, a number of definitions are written to the
317 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
318 ;; for an attribute, the following are defined:
320 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
322 ;; * An enumeral class is defined for `attr_NAME' with elements of the
323 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
324 ;; converted to upper case.
326 ;; * A function `get_attr_NAME' is defined that is passed an insn and
327 ;; returns the attribute value for that insn.
329 ;; For example, if the following is present in the `md' file:
331 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
333 ;; the following lines will be written to the file `insn-attr.h'.
335 ;; #define HAVE_ATTR_type
336 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
337 ;; extern enum attr_type get_attr_type ();
339 ;; If the attribute takes numeric values, no `enum' type will be defined and
340 ;; the function to obtain the attribute's value will return `int'.
342 (define_attr "length" "" (const_int 4))
344 ;; Processor type -- this attribute must exactly match the processor_type
345 ;; enumeration in frv-protos.h.
347 (define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"
348 (const (symbol_ref "(enum attr_cpu) frv_cpu_type")))
350 ;; Attribute is "yes" for branches and jumps that span too great a distance
351 ;; to be implemented in the most natural way. Such instructions will use
352 ;; a call instruction in some way.
354 (define_attr "far_jump" "yes,no" (const_string "no"))
357 ;; "unknown" must come last.
359 "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"
360 (const_string "unknown"))
362 (define_attr "acc_group" "none,even,odd"
363 (symbol_ref "(enum attr_acc_group) frv_acc_group (insn)"))
365 ;; Scheduling and Packing Overview
366 ;; -------------------------------
368 ;; FR-V instructions are divided into five groups: integer, floating-point,
369 ;; media, branch and control. Each group is associated with a separate set
370 ;; of processing units, the number and behavior of which depend on the target
371 ;; target processor. Integer units have names like I0 and I1, floating-point
372 ;; units have names like F0 and F1, and so on.
374 ;; Each member of the FR-V family has its own restrictions on which
375 ;; instructions can issue to which units. For example, some processors
376 ;; allow loads to issue to I0 or I1 while others only allow them to issue
377 ;; to I0. As well as these processor-specific restrictions, there is a
378 ;; general rule that an instruction can only issue to unit X + 1 if an
379 ;; instruction in the same packet issued to unit X.
381 ;; Sometimes the only way to honor these restrictions is by adding nops
382 ;; to a packet. For example, on the fr550, media instructions that access
383 ;; ACC4-7 can only issue to M1 or M3. It is therefore only possible to
384 ;; execute these instructions by packing them with something that issues
385 ;; to M0. When no useful M0 instruction exists, an "mnop" can be used
388 ;; Having decided which instructions should issue to which units, the packet
389 ;; should be ordered according to the following template:
391 ;; I0 F0/M0 I1 F1/M1 .... B0 B1 ...
393 ;; Note that VLIW packets execute strictly in parallel. Every instruction
394 ;; in the packet will stall until all input operands are ready. These
395 ;; operands are then read simultaneously before any registers are modified.
396 ;; This means that it's OK to have write-after-read hazards between
397 ;; instructions in the same packet, even if the write is listed earlier
400 ;; Three gcc passes are involved in generating VLIW packets:
402 ;; (1) The scheduler. This pass uses the standard scheduling code and
403 ;; behaves in much the same way as it would for a superscalar RISC
406 ;; (2) frv_reorg. This pass inserts nops into packets in order to meet
407 ;; the processor's issue requirements. It also has code to optimize
408 ;; the type of padding used to align labels.
410 ;; (3) frv_pack_insns. The final packing phase, which puts the
411 ;; instructions into assembly language order according to the
412 ;; "I0 F0/M0 ..." template above.
414 ;; In the ideal case, these three passes will agree on which instructions
415 ;; should be packed together, but this won't always happen. In particular:
417 ;; (a) (2) might not pack predicated instructions in the same way as (1).
418 ;; The scheduler tries to schedule predicated instructions for the
419 ;; worst case, assuming the predicate is true. However, if we have
420 ;; something like a predicated load, it isn't always possible to
421 ;; fill the load delay with useful instructions. (2) should then
422 ;; pack the user of the loaded value as aggressively as possible,
423 ;; in order to optimize the case when the predicate is false.
424 ;; See frv_pack_insn_p for more details.
426 ;; (b) The final shorten_branches pass runs between (2) and (3).
427 ;; Since (2) inserts nops, it is possible that some branches
428 ;; that were thought to be in range during (2) turned out to
429 ;; out-of-range in (3).
431 ;; All three passes use DFAs to model issue restrictions. The main
432 ;; question that the DFAs are supposed to answer is simply: can these
433 ;; instructions be packed together? The DFAs are not responsible for
434 ;; assigning instructions to execution units; that's the job of
435 ;; frv_sort_insn_group, see below for details.
437 ;; To get the best results, the DFAs should try to allow packets to
438 ;; be built in every possible order. This gives the scheduler more
439 ;; flexibility, removing the need for things like multipass lookahead.
440 ;; It also means we can take more advantage of inter-packet dependencies.
442 ;; For example, suppose we're compiling for the fr400 and we have:
445 ;; ldi @(gr6,gr0),gr4
447 ;; We can pack these instructions together by assigning the load to I0 and
448 ;; the addition to I1. However, because of the anti dependence between the
449 ;; two instructions, the scheduler must schedule the addition first.
450 ;; We should generally get better schedules if the DFA allows both
451 ;; (ldi, addi) and (addi, ldi), leaving the final packing pass to
452 ;; reorder the packet where appropriate.
454 ;; Almost all integer instructions can issue to any unit in the range I0
455 ;; to Ix, where the value of "x" depends on the type of instruction and
456 ;; on the target processor. The rules for other instruction groups are
459 ;; When the restrictions are as regular as this, we can get the desired
460 ;; behavior by claiming the DFA unit associated with the highest unused
461 ;; execution unit. For example, if an instruction can issue to I0 or I1,
462 ;; the DFA first tries to take the DFA unit associated with I1, and will
463 ;; only take I0's unit if I1 isn't free. (Note that, as mentioned above,
464 ;; the DFA does not assign instructions to units. An instruction that
465 ;; claims DFA unit I1 will not necessarily issue to I1 in the final packet.)
467 ;; There are some cases, such as the fr550 media restriction mentioned
468 ;; above, where the rule is not as simple as "any unit between 0 and X".
469 ;; Even so, allocating higher units first brings us close to the ideal.
471 ;; Having divided instructions into packets, passes (2) and (3) must
472 ;; assign instructions to specific execution units. They do this using
473 ;; the following algorithm:
475 ;; 1. Partition the instructions into groups (integer, float/media, etc.)
477 ;; 2. For each group of instructions:
479 ;; (a) Issue each instruction in the reset DFA state and use the
480 ;; DFA cpu_unit_query interface to find out which unit it picks
483 ;; (b) Sort the instructions into ascending order of picked units.
484 ;; Instructions that pick I1 first come after those that pick
485 ;; I0 first, and so on. Let S be the sorted sequence and S[i]
486 ;; be the ith element of it (counting from zero).
488 ;; (c) If this is the control or branch group, goto (i)
490 ;; (d) Find the largest L such that S[0]...S[L-1] can be issued
491 ;; consecutively from the reset state and such that the DFA
492 ;; claims unit X when S[X] is added. Let D be the DFA state
493 ;; after instructions S[0]...S[L-1] have been issued.
495 ;; (e) If L is the length of S, goto (i)
497 ;; (f) Let U be the number of units belonging to this group and #S be
498 ;; the length of S. Create a new sequence S' by concatenating
499 ;; S[L]...S[#S-1] and (U - #S) nops.
501 ;; (g) For each permutation S'' of S', try issuing S'' from last to
502 ;; first, starting with state D. See if the DFA claims unit
503 ;; X + L when each S''[X] is added. If so, set S to the
504 ;; concatenation of S[0]...S[L-1] and S'', then goto (i).
506 ;; (h) If (g) found no permutation, abort.
508 ;; (i) S is now the sorted sequence for this group, meaning that S[X]
509 ;; issues to unit X. Trim any unwanted nops from the end of S.
511 ;; The sequence calculated by (b) is trivially correct for control
512 ;; instructions since they can't be packed. It is also correct for branch
513 ;; instructions due to their simple issue requirements. For integer and
514 ;; floating-point/media instructions, the sequence calculated by (b) is
515 ;; often the correct answer; the rest of the algorithm is optimized for
516 ;; the case in which it is correct.
518 ;; If there were no irregularities in the issue restrictions then step
519 ;; (d) would not be needed. It is mainly there to cope with the fr550
520 ;; integer restrictions, where a store can issue to I1, but only if a store
521 ;; also issues to I0. (Note that if a packet has two stores, they will be
522 ;; at the beginning of the sequence calculated by (b).) It also copes
523 ;; with fr400 M-2 instructions, which must issue to M0, and which cannot
524 ;; be issued together with an mnop in M1.
526 ;; Step (g) is the main one for integer and float/media instructions.
527 ;; The first permutation it tries is S' itself (because, as noted above,
528 ;; the sequence calculated by (b) is often correct). If S' doesn't work,
529 ;; the implementation tries varying the beginning of the sequence first.
530 ;; Thus the nops towards the end of the sequence will only move to lower
531 ;; positions if absolutely necessary.
533 ;; The algorithm is theoretically exponential in the number of instructions
534 ;; in a group, although it's only O(n log(n)) if the sequence calculated by
535 ;; (b) is acceptable. In practice, the algorithm completes quickly even
536 ;; in the rare cases where (g) needs to try other permutations.
537 (define_automaton "integer, float_media, branch, control, idiv, div")
539 ;; The main issue units. Note that not all units are available on
541 (define_query_cpu_unit "i0,i1,i2,i3" "integer")
542 (define_query_cpu_unit "f0,f1,f2,f3" "float_media")
543 (define_query_cpu_unit "b0,b1" "branch")
544 (define_query_cpu_unit "c" "control")
547 (define_cpu_unit "idiv1,idiv2" "idiv")
548 (define_cpu_unit "div1,div2,root" "div")
550 ;; Control instructions cannot be packed with others.
551 (define_reservation "control" "i0+i1+i2+i3+f0+f1+f2+f3+b0+b1")
553 ;; Generic reservation for control insns
554 (define_insn_reservation "control" 1
555 (eq_attr "type" "trap,spr,unknown,multi")
558 ;; Reservation for relaxable calls to gettlsoff.
559 (define_insn_reservation "load_or_call" 3
560 (eq_attr "type" "load_or_call")
563 ;; ::::::::::::::::::::
565 ;; :: Generic/FR500 scheduler description
567 ;; ::::::::::::::::::::
570 ;; Synthetic units used to describe issue restrictions.
571 (define_automaton "fr500_integer")
572 (define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")
573 (exclusion_set "fr500_load0,fr500_load1" "fr500_store0")
575 (define_bypass 0 "fr500_i1_sethi" "fr500_i1_setlo")
576 (define_insn_reservation "fr500_i1_sethi" 1
577 (and (eq_attr "cpu" "generic,fr500,tomcat")
578 (eq_attr "type" "sethi"))
581 (define_insn_reservation "fr500_i1_setlo" 1
582 (and (eq_attr "cpu" "generic,fr500,tomcat")
583 (eq_attr "type" "setlo"))
586 (define_insn_reservation "fr500_i1_int" 1
587 (and (eq_attr "cpu" "generic,fr500,tomcat")
588 (eq_attr "type" "int"))
591 (define_insn_reservation "fr500_i1_mul" 3
592 (and (eq_attr "cpu" "generic,fr500,tomcat")
593 (eq_attr "type" "mul"))
596 (define_insn_reservation "fr500_i1_div" 19
597 (and (eq_attr "cpu" "generic,fr500,tomcat")
598 (eq_attr "type" "div"))
599 "(i1|i0),(idiv1*18|idiv2*18)")
601 (define_insn_reservation "fr500_i2" 4
602 (and (eq_attr "cpu" "generic,fr500,tomcat")
603 (eq_attr "type" "gload,fload"))
604 "(i1|i0) + (fr500_load0|fr500_load1)")
606 (define_insn_reservation "fr500_i3" 0
607 (and (eq_attr "cpu" "generic,fr500,tomcat")
608 (eq_attr "type" "gstore,fstore"))
611 (define_insn_reservation "fr500_i4" 3
612 (and (eq_attr "cpu" "generic,fr500,tomcat")
613 (eq_attr "type" "movgf,movfg"))
616 (define_insn_reservation "fr500_i5" 0
617 (and (eq_attr "cpu" "generic,fr500,tomcat")
618 (eq_attr "type" "jumpl"))
622 ;; Branch-instructions
624 (define_insn_reservation "fr500_branch" 0
625 (and (eq_attr "cpu" "generic,fr500,tomcat")
626 (eq_attr "type" "jump,branch,ccr"))
629 (define_insn_reservation "fr500_call" 0
630 (and (eq_attr "cpu" "generic,fr500,tomcat")
631 (eq_attr "type" "call"))
634 ;; Floating point insns. The default latencies are for non-media
635 ;; instructions; media instructions incur an extra cycle.
637 (define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,
638 fr500_m4,fr500_m5,fr500_m6")
639 (define_insn_reservation "fr500_farith" 3
640 (and (eq_attr "cpu" "generic,fr500,tomcat")
641 (eq_attr "type" "fnop,fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))
644 (define_insn_reservation "fr500_fcmp" 4
645 (and (eq_attr "cpu" "generic,fr500,tomcat")
646 (eq_attr "type" "fscmp,fdcmp"))
649 (define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,
650 fr500_m4,fr500_m5,fr500_m6")
651 (define_insn_reservation "fr500_fdiv" 10
652 (and (eq_attr "cpu" "generic,fr500,tomcat")
653 (eq_attr "type" "fsdiv,fddiv"))
654 "(f1|f0),(div1*9 | div2*9)")
656 (define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,
657 fr500_m4,fr500_m5,fr500_m6")
658 (define_insn_reservation "fr500_froot" 15
659 (and (eq_attr "cpu" "generic,fr500,tomcat")
660 (eq_attr "type" "sqrt_single,sqrt_double"))
663 ;; Media insns. Conflict table is as follows:
673 ;; where X indicates an invalid combination.
675 ;; Target registers are as follows:
684 ;; The default FPR latencies are for integer instructions.
685 ;; Floating-point instructions need one cycle more and media
686 ;; instructions need one cycle less.
687 (define_automaton "fr500_media")
688 (define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")
689 (define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")
690 (define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")
691 (define_cpu_unit "fr500_m5" "fr500_media")
692 (define_cpu_unit "fr500_m6" "fr500_media")
694 (exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,
695 fr500_m3_0,fr500_m3_1")
696 (exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1,fr500_m5")
698 (define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
699 fr500_m4,fr500_m5,fr500_m6")
700 (define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
701 (define_insn_reservation "fr500_m1" 3
702 (and (eq_attr "cpu" "generic,fr500,tomcat")
703 (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))
706 (define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
707 fr500_m4,fr500_m5,fr500_m6")
708 (define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
709 (define_insn_reservation "fr500_m2" 3
710 (and (eq_attr "cpu" "generic,fr500,tomcat")
711 (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
712 "(f1|f0) + (fr500_m2_0|fr500_m2_1)")
714 (define_bypass 1 "fr500_m3" "fr500_m4")
715 (define_insn_reservation "fr500_m3" 2
716 (and (eq_attr "cpu" "generic,fr500,tomcat")
717 (eq_attr "type" "mclracc,mwtacc"))
718 "(f1|f0) + (fr500_m3_0|fr500_m3_1)")
720 (define_bypass 1 "fr500_m4" "fr500_m4")
721 (define_insn_reservation "fr500_m4" 2
722 (and (eq_attr "cpu" "generic,fr500,tomcat")
723 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
724 "(f1|f0) + (fr500_m4_0|fr500_m4_1)")
726 (define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
727 fr500_m4,fr500_m5,fr500_m6")
728 (define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
729 (define_insn_reservation "fr500_m5" 3
730 (and (eq_attr "cpu" "generic,fr500,tomcat")
731 (eq_attr "type" "mdpackh"))
732 "(f1|f0) + fr500_m5")
734 (define_bypass 1 "fr500_m6" "fr500_m4")
735 (define_insn_reservation "fr500_m6" 2
736 (and (eq_attr "cpu" "generic,fr500,tomcat")
737 (eq_attr "type" "mclracca"))
738 "(f1|f0) + fr500_m6")
740 ;; ::::::::::::::::::::
742 ;; :: FR400 scheduler description
744 ;; ::::::::::::::::::::
746 ;; Category 2 media instructions use both media units, but can be packed
747 ;; with non-media instructions. Use fr400_m1unit to claim the M1 unit
748 ;; without claiming a slot.
750 ;; Name Class Units Latency
751 ;; ==== ===== ===== =======
753 ;; sethi I1 I0/I1 0 -- does not interfere with setlo
758 ;; fload I2 I0 4 -- only 3 if read by a media insn
759 ;; gstore I3 I0 0 -- provides no result
760 ;; fstore I3 I0 0 -- provides no result
763 ;; jumpl I5 I0 0 -- provides no result
765 ;; (*) The results of these instructions can be read one cycle earlier
766 ;; than indicated. The penalty given is for instructions with write-after-
767 ;; write dependencies.
769 ;; The FR400 can only do loads and stores in I0, so we there's no danger
770 ;; of memory unit collision in the same packet. There's only one divide
773 (define_automaton "fr400_integer")
774 (define_cpu_unit "fr400_mul" "fr400_integer")
776 (define_insn_reservation "fr400_i1_int" 1
777 (and (eq_attr "cpu" "fr400,fr405,fr450")
778 (eq_attr "type" "int"))
781 (define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")
782 (define_insn_reservation "fr400_i1_sethi" 1
783 (and (eq_attr "cpu" "fr400,fr405,fr450")
784 (eq_attr "type" "sethi"))
787 (define_insn_reservation "fr400_i1_setlo" 1
788 (and (eq_attr "cpu" "fr400,fr405,fr450")
789 (eq_attr "type" "setlo"))
792 ;; 3 is the worst case (write-after-write hazard).
793 (define_insn_reservation "fr400_i1_mul" 3
794 (and (eq_attr "cpu" "fr400,fr405")
795 (eq_attr "type" "mul"))
798 (define_insn_reservation "fr450_i1_mul" 2
799 (and (eq_attr "cpu" "fr450")
800 (eq_attr "type" "mul"))
803 (define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
804 (define_insn_reservation "fr400_i1_macc" 2
805 (and (eq_attr "cpu" "fr405,fr450")
806 (eq_attr "type" "macc"))
807 "(i0|i1) + fr400_mul")
809 (define_insn_reservation "fr400_i1_scan" 1
810 (and (eq_attr "cpu" "fr400,fr405,fr450")
811 (eq_attr "type" "scan"))
814 (define_insn_reservation "fr400_i1_cut" 2
815 (and (eq_attr "cpu" "fr405,fr450")
816 (eq_attr "type" "cut"))
819 ;; 20 is for a write-after-write hazard.
820 (define_insn_reservation "fr400_i1_div" 20
821 (and (eq_attr "cpu" "fr400,fr405")
822 (eq_attr "type" "div"))
825 (define_insn_reservation "fr450_i1_div" 19
826 (and (eq_attr "cpu" "fr450")
827 (eq_attr "type" "div"))
830 ;; 4 is for a write-after-write hazard.
831 (define_insn_reservation "fr400_i2" 4
832 (and (eq_attr "cpu" "fr400,fr405")
833 (eq_attr "type" "gload,fload"))
836 (define_insn_reservation "fr450_i2_gload" 3
837 (and (eq_attr "cpu" "fr450")
838 (eq_attr "type" "gload"))
841 ;; 4 is for a write-after-write hazard.
842 (define_insn_reservation "fr450_i2_fload" 4
843 (and (eq_attr "cpu" "fr450")
844 (eq_attr "type" "fload"))
847 (define_insn_reservation "fr400_i3" 0
848 (and (eq_attr "cpu" "fr400,fr405,fr450")
849 (eq_attr "type" "gstore,fstore"))
852 ;; 3 is for a write-after-write hazard.
853 (define_insn_reservation "fr400_i4" 3
854 (and (eq_attr "cpu" "fr400,fr405")
855 (eq_attr "type" "movfg,movgf"))
858 (define_insn_reservation "fr450_i4_movfg" 2
859 (and (eq_attr "cpu" "fr450")
860 (eq_attr "type" "movfg"))
863 ;; 3 is for a write-after-write hazard.
864 (define_insn_reservation "fr450_i4_movgf" 3
865 (and (eq_attr "cpu" "fr450")
866 (eq_attr "type" "movgf"))
869 (define_insn_reservation "fr400_i5" 0
870 (and (eq_attr "cpu" "fr400,fr405,fr450")
871 (eq_attr "type" "jumpl"))
874 ;; The bypass between FPR loads and media instructions, described above.
878 "fr400_m1_1,fr400_m1_2,\
879 fr400_m2_1,fr400_m2_2,\
880 fr400_m3_1,fr400_m3_2,\
881 fr400_m4_1,fr400_m4_2,\
884 ;; The branch instructions all use the B unit and produce no result.
886 (define_insn_reservation "fr400_b" 0
887 (and (eq_attr "cpu" "fr400,fr405,fr450")
888 (eq_attr "type" "jump,branch,ccr,call"))
891 ;; FP->FP moves are marked as "fsconv" instructions in the define_insns
892 ;; below, but are implemented on the FR400 using "mlogic" instructions.
893 ;; It's easier to class "fsconv" as a "m1:1" instruction than provide
894 ;; separate define_insns for the FR400.
896 ;; M1 instructions store their results in FPRs. Any instruction can read
897 ;; the result in the following cycle, so no penalty occurs.
899 (define_automaton "fr400_media")
900 (define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")
901 (exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")
903 (define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")
904 (define_reservation "fr400_m2" "f0 + fr400_m2a")
906 (define_insn_reservation "fr400_m1_1" 1
907 (and (eq_attr "cpu" "fr400,fr405")
908 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))
911 (define_insn_reservation "fr400_m1_2" 1
912 (and (eq_attr "cpu" "fr400,fr405")
913 (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))
916 ;; M2 instructions store their results in accumulators, which are read
917 ;; by M2 or M4 media commands. M2 instructions can read the results in
918 ;; the following cycle, but M4 instructions must wait a cycle more.
921 "fr400_m2_1,fr400_m2_2"
922 "fr400_m2_1,fr400_m2_2")
924 (define_insn_reservation "fr400_m2_1" 2
925 (and (eq_attr "cpu" "fr400,fr405")
926 (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
929 (define_insn_reservation "fr400_m2_2" 2
930 (and (eq_attr "cpu" "fr400,fr405")
931 (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
934 ;; For our purposes, there seems to be little real difference between
935 ;; M1 and M3 instructions. Keep them separate anyway in case the distinction
938 (define_insn_reservation "fr400_m3_1" 1
939 (and (eq_attr "cpu" "fr400,fr405")
940 (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
943 (define_insn_reservation "fr400_m3_2" 1
944 (and (eq_attr "cpu" "fr400,fr405")
945 (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
948 ;; M4 instructions write to accumulators or FPRs. MOVFG and STF
949 ;; instructions can read an FPR result in the following cycle, but
950 ;; M-unit instructions must wait a cycle more for either kind of result.
952 (define_bypass 1 "fr400_m4_1,fr400_m4_2" "fr400_i3,fr400_i4")
954 (define_insn_reservation "fr400_m4_1" 2
955 (and (eq_attr "cpu" "fr400,fr405")
956 (eq_attr "type" "mrdacc,mcut,mclracc"))
959 (define_insn_reservation "fr400_m4_2" 2
960 (and (eq_attr "cpu" "fr400,fr405")
961 (eq_attr "type" "mclracca,mdcut"))
964 ;; M5 instructions always incur a 1-cycle penalty.
966 (define_insn_reservation "fr400_m5" 2
967 (and (eq_attr "cpu" "fr400,fr405")
968 (eq_attr "type" "mwtacc"))
971 ;; ::::::::::::::::::::
973 ;; :: FR450 media scheduler description
975 ;; ::::::::::::::::::::
977 ;; The FR451 media restrictions are similar to the FR400's, but not as
978 ;; strict and not as regular. There are 6 categories with the following
982 ;; M-1 M-2 M-3 M-4 M-5 M-6
990 ;; where "x" indicates a conflict.
992 ;; There is no difference between M-1 and M-3 as far as issue
993 ;; restrictions are concerned, so they are combined as "m13".
995 ;; Units for odd-numbered categories. There can be two of these
997 (define_cpu_unit "fr450_m13a,fr450_m13b" "float_media")
998 (define_cpu_unit "fr450_m5a,fr450_m5b" "float_media")
1000 ;; Units for even-numbered categories. There can only be one per packet.
1001 (define_cpu_unit "fr450_m2a,fr450_m4a,fr450_m6a" "float_media")
1003 ;; Enforce the restriction matrix above.
1004 (exclusion_set "fr450_m2a,fr450_m4a,fr450_m6a" "fr450_m13a,fr450_m13b")
1005 (exclusion_set "fr450_m2a,fr450_m6a" "fr450_m5a,fr450_m5b")
1006 (exclusion_set "fr450_m4a,fr450_m6a" "fr450_m2a")
1008 (define_reservation "fr450_m13" "(f1|f0) + (fr450_m13a|fr450_m13b)")
1009 (define_reservation "fr450_m2" "f0 + fr450_m2a")
1010 (define_reservation "fr450_m4" "f0 + fr450_m4a")
1011 (define_reservation "fr450_m5" "(f1|f0) + (fr450_m5a|fr450_m5b)")
1012 (define_reservation "fr450_m6" "(f0|f1) + fr450_m6a")
1014 ;; MD-1, MD-3 and MD-8 instructions, which are the same as far
1015 ;; as scheduling is concerned. The inputs and outputs are FPRs.
1016 ;; Instructions that have 32-bit inputs and outputs belong to M-1 while
1017 ;; the rest belong to M-2.
1019 ;; ??? Arithmetic shifts (MD-6) have an extra cycle latency, but we don't
1020 ;; make the distinction between them and logical shifts.
1021 (define_insn_reservation "fr450_md138_1" 1
1022 (and (eq_attr "cpu" "fr450")
1023 (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset,
1024 mrot,mshift,mexpdhw,mpackh"))
1027 (define_insn_reservation "fr450_md138_2" 1
1028 (and (eq_attr "cpu" "fr450")
1029 (eq_attr "type" "mqaddh,mqsath,mqlimh,
1030 mdrot,mwcut,mqshift,mexpdhd,
1031 munpackh,mdpackh,mbhconv,mcpl"))
1034 ;; MD-2 instructions. These take FPR or ACC inputs and produce an ACC output.
1035 ;; Instructions that write to double ACCs belong to M-3 while those that write
1036 ;; to quad ACCs belong to M-4.
1037 (define_insn_reservation "fr450_md2_3" 2
1038 (and (eq_attr "cpu" "fr450")
1039 (eq_attr "type" "mmulh,mmach,mcpx,mmulxh,mmrdh,maddacc"))
1042 (define_insn_reservation "fr450_md2_4" 2
1043 (and (eq_attr "cpu" "fr450")
1044 (eq_attr "type" "mqmulh,mqmach,mqcpx,mqmulxh,mdaddacc"))
1047 ;; Another MD-2 instruction can use the result on the following cycle.
1048 (define_bypass 1 "fr450_md2_3,fr450_md2_4" "fr450_md2_3,fr450_md2_4")
1050 ;; MD-4 instructions that write to ACCs.
1051 (define_insn_reservation "fr450_md4_3" 2
1052 (and (eq_attr "cpu" "fr450")
1053 (eq_attr "type" "mclracc"))
1056 (define_insn_reservation "fr450_md4_4" 3
1057 (and (eq_attr "cpu" "fr450")
1058 (eq_attr "type" "mclracca"))
1061 ;; MD-4 instructions that write to FPRs.
1062 (define_insn_reservation "fr450_md4_1" 2
1063 (and (eq_attr "cpu" "fr450")
1064 (eq_attr "type" "mcut"))
1067 (define_insn_reservation "fr450_md4_5" 2
1068 (and (eq_attr "cpu" "fr450")
1069 (eq_attr "type" "mrdacc"))
1072 (define_insn_reservation "fr450_md4_6" 2
1073 (and (eq_attr "cpu" "fr450")
1074 (eq_attr "type" "mdcut"))
1077 ;; Integer instructions can read the FPR result of an MD-4 instruction on
1078 ;; the following cycle.
1079 (define_bypass 1 "fr450_md4_1,fr450_md4_5,fr450_md4_6"
1080 "fr400_i3,fr450_i4_movfg")
1082 ;; MD-5 instructions, which belong to M-3. They take FPR inputs and
1084 (define_insn_reservation "fr450_md5_3" 2
1085 (and (eq_attr "cpu" "fr450")
1086 (eq_attr "type" "mwtacc"))
1089 ;; ::::::::::::::::::::
1091 ;; :: FR550 scheduler description
1093 ;; ::::::::::::::::::::
1095 ;; Prevent loads and stores from being issued in the same packet.
1096 ;; These units must go into the generic "integer" reservation because
1097 ;; of the constraints on fr550_store0 and fr550_store1.
1098 (define_cpu_unit "fr550_load0,fr550_load1" "integer")
1099 (define_cpu_unit "fr550_store0,fr550_store1" "integer")
1100 (exclusion_set "fr550_load0,fr550_load1" "fr550_store0,fr550_store1")
1102 ;; A store can only issue to I1 if one has also been issued to I0.
1103 (presence_set "fr550_store1" "fr550_store0")
1105 (define_bypass 0 "fr550_sethi" "fr550_setlo")
1106 (define_insn_reservation "fr550_sethi" 1
1107 (and (eq_attr "cpu" "fr550")
1108 (eq_attr "type" "sethi"))
1111 (define_insn_reservation "fr550_setlo" 1
1112 (and (eq_attr "cpu" "fr550")
1113 (eq_attr "type" "setlo"))
1116 (define_insn_reservation "fr550_int" 1
1117 (and (eq_attr "cpu" "fr550")
1118 (eq_attr "type" "int"))
1121 (define_insn_reservation "fr550_mul" 2
1122 (and (eq_attr "cpu" "fr550")
1123 (eq_attr "type" "mul"))
1126 (define_insn_reservation "fr550_div" 19
1127 (and (eq_attr "cpu" "fr550")
1128 (eq_attr "type" "div"))
1129 "(i1|i0),(idiv1*18 | idiv2*18)")
1131 (define_insn_reservation "fr550_load" 3
1132 (and (eq_attr "cpu" "fr550")
1133 (eq_attr "type" "gload,fload"))
1134 "(i1|i0)+(fr550_load0|fr550_load1)")
1136 ;; We can only issue a store to I1 if one was also issued to I0.
1137 ;; This means that, as far as frv_reorder_packet is concerned,
1138 ;; the instruction has the same priority as an I0-only instruction.
1139 (define_insn_reservation "fr550_store" 1
1140 (and (eq_attr "cpu" "fr550")
1141 (eq_attr "type" "gstore,fstore"))
1142 "(i0+fr550_store0)|(i1+fr550_store1)")
1144 (define_insn_reservation "fr550_transfer" 2
1145 (and (eq_attr "cpu" "fr550")
1146 (eq_attr "type" "movgf,movfg"))
1149 (define_insn_reservation "fr550_jumpl" 0
1150 (and (eq_attr "cpu" "fr550")
1151 (eq_attr "type" "jumpl"))
1154 (define_cpu_unit "fr550_ccr0,fr550_ccr1" "float_media")
1156 (define_insn_reservation "fr550_branch" 0
1157 (and (eq_attr "cpu" "fr550")
1158 (eq_attr "type" "jump,branch"))
1161 (define_insn_reservation "fr550_ccr" 0
1162 (and (eq_attr "cpu" "fr550")
1163 (eq_attr "type" "ccr"))
1164 "(b1|b0) + (fr550_ccr1|fr550_ccr0)")
1166 (define_insn_reservation "fr550_call" 0
1167 (and (eq_attr "cpu" "fr550")
1168 (eq_attr "type" "call"))
1171 (define_automaton "fr550_float_media")
1172 (define_cpu_unit "fr550_add0,fr550_add1" "fr550_float_media")
1174 ;; There are three possible combinations of floating-point/media instructions:
1176 ;; - one media and one float
1177 ;; - up to four float, no media
1178 ;; - up to four media, no float
1179 (define_cpu_unit "fr550_f0,fr550_f1,fr550_f2,fr550_f3" "fr550_float_media")
1180 (define_cpu_unit "fr550_m0,fr550_m1,fr550_m2,fr550_m3" "fr550_float_media")
1181 (exclusion_set "fr550_f1,fr550_f2,fr550_f3" "fr550_m1,fr550_m2,fr550_m3")
1182 (exclusion_set "fr550_m0" "fr550_f1,fr550_f2,fr550_f3")
1183 ;; FIXME: This next exclusion set should be defined as well, so that we do
1184 ;; not get a packet containing multiple media instructions plus a single
1185 ;; floating point instruction. At the moment we can get away with not
1186 ;; defining it because gcc does not seem to generate such packets.
1188 ;; If we do enable the exclusion however the insertion of fnop insns into
1189 ;; a packet containing media instructions will stop working, because the
1190 ;; fnop insn counts as a floating point instruction. The correct solution
1191 ;; is to fix the reservation for the fnop insn so that it does not have the
1192 ;; same restrictions as ordinary floating point insns.
1193 ;;(exclusion_set "fr550_f0" "fr550_m1,fr550_m2,fr550_m3")
1195 (define_reservation "fr550_float" "fr550_f0|fr550_f1|fr550_f2|fr550_f3")
1196 (define_reservation "fr550_media" "fr550_m0|fr550_m1|fr550_m2|fr550_m3")
1198 (define_insn_reservation "fr550_f1" 0
1199 (and (eq_attr "cpu" "fr550")
1200 (eq_attr "type" "fnop"))
1201 "(f3|f2|f1|f0) + fr550_float")
1203 (define_insn_reservation "fr550_f2" 3
1204 (and (eq_attr "cpu" "fr550")
1205 (eq_attr "type" "fsconv,fsadd,fscmp"))
1206 "(f3|f2|f1|f0) + (fr550_add0|fr550_add1) + fr550_float")
1208 (define_insn_reservation "fr550_f3_mul" 3
1209 (and (eq_attr "cpu" "fr550")
1210 (eq_attr "type" "fsmul"))
1211 "(f1|f0) + fr550_float")
1213 (define_insn_reservation "fr550_f3_div" 10
1214 (and (eq_attr "cpu" "fr550")
1215 (eq_attr "type" "fsdiv"))
1216 "(f1|f0) + fr550_float")
1218 (define_insn_reservation "fr550_f3_sqrt" 15
1219 (and (eq_attr "cpu" "fr550")
1220 (eq_attr "type" "sqrt_single"))
1221 "(f1|f0) + fr550_float")
1223 ;; Synthetic units for enforcing media issue restrictions. Certain types
1224 ;; of insn in M2 conflict with certain types in M0:
1227 ;; MNOP MALU MSFT MMAC MSET
1230 ;; M0 MSFT - - x - x
1234 ;; where "x" indicates a conflict. The same restrictions apply to
1237 ;; In addition -- and this is the awkward bit! -- instructions that
1238 ;; access ACC0-3 can only issue to M0 or M2. Those that access ACC4-7
1239 ;; can only issue to M1 or M3. We refer to such instructions as "even"
1240 ;; and "odd" respectively.
1241 (define_cpu_unit "fr550_malu0,fr550_malu1" "float_media")
1242 (define_cpu_unit "fr550_malu2,fr550_malu3" "float_media")
1243 (define_cpu_unit "fr550_msft0,fr550_msft1" "float_media")
1244 (define_cpu_unit "fr550_mmac0,fr550_mmac1" "float_media")
1245 (define_cpu_unit "fr550_mmac2,fr550_mmac3" "float_media")
1246 (define_cpu_unit "fr550_mset0,fr550_mset1" "float_media")
1247 (define_cpu_unit "fr550_mset2,fr550_mset3" "float_media")
1249 (exclusion_set "fr550_malu0" "fr550_malu2")
1250 (exclusion_set "fr550_malu1" "fr550_malu3")
1252 (exclusion_set "fr550_msft0" "fr550_mset2")
1253 (exclusion_set "fr550_msft1" "fr550_mset3")
1255 (exclusion_set "fr550_mmac0" "fr550_mmac2")
1256 (exclusion_set "fr550_mmac1" "fr550_mmac3")
1258 ;; If an MSFT or MMAC instruction issues to a unit other than M0, we may
1259 ;; need to insert some nops. In the worst case, the packet will end up
1260 ;; having 4 integer instructions and 4 media instructions, leaving no
1261 ;; room for any branch instructions that the DFA might have accepted.
1263 ;; This doesn't matter for JUMP_INSNs and CALL_INSNs because they are
1264 ;; always the last instructions to be passed to the DFA, and could be
1265 ;; pushed out to a separate packet once the nops have been added.
1266 ;; However, it does cause problems for ccr instructions since they
1267 ;; can occur anywhere in the unordered packet.
1268 (exclusion_set "fr550_msft1,fr550_mmac1,fr550_mmac2,fr550_mmac3"
1269 "fr550_ccr0,fr550_ccr1")
1271 (define_reservation "fr550_malu"
1272 "(f3 + fr550_malu3) | (f2 + fr550_malu2)
1273 | (f1 + fr550_malu1) | (f0 + fr550_malu0)")
1275 (define_reservation "fr550_msft_even"
1278 (define_reservation "fr550_msft_odd"
1281 (define_reservation "fr550_msft_either"
1282 "(f1 + fr550_msft1) | (f0 + fr550_msft0)")
1284 (define_reservation "fr550_mmac_even"
1285 "(f2 + fr550_mmac2) | (f0 + fr550_mmac0)")
1287 (define_reservation "fr550_mmac_odd"
1288 "(f3 + fr550_mmac3) | (f1 + fr550_mmac1)")
1290 (define_reservation "fr550_mset"
1291 "(f3 + fr550_mset3) | (f2 + fr550_mset2)
1292 | (f1 + fr550_mset1) | (f0 + fr550_mset0)")
1294 (define_insn_reservation "fr550_mnop" 0
1295 (and (eq_attr "cpu" "fr550")
1296 (eq_attr "type" "mnop"))
1297 "fr550_media + (f3|f2|f1|f0)")
1299 (define_insn_reservation "fr550_malu" 2
1300 (and (eq_attr "cpu" "fr550")
1301 (eq_attr "type" "mlogic,maveh,msath,mabsh,maddh,mqaddh,mqsath"))
1302 "fr550_media + fr550_malu")
1304 ;; These insns only operate on FPRs and so don't need to be classified
1306 (define_insn_reservation "fr550_msft_1_either" 2
1307 (and (eq_attr "cpu" "fr550")
1308 (eq_attr "type" "mrot,mwcut,mshift,mexpdhw,mexpdhd,mpackh,
1309 munpackh,mdpackh,mbhconv,mdrot,mcpl"))
1310 "fr550_media + fr550_msft_either")
1312 ;; These insns read from ACC0-3.
1313 (define_insn_reservation "fr550_msft_1_even" 2
1314 (and (eq_attr "cpu" "fr550")
1315 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1316 (eq_attr "acc_group" "even")))
1317 "fr550_media + fr550_msft_even")
1319 ;; These insns read from ACC4-7.
1320 (define_insn_reservation "fr550_msft_1_odd" 2
1321 (and (eq_attr "cpu" "fr550")
1322 (and (eq_attr "type" "mcut,mrdacc,mdcut")
1323 (eq_attr "acc_group" "odd")))
1324 "fr550_media + fr550_msft_odd")
1326 ;; MCLRACC with A=1 can issue to either M0 or M1.
1327 (define_insn_reservation "fr550_msft_2_either" 2
1328 (and (eq_attr "cpu" "fr550")
1329 (eq_attr "type" "mclracca"))
1330 "fr550_media + fr550_msft_either")
1332 ;; These insns write to ACC0-3.
1333 (define_insn_reservation "fr550_msft_2_even" 2
1334 (and (eq_attr "cpu" "fr550")
1335 (and (eq_attr "type" "mclracc,mwtacc")
1336 (eq_attr "acc_group" "even")))
1337 "fr550_media + fr550_msft_even")
1339 ;; These insns write to ACC4-7.
1340 (define_insn_reservation "fr550_msft_2_odd" 2
1341 (and (eq_attr "cpu" "fr550")
1342 (and (eq_attr "type" "mclracc,mwtacc")
1343 (eq_attr "acc_group" "odd")))
1344 "fr550_media + fr550_msft_odd")
1346 ;; These insns read from and write to ACC0-3.
1347 (define_insn_reservation "fr550_mmac_even" 2
1348 (and (eq_attr "cpu" "fr550")
1349 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1350 maddacc,mdaddacc,mcpx,mqcpx")
1351 (eq_attr "acc_group" "even")))
1352 "fr550_media + fr550_mmac_even")
1354 ;; These insns read from and write to ACC4-7.
1355 (define_insn_reservation "fr550_mmac_odd" 2
1356 (and (eq_attr "cpu" "fr550")
1357 (and (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,
1358 maddacc,mdaddacc,mcpx,mqcpx")
1359 (eq_attr "acc_group" "odd")))
1360 "fr550_media + fr550_mmac_odd")
1362 (define_insn_reservation "fr550_mset" 1
1363 (and (eq_attr "cpu" "fr550")
1364 (eq_attr "type" "mset"))
1365 "fr550_media + fr550_mset")
1367 ;; ::::::::::::::::::::
1369 ;; :: Simple/FR300 scheduler description
1371 ;; ::::::::::::::::::::
1373 ;; Fr300 or simple processor. To describe it as 1 insn issue
1374 ;; processor, we use control unit.
1376 (define_insn_reservation "fr300_lat1" 1
1377 (and (eq_attr "cpu" "fr300,simple")
1378 (eq_attr "type" "!gload,fload,movfg,movgf"))
1381 (define_insn_reservation "fr300_lat2" 2
1382 (and (eq_attr "cpu" "fr300,simple")
1383 (eq_attr "type" "gload,fload,movfg,movgf"))
1387 ;; ::::::::::::::::::::
1391 ;; ::::::::::::::::::::
1393 ;; The insn attribute mechanism can be used to specify the requirements for
1394 ;; delay slots, if any, on a target machine. An instruction is said to require
1395 ;; a "delay slot" if some instructions that are physically after the
1396 ;; instruction are executed as if they were located before it. Classic
1397 ;; examples are branch and call instructions, which often execute the following
1398 ;; instruction before the branch or call is performed.
1400 ;; On some machines, conditional branch instructions can optionally "annul"
1401 ;; instructions in the delay slot. This means that the instruction will not be
1402 ;; executed for certain branch outcomes. Both instructions that annul if the
1403 ;; branch is true and instructions that annul if the branch is false are
1406 ;; Delay slot scheduling differs from instruction scheduling in that
1407 ;; determining whether an instruction needs a delay slot is dependent only
1408 ;; on the type of instruction being generated, not on data flow between the
1409 ;; instructions. See the next section for a discussion of data-dependent
1410 ;; instruction scheduling.
1412 ;; The requirement of an insn needing one or more delay slots is indicated via
1413 ;; the `define_delay' expression. It has the following form:
1415 ;; (define_delay TEST
1416 ;; [DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
1417 ;; DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
1420 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1421 ;; to a particular insn. If so, the number of required delay slots is
1422 ;; determined by the length of the vector specified as the second argument. An
1423 ;; insn placed in delay slot N must satisfy attribute test DELAY-N.
1424 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1425 ;; if the branch is true. Similarly, ANNUL-FALSE-N specifies which insns in
1426 ;; the delay slot may be annulled if the branch is false. If annulling is not
1427 ;; supported for that delay slot, `(nil)' should be coded.
1429 ;; For example, in the common case where branch and call insns require a single
1430 ;; delay slot, which may contain any insn other than a branch or call, the
1431 ;; following would be placed in the `md' file:
1433 ;; (define_delay (eq_attr "type" "branch,call")
1434 ;; [(eq_attr "type" "!branch,call") (nil) (nil)])
1436 ;; Multiple `define_delay' expressions may be specified. In this case, each
1437 ;; such expression specifies different delay slot requirements and there must
1438 ;; be no insn for which tests in two `define_delay' expressions are both true.
1440 ;; For example, if we have a machine that requires one delay slot for branches
1441 ;; but two for calls, no delay slot can contain a branch or call insn, and any
1442 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1443 ;; true, we might represent this as follows:
1445 ;; (define_delay (eq_attr "type" "branch")
1446 ;; [(eq_attr "type" "!branch,call")
1447 ;; (eq_attr "type" "!branch,call")
1450 ;; (define_delay (eq_attr "type" "call")
1451 ;; [(eq_attr "type" "!branch,call") (nil) (nil)
1452 ;; (eq_attr "type" "!branch,call") (nil) (nil)])
1454 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1455 ;; at assembler generation time. This is usually done by adding a special print
1456 ;; operand to the delayed instruction, and then in the PRINT_OPERAND function
1457 ;; calling dbr_sequence_length() to determine how many delay slots were filled.
1460 ;; --------------<machine>.md-----------------
1461 ;; (define_insn "call"
1462 ;; [(call (match_operand 0 "memory_operand" "m")
1463 ;; (match_operand 1 "" ""))]
1465 ;; "call_delayed %0,%1,%2%#"
1466 ;; [(set_attr "length" "4")
1467 ;; (set_attr "type" "call")])
1469 ;; -------------<machine>.h-------------------
1470 ;; #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '#')
1472 ;; ------------<machine>.c------------------
1474 ;; machine_print_operand (file, x, code)
1482 ;; if (dbr_sequence_length () == 0)
1483 ;; fputs ("\n\tnop", file);
1486 ;; ::::::::::::::::::::
1488 ;; :: Notes on Patterns
1490 ;; ::::::::::::::::::::
1492 ;; If you need to construct a sequence of assembler instructions in order
1493 ;; to implement a pattern be sure to escape any backslashes and double quotes
1494 ;; that you use, e.g.:
1496 ;; (define_insn "an example"
1500 ;; { static char buffer [100];
1501 ;; sprintf (buffer, \"insn \\t %d\", REGNO (operands[1]));
1506 ;; Also if there is more than one instruction, they can be separated by \\;
1507 ;; which is a space saving synonym for \\n\\t:
1509 ;; (define_insn "another example"
1513 ;; { static char buffer [100];
1514 ;; sprintf (buffer, \"insn1 \\t %d\\;insn2 \\t %%1\",
1515 ;; REGNO (operands[1]));
1521 (include "predicates.md")
1523 ;; ::::::::::::::::::::
1527 ;; ::::::::::::::::::::
1529 ;; Wrap moves in define_expand to prevent memory->memory moves from being
1530 ;; generated at the RTL level, which generates better code for most machines
1531 ;; which can't do mem->mem moves.
1533 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1534 ;; than M, the effect of this instruction is to store the specified value in
1535 ;; the part of the register that corresponds to mode M. The effect on the rest
1536 ;; of the register is undefined.
1538 ;; This class of patterns is special in several ways. First of all, each of
1539 ;; these names *must* be defined, because there is no other way to copy a datum
1540 ;; from one place to another.
1542 ;; Second, these patterns are not used solely in the RTL generation pass. Even
1543 ;; the reload pass can generate move insns to copy values from stack slots into
1544 ;; temporary registers. When it does so, one of the operands is a hard
1545 ;; register and the other is an operand that can need to be reloaded into a
1548 ;; Therefore, when given such a pair of operands, the pattern must
1549 ;; generate RTL which needs no reloading and needs no temporary
1550 ;; registers--no registers other than the operands. For example, if
1551 ;; you support the pattern with a `define_expand', then in such a
1552 ;; case the `define_expand' mustn't call `force_reg' or any other such
1553 ;; function which might generate new pseudo registers.
1555 ;; This requirement exists even for subword modes on a RISC machine
1556 ;; where fetching those modes from memory normally requires several
1557 ;; insns and some temporary registers. Look in `spur.md' to see how
1558 ;; the requirement can be satisfied.
1560 ;; During reload a memory reference with an invalid address may be passed as an
1561 ;; operand. Such an address will be replaced with a valid address later in the
1562 ;; reload pass. In this case, nothing may be done with the address except to
1563 ;; use it as it stands. If it is copied, it will not be replaced with a valid
1564 ;; address. No attempt should be made to make such an address into a valid
1565 ;; address and no routine (such as `change_address') that will do so may be
1566 ;; called. Note that `general_operand' will fail when applied to such an
1569 ;; The global variable `reload_in_progress' (which must be explicitly declared
1570 ;; if required) can be used to determine whether such special handling is
1573 ;; The variety of operands that have reloads depends on the rest of
1574 ;; the machine description, but typically on a RISC machine these can
1575 ;; only be pseudo registers that did not get hard registers, while on
1576 ;; other machines explicit memory references will get optional
1579 ;; If a scratch register is required to move an object to or from memory, it
1580 ;; can be allocated using `gen_reg_rtx' prior to reload. But this is
1581 ;; impossible during and after reload. If there are cases needing scratch
1582 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1583 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1584 ;; patterns `reload_inM' or `reload_outM' to handle them.
1586 ;; The constraints on a `moveM' must permit moving any hard register to any
1587 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in
1588 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a
1591 ;; It is obligatory to support floating point `moveM' instructions
1592 ;; into and out of any registers that can hold fixed point values,
1593 ;; because unions and structures (which have modes `SImode' or
1594 ;; `DImode') can be in those registers and they may have floating
1597 ;; There may also be a need to support fixed point `moveM' instructions in and
1598 ;; out of floating point registers. Unfortunately, I have forgotten why this
1599 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK'
1600 ;; rejects fixed point values in floating point registers, then the constraints
1601 ;; of the fixed point `moveM' instructions must be designed to avoid ever
1602 ;; trying to reload into a floating point register.
1604 (define_expand "movqi"
1605 [(set (match_operand:QI 0 "general_operand" "")
1606 (match_operand:QI 1 "general_operand" ""))]
1608 "{ frv_emit_move (QImode, operands[0], operands[1]); DONE; }")
1610 (define_insn "*movqi_load"
1611 [(set (match_operand:QI 0 "register_operand" "=d,f")
1612 (match_operand:QI 1 "frv_load_operand" "m,m"))]
1614 "* return output_move_single (operands, insn);"
1615 [(set_attr "length" "4")
1616 (set_attr "type" "gload,fload")])
1618 (define_insn "*movqi_internal"
1619 [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
1620 (match_operand:QI 1 "move_source_operand" "L,d,d,O, d, f, f, f,GO,!m,!m"))]
1621 "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
1622 "* return output_move_single (operands, insn);"
1623 [(set_attr "length" "4")
1624 (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1626 (define_expand "movhi"
1627 [(set (match_operand:HI 0 "general_operand" "")
1628 (match_operand:HI 1 "general_operand" ""))]
1630 "{ frv_emit_move (HImode, operands[0], operands[1]); DONE; }")
1632 (define_insn "*movhi_load"
1633 [(set (match_operand:HI 0 "register_operand" "=d,f")
1634 (match_operand:HI 1 "frv_load_operand" "m,m"))]
1636 "* return output_move_single (operands, insn);"
1637 [(set_attr "length" "4")
1638 (set_attr "type" "gload,fload")])
1640 (define_insn "*movhi_internal"
1641 [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
1642 (match_operand:HI 1 "move_source_operand" "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
1643 "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
1644 "* return output_move_single (operands, insn);"
1645 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
1646 (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
1648 ;; Split 2 word load of constants into sethi/setlo instructions
1650 [(set (match_operand:HI 0 "integer_register_operand" "")
1651 (match_operand:HI 1 "int_2word_operand" ""))]
1654 (high:HI (match_dup 1)))
1656 (lo_sum:HI (match_dup 0)
1660 (define_insn "movhi_high"
1661 [(set (match_operand:HI 0 "integer_register_operand" "=d")
1662 (high:HI (match_operand:HI 1 "int_2word_operand" "i")))]
1665 [(set_attr "type" "sethi")
1666 (set_attr "length" "4")])
1668 (define_insn "movhi_lo_sum"
1669 [(set (match_operand:HI 0 "integer_register_operand" "+d")
1670 (lo_sum:HI (match_dup 0)
1671 (match_operand:HI 1 "int_2word_operand" "i")))]
1674 [(set_attr "type" "setlo")
1675 (set_attr "length" "4")])
1677 (define_expand "movsi"
1678 [(set (match_operand:SI 0 "move_destination_operand" "")
1679 (match_operand:SI 1 "move_source_operand" ""))]
1681 "{ frv_emit_move (SImode, operands[0], operands[1]); DONE; }")
1683 ;; Note - it is best to only have one movsi pattern and to handle
1684 ;; all the various contingencies by the use of alternatives. This
1685 ;; allows reload the greatest amount of flexibility (since reload will
1686 ;; only choose amongst alternatives for a selected insn, it will not
1687 ;; replace the insn with another one).
1689 ;; Unfortunately, we do have to separate out load-type moves from the rest,
1690 ;; and only allow memory source operands in the former. If we do memory and
1691 ;; constant loads in a single pattern, reload will be tempted to force
1692 ;; constants into memory when the destination is a floating-point register.
1693 ;; That may make a function use a PIC pointer when it didn't before, and we
1694 ;; cannot change PIC usage (and hence stack layout) so late in the game.
1695 ;; The resulting sequences for loading constants into FPRs are preferable
1696 ;; even when we're not generating PIC code.
1698 ;; However, if we don't accept input from memory at all in the generic
1699 ;; movsi pattern, reloads for asm instructions that reference pseudos
1700 ;; that end up assigned to memory will fail to match, because we
1701 ;; recognize them right after they're emitted, and we don't
1702 ;; re-recognize them again after the substitution for memory. So keep
1703 ;; a memory constraint available, just make sure reload won't be
1704 ;; tempted to use it.
1708 (define_insn "*movsi_load"
1709 [(set (match_operand:SI 0 "register_operand" "=d,f")
1710 (match_operand:SI 1 "frv_load_operand" "m,m"))]
1712 "* return output_move_single (operands, insn);"
1713 [(set_attr "length" "4")
1714 (set_attr "type" "gload,fload")])
1716 (define_insn "*movsi_got"
1717 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1718 (match_operand:SI 1 "got12_operand" ""))]
1721 [(set_attr "type" "int")
1722 (set_attr "length" "4")])
1724 (define_insn "*movsi_high_got"
1725 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1726 (high:SI (match_operand:SI 1 "const_unspec_operand" "")))]
1729 [(set_attr "type" "sethi")
1730 (set_attr "length" "4")])
1732 (define_insn "*movsi_lo_sum_got"
1733 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1734 (lo_sum:SI (match_operand:SI 1 "integer_register_operand" "0")
1735 (match_operand:SI 2 "const_unspec_operand" "")))]
1738 [(set_attr "type" "setlo")
1739 (set_attr "length" "4")])
1741 (define_insn "*movsi_internal"
1742 [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
1743 (match_operand:SI 1 "move_source_operand" "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
1744 "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
1745 "* return output_move_single (operands, insn);"
1746 [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
1747 (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
1749 ;; Split 2 word load of constants into sethi/setlo instructions
1750 (define_insn_and_split "*movsi_2word"
1751 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1752 (match_operand:SI 1 "int_2word_operand" "i"))]
1757 (high:SI (match_dup 1)))
1759 (lo_sum:SI (match_dup 0)
1762 [(set_attr "length" "8")
1763 (set_attr "type" "multi")])
1765 (define_insn "movsi_high"
1766 [(set (match_operand:SI 0 "integer_register_operand" "=d")
1767 (high:SI (match_operand:SI 1 "int_2word_operand" "i")))]
1770 [(set_attr "type" "sethi")
1771 (set_attr "length" "4")])
1773 (define_insn "movsi_lo_sum"
1774 [(set (match_operand:SI 0 "integer_register_operand" "+d")
1775 (lo_sum:SI (match_dup 0)
1776 (match_operand:SI 1 "int_2word_operand" "i")))]
1779 [(set_attr "type" "setlo")
1780 (set_attr "length" "4")])
1782 (define_expand "movdi"
1783 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1784 (match_operand:DI 1 "general_operand" ""))]
1786 "{ frv_emit_move (DImode, operands[0], operands[1]); DONE; }")
1788 (define_insn "*movdi_double"
1789 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1790 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1792 && (register_operand (operands[0], DImode)
1793 || reg_or_0_operand (operands[1], DImode))"
1794 "* return output_move_double (operands, insn);"
1795 [(set_attr "length" "8,4,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,16,16,8,8")
1796 (set_attr "type" "multi,fdconv,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1798 (define_insn "*movdi_nodouble"
1799 [(set (match_operand:DI 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
1800 (match_operand:DI 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
1802 && (register_operand (operands[0], DImode)
1803 || reg_or_0_operand (operands[1], DImode))"
1804 "* return output_move_double (operands, insn);"
1805 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
1806 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
1809 [(set (match_operand:DI 0 "register_operand" "")
1810 (match_operand:DI 1 "dbl_memory_two_insn_operand" ""))]
1813 "frv_split_double_load (operands[0], operands[1]);")
1816 [(set (match_operand:DI 0 "odd_reg_operand" "")
1817 (match_operand:DI 1 "memory_operand" ""))]
1820 "frv_split_double_load (operands[0], operands[1]);")
1823 [(set (match_operand:DI 0 "dbl_memory_two_insn_operand" "")
1824 (match_operand:DI 1 "reg_or_0_operand" ""))]
1827 "frv_split_double_store (operands[0], operands[1]);")
1830 [(set (match_operand:DI 0 "memory_operand" "")
1831 (match_operand:DI 1 "odd_reg_operand" ""))]
1834 "frv_split_double_store (operands[0], operands[1]);")
1837 [(set (match_operand:DI 0 "register_operand" "")
1838 (match_operand:DI 1 "register_operand" ""))]
1840 && (odd_reg_operand (operands[0], DImode)
1841 || odd_reg_operand (operands[1], DImode)
1842 || (integer_register_operand (operands[0], DImode)
1843 && integer_register_operand (operands[1], DImode))
1845 && fpr_operand (operands[0], DImode)
1846 && fpr_operand (operands[1], DImode)))"
1847 [(set (match_dup 2) (match_dup 4))
1848 (set (match_dup 3) (match_dup 5))]
1851 rtx op0 = operands[0];
1852 rtx op0_low = gen_lowpart (SImode, op0);
1853 rtx op0_high = gen_highpart (SImode, op0);
1854 rtx op1 = operands[1];
1855 rtx op1_low = gen_lowpart (SImode, op1);
1856 rtx op1_high = gen_highpart (SImode, op1);
1858 /* We normally copy the low-numbered register first. However, if the first
1859 register operand 0 is the same as the second register of operand 1, we
1860 must copy in the opposite order. */
1862 if (REGNO (op0_high) == REGNO (op1_low))
1864 operands[2] = op0_low;
1865 operands[3] = op0_high;
1866 operands[4] = op1_low;
1867 operands[5] = op1_high;
1871 operands[2] = op0_high;
1872 operands[3] = op0_low;
1873 operands[4] = op1_high;
1874 operands[5] = op1_low;
1879 [(set (match_operand:DI 0 "register_operand" "")
1880 (match_operand:DI 1 "const_int_operand" ""))]
1882 [(set (match_dup 2) (match_dup 4))
1883 (set (match_dup 3) (match_dup 5))]
1886 rtx op0 = operands[0];
1887 rtx op1 = operands[1];
1889 operands[2] = gen_highpart (SImode, op0);
1890 operands[3] = gen_lowpart (SImode, op0);
1891 if (HOST_BITS_PER_WIDE_INT <= 32)
1893 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
1898 operands[4] = gen_int_mode ((INTVAL (op1) >> 16) >> 16, SImode);
1899 operands[5] = gen_int_mode (INTVAL (op1), SImode);
1904 [(set (match_operand:DI 0 "register_operand" "")
1905 (match_operand:DI 1 "const_double_operand" ""))]
1907 [(set (match_dup 2) (match_dup 4))
1908 (set (match_dup 3) (match_dup 5))]
1911 rtx op0 = operands[0];
1912 rtx op1 = operands[1];
1914 operands[2] = gen_highpart (SImode, op0);
1915 operands[3] = gen_lowpart (SImode, op0);
1916 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (op1));
1917 operands[5] = GEN_INT (CONST_DOUBLE_LOW (op1));
1920 ;; Floating Point Moves
1922 ;; Note - Patterns for SF mode moves are compulsory, but
1923 ;; patterns for DF are optional, as GCC can synthesize them.
1925 (define_expand "movsf"
1926 [(set (match_operand:SF 0 "general_operand" "")
1927 (match_operand:SF 1 "general_operand" ""))]
1929 "{ frv_emit_move (SFmode, operands[0], operands[1]); DONE; }")
1932 [(set (match_operand:SF 0 "integer_register_operand" "")
1933 (match_operand:SF 1 "int_2word_operand" ""))]
1936 (high:SF (match_dup 1)))
1938 (lo_sum:SF (match_dup 0)
1942 (define_insn "*movsf_load_has_fprs"
1943 [(set (match_operand:SF 0 "register_operand" "=f,d")
1944 (match_operand:SF 1 "frv_load_operand" "m,m"))]
1946 "* return output_move_single (operands, insn);"
1947 [(set_attr "length" "4")
1948 (set_attr "type" "fload,gload")])
1950 (define_insn "*movsf_internal_has_fprs"
1951 [(set (match_operand:SF 0 "move_destination_operand" "=f,f,m,m,?f,?d,?d,m,?d")
1952 (match_operand:SF 1 "move_source_operand" "f,OG,f,OG,d,f,d,d,F"))]
1954 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1955 "* return output_move_single (operands, insn);"
1956 [(set_attr "length" "4,4,4,4,4,4,4,4,8")
1957 (set_attr "type" "fsconv,movgf,fstore,gstore,movgf,movfg,int,gstore,multi")])
1959 ;; If we don't support the double instructions, prefer gprs over fprs, since it
1960 ;; will all be emulated
1961 (define_insn "*movsf_internal_no_fprs"
1962 [(set (match_operand:SF 0 "move_destination_operand" "=d,d,m,d,d")
1963 (match_operand:SF 1 "move_source_operand" " d,OG,dOG,m,F"))]
1965 && (register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode))"
1966 "* return output_move_single (operands, insn);"
1967 [(set_attr "length" "4,4,4,4,8")
1968 (set_attr "type" "int,int,gstore,gload,multi")])
1970 (define_insn "movsf_high"
1971 [(set (match_operand:SF 0 "integer_register_operand" "=d")
1972 (high:SF (match_operand:SF 1 "int_2word_operand" "i")))]
1975 [(set_attr "type" "sethi")
1976 (set_attr "length" "4")])
1978 (define_insn "movsf_lo_sum"
1979 [(set (match_operand:SF 0 "integer_register_operand" "+d")
1980 (lo_sum:SF (match_dup 0)
1981 (match_operand:SF 1 "int_2word_operand" "i")))]
1984 [(set_attr "type" "setlo")
1985 (set_attr "length" "4")])
1987 (define_expand "movdf"
1988 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1989 (match_operand:DF 1 "general_operand" ""))]
1991 "{ frv_emit_move (DFmode, operands[0], operands[1]); DONE; }")
1993 (define_insn "*movdf_double"
1994 [(set (match_operand:DF 0 "move_destination_operand" "=h,?e,??f,??d,R,?R,??m,??m,h,?e,??f,??d,?h,??f,?e,??d,R,m,h,??f,e,??d,e,??d")
1995 (match_operand:DF 1 "move_source_operand" " h,e,f,d,h,e,f,d,R,R,m,m,e,d,h,f,GO,GO,GO,GO,GO,GO,F,F"))]
1997 && (register_operand (operands[0], DFmode)
1998 || reg_or_0_operand (operands[1], DFmode))"
1999 "* return output_move_double (operands, insn);"
2000 [(set_attr "length" "4,8,8,8,4,4,8,8,4,4,8,8,4,8,4,8,4,8,8,8,8,8,16,16")
2001 (set_attr "type" "fdconv,multi,multi,multi,fstore,gstore,fstore,gstore,fload,gload,fload,gload,movgf,movgf,movfg,movfg,gstore,gstore,movgf,movgf,multi,multi,multi,multi")])
2003 ;; If we don't support the double instructions, prefer gprs over fprs, since it
2004 ;; will all be emulated
2005 (define_insn "*movdf_nodouble"
2006 [(set (match_operand:DF 0 "move_destination_operand" "=e,?h,??d,??f,R,?R,??m,??m,e,?h,??d,??f,?e,??d,?h,??f,R,m,e,??d,e,??d,?h,??f")
2007 (match_operand:DF 1 "move_source_operand" " e,h,d,f,e,h,d,f,R,R,m,m,h,f,e,d,GO,GO,GO,GO,nF,nF,GO,GO"))]
2009 && (register_operand (operands[0], DFmode)
2010 || reg_or_0_operand (operands[1], DFmode))"
2011 "* return output_move_double (operands, insn);"
2012 [(set_attr "length" "8,8,8,8,4,4,8,8,4,4,8,8,8,8,8,8,4,8,8,8,16,16,8,8")
2013 (set_attr "type" "multi,multi,multi,multi,gstore,fstore,gstore,fstore,gload,fload,gload,fload,movfg,movfg,movgf,movgf,gstore,gstore,multi,multi,multi,multi,movgf,movgf")])
2016 [(set (match_operand:DF 0 "register_operand" "")
2017 (match_operand:DF 1 "dbl_memory_two_insn_operand" ""))]
2020 "frv_split_double_load (operands[0], operands[1]);")
2023 [(set (match_operand:DF 0 "odd_reg_operand" "")
2024 (match_operand:DF 1 "memory_operand" ""))]
2027 "frv_split_double_load (operands[0], operands[1]);")
2030 [(set (match_operand:DF 0 "dbl_memory_two_insn_operand" "")
2031 (match_operand:DF 1 "reg_or_0_operand" ""))]
2034 "frv_split_double_store (operands[0], operands[1]);")
2037 [(set (match_operand:DF 0 "memory_operand" "")
2038 (match_operand:DF 1 "odd_reg_operand" ""))]
2041 "frv_split_double_store (operands[0], operands[1]);")
2044 [(set (match_operand:DF 0 "register_operand" "")
2045 (match_operand:DF 1 "register_operand" ""))]
2047 && (odd_reg_operand (operands[0], DFmode)
2048 || odd_reg_operand (operands[1], DFmode)
2049 || (integer_register_operand (operands[0], DFmode)
2050 && integer_register_operand (operands[1], DFmode))
2052 && fpr_operand (operands[0], DFmode)
2053 && fpr_operand (operands[1], DFmode)))"
2054 [(set (match_dup 2) (match_dup 4))
2055 (set (match_dup 3) (match_dup 5))]
2058 rtx op0 = operands[0];
2059 rtx op0_low = gen_lowpart (SImode, op0);
2060 rtx op0_high = gen_highpart (SImode, op0);
2061 rtx op1 = operands[1];
2062 rtx op1_low = gen_lowpart (SImode, op1);
2063 rtx op1_high = gen_highpart (SImode, op1);
2065 /* We normally copy the low-numbered register first. However, if the first
2066 register operand 0 is the same as the second register of operand 1, we
2067 must copy in the opposite order. */
2069 if (REGNO (op0_high) == REGNO (op1_low))
2071 operands[2] = op0_low;
2072 operands[3] = op0_high;
2073 operands[4] = op1_low;
2074 operands[5] = op1_high;
2078 operands[2] = op0_high;
2079 operands[3] = op0_low;
2080 operands[4] = op1_high;
2081 operands[5] = op1_low;
2086 [(set (match_operand:DF 0 "register_operand" "")
2087 (match_operand:DF 1 "const_int_operand" ""))]
2089 [(set (match_dup 2) (match_dup 4))
2090 (set (match_dup 3) (match_dup 5))]
2093 rtx op0 = operands[0];
2094 rtx op1 = operands[1];
2096 operands[2] = gen_highpart (SImode, op0);
2097 operands[3] = gen_lowpart (SImode, op0);
2098 if (HOST_BITS_PER_WIDE_INT <= 32)
2100 operands[4] = GEN_INT ((INTVAL (op1) < 0) ? -1 : 0);
2105 operands[4] = GEN_INT (((((unsigned HOST_WIDE_INT)INTVAL (op1) >> 16)
2106 >> 16) ^ ((unsigned HOST_WIDE_INT)1 << 31))
2107 - ((unsigned HOST_WIDE_INT)1 << 31));
2108 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (op1), SImode));
2113 [(set (match_operand:DF 0 "register_operand" "")
2114 (match_operand:DF 1 "const_double_operand" ""))]
2116 [(set (match_dup 2) (match_dup 4))
2117 (set (match_dup 3) (match_dup 5))]
2120 rtx op0 = operands[0];
2121 rtx op1 = operands[1];
2125 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1);
2126 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2128 operands[2] = gen_highpart (SImode, op0);
2129 operands[3] = gen_lowpart (SImode, op0);
2130 operands[4] = GEN_INT (l[0]);
2131 operands[5] = GEN_INT (l[1]);
2134 ;; String/block move insn.
2135 ;; Argument 0 is the destination
2136 ;; Argument 1 is the source
2137 ;; Argument 2 is the length
2138 ;; Argument 3 is the alignment
2140 (define_expand "movmemsi"
2141 [(parallel [(set (match_operand:BLK 0 "" "")
2142 (match_operand:BLK 1 "" ""))
2143 (use (match_operand:SI 2 "" ""))
2144 (use (match_operand:SI 3 "" ""))])]
2148 if (frv_expand_block_move (operands))
2154 ;; String/block set insn.
2155 ;; Argument 0 is the destination
2156 ;; Argument 1 is the length
2157 ;; Argument 2 is the byte value -- ignore any value but zero
2158 ;; Argument 3 is the alignment
2160 (define_expand "setmemsi"
2161 [(parallel [(set (match_operand:BLK 0 "" "")
2162 (match_operand 2 "" ""))
2163 (use (match_operand:SI 1 "" ""))
2164 (use (match_operand:SI 3 "" ""))])]
2168 /* If value to set is not zero, use the library routine. */
2169 if (operands[2] != const0_rtx)
2172 if (frv_expand_block_clear (operands))
2179 ;; The "membar" part of a __builtin_read* or __builtin_write* function.
2180 ;; Operand 0 is a volatile reference to the memory that the function reads
2181 ;; or writes. Operand 1 is the address being accessed, or zero if the
2182 ;; address isn't a known constant. Operand 2 describes the __builtin
2183 ;; function (either FRV_IO_READ or FRV_IO_WRITE).
2184 (define_insn "optional_membar_<mode>"
2185 [(set (match_operand:IMODE 0 "memory_operand" "=m")
2186 (unspec:IMODE [(match_operand 1 "const_int_operand" "")
2187 (match_operand 2 "const_int_operand" "")]
2188 UNSPEC_OPTIONAL_MEMBAR))]
2191 [(set_attr "length" "4")])
2193 ;; ::::::::::::::::::::
2195 ;; :: Reload CC registers
2197 ;; ::::::::::::::::::::
2199 ;; Use as a define_expand so that cse/gcse/combine can't accidentally
2200 ;; create movcc insns.
2202 (define_expand "movcc"
2203 [(parallel [(set (match_operand:CC 0 "move_destination_operand" "")
2204 (match_operand:CC 1 "move_source_operand" ""))
2205 (clobber (match_dup 2))])]
2209 if (! reload_in_progress && ! reload_completed)
2212 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2215 (define_insn "*internal_movcc"
2216 [(set (match_operand:CC 0 "move_destination_operand" "=t,d,d,m,d")
2217 (match_operand:CC 1 "move_source_operand" "d,d,m,d,t"))
2218 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2219 "reload_in_progress || reload_completed"
2226 [(set_attr "length" "4,4,4,4,20")
2227 (set_attr "type" "int,int,gload,gstore,multi")])
2229 ;; To move an ICC value to a GPR for a signed comparison, we create a value
2230 ;; that when compared to 0, sets the N and Z flags appropriately (we don't care
2231 ;; about the V and C flags, since these comparisons are signed).
2234 [(set (match_operand:CC 0 "integer_register_operand" "")
2235 (match_operand:CC 1 "icc_operand" ""))
2236 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2237 "reload_in_progress || reload_completed"
2241 rtx dest = simplify_gen_subreg (SImode, operands[0], CCmode, 0);
2242 rtx icc = operands[1];
2243 rtx icr = operands[2];
2247 emit_insn (gen_rtx_SET (VOIDmode, icr,
2248 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2250 emit_insn (gen_movsi (dest, const1_rtx));
2252 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2253 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2254 gen_rtx_SET (VOIDmode, dest,
2255 gen_rtx_NEG (SImode, dest))));
2257 emit_insn (gen_rtx_SET (VOIDmode, icr,
2258 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2260 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2261 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2262 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2264 operands[3] = get_insns ();
2268 ;; Reload CC_UNSmode for unsigned integer comparisons
2269 ;; Use define_expand so that cse/gcse/combine can't create movcc_uns insns
2271 (define_expand "movcc_uns"
2272 [(parallel [(set (match_operand:CC_UNS 0 "move_destination_operand" "")
2273 (match_operand:CC_UNS 1 "move_source_operand" ""))
2274 (clobber (match_dup 2))])]
2278 if (! reload_in_progress && ! reload_completed)
2280 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2283 (define_insn "*internal_movcc_uns"
2284 [(set (match_operand:CC_UNS 0 "move_destination_operand" "=t,d,d,m,d")
2285 (match_operand:CC_UNS 1 "move_source_operand" "d,d,m,d,t"))
2286 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2287 "reload_in_progress || reload_completed"
2294 [(set_attr "length" "4,4,4,4,20")
2295 (set_attr "type" "int,int,gload,gstore,multi")])
2297 ;; To move an ICC value to a GPR for an unsigned comparison, we create a value
2298 ;; that when compared to 1, sets the Z, V, and C flags appropriately (we don't
2299 ;; care about the N flag, since these comparisons are unsigned).
2302 [(set (match_operand:CC_UNS 0 "integer_register_operand" "")
2303 (match_operand:CC_UNS 1 "icc_operand" ""))
2304 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2305 "reload_in_progress || reload_completed"
2309 rtx dest = simplify_gen_subreg (SImode, operands[0], CC_UNSmode, 0);
2310 rtx icc = operands[1];
2311 rtx icr = operands[2];
2315 emit_insn (gen_rtx_SET (VOIDmode, icr,
2316 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2318 emit_insn (gen_movsi (dest, const1_rtx));
2320 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2321 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2322 gen_addsi3 (dest, dest, dest)));
2324 emit_insn (gen_rtx_SET (VOIDmode, icr,
2325 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2327 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2328 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2329 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
2331 operands[3] = get_insns ();
2335 ;; Reload CC_NZmode. This is mostly the same as the CCmode and CC_UNSmode
2336 ;; handling, but it uses different sequences for moving between GPRs and ICCs.
2338 (define_expand "movcc_nz"
2339 [(parallel [(set (match_operand:CC_NZ 0 "move_destination_operand" "")
2340 (match_operand:CC_NZ 1 "move_source_operand" ""))
2341 (clobber (match_dup 2))])]
2345 if (!reload_in_progress && !reload_completed)
2347 operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
2350 (define_insn "*internal_movcc_nz"
2351 [(set (match_operand:CC_NZ 0 "move_destination_operand" "=t,d,d,m,d")
2352 (match_operand:CC_NZ 1 "move_source_operand" "d,d,m,d,t"))
2353 (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
2354 "reload_in_progress || reload_completed"
2361 [(set_attr "length" "4,4,4,4,20")
2362 (set_attr "type" "int,int,gload,gstore,multi")])
2364 ;; Set the destination to a value that, when compared with zero, will
2365 ;; restore the value of the Z and N flags. The values of the other
2366 ;; flags don't matter. The sequence is:
2370 ;; csub gr0,op0,op0,op2
2374 [(set (match_operand:CC_NZ 0 "integer_register_operand" "")
2375 (match_operand:CC_NZ 1 "icc_operand" ""))
2376 (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
2377 "reload_in_progress || reload_completed"
2381 (ge:CC_CCR (match_dup 1)
2383 (cond_exec (ne:CC_CCR (match_dup 2)
2386 (neg:SI (match_dup 3))))
2388 (eq:CC_CCR (match_dup 1)
2390 (cond_exec (ne:CC_CCR (match_dup 2)
2392 (set (match_dup 3) (const_int 0)))]
2393 "operands[3] = simplify_gen_subreg (SImode, operands[0], CC_NZmode, 0);")
2395 ;; Reload CC_FPmode for floating point comparisons
2396 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
2397 ;; create movcc insns. If this was a named define_insn, we would not be able
2398 ;; to make it conditional on reload.
2400 (define_expand "movcc_fp"
2401 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "")
2402 (match_operand:CC_FP 1 "move_source_operand" ""))]
2406 if (! reload_in_progress && ! reload_completed)
2410 (define_insn "*movcc_fp_internal"
2411 [(set (match_operand:CC_FP 0 "movcc_fp_destination_operand" "=d,d,d,m")
2412 (match_operand:CC_FP 1 "move_source_operand" "u,d,m,d"))]
2413 "TARGET_HAS_FPRS && (reload_in_progress || reload_completed)"
2419 [(set_attr "length" "12,4,4,4")
2420 (set_attr "type" "multi,int,gload,gstore")])
2423 (define_expand "reload_incc_fp"
2424 [(match_operand:CC_FP 0 "fcc_operand" "=u")
2425 (match_operand:CC_FP 1 "gpr_or_memory_operand_with_scratch" "m")
2426 (match_operand:TI 2 "integer_register_operand" "=&d")]
2430 rtx cc_op2 = simplify_gen_subreg (CC_FPmode, operands[2], TImode, 0);
2431 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], TImode, 0);
2432 rtx temp1 = simplify_gen_subreg (SImode, operands[2], TImode, 4);
2433 rtx temp2 = simplify_gen_subreg (SImode, operands[2], TImode, 8);
2434 int shift = CC_SHIFT_RIGHT (REGNO (operands[0]));
2437 if (!gpr_or_memory_operand (operands[1], CC_FPmode))
2440 rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
2442 gcc_assert (GET_CODE (operands[1]) == MEM);
2444 addr = XEXP (operands[1], 0);
2446 gcc_assert (GET_CODE (addr) == PLUS);
2448 emit_move_insn (temp3, XEXP (addr, 1));
2450 operands[1] = replace_equiv_address (operands[1],
2451 gen_rtx_PLUS (GET_MODE (addr),
2456 emit_insn (gen_movcc_fp (cc_op2, operands[1]));
2458 emit_insn (gen_ashlsi3 (int_op2, int_op2, GEN_INT (shift)));
2460 mask = ~ ((HOST_WIDE_INT)CC_MASK << shift);
2461 emit_insn (gen_movsi (temp1, GEN_INT (mask)));
2462 emit_insn (gen_update_fcc (operands[0], int_op2, temp1, temp2));
2466 (define_expand "reload_outcc_fp"
2467 [(set (match_operand:CC_FP 2 "integer_register_operand" "=&d")
2468 (match_operand:CC_FP 1 "fcc_operand" "u"))
2469 (set (match_operand:CC_FP 0 "memory_operand" "=m")
2474 ;; Convert a FCC value to gpr
2475 (define_insn "read_fcc"
2476 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2477 (unspec:SI [(match_operand:CC_FP 1 "fcc_operand" "u")]
2481 [(set_attr "type" "spr")
2482 (set_attr "length" "4")])
2485 [(set (match_operand:CC_FP 0 "integer_register_operand" "")
2486 (match_operand:CC_FP 1 "fcc_operand" ""))]
2487 "reload_completed && TARGET_HAS_FPRS"
2491 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_FPmode, 0);
2492 int shift = CC_SHIFT_RIGHT (REGNO (operands[1]));
2496 emit_insn (gen_read_fcc (int_op0, operands[1]));
2498 emit_insn (gen_lshrsi3 (int_op0, int_op0, GEN_INT (shift)));
2500 emit_insn (gen_andsi3 (int_op0, int_op0, GEN_INT (CC_MASK)));
2502 operands[2] = get_insns ();
2506 ;; Move a gpr value to FCC.
2508 ;; Operand1 = reloaded value shifted appropriately
2509 ;; Operand2 = mask to eliminate current register
2510 ;; Operand3 = temporary to load/store ccr
2511 (define_insn "update_fcc"
2512 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
2513 (unspec:CC_FP [(match_operand:SI 1 "integer_register_operand" "d")
2514 (match_operand:SI 2 "integer_register_operand" "d")]
2516 (clobber (match_operand:SI 3 "integer_register_operand" "=&d"))]
2518 "movsg ccr, %3\;and %2, %3, %3\;or %1, %3, %3\;movgs %3, ccr"
2519 [(set_attr "type" "multi")
2520 (set_attr "length" "16")])
2522 ;; Reload CC_CCRmode for conditional execution registers
2523 (define_insn "movcc_ccr"
2524 [(set (match_operand:CC_CCR 0 "move_destination_operand" "=d,d,d,m,v,?w,C,d")
2525 (match_operand:CC_CCR 1 "move_source_operand" "C,d,m,d,n,n,C,L"))]
2536 [(set_attr "length" "8,4,4,4,8,12,4,4")
2537 (set_attr "type" "multi,int,gload,gstore,multi,multi,ccr,int")])
2539 (define_expand "reload_incc_ccr"
2540 [(match_operand:CC_CCR 0 "cr_operand" "=C")
2541 (match_operand:CC_CCR 1 "memory_operand" "m")
2542 (match_operand:CC_CCR 2 "integer_register_operand" "=&d")]
2546 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2547 rtx int_op2 = simplify_gen_subreg (SImode, operands[2], CC_CCRmode, 0);
2548 rtx icr = (ICR_P (REGNO (operands[0]))
2549 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2551 emit_insn (gen_movcc_ccr (operands[2], operands[1]));
2552 emit_insn (gen_cmpsi_cc (icc, int_op2, const0_rtx));
2553 emit_insn (gen_movcc_ccr (icr, gen_rtx_NE (CC_CCRmode, icc, const0_rtx)));
2555 if (! ICR_P (REGNO (operands[0])))
2556 emit_insn (gen_movcc_ccr (operands[0], icr));
2561 (define_expand "reload_outcc_ccr"
2562 [(set (match_operand:CC_CCR 2 "integer_register_operand" "=&d")
2563 (match_operand:CC_CCR 1 "cr_operand" "C"))
2564 (set (match_operand:CC_CCR 0 "memory_operand" "=m")
2570 [(set (match_operand:CC_CCR 0 "integer_register_operand" "")
2571 (match_operand:CC_CCR 1 "cr_operand" ""))]
2576 rtx int_op0 = simplify_gen_subreg (SImode, operands[0], CC_CCRmode, 0);
2579 emit_move_insn (operands[0], const1_rtx);
2580 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2581 gen_rtx_EQ (CC_CCRmode,
2584 gen_rtx_SET (VOIDmode, int_op0,
2587 operands[2] = get_insns ();
2592 [(set (match_operand:CC_CCR 0 "cr_operand" "")
2593 (match_operand:CC_CCR 1 "const_int_operand" ""))]
2598 rtx icc = gen_rtx_REG (CCmode, ICC_TEMP);
2599 rtx r0 = gen_rtx_REG (SImode, GPR_FIRST);
2600 rtx icr = (ICR_P (REGNO (operands[0]))
2601 ? operands[0] : gen_rtx_REG (CC_CCRmode, ICR_TEMP));
2605 emit_insn (gen_cmpsi_cc (icc, r0, const0_rtx));
2607 emit_insn (gen_movcc_ccr (icr,
2608 gen_rtx_fmt_ee (((INTVAL (operands[1]) == 0)
2609 ? EQ : NE), CC_CCRmode,
2612 if (! ICR_P (REGNO (operands[0])))
2613 emit_insn (gen_movcc_ccr (operands[0], icr));
2615 operands[2] = get_insns ();
2620 ;; ::::::::::::::::::::
2624 ;; ::::::::::::::::::::
2626 ;; Signed conversions from a smaller integer to a larger integer
2628 ;; These operations are optional. If they are not
2629 ;; present GCC will synthesize them for itself
2630 ;; Even though frv does not provide these instructions, we define them
2631 ;; to allow load + sign extend to be collapsed together
2632 (define_insn "extendqihi2"
2633 [(set (match_operand:HI 0 "integer_register_operand" "=d,d")
2634 (sign_extend:HI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2639 [(set_attr "length" "8,4")
2640 (set_attr "type" "multi,gload")])
2643 [(set (match_operand:HI 0 "integer_register_operand" "")
2644 (sign_extend:HI (match_operand:QI 1 "integer_register_operand" "")))]
2650 rtx op0 = gen_lowpart (SImode, operands[0]);
2651 rtx op1 = gen_lowpart (SImode, operands[1]);
2652 rtx shift = GEN_INT (24);
2654 operands[2] = gen_ashlsi3 (op0, op1, shift);
2655 operands[3] = gen_ashrsi3 (op0, op0, shift);
2658 (define_insn "extendqisi2"
2659 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2660 (sign_extend:SI (match_operand:QI 1 "gpr_or_memory_operand" "d,m")))]
2665 [(set_attr "length" "8,4")
2666 (set_attr "type" "multi,gload")])
2669 [(set (match_operand:SI 0 "integer_register_operand" "")
2670 (sign_extend:SI (match_operand:QI 1 "integer_register_operand" "")))]
2676 rtx op0 = gen_lowpart (SImode, operands[0]);
2677 rtx op1 = gen_lowpart (SImode, operands[1]);
2678 rtx shift = GEN_INT (24);
2680 operands[2] = gen_ashlsi3 (op0, op1, shift);
2681 operands[3] = gen_ashrsi3 (op0, op0, shift);
2684 ;;(define_insn "extendqidi2"
2685 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2686 ;; (sign_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2688 ;; "extendqihi2 %0,%1"
2689 ;; [(set_attr "length" "4")])
2691 (define_insn "extendhisi2"
2692 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2693 (sign_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "d,m")))]
2698 [(set_attr "length" "8,4")
2699 (set_attr "type" "multi,gload")])
2702 [(set (match_operand:SI 0 "integer_register_operand" "")
2703 (sign_extend:SI (match_operand:HI 1 "integer_register_operand" "")))]
2709 rtx op0 = gen_lowpart (SImode, operands[0]);
2710 rtx op1 = gen_lowpart (SImode, operands[1]);
2711 rtx shift = GEN_INT (16);
2713 operands[2] = gen_ashlsi3 (op0, op1, shift);
2714 operands[3] = gen_ashrsi3 (op0, op0, shift);
2717 ;;(define_insn "extendhidi2"
2718 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2719 ;; (sign_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2721 ;; "extendhihi2 %0,%1"
2722 ;; [(set_attr "length" "4")])
2724 ;;(define_insn "extendsidi2"
2725 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2726 ;; (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2728 ;; "extendsidi2 %0,%1"
2729 ;; [(set_attr "length" "4")])
2731 ;; Unsigned conversions from a smaller integer to a larger integer
2732 (define_insn "zero_extendqihi2"
2733 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
2735 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2741 [(set_attr "length" "4")
2742 (set_attr "type" "int,int,gload")])
2744 (define_insn "zero_extendqisi2"
2745 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
2747 (match_operand:QI 1 "gpr_or_memory_operand" "d,L,m")))]
2753 [(set_attr "length" "4")
2754 (set_attr "type" "int,int,gload")])
2756 ;;(define_insn "zero_extendqidi2"
2757 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2758 ;; (zero_extend:DI (match_operand:QI 1 "general_operand" "g")))]
2760 ;; "zero_extendqihi2 %0,%1"
2761 ;; [(set_attr "length" "4")])
2763 ;; Do not set the type for the sethi to "sethi", since the scheduler will think
2764 ;; the sethi takes 0 cycles as part of allowing sethi/setlo to be in the same
2765 ;; VLIW instruction.
2766 (define_insn "zero_extendhisi2"
2767 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
2768 (zero_extend:SI (match_operand:HI 1 "gpr_or_memory_operand" "0,m")))]
2773 [(set_attr "length" "4")
2774 (set_attr "type" "int,gload")])
2776 ;;(define_insn "zero_extendhidi2"
2777 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2778 ;; (zero_extend:DI (match_operand:HI 1 "general_operand" "g")))]
2780 ;; "zero_extendhihi2 %0,%1"
2781 ;; [(set_attr "length" "4")])
2783 ;;(define_insn "zero_extendsidi2"
2784 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2785 ;; (zero_extend:DI (match_operand:SI 1 "general_operand" "g")))]
2787 ;; "zero_extendsidi2 %0,%1"
2788 ;; [(set_attr "length" "4")])
2790 ;;;; Convert between floating point types of different sizes.
2792 ;;(define_insn "extendsfdf2"
2793 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2794 ;; (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
2796 ;; "extendsfdf2 %0,%1"
2797 ;; [(set_attr "length" "4")])
2799 ;;(define_insn "truncdfsf2"
2800 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2801 ;; (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
2803 ;; "truncdfsf2 %0,%1"
2804 ;; [(set_attr "length" "4")])
2806 ;;;; Convert between signed integer types and floating point.
2807 (define_insn "floatsisf2"
2808 [(set (match_operand:SF 0 "fpr_operand" "=f")
2809 (float:SF (match_operand:SI 1 "fpr_operand" "f")))]
2812 [(set_attr "length" "4")
2813 (set_attr "type" "fsconv")])
2815 (define_insn "floatsidf2"
2816 [(set (match_operand:DF 0 "fpr_operand" "=h")
2817 (float:DF (match_operand:SI 1 "fpr_operand" "f")))]
2818 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2820 [(set_attr "length" "4")
2821 (set_attr "type" "fdconv")])
2823 ;;(define_insn "floatdisf2"
2824 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2825 ;; (float:SF (match_operand:DI 1 "register_operand" "r")))]
2827 ;; "floatdisf2 %0,%1"
2828 ;; [(set_attr "length" "4")])
2830 ;;(define_insn "floatdidf2"
2831 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2832 ;; (float:DF (match_operand:DI 1 "register_operand" "r")))]
2834 ;; "floatdidf2 %0,%1"
2835 ;; [(set_attr "length" "4")])
2837 (define_insn "fix_truncsfsi2"
2838 [(set (match_operand:SI 0 "fpr_operand" "=f")
2839 (fix:SI (match_operand:SF 1 "fpr_operand" "f")))]
2842 [(set_attr "length" "4")
2843 (set_attr "type" "fsconv")])
2845 (define_insn "fix_truncdfsi2"
2846 [(set (match_operand:SI 0 "fpr_operand" "=f")
2847 (fix:SI (match_operand:DF 1 "fpr_operand" "h")))]
2848 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
2850 [(set_attr "length" "4")
2851 (set_attr "type" "fdconv")])
2853 ;;(define_insn "fix_truncsfdi2"
2854 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2855 ;; (fix:DI (match_operand:SF 1 "register_operand" "r")))]
2857 ;; "fix_truncsfdi2 %0,%1"
2858 ;; [(set_attr "length" "4")])
2860 ;;(define_insn "fix_truncdfdi2"
2861 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2862 ;; (fix:DI (match_operand:DF 1 "register_operand" "r")))]
2864 ;; "fix_truncdfdi2 %0,%1"
2865 ;; [(set_attr "length" "4")])
2867 ;;;; Convert between unsigned integer types and floating point.
2869 ;;(define_insn "floatunssisf2"
2870 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2871 ;; (unsigned_float:SF (match_operand:SI 1 "register_operand" "r")))]
2873 ;; "floatunssisf2 %0,%1"
2874 ;; [(set_attr "length" "4")])
2876 ;;(define_insn "floatunssidf2"
2877 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2878 ;; (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
2880 ;; "floatunssidf2 %0,%1"
2881 ;; [(set_attr "length" "4")])
2883 ;;(define_insn "floatunsdisf2"
2884 ;; [(set (match_operand:SF 0 "register_operand" "=r")
2885 ;; (unsigned_float:SF (match_operand:DI 1 "register_operand" "r")))]
2887 ;; "floatunsdisf2 %0,%1"
2888 ;; [(set_attr "length" "4")])
2890 ;;(define_insn "floatunsdidf2"
2891 ;; [(set (match_operand:DF 0 "register_operand" "=r")
2892 ;; (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
2894 ;; "floatunsdidf2 %0,%1"
2895 ;; [(set_attr "length" "4")])
2897 ;;(define_insn "fixuns_truncsfsi2"
2898 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2899 ;; (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
2901 ;; "fixuns_truncsfsi2 %0,%1"
2902 ;; [(set_attr "length" "4")])
2904 ;;(define_insn "fixuns_truncdfsi2"
2905 ;; [(set (match_operand:SI 0 "register_operand" "=r")
2906 ;; (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
2908 ;; "fixuns_truncdfsi2 %0,%1"
2909 ;; [(set_attr "length" "4")])
2911 ;;(define_insn "fixuns_truncsfdi2"
2912 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2913 ;; (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
2915 ;; "fixuns_truncsfdi2 %0,%1"
2916 ;; [(set_attr "length" "4")])
2918 ;;(define_insn "fixuns_truncdfdi2"
2919 ;; [(set (match_operand:DI 0 "register_operand" "=r")
2920 ;; (unsigned_fix:DI (match_operand:DF 1 "register_operand" "r")))]
2922 ;; "fixuns_truncdfdi2 %0,%1"
2923 ;; [(set_attr "length" "4")])
2926 ;; ::::::::::::::::::::
2928 ;; :: 32-bit Integer arithmetic
2930 ;; ::::::::::::::::::::
2933 (define_insn "addsi3"
2934 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2935 (plus:SI (match_operand:SI 1 "integer_register_operand" "%d")
2936 (match_operand:SI 2 "gpr_or_int12_operand" "dNOPQ")))]
2939 [(set_attr "length" "4")
2940 (set_attr "type" "int")])
2942 ;; Subtraction. No need to worry about constants, since the compiler
2943 ;; canonicalizes them into addsi3's. We prevent SUBREG's here to work around a
2944 ;; combine bug, that combines the 32x32->upper 32 bit multiply that uses a
2945 ;; SUBREG with a minus that shows up in modulus by constants.
2946 (define_insn "subsi3"
2947 [(set (match_operand:SI 0 "integer_register_operand" "=d")
2948 (minus:SI (match_operand:SI 1 "gpr_no_subreg_operand" "d")
2949 (match_operand:SI 2 "gpr_no_subreg_operand" "d")))]
2952 [(set_attr "length" "4")
2953 (set_attr "type" "int")])
2955 ;; Signed multiplication producing 64-bit results from 32-bit inputs
2956 ;; Note, frv doesn't have a 32x32->32 bit multiply, but the compiler
2957 ;; will do the 32x32->64 bit multiply and use the bottom word.
2958 (define_expand "mulsidi3"
2959 [(set (match_operand:DI 0 "integer_register_operand" "")
2960 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2961 (sign_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2965 if (GET_CODE (operands[2]) == CONST_INT)
2967 emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
2972 (define_insn "*mulsidi3_reg"
2973 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2974 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
2975 (sign_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
2978 [(set_attr "length" "4")
2979 (set_attr "type" "mul")])
2981 (define_insn "mulsidi3_const"
2982 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
2983 (mult:DI (sign_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
2984 (match_operand:SI 2 "int12_operand" "NOP")))]
2987 [(set_attr "length" "4")
2988 (set_attr "type" "mul")])
2990 ;; Unsigned multiplication producing 64-bit results from 32-bit inputs
2991 (define_expand "umulsidi3"
2992 [(set (match_operand:DI 0 "even_gpr_operand" "")
2993 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" ""))
2994 (zero_extend:DI (match_operand:SI 2 "gpr_or_int12_operand" ""))))]
2998 if (GET_CODE (operands[2]) == CONST_INT)
3000 emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
3005 (define_insn "*mulsidi3_reg"
3006 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3007 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "%d"))
3008 (zero_extend:DI (match_operand:SI 2 "integer_register_operand" "d"))))]
3011 [(set_attr "length" "4")
3012 (set_attr "type" "mul")])
3014 (define_insn "umulsidi3_const"
3015 [(set (match_operand:DI 0 "even_gpr_operand" "=e")
3016 (mult:DI (zero_extend:DI (match_operand:SI 1 "integer_register_operand" "d"))
3017 (match_operand:SI 2 "int12_operand" "NOP")))]
3020 [(set_attr "length" "4")
3021 (set_attr "type" "mul")])
3024 (define_insn "divsi3"
3025 [(set (match_operand:SI 0 "register_operand" "=d,d")
3026 (div:SI (match_operand:SI 1 "register_operand" "d,d")
3027 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3030 [(set_attr "length" "4")
3031 (set_attr "type" "div")])
3033 ;; Unsigned Division
3034 (define_insn "udivsi3"
3035 [(set (match_operand:SI 0 "register_operand" "=d,d")
3036 (udiv:SI (match_operand:SI 1 "register_operand" "d,d")
3037 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3040 [(set_attr "length" "4")
3041 (set_attr "type" "div")])
3044 (define_insn "negsi2"
3045 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3046 (neg:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3049 [(set_attr "length" "4")
3050 (set_attr "type" "int")])
3052 ;; Find first one bit
3053 ;; (define_insn "ffssi2"
3054 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3055 ;; (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
3058 ;; [(set_attr "length" "4")])
3061 ;; ::::::::::::::::::::
3063 ;; :: 64-bit Integer arithmetic
3065 ;; ::::::::::::::::::::
3068 (define_insn_and_split "adddi3"
3069 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3070 (plus:DI (match_operand:DI 1 "integer_register_operand" "%e,0")
3071 (match_operand:DI 2 "gpr_or_int10_operand" "eJ,eJ")))
3072 (clobber (match_scratch:CC 3 "=t,t"))]
3083 for (op = 0; op < 3; op++)
3084 for (part = 0; part < 2; part++)
3085 parts[op][part] = simplify_gen_subreg (SImode, operands[op],
3086 DImode, part * UNITS_PER_WORD);
3088 operands[4] = gen_adddi3_lower (parts[0][1], parts[1][1], parts[2][1],
3090 operands[5] = gen_adddi3_upper (parts[0][0], parts[1][0], parts[2][0],
3091 copy_rtx (operands[3]));
3093 [(set_attr "length" "8")
3094 (set_attr "type" "multi")])
3096 ;; Subtraction No need to worry about constants, since the compiler
3097 ;; canonicalizes them into adddi3's.
3098 (define_insn_and_split "subdi3"
3099 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e,e")
3100 (minus:DI (match_operand:DI 1 "integer_register_operand" "e,0,e")
3101 (match_operand:DI 2 "integer_register_operand" "e,e,0")))
3102 (clobber (match_scratch:CC 3 "=t,t,t"))]
3110 rtx op0_high = gen_highpart (SImode, operands[0]);
3111 rtx op1_high = gen_highpart (SImode, operands[1]);
3112 rtx op2_high = gen_highpart (SImode, operands[2]);
3113 rtx op0_low = gen_lowpart (SImode, operands[0]);
3114 rtx op1_low = gen_lowpart (SImode, operands[1]);
3115 rtx op2_low = gen_lowpart (SImode, operands[2]);
3116 rtx op3 = operands[3];
3118 operands[4] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3119 operands[5] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3121 [(set_attr "length" "8")
3122 (set_attr "type" "multi")])
3124 ;; Patterns for addsi3/subdi3 after splitting
3125 (define_insn "adddi3_lower"
3126 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3127 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3128 (match_operand:SI 2 "gpr_or_int10_operand" "dJ")))
3129 (set (match_operand:CC 3 "icc_operand" "=t")
3130 (compare:CC (plus:SI (match_dup 1)
3134 "add%I2cc %1,%2,%0,%3"
3135 [(set_attr "length" "4")
3136 (set_attr "type" "int")])
3138 (define_insn "adddi3_upper"
3139 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3140 (plus:SI (match_operand:SI 1 "integer_register_operand" "d")
3141 (plus:SI (match_operand:SI 2 "gpr_or_int10_operand" "dJ")
3142 (match_operand:CC 3 "icc_operand" "t"))))]
3144 "addx%I2 %1,%2,%0,%3"
3145 [(set_attr "length" "4")
3146 (set_attr "type" "int")])
3148 (define_insn "subdi3_lower"
3149 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3150 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3151 (match_operand:SI 2 "integer_register_operand" "d")))
3152 (set (match_operand:CC 3 "icc_operand" "=t")
3153 (compare:CC (plus:SI (match_dup 1)
3158 [(set_attr "length" "4")
3159 (set_attr "type" "int")])
3161 (define_insn "subdi3_upper"
3162 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3163 (minus:SI (match_operand:SI 1 "integer_register_operand" "d")
3164 (minus:SI (match_operand:SI 2 "integer_register_operand" "d")
3165 (match_operand:CC 3 "icc_operand" "t"))))]
3168 [(set_attr "length" "4")
3169 (set_attr "type" "int")])
3171 (define_insn_and_split "negdi2"
3172 [(set (match_operand:DI 0 "integer_register_operand" "=&e,e")
3173 (neg:DI (match_operand:DI 1 "integer_register_operand" "e,0")))
3174 (clobber (match_scratch:CC 2 "=t,t"))]
3182 rtx op0_high = gen_highpart (SImode, operands[0]);
3183 rtx op1_high = gen_rtx_REG (SImode, GPR_FIRST);
3184 rtx op2_high = gen_highpart (SImode, operands[1]);
3185 rtx op0_low = gen_lowpart (SImode, operands[0]);
3186 rtx op1_low = op1_high;
3187 rtx op2_low = gen_lowpart (SImode, operands[1]);
3188 rtx op3 = operands[2];
3190 operands[3] = gen_subdi3_lower (op0_low, op1_low, op2_low, op3);
3191 operands[4] = gen_subdi3_upper (op0_high, op1_high, op2_high, op3);
3193 [(set_attr "length" "8")
3194 (set_attr "type" "multi")])
3196 ;; Multiplication (same size)
3197 ;; (define_insn "muldi3"
3198 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3199 ;; (mult:DI (match_operand:DI 1 "register_operand" "%r")
3200 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3202 ;; "muldi3 %0,%1,%2"
3203 ;; [(set_attr "length" "4")])
3206 ;; (define_insn "divdi3"
3207 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3208 ;; (div:DI (match_operand:DI 1 "register_operand" "r")
3209 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3211 ;; "divdi3 %0,%1,%2"
3212 ;; [(set_attr "length" "4")])
3214 ;; Undsgned Division
3215 ;; (define_insn "udivdi3"
3216 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3217 ;; (udiv:DI (match_operand:DI 1 "register_operand" "r")
3218 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3220 ;; "udivdi3 %0,%1,%2"
3221 ;; [(set_attr "length" "4")])
3224 ;; (define_insn "negdi2"
3225 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3226 ;; (neg:DI (match_operand:DI 1 "register_operand" "r")))]
3229 ;; [(set_attr "length" "4")])
3231 ;; Find first one bit
3232 ;; (define_insn "ffsdi2"
3233 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3234 ;; (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
3237 ;; [(set_attr "length" "4")])
3240 ;; ::::::::::::::::::::
3242 ;; :: 32-bit floating point arithmetic
3244 ;; ::::::::::::::::::::
3247 (define_insn "addsf3"
3248 [(set (match_operand:SF 0 "fpr_operand" "=f")
3249 (plus:SF (match_operand:SF 1 "fpr_operand" "%f")
3250 (match_operand:SF 2 "fpr_operand" "f")))]
3253 [(set_attr "length" "4")
3254 (set_attr "type" "fsadd")])
3257 (define_insn "subsf3"
3258 [(set (match_operand:SF 0 "fpr_operand" "=f")
3259 (minus:SF (match_operand:SF 1 "fpr_operand" "f")
3260 (match_operand:SF 2 "fpr_operand" "f")))]
3263 [(set_attr "length" "4")
3264 (set_attr "type" "fsadd")])
3267 (define_insn "mulsf3"
3268 [(set (match_operand:SF 0 "fpr_operand" "=f")
3269 (mult:SF (match_operand:SF 1 "fpr_operand" "%f")
3270 (match_operand:SF 2 "fpr_operand" "f")))]
3273 [(set_attr "length" "4")
3274 (set_attr "type" "fsmul")])
3276 ;; Multiplication with addition/subtraction
3277 (define_insn "fmasf4"
3278 [(set (match_operand:SF 0 "fpr_operand" "=f")
3279 (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3280 (match_operand:SF 2 "fpr_operand" "f")
3281 (match_operand:SF 3 "fpr_operand" "0")))]
3282 "TARGET_HARD_FLOAT && TARGET_MULADD"
3284 [(set_attr "length" "4")
3285 (set_attr "type" "fsmadd")])
3287 (define_insn "fmssf4"
3288 [(set (match_operand:SF 0 "fpr_operand" "=f")
3289 (fma:SF (match_operand:SF 1 "fpr_operand" "f")
3290 (match_operand:SF 2 "fpr_operand" "f")
3291 (neg:SF (match_operand:SF 3 "fpr_operand" "0"))))]
3292 "TARGET_HARD_FLOAT && TARGET_MULADD"
3294 [(set_attr "length" "4")
3295 (set_attr "type" "fsmadd")])
3298 (define_insn "divsf3"
3299 [(set (match_operand:SF 0 "fpr_operand" "=f")
3300 (div:SF (match_operand:SF 1 "fpr_operand" "f")
3301 (match_operand:SF 2 "fpr_operand" "f")))]
3304 [(set_attr "length" "4")
3305 (set_attr "type" "fsdiv")])
3308 (define_insn "negsf2"
3309 [(set (match_operand:SF 0 "fpr_operand" "=f")
3310 (neg:SF (match_operand:SF 1 "fpr_operand" "f")))]
3313 [(set_attr "length" "4")
3314 (set_attr "type" "fsconv")])
3317 (define_insn "abssf2"
3318 [(set (match_operand:SF 0 "fpr_operand" "=f")
3319 (abs:SF (match_operand:SF 1 "fpr_operand" "f")))]
3322 [(set_attr "length" "4")
3323 (set_attr "type" "fsconv")])
3326 (define_insn "sqrtsf2"
3327 [(set (match_operand:SF 0 "fpr_operand" "=f")
3328 (sqrt:SF (match_operand:SF 1 "fpr_operand" "f")))]
3331 [(set_attr "length" "4")
3332 (set_attr "type" "sqrt_single")])
3335 ;; ::::::::::::::::::::
3337 ;; :: 64-bit floating point arithmetic
3339 ;; ::::::::::::::::::::
3342 (define_insn "adddf3"
3343 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3344 (plus:DF (match_operand:DF 1 "fpr_operand" "%h")
3345 (match_operand:DF 2 "fpr_operand" "h")))]
3346 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3348 [(set_attr "length" "4")
3349 (set_attr "type" "fdadd")])
3352 (define_insn "subdf3"
3353 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3354 (minus:DF (match_operand:DF 1 "fpr_operand" "h")
3355 (match_operand:DF 2 "fpr_operand" "h")))]
3356 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3358 [(set_attr "length" "4")
3359 (set_attr "type" "fdadd")])
3362 (define_insn "muldf3"
3363 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3364 (mult:DF (match_operand:DF 1 "fpr_operand" "%h")
3365 (match_operand:DF 2 "fpr_operand" "h")))]
3366 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3368 [(set_attr "length" "4")
3369 (set_attr "type" "fdmul")])
3371 ;; Multiplication with addition/subtraction
3372 (define_insn "*muladddf4"
3373 [(set (match_operand:DF 0 "fpr_operand" "=f")
3374 (plus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3375 (match_operand:DF 2 "fpr_operand" "f"))
3376 (match_operand:DF 3 "fpr_operand" "0")))]
3377 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3379 [(set_attr "length" "4")
3380 (set_attr "type" "fdmadd")])
3382 (define_insn "*mulsubdf4"
3383 [(set (match_operand:DF 0 "fpr_operand" "=f")
3384 (minus:DF (mult:DF (match_operand:DF 1 "fpr_operand" "%f")
3385 (match_operand:DF 2 "fpr_operand" "f"))
3386 (match_operand:DF 3 "fpr_operand" "0")))]
3387 "TARGET_HARD_FLOAT && TARGET_DOUBLE && TARGET_MULADD"
3389 [(set_attr "length" "4")
3390 (set_attr "type" "fdmadd")])
3393 (define_insn "divdf3"
3394 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3395 (div:DF (match_operand:DF 1 "fpr_operand" "h")
3396 (match_operand:DF 2 "fpr_operand" "h")))]
3397 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3399 [(set_attr "length" "4")
3400 (set_attr "type" "fddiv")])
3403 (define_insn "negdf2"
3404 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3405 (neg:DF (match_operand:DF 1 "fpr_operand" "h")))]
3406 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3408 [(set_attr "length" "4")
3409 (set_attr "type" "fdconv")])
3412 (define_insn "absdf2"
3413 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3414 (abs:DF (match_operand:DF 1 "fpr_operand" "h")))]
3415 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3417 [(set_attr "length" "4")
3418 (set_attr "type" "fdconv")])
3421 (define_insn "sqrtdf2"
3422 [(set (match_operand:DF 0 "even_fpr_operand" "=h")
3423 (sqrt:DF (match_operand:DF 1 "fpr_operand" "h")))]
3424 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3426 [(set_attr "length" "4")
3427 (set_attr "type" "sqrt_double")])
3430 ;; ::::::::::::::::::::
3432 ;; :: 32-bit Integer Shifts and Rotates
3434 ;; ::::::::::::::::::::
3436 ;; Arithmetic Shift Left
3437 (define_insn "ashlsi3"
3438 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3439 (ashift:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3440 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3443 [(set_attr "length" "4")
3444 (set_attr "type" "int")])
3446 ;; Arithmetic Shift Right
3447 (define_insn "ashrsi3"
3448 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3449 (ashiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3450 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3453 [(set_attr "length" "4")
3454 (set_attr "type" "int")])
3456 ;; Logical Shift Right
3457 (define_insn "lshrsi3"
3458 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
3459 (lshiftrt:SI (match_operand:SI 1 "integer_register_operand" "d,d")
3460 (match_operand:SI 2 "gpr_or_int12_operand" "d,NOP")))]
3463 [(set_attr "length" "4")
3464 (set_attr "type" "int")])
3467 ;; (define_insn "rotlsi3"
3468 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3469 ;; (rotate:SI (match_operand:SI 1 "register_operand" "r")
3470 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3472 ;; "rotlsi3 %0,%1,%2"
3473 ;; [(set_attr "length" "4")])
3476 ;; (define_insn "rotrsi3"
3477 ;; [(set (match_operand:SI 0 "register_operand" "=r")
3478 ;; (rotatert:SI (match_operand:SI 1 "register_operand" "r")
3479 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3481 ;; "rotrsi3 %0,%1,%2"
3482 ;; [(set_attr "length" "4")])
3485 ;; ::::::::::::::::::::
3487 ;; :: 64-bit Integer Shifts and Rotates
3489 ;; ::::::::::::::::::::
3491 ;; Arithmetic Shift Left
3492 ;; (define_insn "ashldi3"
3493 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3494 ;; (ashift:DI (match_operand:DI 1 "register_operand" "r")
3495 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3497 ;; "ashldi3 %0,%1,%2"
3498 ;; [(set_attr "length" "4")])
3500 ;; Arithmetic Shift Right
3501 ;; (define_insn "ashrdi3"
3502 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3503 ;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
3504 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3506 ;; "ashrdi3 %0,%1,%2"
3507 ;; [(set_attr "length" "4")])
3509 ;; Logical Shift Right
3510 ;; (define_insn "lshrdi3"
3511 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3512 ;; (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
3513 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3515 ;; "lshrdi3 %0,%1,%2"
3516 ;; [(set_attr "length" "4")])
3519 ;; (define_insn "rotldi3"
3520 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3521 ;; (rotate:DI (match_operand:DI 1 "register_operand" "r")
3522 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3524 ;; "rotldi3 %0,%1,%2"
3525 ;; [(set_attr "length" "4")])
3528 ;; (define_insn "rotrdi3"
3529 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3530 ;; (rotatert:DI (match_operand:DI 1 "register_operand" "r")
3531 ;; (match_operand:SI 2 "nonmemory_operand" "ri")))]
3533 ;; "rotrdi3 %0,%1,%2"
3534 ;; [(set_attr "length" "4")])
3537 ;; ::::::::::::::::::::
3539 ;; :: 32-Bit Integer Logical operations
3541 ;; ::::::::::::::::::::
3543 ;; Logical AND, 32-bit integers
3544 (define_insn "andsi3_media"
3545 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3546 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3547 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3552 [(set_attr "length" "4")
3553 (set_attr "type" "int,mlogic")])
3555 (define_insn "andsi3_nomedia"
3556 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3557 (and:SI (match_operand:SI 1 "integer_register_operand" "%d")
3558 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3561 [(set_attr "length" "4")
3562 (set_attr "type" "int")])
3564 (define_expand "andsi3"
3565 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3566 (and:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3567 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3571 ;; Inclusive OR, 32-bit integers
3572 (define_insn "iorsi3_media"
3573 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3574 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3575 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3580 [(set_attr "length" "4")
3581 (set_attr "type" "int,mlogic")])
3583 (define_insn "iorsi3_nomedia"
3584 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3585 (ior:SI (match_operand:SI 1 "integer_register_operand" "%d")
3586 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3589 [(set_attr "length" "4")
3590 (set_attr "type" "int")])
3592 (define_expand "iorsi3"
3593 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3594 (ior:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3595 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3599 ;; Exclusive OR, 32-bit integers
3600 (define_insn "xorsi3_media"
3601 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3602 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "%d,f")
3603 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "dNOP,f")))]
3608 [(set_attr "length" "4")
3609 (set_attr "type" "int,mlogic")])
3611 (define_insn "xorsi3_nomedia"
3612 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3613 (xor:SI (match_operand:SI 1 "integer_register_operand" "%d")
3614 (match_operand:SI 2 "gpr_or_int12_operand" "dNOP")))]
3617 [(set_attr "length" "4")
3618 (set_attr "type" "int")])
3620 (define_expand "xorsi3"
3621 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3622 (xor:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")
3623 (match_operand:SI 2 "gpr_fpr_or_int12_operand" "")))]
3627 ;; One's complement, 32-bit integers
3628 (define_insn "one_cmplsi2_media"
3629 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "=d,f")
3630 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "d,f")))]
3635 [(set_attr "length" "4")
3636 (set_attr "type" "int,mlogic")])
3638 (define_insn "one_cmplsi2_nomedia"
3639 [(set (match_operand:SI 0 "integer_register_operand" "=d")
3640 (not:SI (match_operand:SI 1 "integer_register_operand" "d")))]
3643 [(set_attr "length" "4")
3644 (set_attr "type" "int")])
3646 (define_expand "one_cmplsi2"
3647 [(set (match_operand:SI 0 "gpr_or_fpr_operand" "")
3648 (not:SI (match_operand:SI 1 "gpr_or_fpr_operand" "")))]
3653 ;; ::::::::::::::::::::
3655 ;; :: 64-Bit Integer Logical operations
3657 ;; ::::::::::::::::::::
3659 ;; Logical AND, 64-bit integers
3660 ;; (define_insn "anddi3"
3661 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3662 ;; (and:DI (match_operand:DI 1 "register_operand" "%r")
3663 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3665 ;; "anddi3 %0,%1,%2"
3666 ;; [(set_attr "length" "4")])
3668 ;; Inclusive OR, 64-bit integers
3669 ;; (define_insn "iordi3"
3670 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3671 ;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
3672 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3674 ;; "iordi3 %0,%1,%2"
3675 ;; [(set_attr "length" "4")])
3677 ;; Exclusive OR, 64-bit integers
3678 ;; (define_insn "xordi3"
3679 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3680 ;; (xor:DI (match_operand:DI 1 "register_operand" "%r")
3681 ;; (match_operand:DI 2 "nonmemory_operand" "ri")))]
3683 ;; "xordi3 %0,%1,%2"
3684 ;; [(set_attr "length" "4")])
3686 ;; One's complement, 64-bit integers
3687 ;; (define_insn "one_cmpldi2"
3688 ;; [(set (match_operand:DI 0 "register_operand" "=r")
3689 ;; (not:DI (match_operand:DI 1 "register_operand" "r")))]
3692 ;; [(set_attr "length" "4")])
3695 ;; ::::::::::::::::::::
3697 ;; :: Combination of integer operation with comparison
3699 ;; ::::::::::::::::::::
3701 (define_insn "*combo_intop_compare1"
3702 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3704 (match_operator:SI 1 "intop_compare_operator"
3705 [(match_operand:SI 2 "integer_register_operand" "d")
3706 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3709 "%O1%I3cc %2, %3, %., %0"
3710 [(set_attr "type" "int")
3711 (set_attr "length" "4")])
3713 (define_insn "*combo_intop_compare2"
3714 [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
3716 (match_operator:SI 1 "intop_compare_operator"
3717 [(match_operand:SI 2 "integer_register_operand" "d")
3718 (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
3720 (set (match_operand:SI 4 "integer_register_operand" "=d")
3721 (match_operator:SI 5 "intop_compare_operator"
3724 "GET_CODE (operands[1]) == GET_CODE (operands[5])"
3725 "%O1%I3cc %2, %3, %4, %0"
3726 [(set_attr "type" "int")
3727 (set_attr "length" "4")])
3729 ;; ::::::::::::::::::::
3733 ;; ::::::::::::::::::::
3735 ;; The comparisons are generated by the branch and/or scc operations
3737 (define_insn "cmpsi_cc"
3738 [(set (match_operand:CC 0 "icc_operand" "=t,t")
3739 (compare:CC (match_operand:SI 1 "integer_register_operand" "d,d")
3740 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3743 [(set_attr "length" "4")
3744 (set_attr "type" "int")])
3746 (define_insn "*cmpsi_cc_uns"
3747 [(set (match_operand:CC_UNS 0 "icc_operand" "=t,t")
3748 (compare:CC_UNS (match_operand:SI 1 "integer_register_operand" "d,d")
3749 (match_operand:SI 2 "gpr_or_int10_operand" "d,J")))]
3752 [(set_attr "length" "4")
3753 (set_attr "type" "int")])
3755 ;; The only requirement for a CC_NZmode GPR or memory value is that
3756 ;; comparing it against zero must set the Z and N flags appropriately.
3757 ;; The source operand is therefore a valid CC_NZmode value.
3758 (define_insn "*cmpsi_cc_nz"
3759 [(set (match_operand:CC_NZ 0 "nonimmediate_operand" "=t,d,m")
3760 (compare:CC_NZ (match_operand:SI 1 "integer_register_operand" "d,d,d")
3767 [(set_attr "length" "4,4,4")
3768 (set_attr "type" "int,int,gstore")])
3770 (define_insn "*cmpsf_cc_fp"
3771 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3772 (compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
3773 (match_operand:SF 2 "fpr_operand" "f")))]
3776 [(set_attr "length" "4")
3777 (set_attr "type" "fscmp")])
3779 (define_insn "*cmpdf_cc_fp"
3780 [(set (match_operand:CC_FP 0 "fcc_operand" "=u")
3781 (compare:CC_FP (match_operand:DF 1 "even_fpr_operand" "h")
3782 (match_operand:DF 2 "even_fpr_operand" "h")))]
3783 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3785 [(set_attr "length" "4")
3786 (set_attr "type" "fdcmp")])
3789 ;; ::::::::::::::::::::
3793 ;; ::::::::::::::::::::
3795 ;; Define_expands called by the machine independent part of the compiler
3796 ;; to allocate a new comparison register.
3798 (define_expand "cbranchdf4"
3799 [(use (match_operator 0 "ordered_comparison_operator"
3800 [(match_operand:DF 1 "fpr_operand" "")
3801 (match_operand:DF 2 "fpr_operand" "")]))
3802 (use (match_operand 3 ""))]
3803 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3804 { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3806 (define_expand "cbranchsf4"
3807 [(use (match_operator 0 "ordered_comparison_operator"
3808 [(match_operand:SF 1 "fpr_operand" "")
3809 (match_operand:SF 2 "fpr_operand" "")]))
3810 (use (match_operand 3 ""))]
3812 { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3814 (define_expand "cbranchsi4"
3815 [(use (match_operator 0 "ordered_comparison_operator"
3816 [(match_operand:SI 1 "integer_register_operand" "")
3817 (match_operand:SI 2 "gpr_or_int10_operand" "")]))
3818 (use (match_operand 3 ""))]
3820 { if (frv_emit_cond_branch (operands)) DONE; gcc_unreachable (); })
3822 ;; Actual branches. We must allow for the (label_ref) and the (pc) to be
3823 ;; swapped. If they are swapped, it reverses the sense of the branch.
3825 ;; Note - unlike the define expands above, these patterns can be amalgamated
3826 ;; into one pattern for branch-if-true and one for branch-if-false. This does
3827 ;; require an operand operator to select the correct branch mnemonic.
3829 ;; If a fixed condition code register is being used, (as opposed to, say,
3830 ;; using cc0), then the expands could look like this:
3832 ;; (define_insn "*branch_true"
3834 ;; (if_then_else (match_operator:CC 0 "comparison_operator"
3835 ;; [(reg:CC <number_of_CC_register>)
3837 ;; (label_ref (match_operand 1 "" ""))
3841 ;; [(set_attr "length" "4")]
3844 ;; In the above example the %B is a directive to frv_print_operand()
3845 ;; to decode and print the correct branch mnemonic.
3847 (define_insn "*branch_int_true"
3849 (if_then_else (match_operator 0 "integer_relational_operator"
3850 [(match_operand 1 "icc_operand" "t")
3852 (label_ref (match_operand 2 "" ""))
3857 if (get_attr_length (insn) == 4)
3858 return \"b%c0 %1,%#,%l2\";
3860 return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
3862 [(set (attr "length")
3864 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3865 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3868 (set (attr "far_jump")
3870 (eq_attr "length" "4")
3872 (const_string "yes")))
3875 (eq_attr "length" "4")
3876 (const_string "branch")
3877 (const_string "multi")))])
3879 (define_insn "*branch_int_false"
3881 (if_then_else (match_operator 0 "integer_relational_operator"
3882 [(match_operand 1 "icc_operand" "t")
3885 (label_ref (match_operand 2 "" ""))))]
3889 if (get_attr_length (insn) == 4)
3890 return \"b%C0 %1,%#,%l2\";
3892 return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
3894 [(set (attr "length")
3896 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3897 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3900 (set (attr "far_jump")
3902 (eq_attr "length" "4")
3904 (const_string "yes")))
3907 (eq_attr "length" "4")
3908 (const_string "branch")
3909 (const_string "multi")))])
3911 (define_insn "*branch_fp_true"
3913 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3914 [(match_operand 1 "fcc_operand" "u")
3916 (label_ref (match_operand 2 "" ""))
3921 if (get_attr_length (insn) == 4)
3922 return \"fb%f0 %1,%#,%l2\";
3924 return \"fb%F0 %1,%#,1f\;call %l2\\n1:\";
3926 [(set (attr "length")
3928 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3929 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3932 (set (attr "far_jump")
3934 (eq_attr "length" "4")
3936 (const_string "yes")))
3939 (eq_attr "length" "4")
3940 (const_string "branch")
3941 (const_string "multi")))])
3943 (define_insn "*branch_fp_false"
3945 (if_then_else (match_operator:CC_FP 0 "float_relational_operator"
3946 [(match_operand 1 "fcc_operand" "u")
3949 (label_ref (match_operand 2 "" ""))))]
3953 if (get_attr_length (insn) == 4)
3954 return \"fb%F0 %1,%#,%l2\";
3956 return \"fb%f0 %1,%#,1f\;call %l2\\n1:\";
3958 [(set (attr "length")
3960 (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
3961 (le (minus (match_dup 2) (pc)) (const_int 32764)))
3964 (set (attr "far_jump")
3966 (eq_attr "length" "4")
3968 (const_string "yes")))
3971 (eq_attr "length" "4")
3972 (const_string "branch")
3973 (const_string "multi")))])
3976 ;; ::::::::::::::::::::
3978 ;; :: Set flag operations
3980 ;; ::::::::::::::::::::
3982 ;; Define_expands called by the machine independent part of the compiler
3983 ;; to allocate a new comparison register
3985 (define_expand "cstoredf4"
3986 [(use (match_operator:SI 1 "ordered_comparison_operator"
3987 [(match_operand:DF 2 "fpr_operand")
3988 (match_operand:DF 3 "fpr_operand")]))
3989 (clobber (match_operand:SI 0 "register_operand"))]
3990 "TARGET_HARD_FLOAT && TARGET_DOUBLE"
3991 { if (frv_emit_scc (operands)) DONE; else FAIL; })
3993 (define_expand "cstoresf4"
3994 [(use (match_operator:SI 1 "ordered_comparison_operator"
3995 [(match_operand:SF 2 "fpr_operand")
3996 (match_operand:SF 3 "fpr_operand")]))
3997 (clobber (match_operand:SI 0 "register_operand"))]
3999 { if (frv_emit_scc (operands)) DONE; else FAIL; })
4001 (define_expand "cstoresi4"
4002 [(use (match_operator:SI 1 "ordered_comparison_operator"
4003 [(match_operand:SI 2 "integer_register_operand")
4004 (match_operand:SI 3 "gpr_or_int10_operand")]))
4005 (clobber (match_operand:SI 0 "register_operand"))]
4007 { if (frv_emit_scc (operands)) DONE; else FAIL; })
4009 (define_insn "*scc_int"
4010 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4011 (match_operator:SI 1 "integer_relational_operator"
4012 [(match_operand 2 "icc_operand" "t")
4014 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4017 [(set_attr "length" "12")
4018 (set_attr "type" "multi")])
4020 (define_insn "*scc_float"
4021 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4022 (match_operator:SI 1 "float_relational_operator"
4023 [(match_operand:CC_FP 2 "fcc_operand" "u")
4025 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4028 [(set_attr "length" "12")
4029 (set_attr "type" "multi")])
4031 ;; XXX -- add reload_completed to the splits, because register allocation
4032 ;; currently isn't ready to see cond_exec packets.
4034 [(set (match_operand:SI 0 "integer_register_operand" "")
4035 (match_operator:SI 1 "relational_operator"
4036 [(match_operand 2 "cc_operand" "")
4038 (clobber (match_operand 3 "cr_operand" ""))]
4041 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4042 operands[3], (HOST_WIDE_INT) 1);")
4044 (define_insn "*scc_neg1_int"
4045 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4046 (neg:SI (match_operator:SI 1 "integer_relational_operator"
4047 [(match_operand 2 "icc_operand" "t")
4049 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
4052 [(set_attr "length" "12")
4053 (set_attr "type" "multi")])
4055 (define_insn "*scc_neg1_float"
4056 [(set (match_operand:SI 0 "integer_register_operand" "=d")
4057 (neg:SI (match_operator:SI 1 "float_relational_operator"
4058 [(match_operand:CC_FP 2 "fcc_operand" "u")
4060 (clobber (match_operand:CC_CCR 3 "fcr_operand" "=w"))]
4063 [(set_attr "length" "12")
4064 (set_attr "type" "multi")])
4067 [(set (match_operand:SI 0 "integer_register_operand" "")
4068 (neg:SI (match_operator:SI 1 "relational_operator"
4069 [(match_operand 2 "cc_operand" "")
4071 (clobber (match_operand 3 "cr_operand" ""))]
4074 "operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
4075 operands[3], (HOST_WIDE_INT) -1);")
4078 ;; ::::::::::::::::::::
4080 ;; :: Conditionally executed instructions
4082 ;; ::::::::::::::::::::
4084 ;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
4085 (define_insn "*ck_signed"
4086 [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
4087 (match_operator:CC_CCR 1 "integer_relational_operator"
4088 [(match_operand 2 "icc_operand" "t")
4092 [(set_attr "length" "4")
4093 (set_attr "type" "ccr")])
4095 (define_insn "*fck_float"
4096 [(set (match_operand:CC_CCR 0 "fcr_operand" "=w")
4097 (match_operator:CC_CCR 1 "float_relational_operator"
4098 [(match_operand:CC_FP 2 "fcc_operand" "u")
4102 [(set_attr "length" "4")
4103 (set_attr "type" "ccr")])
4105 ;; Conditionally convert ICC/FCC comparison into CCR bits to provide && and ||
4106 ;; tests in conditional execution
4107 (define_insn "cond_exec_ck"
4108 [(set (match_operand:CC_CCR 0 "cr_operand" "=v,w")
4109 (if_then_else:CC_CCR (match_operator 1 "ccr_eqne_operator"
4110 [(match_operand 2 "cr_operand" "C,C")
4112 (match_operator 3 "relational_operator"
4113 [(match_operand 4 "cc_operand" "t,u")
4118 cck%c3 %4, %0, %2, %e1
4119 cfck%f3 %4, %0, %2, %e1"
4120 [(set_attr "length" "4")
4121 (set_attr "type" "ccr")])
4123 ;; Conditionally set a register to either 0 or another register
4124 (define_insn "*cond_exec_movqi"
4126 (match_operator 0 "ccr_eqne_operator"
4127 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4129 (set (match_operand:QI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4130 (match_operand:QI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4131 "register_operand(operands[2], QImode) || reg_or_0_operand (operands[3], QImode)"
4132 "* return output_condmove_single (operands, insn);"
4133 [(set_attr "length" "4")
4134 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4136 (define_insn "*cond_exec_movhi"
4138 (match_operator 0 "ccr_eqne_operator"
4139 [(match_operand 1 "cr_operand" "C,C,C,C,C,C")
4141 (set (match_operand:HI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d")
4142 (match_operand:HI 3 "condexec_source_operand" "dO,U,dO,f,d,f")))]
4143 "register_operand(operands[2], HImode) || reg_or_0_operand (operands[3], HImode)"
4144 "* return output_condmove_single (operands, insn);"
4145 [(set_attr "length" "4")
4146 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg")])
4148 (define_insn "*cond_exec_movsi"
4150 (match_operator 0 "ccr_eqne_operator"
4151 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C")
4153 (set (match_operand:SI 2 "condexec_dest_operand" "=d,d,U,?f,?f,?d,?f,?m")
4154 (match_operand:SI 3 "condexec_source_operand" "dO,U,dO,f,d,f,m,f")))]
4155 "register_operand(operands[2], SImode) || reg_or_0_operand (operands[3], SImode)"
4156 "* return output_condmove_single (operands, insn);"
4157 [(set_attr "length" "4")
4158 (set_attr "type" "int,gload,gstore,fsconv,movgf,movfg,fload,fstore")])
4161 (define_insn "*cond_exec_movsf_has_fprs"
4163 (match_operator 0 "ccr_eqne_operator"
4164 [(match_operand 1 "cr_operand" "C,C,C,C,C,C,C,C,C,C")
4166 (set (match_operand:SF 2 "condexec_dest_operand" "=f,?d,?d,?f,f,f,?d,U,?U,U")
4167 (match_operand:SF 3 "condexec_source_operand" "f,d,f,d,G,U,U,f,d,G")))]
4169 "* return output_condmove_single (operands, insn);"
4170 [(set_attr "length" "4")
4171 (set_attr "type" "fsconv,int,movgf,movfg,movgf,fload,gload,fstore,gstore,gstore")])
4173 (define_insn "*cond_exec_movsf_no_fprs"
4175 (match_operator 0 "ccr_eqne_operator"
4176 [(match_operand 1 "cr_operand" "C,C,C")
4178 (set (match_operand:SF 2 "condexec_dest_operand" "=d,d,U")
4179 (match_operand:SF 3 "condexec_source_operand" "d,U,dG")))]
4181 "* return output_condmove_single (operands, insn);"
4182 [(set_attr "length" "4")
4183 (set_attr "type" "int,gload,gstore")])
4185 (define_insn "*cond_exec_si_binary1"
4187 (match_operator 0 "ccr_eqne_operator"
4188 [(match_operand 1 "cr_operand" "C")
4190 (set (match_operand:SI 2 "integer_register_operand" "=d")
4191 (match_operator:SI 3 "condexec_si_binary_operator"
4192 [(match_operand:SI 4 "integer_register_operand" "d")
4193 (match_operand:SI 5 "integer_register_operand" "d")])))]
4197 switch (GET_CODE (operands[3]))
4199 case PLUS: return \"cadd %4, %z5, %2, %1, %e0\";
4200 case MINUS: return \"csub %4, %z5, %2, %1, %e0\";
4201 case AND: return \"cand %4, %z5, %2, %1, %e0\";
4202 case IOR: return \"cor %4, %z5, %2, %1, %e0\";
4203 case XOR: return \"cxor %4, %z5, %2, %1, %e0\";
4204 case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
4205 case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
4206 case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
4207 default: gcc_unreachable ();
4210 [(set_attr "length" "4")
4211 (set_attr "type" "int")])
4213 (define_insn "*cond_exec_si_binary2"
4215 (match_operator 0 "ccr_eqne_operator"
4216 [(match_operand 1 "cr_operand" "C")
4218 (set (match_operand:SI 2 "fpr_operand" "=f")
4219 (match_operator:SI 3 "condexec_si_media_operator"
4220 [(match_operand:SI 4 "fpr_operand" "f")
4221 (match_operand:SI 5 "fpr_operand" "f")])))]
4225 switch (GET_CODE (operands[3]))
4227 case AND: return \"cmand %4, %5, %2, %1, %e0\";
4228 case IOR: return \"cmor %4, %5, %2, %1, %e0\";
4229 case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
4230 default: gcc_unreachable ();
4233 [(set_attr "length" "4")
4234 (set_attr "type" "mlogic")])
4236 ;; Note, flow does not (currently) know how to handle an operation that uses
4237 ;; only part of the hard registers allocated for a multiregister value, such as
4238 ;; DImode in this case if the user is only interested in the lower 32-bits. So
4239 ;; we emit a USE of the entire register after the csmul instruction so it won't
4240 ;; get confused. See frv_ifcvt_modify_insn for more details.
4242 (define_insn "*cond_exec_si_smul"
4244 (match_operator 0 "ccr_eqne_operator"
4245 [(match_operand 1 "cr_operand" "C")
4247 (set (match_operand:DI 2 "even_gpr_operand" "=e")
4248 (mult:DI (sign_extend:DI (match_operand:SI 3 "integer_register_operand" "%d"))
4249 (sign_extend:DI (match_operand:SI 4 "integer_register_operand" "d")))))]
4251 "csmul %3, %4, %2, %1, %e0"
4252 [(set_attr "length" "4")
4253 (set_attr "type" "mul")])
4255 (define_insn "*cond_exec_si_divide"
4257 (match_operator 0 "ccr_eqne_operator"
4258 [(match_operand 1 "cr_operand" "C")
4260 (set (match_operand:SI 2 "integer_register_operand" "=d")
4261 (match_operator:SI 3 "condexec_si_divide_operator"
4262 [(match_operand:SI 4 "integer_register_operand" "d")
4263 (match_operand:SI 5 "integer_register_operand" "d")])))]
4267 switch (GET_CODE (operands[3]))
4269 case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
4270 case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
4271 default: gcc_unreachable ();
4274 [(set_attr "length" "4")
4275 (set_attr "type" "div")])
4277 (define_insn "*cond_exec_si_unary1"
4279 (match_operator 0 "ccr_eqne_operator"
4280 [(match_operand 1 "cr_operand" "C")
4282 (set (match_operand:SI 2 "integer_register_operand" "=d")
4283 (match_operator:SI 3 "condexec_si_unary_operator"
4284 [(match_operand:SI 4 "integer_register_operand" "d")])))]
4288 switch (GET_CODE (operands[3]))
4290 case NOT: return \"cnot %4, %2, %1, %e0\";
4291 case NEG: return \"csub %., %4, %2, %1, %e0\";
4292 default: gcc_unreachable ();
4295 [(set_attr "length" "4")
4296 (set_attr "type" "int")])
4298 (define_insn "*cond_exec_si_unary2"
4300 (match_operator 0 "ccr_eqne_operator"
4301 [(match_operand 1 "cr_operand" "C")
4303 (set (match_operand:SI 2 "fpr_operand" "=f")
4304 (not:SI (match_operand:SI 3 "fpr_operand" "f"))))]
4306 "cmnot %3, %2, %1, %e0"
4307 [(set_attr "length" "4")
4308 (set_attr "type" "mlogic")])
4310 (define_insn "*cond_exec_cmpsi_cc"
4312 (match_operator 0 "ccr_eqne_operator"
4313 [(match_operand 1 "cr_operand" "C")
4315 (set (match_operand:CC 2 "icc_operand" "=t")
4316 (compare:CC (match_operand:SI 3 "integer_register_operand" "d")
4317 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4319 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4320 "ccmp %3, %z4, %1, %e0"
4321 [(set_attr "length" "4")
4322 (set_attr "type" "int")])
4324 (define_insn "*cond_exec_cmpsi_cc_uns"
4326 (match_operator 0 "ccr_eqne_operator"
4327 [(match_operand 1 "cr_operand" "C")
4329 (set (match_operand:CC_UNS 2 "icc_operand" "=t")
4330 (compare:CC_UNS (match_operand:SI 3 "integer_register_operand" "d")
4331 (match_operand:SI 4 "reg_or_0_operand" "dO"))))]
4333 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4334 "ccmp %3, %z4, %1, %e0"
4335 [(set_attr "length" "4")
4336 (set_attr "type" "int")])
4338 (define_insn "*cond_exec_cmpsi_cc_nz"
4340 (match_operator 0 "ccr_eqne_operator"
4341 [(match_operand 1 "cr_operand" "C")
4343 (set (match_operand:CC_NZ 2 "icc_operand" "=t")
4344 (compare:CC_NZ (match_operand:SI 3 "integer_register_operand" "d")
4347 && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
4348 "ccmp %3, %., %1, %e0"
4349 [(set_attr "length" "4")
4350 (set_attr "type" "int")])
4352 (define_insn "*cond_exec_sf_conv"
4354 (match_operator 0 "ccr_eqne_operator"
4355 [(match_operand 1 "cr_operand" "C")
4357 (set (match_operand:SF 2 "fpr_operand" "=f")
4358 (match_operator:SF 3 "condexec_sf_conv_operator"
4359 [(match_operand:SF 4 "fpr_operand" "f")])))]
4363 switch (GET_CODE (operands[3]))
4365 case ABS: return \"cfabss %4, %2, %1, %e0\";
4366 case NEG: return \"cfnegs %4, %2, %1, %e0\";
4367 default: gcc_unreachable ();
4370 [(set_attr "length" "4")
4371 (set_attr "type" "fsconv")])
4373 (define_insn "*cond_exec_sf_add"
4375 (match_operator 0 "ccr_eqne_operator"
4376 [(match_operand 1 "cr_operand" "C")
4378 (set (match_operand:SF 2 "fpr_operand" "=f")
4379 (match_operator:SF 3 "condexec_sf_add_operator"
4380 [(match_operand:SF 4 "fpr_operand" "f")
4381 (match_operand:SF 5 "fpr_operand" "f")])))]
4385 switch (GET_CODE (operands[3]))
4387 case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
4388 case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
4389 default: gcc_unreachable ();
4392 [(set_attr "length" "4")
4393 (set_attr "type" "fsadd")])
4395 (define_insn "*cond_exec_sf_mul"
4397 (match_operator 0 "ccr_eqne_operator"
4398 [(match_operand 1 "cr_operand" "C")
4400 (set (match_operand:SF 2 "fpr_operand" "=f")
4401 (mult:SF (match_operand:SF 3 "fpr_operand" "f")
4402 (match_operand:SF 4 "fpr_operand" "f"))))]
4404 "cfmuls %3, %4, %2, %1, %e0"
4405 [(set_attr "length" "4")
4406 (set_attr "type" "fsmul")])
4408 (define_insn "*cond_exec_sf_div"
4410 (match_operator 0 "ccr_eqne_operator"
4411 [(match_operand 1 "cr_operand" "C")
4413 (set (match_operand:SF 2 "fpr_operand" "=f")
4414 (div:SF (match_operand:SF 3 "fpr_operand" "f")
4415 (match_operand:SF 4 "fpr_operand" "f"))))]
4417 "cfdivs %3, %4, %2, %1, %e0"
4418 [(set_attr "length" "4")
4419 (set_attr "type" "fsdiv")])
4421 (define_insn "*cond_exec_sf_sqrt"
4423 (match_operator 0 "ccr_eqne_operator"
4424 [(match_operand 1 "cr_operand" "C")
4426 (set (match_operand:SF 2 "fpr_operand" "=f")
4427 (sqrt:SF (match_operand:SF 3 "fpr_operand" "f"))))]
4429 "cfsqrts %3, %2, %1, %e0"
4430 [(set_attr "length" "4")
4431 (set_attr "type" "fsdiv")])
4433 (define_insn "*cond_exec_cmpsi_cc_fp"
4435 (match_operator 0 "ccr_eqne_operator"
4436 [(match_operand 1 "cr_operand" "C")
4438 (set (match_operand:CC_FP 2 "fcc_operand" "=u")
4439 (compare:CC_FP (match_operand:SF 3 "fpr_operand" "f")
4440 (match_operand:SF 4 "fpr_operand" "f"))))]
4441 "reload_completed && TARGET_HARD_FLOAT
4442 && REGNO (operands[1]) == REGNO (operands[2]) - FCC_FIRST + FCR_FIRST"
4443 "cfcmps %3, %4, %2, %1, %e0"
4444 [(set_attr "length" "4")
4445 (set_attr "type" "fsconv")])
4448 ;; ::::::::::::::::::::
4450 ;; :: Logical operations on CR registers
4452 ;; ::::::::::::::::::::
4454 ;; We use UNSPEC to encode andcr/iorcr/etc. rather than the normal RTL
4455 ;; operations, since the RTL operations only have an idea of TRUE and FALSE,
4456 ;; while the CRs have TRUE, FALSE, and UNDEFINED.
4458 (define_expand "andcr"
4459 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4460 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4461 (match_operand:CC_CCR 2 "cr_operand" "")
4462 (const_int 0)] UNSPEC_CR_LOGIC))]
4466 (define_expand "orcr"
4467 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4468 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4469 (match_operand:CC_CCR 2 "cr_operand" "")
4470 (const_int 1)] UNSPEC_CR_LOGIC))]
4474 (define_expand "xorcr"
4475 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4476 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4477 (match_operand:CC_CCR 2 "cr_operand" "")
4478 (const_int 2)] UNSPEC_CR_LOGIC))]
4482 (define_expand "nandcr"
4483 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4484 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4485 (match_operand:CC_CCR 2 "cr_operand" "")
4486 (const_int 3)] UNSPEC_CR_LOGIC))]
4490 (define_expand "norcr"
4491 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4492 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4493 (match_operand:CC_CCR 2 "cr_operand" "")
4494 (const_int 4)] UNSPEC_CR_LOGIC))]
4498 (define_expand "andncr"
4499 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4500 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4501 (match_operand:CC_CCR 2 "cr_operand" "")
4502 (const_int 5)] UNSPEC_CR_LOGIC))]
4506 (define_expand "orncr"
4507 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4508 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4509 (match_operand:CC_CCR 2 "cr_operand" "")
4510 (const_int 6)] UNSPEC_CR_LOGIC))]
4514 (define_expand "nandncr"
4515 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4516 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4517 (match_operand:CC_CCR 2 "cr_operand" "")
4518 (const_int 7)] UNSPEC_CR_LOGIC))]
4522 (define_expand "norncr"
4523 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4524 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4525 (match_operand:CC_CCR 2 "cr_operand" "")
4526 (const_int 8)] UNSPEC_CR_LOGIC))]
4530 (define_expand "notcr"
4531 [(set (match_operand:CC_CCR 0 "cr_operand" "")
4532 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "")
4534 (const_int 9)] UNSPEC_CR_LOGIC))]
4538 (define_insn "*logical_cr"
4539 [(set (match_operand:CC_CCR 0 "cr_operand" "=C")
4540 (unspec:CC_CCR [(match_operand:CC_CCR 1 "cr_operand" "C")
4541 (match_operand:CC_CCR 2 "cr_operand" "C")
4542 (match_operand:SI 3 "const_int_operand" "n")]
4547 switch (INTVAL (operands[3]))
4550 case 0: return \"andcr %1, %2, %0\";
4551 case 1: return \"orcr %1, %2, %0\";
4552 case 2: return \"xorcr %1, %2, %0\";
4553 case 3: return \"nandcr %1, %2, %0\";
4554 case 4: return \"norcr %1, %2, %0\";
4555 case 5: return \"andncr %1, %2, %0\";
4556 case 6: return \"orncr %1, %2, %0\";
4557 case 7: return \"nandncr %1, %2, %0\";
4558 case 8: return \"norncr %1, %2, %0\";
4559 case 9: return \"notcr %1, %0\";
4562 fatal_insn (\"logical_cr\", insn);
4564 [(set_attr "length" "4")
4565 (set_attr "type" "ccr")])
4568 ;; ::::::::::::::::::::
4570 ;; :: Conditional move instructions
4572 ;; ::::::::::::::::::::
4575 ;; - conditional moves based on floating-point comparisons require
4576 ;; TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4578 ;; - conditional moves between FPRs based on integer comparisons
4579 ;; require TARGET_HAS_FPRS.
4581 (define_expand "movqicc"
4582 [(set (match_operand:QI 0 "integer_register_operand" "")
4583 (if_then_else:QI (match_operand 1 "" "")
4584 (match_operand:QI 2 "gpr_or_int_operand" "")
4585 (match_operand:QI 3 "gpr_or_int_operand" "")))]
4589 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4595 (define_insn "*movqicc_internal1_int"
4596 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4597 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4598 [(match_operand 2 "icc_operand" "t,t,t")
4600 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4601 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4602 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4605 [(set_attr "length" "8,8,12")
4606 (set_attr "type" "multi")])
4608 (define_insn "*movqicc_internal1_float"
4609 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
4610 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4611 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4613 (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
4614 (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
4615 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4618 [(set_attr "length" "8,8,12")
4619 (set_attr "type" "multi")])
4621 (define_insn "*movqicc_internal2_int"
4622 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4623 (if_then_else:QI (match_operator 1 "integer_relational_operator"
4624 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4626 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4627 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4628 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4629 "(INTVAL (operands[3]) == 0
4630 || INTVAL (operands[4]) == 0
4631 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4632 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4634 [(set_attr "length" "8,12,8,12,12")
4635 (set_attr "type" "multi")])
4637 (define_insn "*movqicc_internal2_float"
4638 [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
4639 (if_then_else:QI (match_operator:CC_FP 1 "float_relational_operator"
4640 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4642 (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
4643 (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
4644 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4646 && (INTVAL (operands[3]) == 0
4647 || INTVAL (operands[4]) == 0
4648 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4649 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4651 [(set_attr "length" "8,12,8,12,12")
4652 (set_attr "type" "multi")])
4655 [(set (match_operand:QI 0 "integer_register_operand" "")
4656 (if_then_else:QI (match_operator 1 "relational_operator"
4657 [(match_operand 2 "cc_operand" "")
4659 (match_operand:QI 3 "gpr_or_int_operand" "")
4660 (match_operand:QI 4 "gpr_or_int_operand" "")))
4661 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4664 "operands[6] = frv_split_cond_move (operands);")
4666 (define_expand "movhicc"
4667 [(set (match_operand:HI 0 "integer_register_operand" "")
4668 (if_then_else:HI (match_operand 1 "" "")
4669 (match_operand:HI 2 "gpr_or_int_operand" "")
4670 (match_operand:HI 3 "gpr_or_int_operand" "")))]
4674 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4680 (define_insn "*movhicc_internal1_int"
4681 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4682 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4683 [(match_operand 2 "icc_operand" "t,t,t")
4685 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4686 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4687 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4690 [(set_attr "length" "8,8,12")
4691 (set_attr "type" "multi")])
4693 (define_insn "*movhicc_internal1_float"
4694 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
4695 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4696 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4698 (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
4699 (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
4700 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4703 [(set_attr "length" "8,8,12")
4704 (set_attr "type" "multi")])
4706 (define_insn "*movhicc_internal2_int"
4707 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4708 (if_then_else:HI (match_operator 1 "integer_relational_operator"
4709 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4711 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4712 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4713 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4714 "(INTVAL (operands[3]) == 0
4715 || INTVAL (operands[4]) == 0
4716 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4717 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4719 [(set_attr "length" "8,12,8,12,12")
4720 (set_attr "type" "multi")])
4722 (define_insn "*movhicc_internal2_float"
4723 [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
4724 (if_then_else:HI (match_operator:CC_FP 1 "float_relational_operator"
4725 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4727 (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
4728 (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
4729 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4731 && (INTVAL (operands[3]) == 0
4732 || INTVAL (operands[4]) == 0
4733 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4734 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4736 [(set_attr "length" "8,12,8,12,12")
4737 (set_attr "type" "multi")])
4740 [(set (match_operand:HI 0 "integer_register_operand" "")
4741 (if_then_else:HI (match_operator 1 "relational_operator"
4742 [(match_operand 2 "cc_operand" "")
4744 (match_operand:HI 3 "gpr_or_int_operand" "")
4745 (match_operand:HI 4 "gpr_or_int_operand" "")))
4746 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4749 "operands[6] = frv_split_cond_move (operands);")
4751 (define_expand "movsicc"
4752 [(set (match_operand:SI 0 "integer_register_operand" "")
4753 (if_then_else:SI (match_operand 1 "" "")
4754 (match_operand:SI 2 "gpr_or_int_operand" "")
4755 (match_operand:SI 3 "gpr_or_int_operand" "")))]
4759 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4765 (define_insn "*movsicc_internal1_int"
4766 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4767 (if_then_else:SI (match_operator 1 "integer_relational_operator"
4768 [(match_operand 2 "icc_operand" "t,t,t")
4770 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4771 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4772 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4775 [(set_attr "length" "8,8,12")
4776 (set_attr "type" "multi")])
4778 (define_insn "*movsicc_internal1_float"
4779 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
4780 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4781 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u")
4783 (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
4784 (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
4785 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
4788 [(set_attr "length" "8,8,12")
4789 (set_attr "type" "multi")])
4791 (define_insn "*movsicc_internal2_int"
4792 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4793 (if_then_else:SI (match_operator 1 "integer_relational_operator"
4794 [(match_operand 2 "icc_operand" "t,t,t,t,t")
4796 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4797 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4798 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
4799 "(INTVAL (operands[3]) == 0
4800 || INTVAL (operands[4]) == 0
4801 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4802 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4804 [(set_attr "length" "8,12,8,12,12")
4805 (set_attr "type" "multi")])
4807 (define_insn "*movsicc_internal2_float"
4808 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
4809 (if_then_else:SI (match_operator:CC_FP 1 "float_relational_operator"
4810 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u")
4812 (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
4813 (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
4814 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w"))]
4816 && (INTVAL (operands[3]) == 0
4817 || INTVAL (operands[4]) == 0
4818 || (IN_RANGE (INTVAL (operands[3]), -2048, 2047)
4819 && IN_RANGE (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
4821 [(set_attr "length" "8,12,8,12,12")
4822 (set_attr "type" "multi")])
4825 [(set (match_operand:SI 0 "integer_register_operand" "")
4826 (if_then_else:SI (match_operator 1 "relational_operator"
4827 [(match_operand 2 "cc_operand" "")
4829 (match_operand:SI 3 "gpr_or_int_operand" "")
4830 (match_operand:SI 4 "gpr_or_int_operand" "")))
4831 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4834 "operands[6] = frv_split_cond_move (operands);")
4836 (define_expand "movsfcc"
4837 [(set (match_operand:SF 0 "register_operand" "")
4838 (if_then_else:SF (match_operand 1 "" "")
4839 (match_operand:SF 2 "register_operand" "")
4840 (match_operand:SF 3 "register_operand" "")))]
4844 if (!frv_emit_cond_move (operands[0], operands[1], operands[2], operands[3]))
4850 (define_insn "*movsfcc_has_fprs_int"
4851 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4852 (if_then_else:SF (match_operator 1 "integer_relational_operator"
4853 [(match_operand 2 "icc_operand" "t,t,t,t,t,t")
4855 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4856 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4857 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
4860 [(set_attr "length" "8,8,12,12,12,12")
4861 (set_attr "type" "multi")])
4863 (define_insn "*movsfcc_hardfloat_float"
4864 [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
4865 (if_then_else:SF (match_operator:CC_FP 1 "float_relational_operator"
4866 [(match_operand:CC_FP 2 "fcc_operand" "u,u,u,u,u,u")
4868 (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
4869 (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
4870 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w,w,w,w"))]
4873 [(set_attr "length" "8,8,12,12,12,12")
4874 (set_attr "type" "multi")])
4876 (define_insn "*movsfcc_no_fprs_int"
4877 [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
4878 (if_then_else:SF (match_operator 1 "integer_relational_operator"
4879 [(match_operand 2 "icc_operand" "t,t,t")
4881 (match_operand:SF 3 "integer_register_operand" "0,d,d")
4882 (match_operand:SF 4 "integer_register_operand" "d,0,d")))
4883 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4886 [(set_attr "length" "8,8,12")
4887 (set_attr "type" "multi")])
4890 [(set (match_operand:SF 0 "register_operand" "")
4891 (if_then_else:SF (match_operator 1 "relational_operator"
4892 [(match_operand 2 "cc_operand" "")
4894 (match_operand:SF 3 "register_operand" "")
4895 (match_operand:SF 4 "register_operand" "")))
4896 (clobber (match_operand:CC_CCR 5 "cr_operand" ""))]
4899 "operands[6] = frv_split_cond_move (operands);")
4902 ;; ::::::::::::::::::::
4904 ;; :: Minimum, maximum, and integer absolute value
4906 ;; ::::::::::::::::::::
4908 ;; These 'instructions' are provided to give the compiler a slightly better
4909 ;; nudge at register allocation, then it would if it constructed the
4910 ;; instructions from basic building blocks (since it indicates it prefers one
4911 ;; of the operands to be the same as the destination. It also helps the
4912 ;; earlier passes of the compiler, by not breaking things into small basic
4915 (define_expand "abssi2"
4916 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4917 (abs:SI (match_operand:SI 1 "integer_register_operand" "")))
4918 (clobber (match_dup 2))
4919 (clobber (match_dup 3))])]
4923 operands[2] = gen_reg_rtx (CCmode);
4924 operands[3] = gen_reg_rtx (CC_CCRmode);
4927 (define_insn_and_split "*abssi2_internal"
4928 [(set (match_operand:SI 0 "integer_register_operand" "=d,d")
4929 (abs:SI (match_operand:SI 1 "integer_register_operand" "0,d")))
4930 (clobber (match_operand:CC 2 "icc_operand" "=t,t"))
4931 (clobber (match_operand:CC_CCR 3 "icr_operand" "=v,v"))]
4936 "operands[4] = frv_split_abs (operands);"
4937 [(set_attr "length" "12,16")
4938 (set_attr "type" "multi")])
4940 (define_expand "sminsi3"
4941 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4942 (smin:SI (match_operand:SI 1 "integer_register_operand" "")
4943 (match_operand:SI 2 "gpr_or_int10_operand" "")))
4944 (clobber (match_dup 3))
4945 (clobber (match_dup 4))])]
4949 operands[3] = gen_reg_rtx (CCmode);
4950 operands[4] = gen_reg_rtx (CC_CCRmode);
4953 (define_expand "smaxsi3"
4954 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4955 (smax:SI (match_operand:SI 1 "integer_register_operand" "")
4956 (match_operand:SI 2 "gpr_or_int10_operand" "")))
4957 (clobber (match_dup 3))
4958 (clobber (match_dup 4))])]
4962 operands[3] = gen_reg_rtx (CCmode);
4963 operands[4] = gen_reg_rtx (CC_CCRmode);
4966 (define_insn_and_split "*minmax_si_signed"
4967 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
4968 (match_operator:SI 1 "minmax_operator"
4969 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
4970 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
4971 (clobber (match_operand:CC 4 "icc_operand" "=t,t,t"))
4972 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
4977 "operands[6] = frv_split_minmax (operands);"
4978 [(set_attr "length" "12,12,16")
4979 (set_attr "type" "multi")])
4981 (define_expand "uminsi3"
4982 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4983 (umin:SI (match_operand:SI 1 "integer_register_operand" "")
4984 (match_operand:SI 2 "gpr_or_int10_operand" "")))
4985 (clobber (match_dup 3))
4986 (clobber (match_dup 4))])]
4990 operands[3] = gen_reg_rtx (CC_UNSmode);
4991 operands[4] = gen_reg_rtx (CC_CCRmode);
4994 (define_expand "umaxsi3"
4995 [(parallel [(set (match_operand:SI 0 "integer_register_operand" "")
4996 (umax:SI (match_operand:SI 1 "integer_register_operand" "")
4997 (match_operand:SI 2 "gpr_or_int10_operand" "")))
4998 (clobber (match_dup 3))
4999 (clobber (match_dup 4))])]
5003 operands[3] = gen_reg_rtx (CC_UNSmode);
5004 operands[4] = gen_reg_rtx (CC_CCRmode);
5007 (define_insn_and_split "*minmax_si_unsigned"
5008 [(set (match_operand:SI 0 "integer_register_operand" "=d,d,&d")
5009 (match_operator:SI 1 "minmax_operator"
5010 [(match_operand:SI 2 "integer_register_operand" "%0,dO,d")
5011 (match_operand:SI 3 "gpr_or_int10_operand" "dO,0,dJ")]))
5012 (clobber (match_operand:CC_UNS 4 "icc_operand" "=t,t,t"))
5013 (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
5018 "operands[6] = frv_split_minmax (operands);"
5019 [(set_attr "length" "12,12,16")
5020 (set_attr "type" "multi")])
5022 (define_expand "sminsf3"
5023 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5024 (smin:SF (match_operand:SF 1 "fpr_operand" "")
5025 (match_operand:SF 2 "fpr_operand" "")))
5026 (clobber (match_dup 3))
5027 (clobber (match_dup 4))])]
5028 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5031 operands[3] = gen_reg_rtx (CC_FPmode);
5032 operands[4] = gen_reg_rtx (CC_CCRmode);
5035 (define_expand "smaxsf3"
5036 [(parallel [(set (match_operand:SF 0 "fpr_operand" "")
5037 (smax:SF (match_operand:SF 1 "fpr_operand" "")
5038 (match_operand:SF 2 "fpr_operand" "")))
5039 (clobber (match_dup 3))
5040 (clobber (match_dup 4))])]
5041 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5044 operands[3] = gen_reg_rtx (CC_FPmode);
5045 operands[4] = gen_reg_rtx (CC_CCRmode);
5048 (define_insn_and_split "*minmax_sf"
5049 [(set (match_operand:SF 0 "fpr_operand" "=f,f,f")
5050 (match_operator:SF 1 "minmax_operator"
5051 [(match_operand:SF 2 "fpr_operand" "%0,f,f")
5052 (match_operand:SF 3 "fpr_operand" "f,0,f")]))
5053 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5054 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5055 "TARGET_COND_MOVE && TARGET_HARD_FLOAT"
5059 "operands[6] = frv_split_minmax (operands);"
5060 [(set_attr "length" "12,12,16")
5061 (set_attr "type" "multi")])
5063 (define_expand "smindf3"
5064 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5065 (smin:DF (match_operand:DF 1 "fpr_operand" "")
5066 (match_operand:DF 2 "fpr_operand" "")))
5067 (clobber (match_dup 3))
5068 (clobber (match_dup 4))])]
5069 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5072 operands[3] = gen_reg_rtx (CC_FPmode);
5073 operands[4] = gen_reg_rtx (CC_CCRmode);
5076 (define_expand "smaxdf3"
5077 [(parallel [(set (match_operand:DF 0 "fpr_operand" "")
5078 (smax:DF (match_operand:DF 1 "fpr_operand" "")
5079 (match_operand:DF 2 "fpr_operand" "")))
5080 (clobber (match_dup 3))
5081 (clobber (match_dup 4))])]
5082 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5085 operands[3] = gen_reg_rtx (CC_FPmode);
5086 operands[4] = gen_reg_rtx (CC_CCRmode);
5089 (define_insn_and_split "*minmax_df"
5090 [(set (match_operand:DF 0 "fpr_operand" "=f,f,f")
5091 (match_operator:DF 1 "minmax_operator"
5092 [(match_operand:DF 2 "fpr_operand" "%0,f,f")
5093 (match_operand:DF 3 "fpr_operand" "f,0,f")]))
5094 (clobber (match_operand:CC_FP 4 "fcc_operand" "=u,u,u"))
5095 (clobber (match_operand:CC_CCR 5 "fcr_operand" "=w,w,w"))]
5096 "TARGET_COND_MOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE"
5100 "operands[6] = frv_split_minmax (operands);"
5101 [(set_attr "length" "12,12,16")
5102 (set_attr "type" "multi")])
5105 ;; ::::::::::::::::::::
5107 ;; :: Call and branch instructions
5109 ;; ::::::::::::::::::::
5111 ;; Subroutine call instruction returning no value. Operand 0 is the function
5112 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
5113 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
5114 ;; registers used as operands.
5116 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
5117 ;; is supplied for the sake of some RISC machines which need to put this
5118 ;; information into the assembler code; they can put it in the RTL instead of
5121 (define_expand "call"
5122 [(use (match_operand:QI 0 "" ""))
5123 (use (match_operand 1 "" ""))
5124 (use (match_operand 2 "" ""))
5125 (use (match_operand 3 "" ""))]
5129 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5132 gcc_assert (GET_CODE (operands[0]) == MEM);
5134 addr = XEXP (operands[0], 0);
5135 if (! call_operand (addr, Pmode))
5136 addr = force_reg (Pmode, addr);
5139 operands[2] = const0_rtx;
5142 frv_expand_fdpic_call (operands, false, false);
5144 emit_call_insn (gen_call_internal (addr, operands[1], operands[2], lr));
5149 (define_insn "call_internal"
5150 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5151 (match_operand 1 "" ""))
5152 (use (match_operand 2 "" ""))
5153 (clobber (match_operand:SI 3 "lr_operand" "=l,l"))]
5158 [(set_attr "length" "4")
5159 (set_attr "type" "call,jumpl")])
5161 ;; The odd use of GR0 within the UNSPEC below prevents cseing or
5162 ;; hoisting function descriptor loads out of loops. This is almost
5163 ;; never desirable, since if we preserve the function descriptor in a
5164 ;; pair of registers, it takes two insns to move it to gr14/gr15, and
5165 ;; if it's in the stack, we just waste space with the store, since
5166 ;; we'll have to load back from memory anyway. And, in the worst
5167 ;; case, we may end up reusing a function descriptor still pointing at
5168 ;; a PLT entry, instead of to the resolved function, which means going
5169 ;; through the resolver for every call that uses the outdated value.
5172 ;; The explicit MEM inside the SPEC prevents the compiler from moving
5173 ;; the load before a branch after a NULL test, or before a store that
5174 ;; initializes a function descriptor.
5176 (define_insn "movdi_ldd"
5177 [(set (match_operand:DI 0 "fdpic_fptr_operand" "=e")
5178 (unspec:DI [(mem:DI (match_operand:SI 1 "ldd_address_operand" "p"))
5179 (reg:SI 0)] UNSPEC_LDD))]
5182 [(set_attr "length" "4")
5183 (set_attr "type" "gload")])
5185 (define_insn "call_fdpicdi"
5186 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5187 (match_operand 1 "" ""))
5188 (clobber (match_operand:SI 2 "lr_operand" "=l"))]
5191 [(set_attr "length" "4")
5192 (set_attr "type" "jumpl")])
5194 (define_insn "call_fdpicsi"
5195 [(call (mem:QI (match_operand:SI 0 "call_operand" "S,dNOP"))
5196 (match_operand 1 "" ""))
5197 (use (match_operand 2 "" ""))
5198 (use (match_operand:SI 3 "fdpic_operand" "Z,Z"))
5199 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5204 [(set_attr "length" "4")
5205 (set_attr "type" "call,jumpl")])
5207 (define_expand "sibcall"
5208 [(use (match_operand:QI 0 "" ""))
5209 (use (match_operand 1 "" ""))
5210 (use (match_operand 2 "" ""))
5211 (use (match_operand 3 "" ""))]
5217 gcc_assert (GET_CODE (operands[0]) == MEM);
5219 addr = XEXP (operands[0], 0);
5220 if (! sibcall_operand (addr, Pmode))
5221 addr = force_reg (Pmode, addr);
5224 operands[2] = const0_rtx;
5227 frv_expand_fdpic_call (operands, false, true);
5229 emit_call_insn (gen_sibcall_internal (addr, operands[1], operands[2]));
5234 ;; It might seem that these sibcall patterns are missing references to
5235 ;; LR, but they're not necessary because sibcall_epilogue will make
5236 ;; sure LR is restored, and having LR here will set
5237 ;; regs_ever_used[REG_LR], forcing it to be saved on the stack, and
5238 ;; then restored in sibcalls and regular return code paths, even if
5239 ;; the function becomes a leaf function after tail-call elimination.
5241 ;; We must not use a call-saved register here. `W' limits ourselves
5242 ;; to gr14 or gr15, but since we're almost running out of constraint
5243 ;; letters, and most other call-clobbered registers are often used for
5244 ;; argument-passing, this will do.
5245 (define_insn "sibcall_internal"
5246 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "WNOP"))
5247 (match_operand 1 "" ""))
5248 (use (match_operand 2 "" ""))
5252 [(set_attr "length" "4")
5253 (set_attr "type" "jumpl")])
5255 (define_insn "sibcall_fdpicdi"
5256 [(call (mem:QI (match_operand:DI 0 "fdpic_fptr_operand" "W"))
5257 (match_operand 1 "" ""))
5261 [(set_attr "length" "4")
5262 (set_attr "type" "jumpl")])
5265 ;; Subroutine call instruction returning a value. Operand 0 is the hard
5266 ;; register in which the value is returned. There are three more operands, the
5267 ;; same as the three operands of the `call' instruction (but with numbers
5268 ;; increased by one).
5270 ;; Subroutines that return `BLKmode' objects use the `call' insn.
5272 (define_expand "call_value"
5273 [(use (match_operand 0 "" ""))
5274 (use (match_operand:QI 1 "" ""))
5275 (use (match_operand 2 "" ""))
5276 (use (match_operand 3 "" ""))
5277 (use (match_operand 4 "" ""))]
5281 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
5284 gcc_assert (GET_CODE (operands[1]) == MEM);
5286 addr = XEXP (operands[1], 0);
5287 if (! call_operand (addr, Pmode))
5288 addr = force_reg (Pmode, addr);
5291 operands[3] = const0_rtx;
5294 frv_expand_fdpic_call (operands, true, false);
5296 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
5302 (define_insn "call_value_internal"
5303 [(set (match_operand 0 "register_operand" "=d,d")
5304 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5305 (match_operand 2 "" "")))
5306 (use (match_operand 3 "" ""))
5307 (clobber (match_operand:SI 4 "lr_operand" "=l,l"))]
5312 [(set_attr "length" "4")
5313 (set_attr "type" "call,jumpl")])
5315 (define_insn "call_value_fdpicdi"
5316 [(set (match_operand 0 "register_operand" "=d")
5317 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5318 (match_operand 2 "" "")))
5319 (clobber (match_operand:SI 3 "lr_operand" "=l"))]
5322 [(set_attr "length" "4")
5323 (set_attr "type" "jumpl")])
5325 (define_insn "call_value_fdpicsi"
5326 [(set (match_operand 0 "register_operand" "=d,d")
5327 (call (mem:QI (match_operand:SI 1 "call_operand" "S,dNOP"))
5328 (match_operand 2 "" "")))
5329 (use (match_operand 3 "" ""))
5330 (use (match_operand:SI 4 "fdpic_operand" "Z,Z"))
5331 (clobber (match_operand:SI 5 "lr_operand" "=l,l"))]
5336 [(set_attr "length" "4")
5337 (set_attr "type" "call,jumpl")])
5339 (define_expand "sibcall_value"
5340 [(use (match_operand 0 "" ""))
5341 (use (match_operand:QI 1 "" ""))
5342 (use (match_operand 2 "" ""))
5343 (use (match_operand 3 "" ""))
5344 (use (match_operand 4 "" ""))]
5350 gcc_assert (GET_CODE (operands[1]) == MEM);
5352 addr = XEXP (operands[1], 0);
5353 if (! sibcall_operand (addr, Pmode))
5354 addr = force_reg (Pmode, addr);
5357 operands[3] = const0_rtx;
5360 frv_expand_fdpic_call (operands, true, true);
5362 emit_call_insn (gen_sibcall_value_internal (operands[0], addr, operands[2],
5367 (define_insn "sibcall_value_internal"
5368 [(set (match_operand 0 "register_operand" "=d")
5369 (call (mem:QI (match_operand:SI 1 "sibcall_operand" "WNOP"))
5370 (match_operand 2 "" "")))
5371 (use (match_operand 3 "" ""))
5375 [(set_attr "length" "4")
5376 (set_attr "type" "jumpl")])
5378 (define_insn "sibcall_value_fdpicdi"
5379 [(set (match_operand 0 "register_operand" "=d")
5380 (call (mem:QI (match_operand:DI 1 "fdpic_fptr_operand" "W"))
5381 (match_operand 2 "" "")))
5385 [(set_attr "length" "4")
5386 (set_attr "type" "jumpl")])
5388 ;; return instruction generated instead of jmp to epilog
5389 (define_expand "return"
5390 [(parallel [(return)
5392 (use (const_int 1))])]
5393 "direct_return_p ()"
5396 operands[0] = gen_rtx_REG (Pmode, LR_REGNO);
5399 ;; return instruction generated by the epilogue
5400 (define_expand "epilogue_return"
5401 [(parallel [(return)
5402 (use (match_operand:SI 0 "register_operand" ""))
5403 (use (const_int 0))])]
5407 (define_insn "*return_internal"
5409 (use (match_operand:SI 0 "register_operand" "l,d"))
5410 (use (match_operand:SI 1 "immediate_operand" "n,n"))]
5415 [(set_attr "length" "4")
5416 (set_attr "type" "jump,jumpl")])
5418 (define_insn "*return_true"
5420 (if_then_else (match_operator 0 "integer_relational_operator"
5421 [(match_operand 1 "icc_operand" "t")
5425 "direct_return_p ()"
5427 [(set_attr "length" "4")
5428 (set_attr "type" "jump")])
5430 (define_insn "*return_false"
5432 (if_then_else (match_operator 0 "integer_relational_operator"
5433 [(match_operand 1 "icc_operand" "t")
5437 "direct_return_p ()"
5439 [(set_attr "length" "4")
5440 (set_attr "type" "jump")])
5442 ;; A version of addsi3 for deallocating stack space at the end of the
5443 ;; epilogue. The addition is done in parallel with an (unspec_volatile),
5444 ;; which represents the clobbering of the deallocated space.
5445 (define_insn "stack_adjust"
5446 [(set (match_operand:SI 0 "register_operand" "=d")
5447 (plus:SI (match_operand:SI 1 "register_operand" "d")
5448 (match_operand:SI 2 "general_operand" "dNOP")))
5449 (unspec_volatile [(const_int 0)] UNSPEC_STACK_ADJUST)]
5452 [(set_attr "length" "4")
5453 (set_attr "type" "int")])
5455 ;; Normal unconditional jump
5457 ;; Use the "call" instruction for long branches, but prefer to use "bra" for
5458 ;; short ones since it does not force us to save the link register.
5460 ;; This define_insn uses the branch-shortening code to decide which
5461 ;; instruction it emits. Since the main branch-shortening interface is
5462 ;; through get_attr_length(), the two alternatives must be given different
5463 ;; lengths. Here we pretend that the far jump is 8 rather than 4 bytes
5464 ;; long, though both alternatives are really the same size.
5466 [(set (pc) (label_ref (match_operand 0 "" "")))]
5470 if (get_attr_length (insn) == 4)
5473 return \"call %l0\";
5475 [(set (attr "length")
5477 (and (ge (minus (match_dup 0) (pc)) (const_int -32768))
5478 (le (minus (match_dup 0) (pc)) (const_int 32764)))
5481 (set (attr "far_jump")
5483 (eq_attr "length" "4")
5485 (const_string "yes")))
5488 (eq_attr "length" "4")
5489 (const_string "jump")
5490 (const_string "call")))])
5492 ;; Indirect jump through a register
5493 (define_insn "indirect_jump"
5494 [(set (pc) (match_operand:SI 0 "register_operand" "d,l"))]
5499 [(set_attr "length" "4")
5500 (set_attr "type" "jumpl,branch")])
5502 ;; Instruction to jump to a variable address. This is a low-level capability
5503 ;; which can be used to implement a dispatch table when there is no `casesi'
5504 ;; pattern. Either the 'casesi' pattern or the 'tablejump' pattern, or both,
5505 ;; MUST be present in this file.
5507 ;; This pattern requires two operands: the address or offset, and a label which
5508 ;; should immediately precede the jump table. If the macro
5509 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5510 ;; which counts from the address of the table; otherwise, it is an absolute
5511 ;; address to jump to. In either case, the first operand has mode `Pmode'.
5513 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5514 ;; Its assembler code normally has no need to use the second operand, but you
5515 ;; should incorporate it in the RTL pattern so that the jump optimizer will not
5516 ;; delete the table as unreachable code.
5518 (define_expand "tablejump"
5519 [(parallel [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5520 (use (label_ref (match_operand 1 "" "")))])]
5524 (define_insn "tablejump_insn"
5525 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
5526 (use (label_ref (match_operand 1 "" "")))]
5529 [(set_attr "length" "4")
5530 (set_attr "type" "jumpl")])
5532 ;; Implement switch statements when generating PIC code. Switches are
5533 ;; implemented by `tablejump' when not using -fpic.
5535 ;; Emit code here to do the range checking and make the index zero based.
5536 ;; operand 0 is the index
5537 ;; operand 1 is the lower bound
5538 ;; operand 2 is the range of indices (highest - lowest + 1)
5539 ;; operand 3 is the label that precedes the table itself
5540 ;; operand 4 is the fall through label
5542 (define_expand "casesi"
5543 [(use (match_operand:SI 0 "integer_register_operand" ""))
5544 (use (match_operand:SI 1 "const_int_operand" ""))
5545 (use (match_operand:SI 2 "const_int_operand" ""))
5546 (use (match_operand 3 "" ""))
5547 (use (match_operand 4 "" ""))]
5553 rtx low = operands[1];
5554 rtx range = operands[2];
5555 rtx table = operands[3];
5557 rtx fail = operands[4];
5562 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5564 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5566 /* If we can't generate an immediate instruction, promote to register. */
5567 if (! IN_RANGE (INTVAL (range), -2048, 2047))
5568 range = force_reg (SImode, range);
5570 /* If low bound is 0, we don't have to subtract it. */
5571 if (INTVAL (operands[1]) == 0)
5575 indx = gen_reg_rtx (SImode);
5576 if (IN_RANGE (INTVAL (low), -2047, 2048))
5577 emit_insn (gen_addsi3 (indx, operands[0], GEN_INT (- INTVAL (low))));
5579 emit_insn (gen_subsi3 (indx, operands[0], force_reg (SImode, low)));
5582 /* Do an unsigned comparison (in the proper mode) between the index
5583 expression and the value which represents the length of the range.
5584 Since we just finished subtracting the lower bound of the range
5585 from the index expression, this comparison allows us to simultaneously
5586 check that the original index expression value is both greater than
5587 or equal to the minimum value of the range and less than or equal to
5588 the maximum value of the range. */
5590 emit_cmp_and_jump_insns (indx, range, GTU, NULL_RTX, SImode, 1, fail);
5592 /* Move the table address to a register. */
5593 treg = gen_reg_rtx (Pmode);
5594 emit_insn (gen_movsi (treg, gen_rtx_LABEL_REF (VOIDmode, table)));
5596 /* Scale index-low by wordsize. */
5597 scale = gen_reg_rtx (SImode);
5598 emit_insn (gen_ashlsi3 (scale, indx, const2_rtx));
5600 /* Load the address, add the start of the table back in,
5602 mem = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, scale, treg));
5603 reg2 = gen_reg_rtx (SImode);
5604 reg3 = gen_reg_rtx (SImode);
5605 emit_insn (gen_movsi (reg2, mem));
5606 emit_insn (gen_addsi3 (reg3, reg2, treg));
5607 emit_jump_insn (gen_tablejump_insn (reg3, table));
5612 ;; ::::::::::::::::::::
5614 ;; :: Prologue and Epilogue instructions
5616 ;; ::::::::::::::::::::
5618 ;; Called after register allocation to add any instructions needed for the
5619 ;; prologue. Using a prologue insn is favored compared to putting all of the
5620 ;; instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
5621 ;; to intermix instructions with the saves of the caller saved registers. In
5622 ;; some cases, it might be necessary to emit a barrier instruction as the last
5623 ;; insn to prevent such scheduling.
5624 (define_expand "prologue"
5629 frv_expand_prologue ();
5633 ;; Called after register allocation to add any instructions needed for the
5634 ;; epilogue. Using an epilogue insn is favored compared to putting all of the
5635 ;; instructions in the FUNCTION_EPILOGUE macro, since it allows the scheduler
5636 ;; to intermix instructions with the restores of the caller saved registers.
5637 ;; In some cases, it might be necessary to emit a barrier instruction as the
5638 ;; first insn to prevent such scheduling.
5639 (define_expand "epilogue"
5644 frv_expand_epilogue (true);
5648 ;; This pattern, if defined, emits RTL for exit from a function without the final
5649 ;; branch back to the calling function. This pattern will be emitted before any
5650 ;; sibling call (aka tail call) sites.
5652 ;; The sibcall_epilogue pattern must not clobber any arguments used for
5653 ;; parameter passing or any stack slots for arguments passed to the current
5655 (define_expand "sibcall_epilogue"
5660 frv_expand_epilogue (false);
5664 ;; Set up the pic register to hold the address of the pic table
5665 (define_insn "pic_prologue"
5666 [(set (match_operand:SI 0 "integer_register_operand" "=d")
5667 (unspec_volatile:SI [(const_int 0)] UNSPEC_PIC_PROLOGUE))
5668 (clobber (match_operand:SI 1 "lr_operand" "=l"))
5669 (clobber (match_operand:SI 2 "integer_register_operand" "=d"))]
5673 static int frv_pic_labelno = 0;
5675 operands[3] = GEN_INT (frv_pic_labelno++);
5676 return \"call %P3\\n%P3:\;movsg %1, %0\;sethi #gprelhi(%P3), %2\;setlo #gprello(%P3), %2\;sub %0,%2,%0\";
5678 [(set_attr "length" "16")
5679 (set_attr "type" "multi")])
5681 ;; ::::::::::::::::::::
5683 ;; :: Miscellaneous instructions
5685 ;; ::::::::::::::::::::
5687 ;; No operation, needed in case the user uses -g but not -O.
5692 [(set_attr "length" "4")
5693 (set_attr "type" "int")])
5699 [(set_attr "length" "4")
5700 (set_attr "type" "fnop")])
5706 [(set_attr "length" "4")
5707 (set_attr "type" "mnop")])
5709 ;; Pseudo instruction that prevents the scheduler from moving code above this
5710 ;; point. Note, type unknown is used to make sure the VLIW instructions are
5711 ;; not continued past this point.
5712 (define_insn "blockage"
5713 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5716 [(set_attr "length" "0")
5717 (set_attr "type" "unknown")])
5719 ;; ::::::::::::::::::::
5721 ;; :: Media instructions
5723 ;; ::::::::::::::::::::
5725 ;; Unimplemented instructions:
5729 [(UNSPEC_MLOGIC 100)
5736 (UNSPEC_MUNPACKH 107)
5737 (UNSPEC_MDPACKH 108)
5742 (UNSPEC_MEXPDHW 113)
5743 (UNSPEC_MEXPDHD 114)
5750 (UNSPEC_MQMULXH 121)
5756 (UNSPEC_MRDACCG 127)
5758 (UNSPEC_MWTACCG 129)
5760 (UNSPEC_MCLRACC 131)
5761 (UNSPEC_MCLRACCA 132)
5764 (UNSPEC_MDUNPACKH 135)
5765 (UNSPEC_MDUNPACKH_INTERNAL 136)
5767 (UNSPEC_MBTOHE_INTERNAL 138)
5769 (UNSPEC_MBTOHE_INTERNAL 138)
5770 (UNSPEC_MQMACH2 139)
5771 (UNSPEC_MADDACC 140)
5772 (UNSPEC_MDADDACC 141)
5774 (UNSPEC_MDROTLI 143)
5777 (UNSPEC_MDCUTSSI 146)
5778 (UNSPEC_MQSATHS 147)
5779 (UNSPEC_MHSETLOS 148)
5780 (UNSPEC_MHSETLOH 149)
5781 (UNSPEC_MHSETHIS 150)
5782 (UNSPEC_MHSETHIH 151)
5783 (UNSPEC_MHDSETS 152)
5784 (UNSPEC_MHDSETH 153)
5785 (UNSPEC_MQLCLRHS 154)
5786 (UNSPEC_MQLMTHS 155)
5787 (UNSPEC_MQSLLHI 156)
5788 (UNSPEC_MQSRAHI 157)
5789 (UNSPEC_MASACCS 158)
5790 (UNSPEC_MDASACCS 159)
5793 ;; Logic operations: type "mlogic"
5795 (define_expand "mand"
5796 [(set (match_operand:SI 0 "fpr_operand" "")
5797 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5798 (match_operand:SI 2 "fpr_operand" "")
5802 "operands[3] = GEN_INT (FRV_BUILTIN_MAND);")
5804 (define_expand "mor"
5805 [(set (match_operand:SI 0 "fpr_operand" "")
5806 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5807 (match_operand:SI 2 "fpr_operand" "")
5811 "operands[3] = GEN_INT (FRV_BUILTIN_MOR);")
5813 (define_expand "mxor"
5814 [(set (match_operand:SI 0 "fpr_operand" "")
5815 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
5816 (match_operand:SI 2 "fpr_operand" "")
5820 "operands[3] = GEN_INT (FRV_BUILTIN_MXOR);")
5822 (define_insn "*mlogic"
5823 [(set (match_operand:SI 0 "fpr_operand" "=f")
5824 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5825 (match_operand:SI 2 "fpr_operand" "f")
5826 (match_operand:SI 3 "const_int_operand" "n")]
5831 switch (INTVAL (operands[3]))
5834 case FRV_BUILTIN_MAND: return \"mand %1, %2, %0\";
5835 case FRV_BUILTIN_MOR: return \"mor %1, %2, %0\";
5836 case FRV_BUILTIN_MXOR: return \"mxor %1, %2, %0\";
5839 fatal_insn (\"Bad media insn, mlogic\", insn);
5841 [(set_attr "length" "4")
5842 (set_attr "type" "mlogic")])
5844 (define_insn "*cond_exec_mlogic"
5846 (match_operator 0 "ccr_eqne_operator"
5847 [(match_operand 1 "cr_operand" "C")
5849 (set (match_operand:SI 2 "fpr_operand" "=f")
5850 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
5851 (match_operand:SI 4 "fpr_operand" "f")
5852 (match_operand:SI 5 "const_int_operand" "n")]
5857 switch (INTVAL (operands[5]))
5860 case FRV_BUILTIN_MAND: return \"cmand %3, %4, %2, %1, %e0\";
5861 case FRV_BUILTIN_MOR: return \"cmor %3, %4, %2, %1, %e0\";
5862 case FRV_BUILTIN_MXOR: return \"cmxor %3, %4, %2, %1, %e0\";
5865 fatal_insn (\"Bad media insn, cond_exec_mlogic\", insn);
5867 [(set_attr "length" "4")
5868 (set_attr "type" "mlogic")])
5870 ;; Logical not: type "mlogic"
5873 [(set (match_operand:SI 0 "fpr_operand" "=f")
5874 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MNOT))]
5877 [(set_attr "length" "4")
5878 (set_attr "type" "mlogic")])
5880 (define_insn "*cond_exec_mnot"
5882 (match_operator 0 "ccr_eqne_operator"
5883 [(match_operand 1 "cr_operand" "C")
5885 (set (match_operand:SI 2 "fpr_operand" "=f")
5886 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")] UNSPEC_MNOT)))]
5888 "cmnot %3, %2, %1, %e0"
5889 [(set_attr "length" "4")
5890 (set_attr "type" "mlogic")])
5892 ;; Dual average (halfword): type "maveh"
5894 (define_insn "maveh"
5895 [(set (match_operand:SI 0 "fpr_operand" "=f")
5896 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5897 (match_operand:SI 2 "fpr_operand" "f")]
5901 [(set_attr "length" "4")
5902 (set_attr "type" "maveh")])
5904 ;; Dual saturation (halfword): type "msath"
5906 (define_expand "msaths"
5907 [(set (match_operand:SI 0 "fpr_operand" "=f")
5908 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5909 (match_operand:SI 2 "fpr_operand" "f")
5913 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHS);")
5915 (define_expand "msathu"
5916 [(set (match_operand:SI 0 "fpr_operand" "=f")
5917 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5918 (match_operand:SI 2 "fpr_operand" "f")
5922 "operands[3] = GEN_INT (FRV_BUILTIN_MSATHU);")
5924 (define_insn "*msath"
5925 [(set (match_operand:SI 0 "fpr_operand" "=f")
5926 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5927 (match_operand:SI 2 "fpr_operand" "f")
5928 (match_operand:SI 3 "const_int_operand" "n")]
5933 switch (INTVAL (operands[3]))
5936 case FRV_BUILTIN_MSATHS: return \"msaths %1, %2, %0\";
5937 case FRV_BUILTIN_MSATHU: return \"msathu %1, %2, %0\";
5940 fatal_insn (\"Bad media insn, msath\", insn);
5942 [(set_attr "length" "4")
5943 (set_attr "type" "msath")])
5945 ;; Dual addition/subtraction with saturation (halfword): type "maddh"
5947 (define_expand "maddhss"
5948 [(set (match_operand:SI 0 "fpr_operand" "=f")
5949 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5950 (match_operand:SI 2 "fpr_operand" "f")
5954 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHSS);")
5956 (define_expand "maddhus"
5957 [(set (match_operand:SI 0 "fpr_operand" "=f")
5958 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5959 (match_operand:SI 2 "fpr_operand" "f")
5963 "operands[3] = GEN_INT (FRV_BUILTIN_MADDHUS);")
5965 (define_expand "msubhss"
5966 [(set (match_operand:SI 0 "fpr_operand" "=f")
5967 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5968 (match_operand:SI 2 "fpr_operand" "f")
5972 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHSS);")
5974 (define_expand "msubhus"
5975 [(set (match_operand:SI 0 "fpr_operand" "=f")
5976 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5977 (match_operand:SI 2 "fpr_operand" "f")
5981 "operands[3] = GEN_INT (FRV_BUILTIN_MSUBHUS);")
5983 (define_insn "*maddh"
5984 [(set (match_operand:SI 0 "fpr_operand" "=f")
5985 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
5986 (match_operand:SI 2 "fpr_operand" "f")
5987 (match_operand:SI 3 "const_int_operand" "n")]
5992 switch (INTVAL (operands[3]))
5995 case FRV_BUILTIN_MADDHSS: return \"maddhss %1, %2, %0\";
5996 case FRV_BUILTIN_MADDHUS: return \"maddhus %1, %2, %0\";
5997 case FRV_BUILTIN_MSUBHSS: return \"msubhss %1, %2, %0\";
5998 case FRV_BUILTIN_MSUBHUS: return \"msubhus %1, %2, %0\";
6001 fatal_insn (\"Bad media insn, maddh\", insn);
6003 [(set_attr "length" "4")
6004 (set_attr "type" "maddh")])
6006 (define_insn "*cond_exec_maddh"
6008 (match_operator 0 "ccr_eqne_operator"
6009 [(match_operand 1 "cr_operand" "C")
6011 (set (match_operand:SI 2 "fpr_operand" "=f")
6012 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6013 (match_operand:SI 4 "fpr_operand" "f")
6014 (match_operand:SI 5 "const_int_operand" "n")]
6019 switch (INTVAL (operands[5]))
6022 case FRV_BUILTIN_MADDHSS: return \"cmaddhss %3, %4, %2, %1, %e0\";
6023 case FRV_BUILTIN_MADDHUS: return \"cmaddhus %3, %4, %2, %1, %e0\";
6024 case FRV_BUILTIN_MSUBHSS: return \"cmsubhss %3, %4, %2, %1, %e0\";
6025 case FRV_BUILTIN_MSUBHUS: return \"cmsubhus %3, %4, %2, %1, %e0\";
6028 fatal_insn (\"Bad media insn, cond_exec_maddh\", insn);
6030 [(set_attr "length" "4")
6031 (set_attr "type" "maddh")])
6033 ;; Quad addition/subtraction with saturation (halfword): type "mqaddh"
6035 (define_expand "mqaddhss"
6036 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6037 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6038 (match_operand:DI 2 "even_fpr_operand" "h")
6042 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHSS);")
6044 (define_expand "mqaddhus"
6045 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6046 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6047 (match_operand:DI 2 "even_fpr_operand" "h")
6051 "operands[3] = GEN_INT (FRV_BUILTIN_MQADDHUS);")
6053 (define_expand "mqsubhss"
6054 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6055 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6056 (match_operand:DI 2 "even_fpr_operand" "h")
6060 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHSS);")
6062 (define_expand "mqsubhus"
6063 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6064 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6065 (match_operand:DI 2 "even_fpr_operand" "h")
6069 "operands[3] = GEN_INT (FRV_BUILTIN_MQSUBHUS);")
6071 (define_insn "*mqaddh"
6072 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6073 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6074 (match_operand:DI 2 "even_fpr_operand" "h")
6075 (match_operand:SI 3 "const_int_operand" "n")]
6080 switch (INTVAL (operands[3]))
6083 case FRV_BUILTIN_MQADDHSS: return \"mqaddhss %1, %2, %0\";
6084 case FRV_BUILTIN_MQADDHUS: return \"mqaddhus %1, %2, %0\";
6085 case FRV_BUILTIN_MQSUBHSS: return \"mqsubhss %1, %2, %0\";
6086 case FRV_BUILTIN_MQSUBHUS: return \"mqsubhus %1, %2, %0\";
6089 fatal_insn (\"Bad media insn, mqaddh\", insn);
6091 [(set_attr "length" "4")
6092 (set_attr "type" "mqaddh")])
6094 (define_insn "*cond_exec_mqaddh"
6096 (match_operator 0 "ccr_eqne_operator"
6097 [(match_operand 1 "cr_operand" "C")
6099 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6100 (unspec:DI [(match_operand:DI 3 "even_fpr_operand" "h")
6101 (match_operand:DI 4 "even_fpr_operand" "h")
6102 (match_operand:SI 5 "const_int_operand" "n")]
6107 switch (INTVAL (operands[5]))
6110 case FRV_BUILTIN_MQADDHSS: return \"cmqaddhss %3, %4, %2, %1, %e0\";
6111 case FRV_BUILTIN_MQADDHUS: return \"cmqaddhus %3, %4, %2, %1, %e0\";
6112 case FRV_BUILTIN_MQSUBHSS: return \"cmqsubhss %3, %4, %2, %1, %e0\";
6113 case FRV_BUILTIN_MQSUBHUS: return \"cmqsubhus %3, %4, %2, %1, %e0\";
6116 fatal_insn (\"Bad media insn, cond_exec_mqaddh\", insn);
6118 [(set_attr "length" "4")
6119 (set_attr "type" "mqaddh")])
6121 ;; Pack halfword: type "mpackh"
6123 (define_insn "mpackh"
6124 [(set (match_operand:SI 0 "fpr_operand" "=f")
6125 (unspec:SI [(match_operand:HI 1 "fpr_operand" "f")
6126 (match_operand:HI 2 "fpr_operand" "f")]
6130 [(set_attr "length" "4")
6131 (set_attr "type" "mpackh")])
6133 ;; Unpack halfword: type "mpackh"
6135 (define_insn "munpackh"
6136 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6137 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6141 [(set_attr "length" "4")
6142 (set_attr "type" "munpackh")])
6144 ;; Dual pack halfword: type "mdpackh"
6146 (define_insn "mdpackh"
6147 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6148 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
6149 (match_operand:DI 2 "even_fpr_operand" "h")]
6152 "mdpackh %1, %2, %0"
6153 [(set_attr "length" "4")
6154 (set_attr "type" "mdpackh")])
6156 ;; Byte-halfword conversion: type "mbhconv"
6158 (define_insn "mbtoh"
6159 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6160 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")]
6164 [(set_attr "length" "4")
6165 (set_attr "type" "mbhconv")])
6167 (define_insn "*cond_exec_mbtoh"
6169 (match_operator 0 "ccr_eqne_operator"
6170 [(match_operand 1 "cr_operand" "C")
6172 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6173 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")]
6176 "cmbtoh %3, %2, %1, %e0"
6177 [(set_attr "length" "4")
6178 (set_attr "type" "mbhconv")])
6180 (define_insn "mhtob"
6181 [(set (match_operand:SI 0 "fpr_operand" "=f")
6182 (unspec:SI [(match_operand:DI 1 "even_fpr_operand" "h")]
6186 [(set_attr "length" "4")
6187 (set_attr "type" "mbhconv")])
6189 (define_insn "*cond_exec_mhtob"
6191 (match_operator 0 "ccr_eqne_operator"
6192 [(match_operand 1 "cr_operand" "C")
6194 (set (match_operand:SI 2 "fpr_operand" "=f")
6195 (unspec:SI [(match_operand:DI 3 "even_fpr_operand" "h")]
6198 "cmhtob %3, %2, %1, %e0"
6199 [(set_attr "length" "4")
6200 (set_attr "type" "mbhconv")])
6202 ;; Rotate: type "mrot"
6204 (define_expand "mrotli"
6205 [(set (match_operand:SI 0 "fpr_operand" "")
6206 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6207 (match_operand:SI 2 "uint5_operand" "")
6211 "operands[3] = GEN_INT (FRV_BUILTIN_MROTLI);")
6213 (define_expand "mrotri"
6214 [(set (match_operand:SI 0 "fpr_operand" "")
6215 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6216 (match_operand:SI 2 "uint5_operand" "")
6220 "operands[3] = GEN_INT (FRV_BUILTIN_MROTRI);")
6222 (define_insn "*mrot"
6223 [(set (match_operand:SI 0 "fpr_operand" "=f")
6224 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6225 (match_operand:SI 2 "uint5_operand" "I")
6226 (match_operand:SI 3 "const_int_operand" "n")]
6231 switch (INTVAL (operands[3]))
6234 case FRV_BUILTIN_MROTLI: return \"mrotli %1, %2, %0\";
6235 case FRV_BUILTIN_MROTRI: return \"mrotri %1, %2, %0\";
6238 fatal_insn (\"Bad media insn, mrot\", insn);
6240 [(set_attr "length" "4")
6241 (set_attr "type" "mrot")])
6243 ;; Dual shift halfword: type "msh"
6245 (define_expand "msllhi"
6246 [(set (match_operand:SI 0 "fpr_operand" "")
6247 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6248 (match_operand:SI 2 "uint4_operand" "")
6252 "operands[3] = GEN_INT (FRV_BUILTIN_MSLLHI);")
6254 (define_expand "msrlhi"
6255 [(set (match_operand:SI 0 "fpr_operand" "")
6256 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6257 (match_operand:SI 2 "uint4_operand" "")
6261 "operands[3] = GEN_INT (FRV_BUILTIN_MSRLHI);")
6263 (define_expand "msrahi"
6264 [(set (match_operand:SI 0 "fpr_operand" "")
6265 (unspec:SI [(match_operand:SI 1 "fpr_operand" "")
6266 (match_operand:SI 2 "uint4_operand" "")
6270 "operands[3] = GEN_INT (FRV_BUILTIN_MSRAHI);")
6272 (define_insn "*mshift"
6273 [(set (match_operand:SI 0 "fpr_operand" "=f")
6274 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6275 (match_operand:SI 2 "uint4_operand" "I")
6276 (match_operand:SI 3 "const_int_operand" "n")]
6281 switch (INTVAL (operands[3]))
6284 case FRV_BUILTIN_MSLLHI: return \"msllhi %1, %2, %0\";
6285 case FRV_BUILTIN_MSRLHI: return \"msrlhi %1, %2, %0\";
6286 case FRV_BUILTIN_MSRAHI: return \"msrahi %1, %2, %0\";
6289 fatal_insn (\"Bad media insn, mshift\", insn);
6291 [(set_attr "length" "4")
6292 (set_attr "type" "mshift")])
6294 ;; Expand halfword to word: type "mexpdhw"
6296 (define_insn "mexpdhw"
6297 [(set (match_operand:SI 0 "fpr_operand" "=f")
6298 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6299 (match_operand:SI 2 "uint1_operand" "I")]
6302 "mexpdhw %1, %2, %0"
6303 [(set_attr "length" "4")
6304 (set_attr "type" "mexpdhw")])
6306 (define_insn "*cond_exec_mexpdhw"
6308 (match_operator 0 "ccr_eqne_operator"
6309 [(match_operand 1 "cr_operand" "C")
6311 (set (match_operand:SI 2 "fpr_operand" "=f")
6312 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6313 (match_operand:SI 4 "uint1_operand" "I")]
6316 "cmexpdhw %3, %4, %2, %1, %e0"
6317 [(set_attr "length" "4")
6318 (set_attr "type" "mexpdhw")])
6320 ;; Expand halfword to double: type "mexpdhd"
6322 (define_insn "mexpdhd"
6323 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
6324 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6325 (match_operand:SI 2 "uint1_operand" "I")]
6328 "mexpdhd %1, %2, %0"
6329 [(set_attr "length" "4")
6330 (set_attr "type" "mexpdhd")])
6332 (define_insn "*cond_exec_mexpdhd"
6334 (match_operator 0 "ccr_eqne_operator"
6335 [(match_operand 1 "cr_operand" "C")
6337 (set (match_operand:DI 2 "even_fpr_operand" "=h")
6338 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6339 (match_operand:SI 4 "uint1_operand" "I")]
6342 "cmexpdhd %3, %4, %2, %1, %e0"
6343 [(set_attr "length" "4")
6344 (set_attr "type" "mexpdhd")])
6346 ;; FR cut: type "mwcut"
6348 (define_insn "mwcut"
6349 [(set (match_operand:SI 0 "fpr_operand" "=f")
6350 (unspec:SI [(match_operand:DI 1 "fpr_operand" "f")
6351 (match_operand:SI 2 "fpr_or_int6_operand" "fI")]
6354 "mwcut%i2 %1, %2, %0"
6355 [(set_attr "length" "4")
6356 (set_attr "type" "mwcut")])
6358 ;; Dual multiplication (halfword): type "mmulh"
6360 (define_expand "mmulhs"
6361 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6362 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6363 (match_operand:SI 2 "fpr_operand" "f")
6366 (set (match_operand:HI 3 "accg_operand" "=B")
6367 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6369 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHS);")
6371 (define_expand "mmulhu"
6372 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6373 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6374 (match_operand:SI 2 "fpr_operand" "f")
6377 (set (match_operand:HI 3 "accg_operand" "=B")
6378 (unspec:HI [(const_int 0)] UNSPEC_MMULH))])]
6380 "operands[4] = GEN_INT (FRV_BUILTIN_MMULHU);")
6382 (define_insn "*mmulh"
6383 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6384 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6385 (match_operand:SI 2 "fpr_operand" "f")
6386 (match_operand:SI 3 "const_int_operand" "n")]
6388 (set (match_operand:HI 4 "accg_operand" "=B")
6389 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]
6393 switch (INTVAL (operands[3]))
6396 case FRV_BUILTIN_MMULHS: return \"mmulhs %1, %2, %0\";
6397 case FRV_BUILTIN_MMULHU: return \"mmulhu %1, %2, %0\";
6400 fatal_insn (\"Bad media insn, mmulh\", insn);
6402 [(set_attr "length" "4")
6403 (set_attr "type" "mmulh")])
6405 (define_insn "*cond_exec_mmulh"
6407 (match_operator 0 "ccr_eqne_operator"
6408 [(match_operand 1 "cr_operand" "C")
6410 (parallel [(set (match_operand:DI 2 "even_acc_operand" "=b")
6411 (unspec:DI [(match_operand:SI 3 "fpr_operand" "f")
6412 (match_operand:SI 4 "fpr_operand" "f")
6413 (match_operand:SI 5 "const_int_operand" "n")]
6415 (set (match_operand:HI 6 "accg_operand" "=B")
6416 (unspec:HI [(const_int 0)] UNSPEC_MMULH))]))]
6420 switch (INTVAL (operands[5]))
6423 case FRV_BUILTIN_MMULHS: return \"cmmulhs %3, %4, %2, %1, %e0\";
6424 case FRV_BUILTIN_MMULHU: return \"cmmulhu %3, %4, %2, %1, %e0\";
6427 fatal_insn (\"Bad media insn, cond_exec_mmulh\", insn);
6429 [(set_attr "length" "4")
6430 (set_attr "type" "mmulh")])
6432 ;; Dual cross multiplication (halfword): type "mmulxh"
6434 (define_expand "mmulxhs"
6435 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6436 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6437 (match_operand:SI 2 "fpr_operand" "f")
6440 (set (match_operand:HI 3 "accg_operand" "=B")
6441 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6443 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHS);")
6445 (define_expand "mmulxhu"
6446 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6447 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6448 (match_operand:SI 2 "fpr_operand" "f")
6451 (set (match_operand:HI 3 "accg_operand" "=B")
6452 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))])]
6454 "operands[4] = GEN_INT (FRV_BUILTIN_MMULXHU);")
6456 (define_insn "*mmulxh"
6457 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6458 (unspec:DI [(match_operand:SI 1 "fpr_operand" "f")
6459 (match_operand:SI 2 "fpr_operand" "f")
6460 (match_operand:SI 3 "const_int_operand" "n")]
6462 (set (match_operand:HI 4 "accg_operand" "=B")
6463 (unspec:HI [(const_int 0)] UNSPEC_MMULXH))]
6467 switch (INTVAL (operands[3]))
6470 case FRV_BUILTIN_MMULXHS: return \"mmulxhs %1, %2, %0\";
6471 case FRV_BUILTIN_MMULXHU: return \"mmulxhu %1, %2, %0\";
6474 fatal_insn (\"Bad media insn, mmulxh\", insn);
6476 [(set_attr "length" "4")
6477 (set_attr "type" "mmulxh")])
6479 ;; Dual product-sum (halfword): type "mmach"
6481 (define_expand "mmachs"
6482 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6483 (unspec:DI [(match_dup 0)
6484 (match_operand:SI 1 "fpr_operand" "f")
6485 (match_operand:SI 2 "fpr_operand" "f")
6486 (match_operand:HI 3 "accg_operand" "+B")
6490 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6492 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHS);")
6494 (define_expand "mmachu"
6495 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6496 (unspec:DI [(match_dup 0)
6497 (match_operand:SI 1 "fpr_operand" "f")
6498 (match_operand:SI 2 "fpr_operand" "f")
6499 (match_operand:HI 3 "accg_operand" "+B")
6503 (unspec:HI [(const_int 0)] UNSPEC_MMACH))])]
6505 "operands[4] = GEN_INT (FRV_BUILTIN_MMACHU);")
6507 (define_insn "*mmach"
6508 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6509 (unspec:DI [(match_dup 0)
6510 (match_operand:SI 1 "fpr_operand" "f")
6511 (match_operand:SI 2 "fpr_operand" "f")
6512 (match_operand:HI 3 "accg_operand" "+B")
6513 (match_operand:SI 4 "const_int_operand" "n")]
6515 (set (match_dup 3) (unspec:HI [(const_int 0)] UNSPEC_MMACH))]
6519 switch (INTVAL (operands[4]))
6522 case FRV_BUILTIN_MMACHS: return \"mmachs %1, %2, %0\";
6523 case FRV_BUILTIN_MMACHU: return \"mmachu %1, %2, %0\";
6526 fatal_insn (\"Bad media insn, mmach\", insn);
6528 [(set_attr "length" "4")
6529 (set_attr "type" "mmach")])
6531 (define_insn "*cond_exec_mmach"
6533 (match_operator 0 "ccr_eqne_operator"
6534 [(match_operand 1 "cr_operand" "C")
6536 (parallel [(set (match_operand:DI 2 "even_acc_operand" "+b")
6537 (unspec:DI [(match_dup 2)
6538 (match_operand:SI 3 "fpr_operand" "f")
6539 (match_operand:SI 4 "fpr_operand" "f")
6540 (match_operand:HI 5 "accg_operand" "+B")
6541 (match_operand:SI 6 "const_int_operand" "n")]
6544 (unspec:HI [(const_int 0)] UNSPEC_MMACH))]))]
6548 switch (INTVAL (operands[6]))
6551 case FRV_BUILTIN_MMACHS: return \"cmmachs %3, %4, %2, %1, %e0\";
6552 case FRV_BUILTIN_MMACHU: return \"cmmachu %3, %4, %2, %1, %e0\";
6555 fatal_insn (\"Bad media insn, cond_exec_mmach\", insn);
6557 [(set_attr "length" "4")
6558 (set_attr "type" "mmach")])
6560 ;; Dual product-difference: type "mmrdh"
6562 (define_expand "mmrdhs"
6563 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6564 (unspec:DI [(match_dup 0)
6565 (match_operand:SI 1 "fpr_operand" "f")
6566 (match_operand:SI 2 "fpr_operand" "f")
6567 (match_operand:HI 3 "accg_operand" "+B")
6571 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6573 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHS);")
6575 (define_expand "mmrdhu"
6576 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "+b")
6577 (unspec:DI [(match_dup 0)
6578 (match_operand:SI 1 "fpr_operand" "f")
6579 (match_operand:SI 2 "fpr_operand" "f")
6580 (match_operand:HI 3 "accg_operand" "+B")
6584 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))])]
6586 "operands[4] = GEN_INT (FRV_BUILTIN_MMRDHU);")
6588 (define_insn "*mmrdh"
6589 [(set (match_operand:DI 0 "even_acc_operand" "+b")
6590 (unspec:DI [(match_dup 0)
6591 (match_operand:SI 1 "fpr_operand" "f")
6592 (match_operand:SI 2 "fpr_operand" "f")
6593 (match_operand:HI 3 "accg_operand" "+B")
6594 (match_operand:SI 4 "const_int_operand" "n")]
6597 (unspec:HI [(const_int 0)] UNSPEC_MMRDH))]
6601 switch (INTVAL (operands[4]))
6604 case FRV_BUILTIN_MMRDHS: return \"mmrdhs %1, %2, %0\";
6605 case FRV_BUILTIN_MMRDHU: return \"mmrdhu %1, %2, %0\";
6608 fatal_insn (\"Bad media insn, mrdh\", insn);
6610 [(set_attr "length" "4")
6611 (set_attr "type" "mmrdh")])
6613 ;; Quad multiply (halfword): type "mqmulh"
6615 (define_expand "mqmulhs"
6616 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6617 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6618 (match_operand:DI 2 "even_fpr_operand" "h")
6621 (set (match_operand:V4QI 3 "accg_operand" "=B")
6622 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6624 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHS);")
6626 (define_expand "mqmulhu"
6627 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6628 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6629 (match_operand:DI 2 "even_fpr_operand" "h")
6632 (set (match_operand:V4QI 3 "accg_operand" "=B")
6633 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))])]
6635 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULHU);")
6637 (define_insn "*mqmulh"
6638 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6639 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6640 (match_operand:DI 2 "even_fpr_operand" "h")
6641 (match_operand:SI 3 "const_int_operand" "n")]
6643 (set (match_operand:V4QI 4 "accg_operand" "=B")
6644 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]
6648 switch (INTVAL (operands[3]))
6651 case FRV_BUILTIN_MQMULHS: return \"mqmulhs %1, %2, %0\";
6652 case FRV_BUILTIN_MQMULHU: return \"mqmulhu %1, %2, %0\";
6655 fatal_insn (\"Bad media insn, mqmulh\", insn);
6657 [(set_attr "length" "4")
6658 (set_attr "type" "mqmulh")])
6660 (define_insn "*cond_exec_mqmulh"
6662 (match_operator 0 "ccr_eqne_operator"
6663 [(match_operand 1 "cr_operand" "C")
6665 (parallel [(set (match_operand:V4SI 2 "quad_acc_operand" "=A")
6666 (unspec:V4SI [(match_operand:DI 3 "even_fpr_operand" "h")
6667 (match_operand:DI 4 "even_fpr_operand" "h")
6668 (match_operand:SI 5 "const_int_operand" "n")]
6670 (set (match_operand:V4QI 6 "accg_operand" "=B")
6671 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULH))]))]
6675 switch (INTVAL (operands[5]))
6678 case FRV_BUILTIN_MQMULHS: return \"cmqmulhs %3, %4, %2, %1, %e0\";
6679 case FRV_BUILTIN_MQMULHU: return \"cmqmulhu %3, %4, %2, %1, %e0\";
6682 fatal_insn (\"Bad media insn, cond_exec_mqmulh\", insn);
6684 [(set_attr "length" "4")
6685 (set_attr "type" "mqmulh")])
6687 ;; Quad cross multiply (halfword): type "mqmulxh"
6689 (define_expand "mqmulxhs"
6690 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6691 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6692 (match_operand:DI 2 "even_fpr_operand" "h")
6695 (set (match_operand:V4QI 3 "accg_operand" "=B")
6696 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6698 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHS);")
6700 (define_expand "mqmulxhu"
6701 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6702 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6703 (match_operand:DI 2 "even_fpr_operand" "h")
6706 (set (match_operand:V4QI 3 "accg_operand" "=B")
6707 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))])]
6709 "operands[4] = GEN_INT (FRV_BUILTIN_MQMULXHU);")
6711 (define_insn "*mqmulxh"
6712 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
6713 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")
6714 (match_operand:DI 2 "even_fpr_operand" "h")
6715 (match_operand:SI 3 "const_int_operand" "n")]
6717 (set (match_operand:V4QI 4 "accg_operand" "=B")
6718 (unspec:V4QI [(const_int 0)] UNSPEC_MQMULXH))]
6722 switch (INTVAL (operands[3]))
6725 case FRV_BUILTIN_MQMULXHS: return \"mqmulxhs %1, %2, %0\";
6726 case FRV_BUILTIN_MQMULXHU: return \"mqmulxhu %1, %2, %0\";
6729 fatal_insn (\"Bad media insn, mqmulxh\", insn);
6731 [(set_attr "length" "4")
6732 (set_attr "type" "mqmulxh")])
6734 ;; Quad product-sum (halfword): type "mqmach"
6736 (define_expand "mqmachs"
6737 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6738 (unspec:V4SI [(match_dup 0)
6739 (match_operand:DI 1 "even_fpr_operand" "h")
6740 (match_operand:DI 2 "even_fpr_operand" "h")
6741 (match_operand:V4QI 3 "accg_operand" "+B")
6745 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6747 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHS);")
6749 (define_expand "mqmachu"
6750 [(parallel [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6751 (unspec:V4SI [(match_dup 0)
6752 (match_operand:DI 1 "even_fpr_operand" "h")
6753 (match_operand:DI 2 "even_fpr_operand" "h")
6754 (match_operand:V4QI 3 "accg_operand" "+B")
6758 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))])]
6760 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACHU);")
6762 (define_insn "*mqmach"
6763 [(set (match_operand:V4SI 0 "even_acc_operand" "+A")
6764 (unspec:V4SI [(match_dup 0)
6765 (match_operand:DI 1 "even_fpr_operand" "h")
6766 (match_operand:DI 2 "even_fpr_operand" "h")
6767 (match_operand:V4QI 3 "accg_operand" "+B")
6768 (match_operand:SI 4 "const_int_operand" "n")]
6771 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]
6775 switch (INTVAL (operands[4]))
6778 case FRV_BUILTIN_MQMACHS: return \"mqmachs %1, %2, %0\";
6779 case FRV_BUILTIN_MQMACHU: return \"mqmachu %1, %2, %0\";
6782 fatal_insn (\"Bad media insn, mqmach\", insn);
6784 [(set_attr "length" "4")
6785 (set_attr "type" "mqmach")])
6787 (define_insn "*cond_exec_mqmach"
6789 (match_operator 0 "ccr_eqne_operator"
6790 [(match_operand 1 "cr_operand" "C")
6792 (parallel [(set (match_operand:V4SI 2 "even_acc_operand" "+A")
6793 (unspec:V4SI [(match_dup 2)
6794 (match_operand:DI 3 "even_fpr_operand" "h")
6795 (match_operand:DI 4 "even_fpr_operand" "h")
6796 (match_operand:V4QI 5 "accg_operand" "+B")
6797 (match_operand:SI 6 "const_int_operand" "n")]
6800 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH))]))]
6804 switch (INTVAL (operands[6]))
6807 case FRV_BUILTIN_MQMACHS: return \"cmqmachs %3, %4, %2, %1, %e0\";
6808 case FRV_BUILTIN_MQMACHU: return \"cmqmachu %3, %4, %2, %1, %e0\";
6811 fatal_insn (\"Bad media insn, cond_exec_mqmach\", insn);
6813 [(set_attr "length" "4")
6814 (set_attr "type" "mqmach")])
6816 ;; Dual complex number product-sum (halfword)
6818 (define_expand "mcpxrs"
6819 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6820 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6821 (match_operand:SI 2 "fpr_operand" "f")
6824 (set (match_operand:QI 3 "accg_operand" "=B")
6825 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6827 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRS);")
6829 (define_expand "mcpxru"
6830 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6831 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6832 (match_operand:SI 2 "fpr_operand" "f")
6835 (set (match_operand:QI 3 "accg_operand" "=B")
6836 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6838 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXRU);")
6840 (define_expand "mcpxis"
6841 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6842 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6843 (match_operand:SI 2 "fpr_operand" "f")
6846 (set (match_operand:QI 3 "accg_operand" "=B")
6847 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6849 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIS);")
6851 (define_expand "mcpxiu"
6852 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6853 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6854 (match_operand:SI 2 "fpr_operand" "f")
6857 (set (match_operand:QI 3 "accg_operand" "=B")
6858 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6860 "operands[4] = GEN_INT (FRV_BUILTIN_MCPXIU);")
6862 (define_insn "*mcpx"
6863 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
6864 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
6865 (match_operand:SI 2 "fpr_operand" "f")
6866 (match_operand:SI 3 "const_int_operand" "n")]
6868 (set (match_operand:QI 4 "accg_operand" "=B")
6869 (unspec:QI [(const_int 0)] UNSPEC_MCPX))])]
6873 switch (INTVAL (operands[3]))
6876 case FRV_BUILTIN_MCPXRS: return \"mcpxrs %1, %2, %0\";
6877 case FRV_BUILTIN_MCPXRU: return \"mcpxru %1, %2, %0\";
6878 case FRV_BUILTIN_MCPXIS: return \"mcpxis %1, %2, %0\";
6879 case FRV_BUILTIN_MCPXIU: return \"mcpxiu %1, %2, %0\";
6882 fatal_insn (\"Bad media insn, mcpx\", insn);
6884 [(set_attr "length" "4")
6885 (set_attr "type" "mcpx")])
6887 (define_insn "*cond_exec_mcpx"
6889 (match_operator 0 "ccr_eqne_operator"
6890 [(match_operand 1 "cr_operand" "C")
6892 (parallel [(set (match_operand:SI 2 "acc_operand" "=a")
6893 (unspec:SI [(match_operand:SI 3 "fpr_operand" "f")
6894 (match_operand:SI 4 "fpr_operand" "f")
6895 (match_operand:SI 5 "const_int_operand" "n")]
6897 (set (match_operand:QI 6 "accg_operand" "=B")
6898 (unspec:QI [(const_int 0)] UNSPEC_MCPX))]))]
6902 switch (INTVAL (operands[5]))
6905 case FRV_BUILTIN_MCPXRS: return \"cmcpxrs %3, %4, %2, %1, %e0\";
6906 case FRV_BUILTIN_MCPXRU: return \"cmcpxru %3, %4, %2, %1, %e0\";
6907 case FRV_BUILTIN_MCPXIS: return \"cmcpxis %3, %4, %2, %1, %e0\";
6908 case FRV_BUILTIN_MCPXIU: return \"cmcpxiu %3, %4, %2, %1, %e0\";
6911 fatal_insn (\"Bad media insn, cond_exec_mcpx\", insn);
6913 [(set_attr "length" "4")
6914 (set_attr "type" "mcpx")])
6916 ;; Quad complex number product-sum (halfword): type "mqcpx"
6918 (define_expand "mqcpxrs"
6919 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6920 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6921 (match_operand:DI 2 "fpr_operand" "f")
6924 (set (match_operand:HI 3 "accg_operand" "=B")
6925 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6927 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRS);")
6929 (define_expand "mqcpxru"
6930 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6931 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6932 (match_operand:DI 2 "fpr_operand" "f")
6935 (set (match_operand:HI 3 "accg_operand" "=B")
6936 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6938 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXRU);")
6940 (define_expand "mqcpxis"
6941 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6942 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6943 (match_operand:DI 2 "fpr_operand" "f")
6946 (set (match_operand:HI 3 "accg_operand" "=B")
6947 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6949 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIS);")
6951 (define_expand "mqcpxiu"
6952 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "=b")
6953 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6954 (match_operand:DI 2 "fpr_operand" "f")
6957 (set (match_operand:HI 3 "accg_operand" "=B")
6958 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))])]
6960 "operands[4] = GEN_INT (FRV_BUILTIN_MQCPXIU);")
6962 (define_insn "*mqcpx"
6963 [(set (match_operand:DI 0 "even_acc_operand" "=b")
6964 (unspec:DI [(match_operand:DI 1 "fpr_operand" "f")
6965 (match_operand:DI 2 "fpr_operand" "f")
6966 (match_operand:SI 3 "const_int_operand" "n")]
6968 (set (match_operand:HI 4 "accg_operand" "=B")
6969 (unspec:HI [(const_int 0)] UNSPEC_MQCPX))]
6973 switch (INTVAL (operands[3]))
6976 case FRV_BUILTIN_MQCPXRS: return \"mqcpxrs %1, %2, %0\";
6977 case FRV_BUILTIN_MQCPXRU: return \"mqcpxru %1, %2, %0\";
6978 case FRV_BUILTIN_MQCPXIS: return \"mqcpxis %1, %2, %0\";
6979 case FRV_BUILTIN_MQCPXIU: return \"mqcpxiu %1, %2, %0\";
6982 fatal_insn (\"Bad media insn, mqcpx\", insn);
6984 [(set_attr "length" "4")
6985 (set_attr "type" "mqcpx")])
6989 (define_expand "mcut"
6990 [(set (match_operand:SI 0 "fpr_operand" "=f")
6991 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
6992 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
6993 (match_operand:QI 3 "accg_operand" "B")
6997 "operands[4] = GEN_INT (FRV_BUILTIN_MCUT);")
6999 (define_expand "mcutss"
7000 [(set (match_operand:SI 0 "fpr_operand" "=f")
7001 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7002 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7003 (match_operand:QI 3 "accg_operand" "B")
7007 "operands[4] = GEN_INT (FRV_BUILTIN_MCUTSS);")
7009 (define_insn "*mcut"
7010 [(set (match_operand:SI 0 "fpr_operand" "=f")
7011 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")
7012 (match_operand:SI 2 "fpr_or_int6_operand" "fI")
7013 (match_operand:QI 3 "accg_operand" "B")
7014 (match_operand:SI 4 "const_int_operand" "n")]
7019 switch (INTVAL (operands[4]))
7022 case FRV_BUILTIN_MCUT: return \"mcut%i2 %1, %2, %0\";
7023 case FRV_BUILTIN_MCUTSS: return \"mcutss%i2 %1, %2, %0\";
7026 fatal_insn (\"Bad media insn, mcut\", insn);
7028 [(set_attr "length" "4")
7029 (set_attr "type" "mcut")])
7031 ;; Accumulator read: type "mrdacc"
7033 (define_insn "mrdacc"
7034 [(set (match_operand:SI 0 "fpr_operand" "=f")
7035 (unspec:SI [(match_operand:SI 1 "acc_operand" "a")] UNSPEC_MRDACC))]
7038 [(set_attr "length" "4")
7039 (set_attr "type" "mrdacc")])
7041 (define_insn "mrdaccg"
7042 [(set (match_operand:SI 0 "fpr_operand" "=f")
7043 (unspec:SI [(match_operand:QI 1 "accg_operand" "B")] UNSPEC_MRDACCG))]
7046 [(set_attr "length" "4")
7047 (set_attr "type" "mrdacc")])
7049 ;; Accumulator write: type "mwtacc"
7051 (define_insn "mwtacc"
7052 [(set (match_operand:SI 0 "acc_operand" "=a")
7053 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACC))]
7056 [(set_attr "length" "4")
7057 (set_attr "type" "mwtacc")])
7059 (define_insn "mwtaccg"
7060 [(set (match_operand:QI 0 "accg_operand" "=B")
7061 (unspec:QI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MWTACCG))]
7064 [(set_attr "length" "4")
7065 (set_attr "type" "mwtacc")])
7067 ;; Trap: This one executes on the control unit, not the media units.
7069 (define_insn "mtrap"
7070 [(unspec_volatile [(const_int 0)] UNSPEC_MTRAP)]
7073 [(set_attr "length" "4")
7074 (set_attr "type" "trap")])
7076 ;; Clear single accumulator: type "mclracc"
7078 (define_insn "mclracc_internal"
7079 [(set (match_operand:SI 0 "acc_operand" "=a")
7080 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7081 (set (match_operand:QI 1 "accg_operand" "=B")
7082 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))]
7085 [(set_attr "length" "4")
7086 (set_attr "type" "mclracc")])
7088 (define_expand "mclracc"
7089 [(parallel [(set (match_operand:SI 0 "acc_operand" "=a")
7090 (unspec:SI [(const_int 0)] UNSPEC_MCLRACC))
7092 (unspec:QI [(const_int 0)] UNSPEC_MCLRACC))])]
7096 if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
7099 operands[1] = frv_matching_accg_for_acc (operands[0]);
7102 ;; Clear all accumulators: type "mclracca"
7104 (define_insn "mclracca8_internal"
7105 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7106 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7107 (set (match_operand:V4SI 1 "quad_acc_operand" "=b")
7108 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7109 (set (match_operand:V4QI 2 "accg_operand" "=B")
7110 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7111 (set (match_operand:V4QI 3 "accg_operand" "=B")
7112 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7113 "TARGET_MEDIA && TARGET_ACC_8"
7115 [(set_attr "length" "4")
7116 (set_attr "type" "mclracca")])
7118 (define_insn "mclracca4_internal"
7119 [(set (match_operand:V4SI 0 "quad_acc_operand" "=b")
7120 (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7121 (set (match_operand:V4QI 1 "accg_operand" "=B")
7122 (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))]
7123 "TARGET_MEDIA && TARGET_ACC_4"
7125 [(set_attr "length" "4")
7126 (set_attr "type" "mclracca")])
7128 (define_expand "mclracca8"
7129 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7130 (set (match_dup 1) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7131 (set (match_dup 2) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))
7132 (set (match_dup 3) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7133 "TARGET_MEDIA && TARGET_ACC_8"
7136 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7137 operands[1] = gen_rtx_REG (V4SImode, ACC_FIRST + (~3 & ACC_MASK));
7138 operands[2] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7139 operands[3] = gen_rtx_REG (V4QImode, ACCG_FIRST + (~3 & ACC_MASK));
7142 (define_expand "mclracca4"
7143 [(parallel [(set (match_dup 0) (unspec:V4SI [(const_int 0)] UNSPEC_MCLRACCA))
7144 (set (match_dup 1) (unspec:V4QI [(const_int 0)] UNSPEC_MCLRACCA))])]
7145 "TARGET_MEDIA && TARGET_ACC_4"
7148 operands[0] = gen_rtx_REG (V4SImode, ACC_FIRST);
7149 operands[1] = gen_rtx_REG (V4QImode, ACCG_FIRST);
7152 (define_insn "mcop1"
7153 [(set (match_operand:SI 0 "fpr_operand" "=f")
7154 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7155 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP1))]
7158 [(set_attr "length" "4")
7159 ;; What is the class of the insn ???
7160 (set_attr "type" "multi")])
7162 (define_insn "mcop2"
7163 [(set (match_operand:SI 0 "fpr_operand" "=f")
7164 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")
7165 (match_operand:SI 2 "fpr_operand" "f")] UNSPEC_MCOP2))]
7168 [(set_attr "length" "4")
7169 ;; What is the class of the insn ???
7170 (set_attr "type" "multi")])
7172 (define_insn "*mdunpackh_internal"
7173 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7174 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7175 UNSPEC_MDUNPACKH_INTERNAL))]
7178 [(set_attr "length" "4")
7179 (set_attr "type" "mdunpackh")])
7181 (define_insn_and_split "mdunpackh"
7182 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7183 (unspec:V4SI [(match_operand:DI 1 "even_fpr_operand" "h")]
7185 (clobber (match_scratch:V4SI 2 "=x"))]
7190 (unspec:V4SI [(match_dup 1)] UNSPEC_MDUNPACKH_INTERNAL))
7197 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7198 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7199 operands[5] = frv_index_memory (operands[0], DImode, 1);
7200 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7202 [(set_attr "length" "20")
7203 (set_attr "type" "multi")])
7205 (define_insn "*mbtohe_internal"
7206 [(set (match_operand:V4SI 0 "quad_fpr_operand" "=x")
7207 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7208 UNSPEC_MBTOHE_INTERNAL))]
7211 [(set_attr "length" "4")
7212 (set_attr "type" "mbhconve")])
7214 (define_insn_and_split "mbtohe"
7215 [(set (match_operand:V4SI 0 "memory_operand" "=o")
7216 (unspec:V4SI [(match_operand:SI 1 "fpr_operand" "f")]
7218 (clobber (match_scratch:V4SI 2 "=x"))]
7223 (unspec:V4SI [(match_dup 1)] UNSPEC_MBTOHE_INTERNAL))
7230 operands[3] = change_address (operands[0], DImode, NULL_RTX);
7231 operands[4] = gen_rtx_REG (DImode, REGNO (operands[2]));
7232 operands[5] = frv_index_memory (operands[0], DImode, 1);
7233 operands[6] = gen_rtx_REG (DImode, REGNO (operands[2])+2);
7235 [(set_attr "length" "20")
7236 (set_attr "type" "multi")])
7238 ;; Quad product-sum (halfword) instructions only found on the FR400.
7241 (define_expand "mqxmachs"
7242 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7243 (unspec:V4SI [(match_dup 0)
7244 (match_operand:DI 1 "even_fpr_operand" "")
7245 (match_operand:DI 2 "even_fpr_operand" "")
7246 (match_operand:V4QI 3 "accg_operand" "")
7250 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7252 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACHS);")
7254 (define_expand "mqxmacxhs"
7255 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7256 (unspec:V4SI [(match_dup 0)
7257 (match_operand:DI 1 "even_fpr_operand" "")
7258 (match_operand:DI 2 "even_fpr_operand" "")
7259 (match_operand:V4QI 3 "accg_operand" "")
7263 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7265 "operands[4] = GEN_INT (FRV_BUILTIN_MQXMACXHS);")
7267 (define_expand "mqmacxhs"
7268 [(parallel [(set (match_operand:V4SI 0 "quad_acc_operand" "")
7269 (unspec:V4SI [(match_dup 0)
7270 (match_operand:DI 1 "even_fpr_operand" "")
7271 (match_operand:DI 2 "even_fpr_operand" "")
7272 (match_operand:V4QI 3 "accg_operand" "")
7276 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))])]
7278 "operands[4] = GEN_INT (FRV_BUILTIN_MQMACXHS);")
7280 (define_insn "*mqmach2"
7281 [(set (match_operand:V4SI 0 "quad_acc_operand" "+A")
7282 (unspec:V4SI [(match_dup 0)
7283 (match_operand:DI 1 "even_fpr_operand" "h")
7284 (match_operand:DI 2 "even_fpr_operand" "h")
7285 (match_operand:V4QI 3 "accg_operand" "+B")
7286 (match_operand:SI 4 "const_int_operand" "n")]
7289 (unspec:V4QI [(const_int 0)] UNSPEC_MQMACH2))]
7293 switch (INTVAL (operands[4]))
7296 case FRV_BUILTIN_MQXMACHS: return \"mqxmachs %1, %2, %0\";
7297 case FRV_BUILTIN_MQXMACXHS: return \"mqxmacxhs %1, %2, %0\";
7298 case FRV_BUILTIN_MQMACXHS: return \"mqmacxhs %1, %2, %0\";
7301 fatal_insn (\"Bad media insn, mqmach2\", insn);
7303 [(set_attr "length" "4")
7304 (set_attr "type" "mqmach")])
7306 ;; Accumulator addition/subtraction: type "maddacc"
7308 (define_expand "maddaccs"
7309 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7310 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7312 (set (match_operand:QI 2 "accg_operand" "")
7313 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7317 "operands[4] = GEN_INT (FRV_BUILTIN_MADDACCS);")
7319 (define_expand "msubaccs"
7320 [(parallel [(set (match_operand:SI 0 "acc_operand" "")
7321 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "")]
7323 (set (match_operand:QI 2 "accg_operand" "")
7324 (unspec:QI [(match_operand:HI 3 "accg_operand" "")
7328 "operands[4] = GEN_INT (FRV_BUILTIN_MSUBACCS);")
7330 (define_insn "masaccs"
7331 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7332 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")]
7334 (set (match_operand:HI 2 "accg_operand" "=B")
7335 (unspec:HI [(match_operand:HI 3 "accg_operand" "B")]
7339 [(set_attr "length" "4")
7340 (set_attr "type" "maddacc")])
7342 (define_insn "*maddacc"
7343 [(set (match_operand:SI 0 "acc_operand" "=a")
7344 (unspec:SI [(match_operand:DI 1 "even_acc_operand" "b")]
7346 (set (match_operand:QI 2 "accg_operand" "=B")
7347 (unspec:QI [(match_operand:HI 3 "accg_operand" "B")
7348 (match_operand:SI 4 "const_int_operand" "n")]
7353 switch (INTVAL (operands[4]))
7356 case FRV_BUILTIN_MADDACCS: return \"maddaccs %1, %0\";
7357 case FRV_BUILTIN_MSUBACCS: return \"msubaccs %1, %0\";
7360 fatal_insn (\"Bad media insn, maddacc\", insn);
7362 [(set_attr "length" "4")
7363 (set_attr "type" "maddacc")])
7365 ;; Dual accumulator addition/subtraction: type "mdaddacc"
7367 (define_expand "mdaddaccs"
7368 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7369 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7371 (set (match_operand:HI 2 "accg_operand" "")
7372 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7374 UNSPEC_MDADDACC))])]
7376 "operands[4] = GEN_INT (FRV_BUILTIN_MDADDACCS);")
7378 (define_expand "mdsubaccs"
7379 [(parallel [(set (match_operand:DI 0 "even_acc_operand" "")
7380 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "")]
7382 (set (match_operand:HI 2 "accg_operand" "")
7383 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "")
7385 UNSPEC_MDADDACC))])]
7387 "operands[4] = GEN_INT (FRV_BUILTIN_MDSUBACCS);")
7389 (define_insn "mdasaccs"
7390 [(set (match_operand:V4SI 0 "quad_acc_operand" "=A")
7391 (unspec:V4SI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7393 (set (match_operand:V4QI 2 "accg_operand" "=B")
7394 (unspec:V4QI [(match_operand:V4QI 3 "accg_operand" "B")]
7398 [(set_attr "length" "4")
7399 (set_attr "type" "mdaddacc")])
7401 (define_insn "*mdaddacc"
7402 [(set (match_operand:DI 0 "even_acc_operand" "=b")
7403 (unspec:DI [(match_operand:V4SI 1 "quad_acc_operand" "A")]
7405 (set (match_operand:HI 2 "accg_operand" "=B")
7406 (unspec:HI [(match_operand:V4QI 3 "accg_operand" "B")
7407 (match_operand:SI 4 "const_int_operand" "n")]
7412 switch (INTVAL (operands[4]))
7415 case FRV_BUILTIN_MDADDACCS: return \"mdaddaccs %1, %0\";
7416 case FRV_BUILTIN_MDSUBACCS: return \"mdsubaccs %1, %0\";
7419 fatal_insn (\"Bad media insn, mdaddacc\", insn);
7421 [(set_attr "length" "4")
7422 (set_attr "type" "mdaddacc")])
7424 ;; Dual absolute (halfword): type "mabsh"
7426 (define_insn "mabshs"
7427 [(set (match_operand:SI 0 "fpr_operand" "=f")
7428 (unspec:SI [(match_operand:SI 1 "fpr_operand" "f")] UNSPEC_MABSHS))]
7431 [(set_attr "length" "4")
7432 (set_attr "type" "mabsh")])
7434 ;; Dual rotate: type "mdrot"
7436 (define_insn "mdrotli"
7437 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7438 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7439 (match_operand:SI 2 "uint5_operand" "I")]
7442 "mdrotli %1, %2, %0"
7443 [(set_attr "length" "4")
7444 (set_attr "type" "mdrot")])
7446 ;; Dual coupling (concatenation): type "mcpl"
7448 (define_insn "mcplhi"
7449 [(set (match_operand:SI 0 "fpr_operand" "=f")
7450 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7451 (match_operand:SI 2 "uint4_operand" "I")]
7455 [(set_attr "length" "4")
7456 (set_attr "type" "mcpl")])
7458 (define_insn "mcpli"
7459 [(set (match_operand:SI 0 "fpr_operand" "=f")
7460 (unspec:SI [(match_operand:DI 1 "fpr_operand" "h")
7461 (match_operand:SI 2 "uint5_operand" "I")]
7465 [(set_attr "length" "4")
7466 (set_attr "type" "mcpl")])
7468 ;; Dual cut: type "mdcut"
7470 (define_insn "mdcutssi"
7471 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7472 (unspec:DI [(match_operand:DI 1 "even_acc_operand" "b")
7473 (match_operand:SI 2 "int6_operand" "I")
7474 (match_operand:HI 3 "accg_operand" "B")]
7477 "mdcutssi %1, %2, %0"
7478 [(set_attr "length" "4")
7479 (set_attr "type" "mdcut")])
7481 ;; Quad saturate (halfword): type "mqsath"
7483 (define_insn "mqsaths"
7484 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7485 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7486 (match_operand:DI 2 "even_fpr_operand" "h")]
7489 "mqsaths %1, %2, %0"
7490 [(set_attr "length" "4")
7491 (set_attr "type" "mqsath")])
7493 ;; Quad limit instructions: type "mqlimh"
7495 (define_insn "mqlclrhs"
7496 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7497 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7498 (match_operand:DI 2 "even_fpr_operand" "h")]
7500 "TARGET_MEDIA_FR450"
7501 "mqlclrhs %1, %2, %0"
7502 [(set_attr "length" "4")
7503 (set_attr "type" "mqlimh")])
7505 (define_insn "mqlmths"
7506 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7507 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7508 (match_operand:DI 2 "even_fpr_operand" "h")]
7510 "TARGET_MEDIA_FR450"
7511 "mqlmths %1, %2, %0"
7512 [(set_attr "length" "4")
7513 (set_attr "type" "mqlimh")])
7515 (define_insn "mqsllhi"
7516 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7517 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7518 (match_operand:SI 2 "int6_operand" "I")]
7520 "TARGET_MEDIA_FR450"
7521 "mqsllhi %1, %2, %0"
7522 [(set_attr "length" "4")
7523 (set_attr "type" "mqshift")])
7525 (define_insn "mqsrahi"
7526 [(set (match_operand:DI 0 "even_fpr_operand" "=h")
7527 (unspec:DI [(match_operand:DI 1 "even_fpr_operand" "h")
7528 (match_operand:SI 2 "int6_operand" "I")]
7530 "TARGET_MEDIA_FR450"
7531 "mqsrahi %1, %2, %0"
7532 [(set_attr "length" "4")
7533 (set_attr "type" "mqshift")])
7535 ;; Set hi/lo instructions: type "mset"
7537 (define_insn "mhsetlos"
7538 [(set (match_operand:SI 0 "fpr_operand" "=f")
7539 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7540 (match_operand:SI 2 "int12_operand" "NOP")]
7544 [(set_attr "length" "4")
7545 (set_attr "type" "mset")])
7547 (define_insn "mhsetloh"
7548 [(set (match_operand:SI 0 "fpr_operand" "=f")
7549 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7550 (match_operand:SI 2 "int5_operand" "I")]
7554 [(set_attr "length" "4")
7555 (set_attr "type" "mset")])
7557 (define_insn "mhsethis"
7558 [(set (match_operand:SI 0 "fpr_operand" "=f")
7559 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7560 (match_operand:SI 2 "int12_operand" "NOP")]
7564 [(set_attr "length" "4")
7565 (set_attr "type" "mset")])
7567 (define_insn "mhsethih"
7568 [(set (match_operand:SI 0 "fpr_operand" "=f")
7569 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7570 (match_operand:SI 2 "int5_operand" "I")]
7574 [(set_attr "length" "4")
7575 (set_attr "type" "mset")])
7577 (define_insn "mhdsets"
7578 [(set (match_operand:SI 0 "fpr_operand" "=f")
7579 (unspec:SI [(match_operand:SI 1 "int12_operand" "NOP")]
7583 [(set_attr "length" "4")
7584 (set_attr "type" "mset")])
7586 (define_insn "mhdseth"
7587 [(set (match_operand:SI 0 "fpr_operand" "=f")
7588 (unspec:SI [(match_operand:SI 1 "fpr_operand" "0")
7589 (match_operand:SI 2 "int5_operand" "I")]
7593 [(set_attr "length" "4")
7594 (set_attr "type" "mset")])
7596 ;;-----------------------------------------------------------------------------
7598 (define_expand "symGOT2reg"
7599 [(match_operand:SI 0 "" "")
7600 (match_operand:SI 1 "" "")
7601 (match_operand:SI 2 "" "")
7602 (match_operand:SI 3 "" "")]
7608 insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7610 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7612 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7617 (define_expand "symGOT2reg_i"
7618 [(set (match_operand:SI 0 "" "")
7619 (mem:SI (plus:SI (match_operand:SI 2 "" "")
7620 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7621 (match_operand:SI 3 "" "")]
7626 (define_expand "symGOT2reg_hilo"
7628 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7629 (match_dup 4)] UNSPEC_GOT))))
7631 (lo_sum:SI (match_dup 6)
7632 (const:SI (unspec:SI [(match_dup 1)
7633 (match_operand:SI 3 "" "")]
7635 (set (match_operand:SI 0 "" "")
7636 (mem:SI (plus:SI (match_dup 5)
7637 (match_operand:SI 2 "" ""))))
7642 if (!can_create_pseudo_p ())
7643 operands[6] = operands[5] = operands[0];
7646 operands[6] = gen_reg_rtx (SImode);
7647 operands[5] = gen_reg_rtx (SImode);
7650 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7651 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7654 (define_expand "symGOTOFF2reg_hilo"
7656 (high:SI (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7657 (match_dup 4)] UNSPEC_GOT))))
7659 (lo_sum:SI (match_dup 6)
7660 (const:SI (unspec:SI [(match_dup 1)
7661 (match_operand:SI 3 "" "")]
7663 (set (match_operand:SI 0 "" "")
7664 (plus:SI (match_dup 5)
7665 (match_operand:SI 2 "" "")))
7670 if (!can_create_pseudo_p ())
7671 operands[6] = operands[5] = operands[0];
7674 operands[6] = gen_reg_rtx (SImode);
7675 operands[5] = gen_reg_rtx (SImode);
7678 operands[4] = GEN_INT (INTVAL (operands[3]) + 1);
7679 operands[3] = GEN_INT (INTVAL (operands[3]) + 2);
7682 (define_expand "symGOTOFF2reg"
7683 [(match_operand:SI 0 "" "")
7684 (match_operand:SI 1 "" "")
7685 (match_operand:SI 2 "" "")
7686 (match_operand:SI 3 "" "")]
7690 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3]));
7692 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7697 (define_expand "symGOTOFF2reg_i"
7698 [(set (match_operand:SI 0 "" "")
7699 (plus:SI (match_operand:SI 2 "" "")
7701 (unspec:SI [(match_operand:SI 1 "" "")
7702 (match_operand:SI 3 "" "")]
7707 (define_expand "symGPREL2reg"
7708 [(match_operand:SI 0 "" "")
7709 (match_operand:SI 1 "" "")
7710 (match_operand:SI 2 "" "")
7711 (match_operand:SI 3 "" "")
7718 if (!can_create_pseudo_p ())
7719 operands[4] = operands[0];
7721 operands[4] = gen_reg_rtx (SImode);
7723 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7725 insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7726 operands[4], operands[3]));
7728 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7733 (define_expand "symGPREL2reg_hilo"
7734 [(match_operand:SI 0 "" "")
7735 (match_operand:SI 1 "" "")
7736 (match_operand:SI 2 "" "")
7737 (match_operand:SI 3 "" "")
7744 if (!can_create_pseudo_p ())
7746 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
7747 GEN_INT (R_FRV_GOT12)));
7751 operands[4] = gen_reg_rtx (SImode);
7753 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7755 insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
7756 operands[4], operands[3]));
7758 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7774 (UNSPEC_PREFETCH0 163)
7775 (UNSPEC_PREFETCH 164)
7776 (UNSPEC_IACCreadll 165)
7777 (UNSPEC_IACCreadl 166)
7778 (UNSPEC_IACCsetll 167)
7779 (UNSPEC_IACCsetl 168)
7788 [(set (match_operand:DI 0 "integer_register_operand" "=d")
7789 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
7790 (match_operand:SI 2 "integer_register_operand" "d")]
7794 [(set_attr "length" "4")
7795 (set_attr "type" "mul")])
7798 [(set (match_operand:DI 0 "integer_register_operand" "=d")
7799 (unspec:DI [(match_operand:SI 1 "integer_register_operand" "d")
7800 (match_operand:SI 2 "integer_register_operand" "d")]
7804 [(set_attr "length" "4")
7805 (set_attr "type" "mul")])
7807 (define_insn "smass"
7808 [(set (reg:DI IACC0_REG)
7809 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7810 (match_operand:SI 1 "integer_register_operand" "d")
7813 "TARGET_FR405_BUILTINS"
7815 [(set_attr "length" "4")
7816 (set_attr "type" "macc")])
7818 (define_insn "smsss"
7819 [(set (reg:DI IACC0_REG)
7820 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7821 (match_operand:SI 1 "integer_register_operand" "d")
7824 "TARGET_FR405_BUILTINS"
7826 [(set_attr "length" "4")
7827 (set_attr "type" "macc")])
7830 [(set (reg:DI IACC0_REG)
7831 (unspec:DI [(match_operand:SI 0 "integer_register_operand" "d")
7832 (match_operand:SI 1 "integer_register_operand" "d")]
7834 "TARGET_FR405_BUILTINS"
7836 [(set_attr "length" "4")
7837 (set_attr "type" "macc")])
7839 (define_insn "addss"
7840 [(set (match_operand:SI 0 "integer_register_operand" "=d")
7841 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7842 (match_operand:SI 2 "integer_register_operand" "d")]
7844 "TARGET_FR405_BUILTINS"
7846 [(set_attr "length" "4")
7847 (set_attr "type" "int")])
7849 (define_insn "subss"
7850 [(set (match_operand:SI 0 "integer_register_operand" "=d")
7851 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7852 (match_operand:SI 2 "integer_register_operand" "d")]
7854 "TARGET_FR405_BUILTINS"
7856 [(set_attr "length" "4")
7857 (set_attr "type" "int")])
7859 (define_insn "slass"
7860 [(set (match_operand:SI 0 "integer_register_operand" "=d")
7861 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7862 (match_operand:SI 2 "integer_register_operand" "d")]
7864 "TARGET_FR405_BUILTINS"
7866 [(set_attr "length" "4")
7867 (set_attr "type" "int")])
7870 [(set (match_operand:SI 0 "integer_register_operand" "=d")
7871 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7872 (match_operand:SI 2 "integer_register_operand" "d")]
7876 [(set_attr "length" "4")
7877 (set_attr "type" "scan")])
7879 (define_insn "scutss"
7880 [(set (match_operand:SI 0 "integer_register_operand" "=d")
7881 (unspec:SI [(match_operand:SI 1 "integer_register_operand" "d")
7884 "TARGET_FR405_BUILTINS"
7886 [(set_attr "length" "4")
7887 (set_attr "type" "cut")])
7889 (define_insn "frv_prefetch0"
7890 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
7896 [(set_attr "length" "4")])
7898 (define_insn "frv_prefetch"
7899 [(prefetch (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
7903 "TARGET_FR500_FR550_BUILTINS"
7904 "nop.p\\n\\tnldub @(%0, gr0), gr0"
7905 [(set_attr "length" "8")])
7909 (define_insn "call_gettlsoff"
7910 [(set (match_operand:SI 0 "register_operand" "=D09")
7912 [(match_operand:SI 1 "symbolic_operand" "")]
7914 (clobber (reg:SI GR8_REG))
7915 (clobber (reg:SI LRREG))
7916 (use (match_operand:SI 2 "register_operand" "D15"))]
7918 "call #gettlsoff(%a1)"
7919 [(set_attr "length" "4")
7920 (set_attr "type" "load_or_call")])
7922 ;; We have to expand this like a libcall (it sort of actually is)
7923 ;; because otherwise sched may move, for example, an insn that sets up
7924 ;; GR8 for a subsequence call before the *tls_indirect_call insn, and
7925 ;; then reload won't be able to fix things up.
7926 (define_expand "tls_indirect_call"
7927 [(set (reg:DI GR8_REG)
7928 (match_operand:DI 2 "register_operand" ""))
7930 [(set (reg:SI GR9_REG)
7932 [(match_operand:SI 1 "symbolic_operand" "")
7934 UNSPEC_TLS_INDIRECT_CALL))
7935 (clobber (reg:SI GR8_REG))
7936 (clobber (reg:SI LRREG))
7937 (use (match_operand:SI 3 "register_operand" ""))])
7938 (set (match_operand:SI 0 "register_operand" "")
7942 (define_insn "*tls_indirect_call"
7943 [(set (reg:SI GR9_REG)
7945 [(match_operand:SI 0 "symbolic_operand" "")
7947 UNSPEC_TLS_INDIRECT_CALL))
7948 (clobber (reg:SI GR8_REG))
7949 (clobber (reg:SI LRREG))
7950 ;; If there was a way to represent the fact that we don't need GR9
7951 ;; or GR15 to be set before this instruction (it could be in
7952 ;; parallel), we could use it here. This change wouldn't apply to
7953 ;; call_gettlsoff, thought, since the linker may turn the latter
7954 ;; into ldi @(gr15,offset),gr9.
7955 (use (match_operand:SI 1 "register_operand" "D15"))]
7957 "calll #gettlsoff(%a0)@(gr8,gr0)"
7958 [(set_attr "length" "4")
7959 (set_attr "type" "jumpl")])
7961 (define_insn "tls_load_gottlsoff12"
7962 [(set (match_operand:SI 0 "register_operand" "=r")
7964 [(match_operand:SI 1 "symbolic_operand" "")
7965 (match_operand:SI 2 "register_operand" "r")]
7966 UNSPEC_TLS_LOAD_GOTTLSOFF12))]
7968 "ldi @(%2, #gottlsoff12(%1)), %0"
7969 [(set_attr "length" "4")])
7971 (define_expand "tlsoff_hilo"
7972 [(set (match_operand:SI 0 "register_operand" "=r")
7973 (high:SI (const:SI (unspec:SI
7974 [(match_operand:SI 1 "symbolic_operand" "")
7975 (match_operand:SI 2 "immediate_operand" "n")]
7978 (lo_sum:SI (match_dup 0)
7979 (const:SI (unspec:SI [(match_dup 1)
7980 (match_dup 3)] UNSPEC_GOT))))]
7984 operands[3] = GEN_INT (INTVAL (operands[2]) + 1);
7987 ;; Just like movdi_ldd, but with relaxation annotations.
7988 (define_insn "tls_tlsdesc_ldd"
7989 [(set (match_operand:DI 0 "register_operand" "=r")
7990 (unspec:DI [(mem:DI (unspec:SI
7991 [(match_operand:SI 1 "register_operand" "r")
7992 (match_operand:SI 2 "register_operand" "r")
7993 (match_operand:SI 3 "symbolic_operand" "")]
7994 UNSPEC_TLS_TLSDESC_LDD_AUX))]
7995 UNSPEC_TLS_TLSDESC_LDD))]
7997 "ldd #tlsdesc(%a3)@(%1,%2), %0"
7998 [(set_attr "length" "4")
7999 (set_attr "type" "gload")])
8001 (define_insn "tls_tlsoff_ld"
8002 [(set (match_operand:SI 0 "register_operand" "=r")
8004 [(match_operand:SI 1 "register_operand" "r")
8005 (match_operand:SI 2 "register_operand" "r")
8006 (match_operand:SI 3 "symbolic_operand" "")]
8007 UNSPEC_TLS_TLSOFF_LD)))]
8009 "ld #tlsoff(%a3)@(%1,%2), %0"
8010 [(set_attr "length" "4")
8011 (set_attr "type" "gload")])
8013 (define_insn "tls_lddi"
8014 [(set (match_operand:DI 0 "register_operand" "=r")
8015 (unspec:DI [(match_operand:SI 1 "symbolic_operand" "")
8016 (match_operand:SI 2 "register_operand" "d")]
8019 "lddi @(%2, #gottlsdesc12(%a1)), %0"
8020 [(set_attr "length" "4")
8021 (set_attr "type" "gload")])