1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
55 /* This is used for communication between ASM_OUTPUT_LABEL and
56 ASM_OUTPUT_LABELREF. */
57 int ia64_asm_output_label
= 0;
59 /* Define the information needed to generate branch and scc insns. This is
60 stored from the compare operation. */
61 struct rtx_def
* ia64_compare_op0
;
62 struct rtx_def
* ia64_compare_op1
;
64 /* Register names for ia64_expand_prologue. */
65 static const char * const ia64_reg_numbers
[96] =
66 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
67 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
68 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
69 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
70 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
71 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
72 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
73 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
74 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
75 "r104","r105","r106","r107","r108","r109","r110","r111",
76 "r112","r113","r114","r115","r116","r117","r118","r119",
77 "r120","r121","r122","r123","r124","r125","r126","r127"};
79 /* ??? These strings could be shared with REGISTER_NAMES. */
80 static const char * const ia64_input_reg_names
[8] =
81 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_local_reg_names
[80] =
85 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
86 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
87 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
88 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
89 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
90 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
91 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
92 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
93 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
94 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
96 /* ??? These strings could be shared with REGISTER_NAMES. */
97 static const char * const ia64_output_reg_names
[8] =
98 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
100 /* String used with the -mfixed-range= option. */
101 const char *ia64_fixed_range_string
;
103 /* Determines whether we use adds, addl, or movl to generate our
104 TLS immediate offsets. */
105 int ia64_tls_size
= 22;
107 /* String used with the -mtls-size= option. */
108 const char *ia64_tls_size_string
;
110 /* Which cpu are we scheduling for. */
111 enum processor_type ia64_tune
;
113 /* String used with the -tune= option. */
114 const char *ia64_tune_string
;
116 /* Determines whether we run our final scheduling pass or not. We always
117 avoid the normal second scheduling pass. */
118 static int ia64_flag_schedule_insns2
;
120 /* Determines whether we run variable tracking in machine dependent
122 static int ia64_flag_var_tracking
;
124 /* Variables which are this size or smaller are put in the sdata/sbss
127 unsigned int ia64_section_threshold
;
129 /* The following variable is used by the DFA insn scheduler. The value is
130 TRUE if we do insn bundling instead of insn scheduling. */
133 /* Structure to be filled in by ia64_compute_frame_size with register
134 save masks and offsets for the current function. */
136 struct ia64_frame_info
138 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
139 the caller's scratch area. */
140 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
141 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
142 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
143 HARD_REG_SET mask
; /* mask of saved registers. */
144 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
145 registers or long-term scratches. */
146 int n_spilled
; /* number of spilled registers. */
147 int reg_fp
; /* register for fp. */
148 int reg_save_b0
; /* save register for b0. */
149 int reg_save_pr
; /* save register for prs. */
150 int reg_save_ar_pfs
; /* save register for ar.pfs. */
151 int reg_save_ar_unat
; /* save register for ar.unat. */
152 int reg_save_ar_lc
; /* save register for ar.lc. */
153 int reg_save_gp
; /* save register for gp. */
154 int n_input_regs
; /* number of input registers used. */
155 int n_local_regs
; /* number of local registers used. */
156 int n_output_regs
; /* number of output registers used. */
157 int n_rotate_regs
; /* number of rotating registers used. */
159 char need_regstk
; /* true if a .regstk directive needed. */
160 char initialized
; /* true if the data is finalized. */
163 /* Current frame information calculated by ia64_compute_frame_size. */
164 static struct ia64_frame_info current_frame_info
;
166 static int ia64_use_dfa_pipeline_interface (void);
167 static int ia64_first_cycle_multipass_dfa_lookahead (void);
168 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
169 static void ia64_init_dfa_pre_cycle_insn (void);
170 static rtx
ia64_dfa_pre_cycle_insn (void);
171 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
173 static rtx
gen_tls_get_addr (void);
174 static rtx
gen_thread_pointer (void);
175 static rtx
ia64_expand_tls_address (enum tls_model
, rtx
, rtx
);
176 static int find_gr_spill (int);
177 static int next_scratch_gr_reg (void);
178 static void mark_reg_gr_used_mask (rtx
, void *);
179 static void ia64_compute_frame_size (HOST_WIDE_INT
);
180 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
181 static void finish_spill_pointers (void);
182 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
183 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
184 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
185 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
186 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
187 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
189 static enum machine_mode
hfa_element_mode (tree
, int);
190 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
192 static bool ia64_function_ok_for_sibcall (tree
, tree
);
193 static bool ia64_return_in_memory (tree
, tree
);
194 static bool ia64_rtx_costs (rtx
, int, int, int *);
195 static void fix_range (const char *);
196 static struct machine_function
* ia64_init_machine_status (void);
197 static void emit_insn_group_barriers (FILE *);
198 static void emit_all_insn_group_barriers (FILE *);
199 static void final_emit_insn_group_barriers (FILE *);
200 static void emit_predicate_relation_info (void);
201 static void ia64_reorg (void);
202 static bool ia64_in_small_data_p (tree
);
203 static void process_epilogue (void);
204 static int process_set (FILE *, rtx
);
206 static rtx
ia64_expand_fetch_and_op (optab
, enum machine_mode
, tree
, rtx
);
207 static rtx
ia64_expand_op_and_fetch (optab
, enum machine_mode
, tree
, rtx
);
208 static rtx
ia64_expand_compare_and_swap (enum machine_mode
, enum machine_mode
,
210 static rtx
ia64_expand_lock_test_and_set (enum machine_mode
, tree
, rtx
);
211 static rtx
ia64_expand_lock_release (enum machine_mode
, tree
, rtx
);
212 static bool ia64_assemble_integer (rtx
, unsigned int, int);
213 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
214 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
215 static void ia64_output_function_end_prologue (FILE *);
217 static int ia64_issue_rate (void);
218 static int ia64_adjust_cost (rtx
, rtx
, rtx
, int);
219 static void ia64_sched_init (FILE *, int, int);
220 static void ia64_sched_finish (FILE *, int);
221 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
222 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
223 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
224 static int ia64_variable_issue (FILE *, int, rtx
, int);
226 static struct bundle_state
*get_free_bundle_state (void);
227 static void free_bundle_state (struct bundle_state
*);
228 static void initiate_bundle_states (void);
229 static void finish_bundle_states (void);
230 static unsigned bundle_state_hash (const void *);
231 static int bundle_state_eq_p (const void *, const void *);
232 static int insert_bundle_state (struct bundle_state
*);
233 static void initiate_bundle_state_table (void);
234 static void finish_bundle_state_table (void);
235 static int try_issue_nops (struct bundle_state
*, int);
236 static int try_issue_insn (struct bundle_state
*, rtx
);
237 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
238 static int get_max_pos (state_t
);
239 static int get_template (state_t
, int);
241 static rtx
get_next_important_insn (rtx
, rtx
);
242 static void bundling (FILE *, int, rtx
, rtx
);
244 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
245 HOST_WIDE_INT
, tree
);
246 static void ia64_file_start (void);
248 static void ia64_select_rtx_section (enum machine_mode
, rtx
,
249 unsigned HOST_WIDE_INT
);
250 static void ia64_rwreloc_select_section (tree
, int, unsigned HOST_WIDE_INT
)
252 static void ia64_rwreloc_unique_section (tree
, int)
254 static void ia64_rwreloc_select_rtx_section (enum machine_mode
, rtx
,
255 unsigned HOST_WIDE_INT
)
257 static unsigned int ia64_rwreloc_section_type_flags (tree
, const char *, int)
260 static void ia64_hpux_add_extern_decl (tree decl
)
262 static void ia64_hpux_file_end (void)
264 static void ia64_init_libfuncs (void)
266 static void ia64_hpux_init_libfuncs (void)
268 static void ia64_vms_init_libfuncs (void)
271 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
272 static void ia64_encode_section_info (tree
, rtx
, int);
273 static rtx
ia64_struct_value_rtx (tree
, int);
276 /* Table of valid machine attributes. */
277 static const struct attribute_spec ia64_attribute_table
[] =
279 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
280 { "syscall_linkage", 0, 0, false, true, true, NULL
},
281 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
282 { NULL
, 0, 0, false, false, false, NULL
}
285 /* Initialize the GCC target structure. */
286 #undef TARGET_ATTRIBUTE_TABLE
287 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
289 #undef TARGET_INIT_BUILTINS
290 #define TARGET_INIT_BUILTINS ia64_init_builtins
292 #undef TARGET_EXPAND_BUILTIN
293 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
295 #undef TARGET_ASM_BYTE_OP
296 #define TARGET_ASM_BYTE_OP "\tdata1\t"
297 #undef TARGET_ASM_ALIGNED_HI_OP
298 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
299 #undef TARGET_ASM_ALIGNED_SI_OP
300 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
301 #undef TARGET_ASM_ALIGNED_DI_OP
302 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
303 #undef TARGET_ASM_UNALIGNED_HI_OP
304 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
305 #undef TARGET_ASM_UNALIGNED_SI_OP
306 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
307 #undef TARGET_ASM_UNALIGNED_DI_OP
308 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
309 #undef TARGET_ASM_INTEGER
310 #define TARGET_ASM_INTEGER ia64_assemble_integer
312 #undef TARGET_ASM_FUNCTION_PROLOGUE
313 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
314 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
315 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
316 #undef TARGET_ASM_FUNCTION_EPILOGUE
317 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
319 #undef TARGET_IN_SMALL_DATA_P
320 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
322 #undef TARGET_SCHED_ADJUST_COST
323 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
324 #undef TARGET_SCHED_ISSUE_RATE
325 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
326 #undef TARGET_SCHED_VARIABLE_ISSUE
327 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
328 #undef TARGET_SCHED_INIT
329 #define TARGET_SCHED_INIT ia64_sched_init
330 #undef TARGET_SCHED_FINISH
331 #define TARGET_SCHED_FINISH ia64_sched_finish
332 #undef TARGET_SCHED_REORDER
333 #define TARGET_SCHED_REORDER ia64_sched_reorder
334 #undef TARGET_SCHED_REORDER2
335 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
337 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
338 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
340 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
341 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
343 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
344 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
346 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
347 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
348 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
349 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
351 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
352 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
353 ia64_first_cycle_multipass_dfa_lookahead_guard
355 #undef TARGET_SCHED_DFA_NEW_CYCLE
356 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
358 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
359 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
361 #undef TARGET_ASM_OUTPUT_MI_THUNK
362 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
363 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
364 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
366 #undef TARGET_ASM_FILE_START
367 #define TARGET_ASM_FILE_START ia64_file_start
369 #undef TARGET_RTX_COSTS
370 #define TARGET_RTX_COSTS ia64_rtx_costs
371 #undef TARGET_ADDRESS_COST
372 #define TARGET_ADDRESS_COST hook_int_rtx_0
374 #undef TARGET_MACHINE_DEPENDENT_REORG
375 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
377 #undef TARGET_ENCODE_SECTION_INFO
378 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
380 /* ??? ABI doesn't allow us to define this. */
382 #undef TARGET_PROMOTE_FUNCTION_ARGS
383 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
386 /* ??? ABI doesn't allow us to define this. */
388 #undef TARGET_PROMOTE_FUNCTION_RETURN
389 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
392 /* ??? Investigate. */
394 #undef TARGET_PROMOTE_PROTOTYPES
395 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
398 #undef TARGET_STRUCT_VALUE_RTX
399 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
400 #undef TARGET_RETURN_IN_MEMORY
401 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
403 #undef TARGET_SETUP_INCOMING_VARARGS
404 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
405 #undef TARGET_STRICT_ARGUMENT_NAMING
406 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
408 struct gcc_target targetm
= TARGET_INITIALIZER
;
410 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
413 call_operand (rtx op
, enum machine_mode mode
)
415 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
418 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
419 || (GET_CODE (op
) == SUBREG
&& GET_CODE (XEXP (op
, 0)) == REG
));
422 /* Return 1 if OP refers to a symbol in the sdata section. */
425 sdata_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
427 switch (GET_CODE (op
))
430 if (GET_CODE (XEXP (op
, 0)) != PLUS
431 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
)
433 op
= XEXP (XEXP (op
, 0), 0);
437 if (CONSTANT_POOL_ADDRESS_P (op
))
438 return GET_MODE_SIZE (get_pool_mode (op
)) <= ia64_section_threshold
;
440 return SYMBOL_REF_LOCAL_P (op
) && SYMBOL_REF_SMALL_P (op
);
450 small_addr_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
452 return SYMBOL_REF_SMALL_ADDR_P (op
);
455 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
458 got_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
460 switch (GET_CODE (op
))
464 if (GET_CODE (op
) != PLUS
)
466 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
469 if (GET_CODE (op
) != CONST_INT
)
474 /* Ok if we're not using GOT entries at all. */
475 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
478 /* "Ok" while emitting rtl, since otherwise we won't be provided
479 with the entire offset during emission, which makes it very
480 hard to split the offset into high and low parts. */
481 if (rtx_equal_function_value_matters
)
484 /* Force the low 14 bits of the constant to zero so that we do not
485 use up so many GOT entries. */
486 return (INTVAL (op
) & 0x3fff) == 0;
489 if (SYMBOL_REF_SMALL_ADDR_P (op
))
500 /* Return 1 if OP refers to a symbol. */
503 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
505 switch (GET_CODE (op
))
518 /* Return tls_model if OP refers to a TLS symbol. */
521 tls_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
523 if (GET_CODE (op
) != SYMBOL_REF
)
525 return SYMBOL_REF_TLS_MODEL (op
);
529 /* Return 1 if OP refers to a function. */
532 function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
534 if (GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (op
))
540 /* Return 1 if OP is setjmp or a similar function. */
542 /* ??? This is an unsatisfying solution. Should rethink. */
545 setjmp_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
550 if (GET_CODE (op
) != SYMBOL_REF
)
555 /* The following code is borrowed from special_function_p in calls.c. */
557 /* Disregard prefix _, __ or __x. */
560 if (name
[1] == '_' && name
[2] == 'x')
562 else if (name
[1] == '_')
572 && (! strcmp (name
, "setjmp")
573 || ! strcmp (name
, "setjmp_syscall")))
575 && ! strcmp (name
, "sigsetjmp"))
577 && ! strcmp (name
, "savectx")));
579 else if ((name
[0] == 'q' && name
[1] == 's'
580 && ! strcmp (name
, "qsetjmp"))
581 || (name
[0] == 'v' && name
[1] == 'f'
582 && ! strcmp (name
, "vfork")))
588 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
591 move_operand (rtx op
, enum machine_mode mode
)
593 return general_operand (op
, mode
) && !tls_symbolic_operand (op
, mode
);
596 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
599 gr_register_operand (rtx op
, enum machine_mode mode
)
601 if (! register_operand (op
, mode
))
603 if (GET_CODE (op
) == SUBREG
)
604 op
= SUBREG_REG (op
);
605 if (GET_CODE (op
) == REG
)
607 unsigned int regno
= REGNO (op
);
608 if (regno
< FIRST_PSEUDO_REGISTER
)
609 return GENERAL_REGNO_P (regno
);
614 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
617 fr_register_operand (rtx op
, enum machine_mode mode
)
619 if (! register_operand (op
, mode
))
621 if (GET_CODE (op
) == SUBREG
)
622 op
= SUBREG_REG (op
);
623 if (GET_CODE (op
) == REG
)
625 unsigned int regno
= REGNO (op
);
626 if (regno
< FIRST_PSEUDO_REGISTER
)
627 return FR_REGNO_P (regno
);
632 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
635 grfr_register_operand (rtx op
, enum machine_mode mode
)
637 if (! register_operand (op
, mode
))
639 if (GET_CODE (op
) == SUBREG
)
640 op
= SUBREG_REG (op
);
641 if (GET_CODE (op
) == REG
)
643 unsigned int regno
= REGNO (op
);
644 if (regno
< FIRST_PSEUDO_REGISTER
)
645 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
650 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
653 gr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
655 if (! nonimmediate_operand (op
, mode
))
657 if (GET_CODE (op
) == SUBREG
)
658 op
= SUBREG_REG (op
);
659 if (GET_CODE (op
) == REG
)
661 unsigned int regno
= REGNO (op
);
662 if (regno
< FIRST_PSEUDO_REGISTER
)
663 return GENERAL_REGNO_P (regno
);
668 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
671 fr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
673 if (! nonimmediate_operand (op
, mode
))
675 if (GET_CODE (op
) == SUBREG
)
676 op
= SUBREG_REG (op
);
677 if (GET_CODE (op
) == REG
)
679 unsigned int regno
= REGNO (op
);
680 if (regno
< FIRST_PSEUDO_REGISTER
)
681 return FR_REGNO_P (regno
);
686 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
689 grfr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
691 if (! nonimmediate_operand (op
, mode
))
693 if (GET_CODE (op
) == SUBREG
)
694 op
= SUBREG_REG (op
);
695 if (GET_CODE (op
) == REG
)
697 unsigned int regno
= REGNO (op
);
698 if (regno
< FIRST_PSEUDO_REGISTER
)
699 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
704 /* Return 1 if OP is a GR register operand, or zero. */
707 gr_reg_or_0_operand (rtx op
, enum machine_mode mode
)
709 return (op
== const0_rtx
|| gr_register_operand (op
, mode
));
712 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
715 gr_reg_or_5bit_operand (rtx op
, enum machine_mode mode
)
717 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0 && INTVAL (op
) < 32)
718 || gr_register_operand (op
, mode
));
721 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
724 gr_reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
726 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
727 || gr_register_operand (op
, mode
));
730 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
733 gr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
735 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
736 || gr_register_operand (op
, mode
));
739 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
742 grfr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
744 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
745 || grfr_register_operand (op
, mode
));
748 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
752 gr_reg_or_8bit_adjusted_operand (rtx op
, enum machine_mode mode
)
754 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
755 || gr_register_operand (op
, mode
));
758 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
759 immediate and an 8 bit adjusted immediate operand. This is necessary
760 because when we emit a compare, we don't know what the condition will be,
761 so we need the union of the immediates accepted by GT and LT. */
764 gr_reg_or_8bit_and_adjusted_operand (rtx op
, enum machine_mode mode
)
766 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
))
767 && CONST_OK_FOR_L (INTVAL (op
)))
768 || gr_register_operand (op
, mode
));
771 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
774 gr_reg_or_14bit_operand (rtx op
, enum machine_mode mode
)
776 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
777 || gr_register_operand (op
, mode
));
780 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
783 gr_reg_or_22bit_operand (rtx op
, enum machine_mode mode
)
785 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
786 || gr_register_operand (op
, mode
));
789 /* Return 1 if OP is a 6 bit immediate operand. */
792 shift_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
794 return (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)));
797 /* Return 1 if OP is a 5 bit immediate operand. */
800 shift_32bit_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
802 return (GET_CODE (op
) == CONST_INT
803 && (INTVAL (op
) >= 0 && INTVAL (op
) < 32));
806 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
809 shladd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
811 return (GET_CODE (op
) == CONST_INT
812 && (INTVAL (op
) == 2 || INTVAL (op
) == 4
813 || INTVAL (op
) == 8 || INTVAL (op
) == 16));
816 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
819 fetchadd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
821 return (GET_CODE (op
) == CONST_INT
822 && (INTVAL (op
) == -16 || INTVAL (op
) == -8 ||
823 INTVAL (op
) == -4 || INTVAL (op
) == -1 ||
824 INTVAL (op
) == 1 || INTVAL (op
) == 4 ||
825 INTVAL (op
) == 8 || INTVAL (op
) == 16));
828 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
831 fr_reg_or_fp01_operand (rtx op
, enum machine_mode mode
)
833 return ((GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (op
))
834 || fr_register_operand (op
, mode
));
837 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
838 POST_MODIFY with a REG as displacement. */
841 destination_operand (rtx op
, enum machine_mode mode
)
843 if (! nonimmediate_operand (op
, mode
))
845 if (GET_CODE (op
) == MEM
846 && GET_CODE (XEXP (op
, 0)) == POST_MODIFY
847 && GET_CODE (XEXP (XEXP (XEXP (op
, 0), 1), 1)) == REG
)
852 /* Like memory_operand, but don't allow post-increments. */
855 not_postinc_memory_operand (rtx op
, enum machine_mode mode
)
857 return (memory_operand (op
, mode
)
858 && GET_RTX_CLASS (GET_CODE (XEXP (op
, 0))) != RTX_AUTOINC
);
861 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
862 signed immediate operand. */
865 normal_comparison_operator (register rtx op
, enum machine_mode mode
)
867 enum rtx_code code
= GET_CODE (op
);
868 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
869 && (code
== EQ
|| code
== NE
870 || code
== GT
|| code
== LE
|| code
== GTU
|| code
== LEU
));
873 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
874 signed immediate operand. */
877 adjusted_comparison_operator (register rtx op
, enum machine_mode mode
)
879 enum rtx_code code
= GET_CODE (op
);
880 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
881 && (code
== LT
|| code
== GE
|| code
== LTU
|| code
== GEU
));
884 /* Return 1 if this is a signed inequality operator. */
887 signed_inequality_operator (register rtx op
, enum machine_mode mode
)
889 enum rtx_code code
= GET_CODE (op
);
890 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
891 && (code
== GE
|| code
== GT
892 || code
== LE
|| code
== LT
));
895 /* Return 1 if this operator is valid for predication. */
898 predicate_operator (register rtx op
, enum machine_mode mode
)
900 enum rtx_code code
= GET_CODE (op
);
901 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
902 && (code
== EQ
|| code
== NE
));
905 /* Return 1 if this operator can be used in a conditional operation. */
908 condop_operator (register rtx op
, enum machine_mode mode
)
910 enum rtx_code code
= GET_CODE (op
);
911 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
912 && (code
== PLUS
|| code
== MINUS
|| code
== AND
913 || code
== IOR
|| code
== XOR
));
916 /* Return 1 if this is the ar.lc register. */
919 ar_lc_reg_operand (register rtx op
, enum machine_mode mode
)
921 return (GET_MODE (op
) == DImode
922 && (mode
== DImode
|| mode
== VOIDmode
)
923 && GET_CODE (op
) == REG
924 && REGNO (op
) == AR_LC_REGNUM
);
927 /* Return 1 if this is the ar.ccv register. */
930 ar_ccv_reg_operand (register rtx op
, enum machine_mode mode
)
932 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
933 && GET_CODE (op
) == REG
934 && REGNO (op
) == AR_CCV_REGNUM
);
937 /* Return 1 if this is the ar.pfs register. */
940 ar_pfs_reg_operand (register rtx op
, enum machine_mode mode
)
942 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
943 && GET_CODE (op
) == REG
944 && REGNO (op
) == AR_PFS_REGNUM
);
947 /* Like general_operand, but don't allow (mem (addressof)). */
950 general_xfmode_operand (rtx op
, enum machine_mode mode
)
952 if (! general_operand (op
, mode
))
954 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
962 destination_xfmode_operand (rtx op
, enum machine_mode mode
)
964 if (! destination_operand (op
, mode
))
966 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
974 xfreg_or_fp01_operand (rtx op
, enum machine_mode mode
)
976 if (GET_CODE (op
) == SUBREG
)
978 return fr_reg_or_fp01_operand (op
, mode
);
981 /* Return 1 if OP is valid as a base register in a reg + offset address. */
984 basereg_operand (rtx op
, enum machine_mode mode
)
986 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
987 checks from pa.c basereg_operand as well? Seems to be OK without them
990 return (register_operand (op
, mode
) &&
991 REG_POINTER ((GET_CODE (op
) == SUBREG
) ? SUBREG_REG (op
) : op
));
996 ADDR_AREA_NORMAL
, /* normal address area */
997 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
1001 static GTY(()) tree small_ident1
;
1002 static GTY(()) tree small_ident2
;
1007 if (small_ident1
== 0)
1009 small_ident1
= get_identifier ("small");
1010 small_ident2
= get_identifier ("__small__");
1014 /* Retrieve the address area that has been chosen for the given decl. */
1016 static ia64_addr_area
1017 ia64_get_addr_area (tree decl
)
1021 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
1027 id
= TREE_VALUE (TREE_VALUE (model_attr
));
1028 if (id
== small_ident1
|| id
== small_ident2
)
1029 return ADDR_AREA_SMALL
;
1031 return ADDR_AREA_NORMAL
;
1035 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
, int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1037 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
1038 ia64_addr_area area
;
1039 tree arg
, decl
= *node
;
1042 arg
= TREE_VALUE (args
);
1043 if (arg
== small_ident1
|| arg
== small_ident2
)
1045 addr_area
= ADDR_AREA_SMALL
;
1049 warning ("invalid argument of `%s' attribute",
1050 IDENTIFIER_POINTER (name
));
1051 *no_add_attrs
= true;
1054 switch (TREE_CODE (decl
))
1057 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
1059 && !TREE_STATIC (decl
))
1061 error ("%Jan address area attribute cannot be specified for "
1062 "local variables", decl
, decl
);
1063 *no_add_attrs
= true;
1065 area
= ia64_get_addr_area (decl
);
1066 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
1068 error ("%Jaddress area of '%s' conflicts with previous "
1069 "declaration", decl
, decl
);
1070 *no_add_attrs
= true;
1075 error ("%Jaddress area attribute cannot be specified for functions",
1077 *no_add_attrs
= true;
1081 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1082 *no_add_attrs
= true;
1090 ia64_encode_addr_area (tree decl
, rtx symbol
)
1094 flags
= SYMBOL_REF_FLAGS (symbol
);
1095 switch (ia64_get_addr_area (decl
))
1097 case ADDR_AREA_NORMAL
: break;
1098 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
1101 SYMBOL_REF_FLAGS (symbol
) = flags
;
1105 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
1107 default_encode_section_info (decl
, rtl
, first
);
1109 /* Careful not to prod global register variables. */
1110 if (TREE_CODE (decl
) == VAR_DECL
1111 && GET_CODE (DECL_RTL (decl
)) == MEM
1112 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
1113 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
1114 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
1117 /* Return 1 if the operands of a move are ok. */
1120 ia64_move_ok (rtx dst
, rtx src
)
1122 /* If we're under init_recog_no_volatile, we'll not be able to use
1123 memory_operand. So check the code directly and don't worry about
1124 the validity of the underlying address, which should have been
1125 checked elsewhere anyway. */
1126 if (GET_CODE (dst
) != MEM
)
1128 if (GET_CODE (src
) == MEM
)
1130 if (register_operand (src
, VOIDmode
))
1133 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1134 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
1135 return src
== const0_rtx
;
1137 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
1141 addp4_optimize_ok (rtx op1
, rtx op2
)
1143 return (basereg_operand (op1
, GET_MODE(op1
)) !=
1144 basereg_operand (op2
, GET_MODE(op2
)));
1147 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1148 Return the length of the field, or <= 0 on failure. */
1151 ia64_depz_field_mask (rtx rop
, rtx rshift
)
1153 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
1154 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
1156 /* Get rid of the zero bits we're shifting in. */
1159 /* We must now have a solid block of 1's at bit 0. */
1160 return exact_log2 (op
+ 1);
1163 /* Expand a symbolic constant load. */
1166 ia64_expand_load_address (rtx dest
, rtx src
)
1168 if (tls_symbolic_operand (src
, VOIDmode
))
1170 if (GET_CODE (dest
) != REG
)
1173 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1174 having to pointer-extend the value afterward. Other forms of address
1175 computation below are also more natural to compute as 64-bit quantities.
1176 If we've been given an SImode destination register, change it. */
1177 if (GET_MODE (dest
) != Pmode
)
1178 dest
= gen_rtx_REG (Pmode
, REGNO (dest
));
1180 if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_ADDR_P (src
))
1182 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
1185 else if (TARGET_AUTO_PIC
)
1187 emit_insn (gen_load_gprel64 (dest
, src
));
1190 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1192 emit_insn (gen_load_fptr (dest
, src
));
1195 else if (sdata_symbolic_operand (src
, VOIDmode
))
1197 emit_insn (gen_load_gprel (dest
, src
));
1201 if (GET_CODE (src
) == CONST
1202 && GET_CODE (XEXP (src
, 0)) == PLUS
1203 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
1204 && (INTVAL (XEXP (XEXP (src
, 0), 1)) & 0x1fff) != 0)
1206 rtx sym
= XEXP (XEXP (src
, 0), 0);
1207 HOST_WIDE_INT ofs
, hi
, lo
;
1209 /* Split the offset into a sign extended 14-bit low part
1210 and a complementary high part. */
1211 ofs
= INTVAL (XEXP (XEXP (src
, 0), 1));
1212 lo
= ((ofs
& 0x3fff) ^ 0x2000) - 0x2000;
1215 ia64_expand_load_address (dest
, plus_constant (sym
, hi
));
1216 emit_insn (gen_adddi3 (dest
, dest
, GEN_INT (lo
)));
1222 tmp
= gen_rtx_HIGH (Pmode
, src
);
1223 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1224 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1226 tmp
= gen_rtx_LO_SUM (GET_MODE (dest
), dest
, src
);
1227 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1231 static GTY(()) rtx gen_tls_tga
;
1233 gen_tls_get_addr (void)
1236 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1240 static GTY(()) rtx thread_pointer_rtx
;
1242 gen_thread_pointer (void)
1244 if (!thread_pointer_rtx
)
1246 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1247 RTX_UNCHANGING_P (thread_pointer_rtx
) = 1;
1249 return thread_pointer_rtx
;
1253 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
)
1255 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1260 case TLS_MODEL_GLOBAL_DYNAMIC
:
1263 tga_op1
= gen_reg_rtx (Pmode
);
1264 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1265 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1266 RTX_UNCHANGING_P (tga_op1
) = 1;
1268 tga_op2
= gen_reg_rtx (Pmode
);
1269 emit_insn (gen_load_ltoff_dtprel (tga_op2
, op1
));
1270 tga_op2
= gen_rtx_MEM (Pmode
, tga_op2
);
1271 RTX_UNCHANGING_P (tga_op2
) = 1;
1273 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1274 LCT_CONST
, Pmode
, 2, tga_op1
,
1275 Pmode
, tga_op2
, Pmode
);
1277 insns
= get_insns ();
1280 if (GET_MODE (op0
) != Pmode
)
1282 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1285 case TLS_MODEL_LOCAL_DYNAMIC
:
1286 /* ??? This isn't the completely proper way to do local-dynamic
1287 If the call to __tls_get_addr is used only by a single symbol,
1288 then we should (somehow) move the dtprel to the second arg
1289 to avoid the extra add. */
1292 tga_op1
= gen_reg_rtx (Pmode
);
1293 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1294 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1295 RTX_UNCHANGING_P (tga_op1
) = 1;
1297 tga_op2
= const0_rtx
;
1299 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1300 LCT_CONST
, Pmode
, 2, tga_op1
,
1301 Pmode
, tga_op2
, Pmode
);
1303 insns
= get_insns ();
1306 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1308 tmp
= gen_reg_rtx (Pmode
);
1309 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1311 if (!register_operand (op0
, Pmode
))
1312 op0
= gen_reg_rtx (Pmode
);
1315 emit_insn (gen_load_dtprel (op0
, op1
));
1316 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1319 emit_insn (gen_add_dtprel (op0
, tmp
, op1
));
1322 case TLS_MODEL_INITIAL_EXEC
:
1323 tmp
= gen_reg_rtx (Pmode
);
1324 emit_insn (gen_load_ltoff_tprel (tmp
, op1
));
1325 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1326 RTX_UNCHANGING_P (tmp
) = 1;
1327 tmp
= force_reg (Pmode
, tmp
);
1329 if (!register_operand (op0
, Pmode
))
1330 op0
= gen_reg_rtx (Pmode
);
1331 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1334 case TLS_MODEL_LOCAL_EXEC
:
1335 if (!register_operand (op0
, Pmode
))
1336 op0
= gen_reg_rtx (Pmode
);
1339 emit_insn (gen_load_tprel (op0
, op1
));
1340 emit_insn (gen_adddi3 (op0
, gen_thread_pointer (), op0
));
1343 emit_insn (gen_add_tprel (op0
, gen_thread_pointer (), op1
));
1350 if (orig_op0
== op0
)
1352 if (GET_MODE (orig_op0
) == Pmode
)
1354 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1358 ia64_expand_move (rtx op0
, rtx op1
)
1360 enum machine_mode mode
= GET_MODE (op0
);
1362 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1363 op1
= force_reg (mode
, op1
);
1365 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1367 enum tls_model tls_kind
;
1368 if ((tls_kind
= tls_symbolic_operand (op1
, VOIDmode
)))
1369 return ia64_expand_tls_address (tls_kind
, op0
, op1
);
1371 if (!TARGET_NO_PIC
&& reload_completed
)
1373 ia64_expand_load_address (op0
, op1
);
1381 /* Split a move from OP1 to OP0 conditional on COND. */
1384 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1386 rtx insn
, first
= get_last_insn ();
1388 emit_move_insn (op0
, op1
);
1390 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1392 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1396 /* Split a post-reload TImode or TFmode reference into two DImode
1397 components. This is made extra difficult by the fact that we do
1398 not get any scratch registers to work with, because reload cannot
1399 be prevented from giving us a scratch that overlaps the register
1400 pair involved. So instead, when addressing memory, we tweak the
1401 pointer register up and back down with POST_INCs. Or up and not
1402 back down when we can get away with it.
1404 REVERSED is true when the loads must be done in reversed order
1405 (high word first) for correctness. DEAD is true when the pointer
1406 dies with the second insn we generate and therefore the second
1407 address must not carry a postmodify.
1409 May return an insn which is to be emitted after the moves. */
1412 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1416 switch (GET_CODE (in
))
1419 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1420 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1425 /* Cannot occur reversed. */
1426 if (reversed
) abort ();
1428 if (GET_MODE (in
) != TFmode
)
1429 split_double (in
, &out
[0], &out
[1]);
1431 /* split_double does not understand how to split a TFmode
1432 quantity into a pair of DImode constants. */
1435 unsigned HOST_WIDE_INT p
[2];
1436 long l
[4]; /* TFmode is 128 bits */
1438 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1439 real_to_target (l
, &r
, TFmode
);
1441 if (FLOAT_WORDS_BIG_ENDIAN
)
1443 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1444 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1448 p
[0] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1449 p
[1] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1451 out
[0] = GEN_INT (p
[0]);
1452 out
[1] = GEN_INT (p
[1]);
1458 rtx base
= XEXP (in
, 0);
1461 switch (GET_CODE (base
))
1466 out
[0] = adjust_automodify_address
1467 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1468 out
[1] = adjust_automodify_address
1469 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1473 /* Reversal requires a pre-increment, which can only
1474 be done as a separate insn. */
1475 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1476 out
[0] = adjust_automodify_address
1477 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1478 out
[1] = adjust_address (in
, DImode
, 0);
1483 if (reversed
|| dead
) abort ();
1484 /* Just do the increment in two steps. */
1485 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1486 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1490 if (reversed
|| dead
) abort ();
1491 /* Add 8, subtract 24. */
1492 base
= XEXP (base
, 0);
1493 out
[0] = adjust_automodify_address
1494 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1495 out
[1] = adjust_automodify_address
1497 gen_rtx_POST_MODIFY (Pmode
, base
, plus_constant (base
, -24)),
1502 if (reversed
|| dead
) abort ();
1503 /* Extract and adjust the modification. This case is
1504 trickier than the others, because we might have an
1505 index register, or we might have a combined offset that
1506 doesn't fit a signed 9-bit displacement field. We can
1507 assume the incoming expression is already legitimate. */
1508 offset
= XEXP (base
, 1);
1509 base
= XEXP (base
, 0);
1511 out
[0] = adjust_automodify_address
1512 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1514 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1516 /* Can't adjust the postmodify to match. Emit the
1517 original, then a separate addition insn. */
1518 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1519 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1521 else if (GET_CODE (XEXP (offset
, 1)) != CONST_INT
)
1523 else if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1525 /* Again the postmodify cannot be made to match, but
1526 in this case it's more efficient to get rid of the
1527 postmodify entirely and fix up with an add insn. */
1528 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1529 fixup
= gen_adddi3 (base
, base
,
1530 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1534 /* Combined offset still fits in the displacement field.
1535 (We cannot overflow it at the high end.) */
1536 out
[1] = adjust_automodify_address
1538 gen_rtx_POST_MODIFY (Pmode
, base
,
1539 gen_rtx_PLUS (Pmode
, base
,
1540 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1558 /* Split a TImode or TFmode move instruction after reload.
1559 This is used by *movtf_internal and *movti_internal. */
1561 ia64_split_tmode_move (rtx operands
[])
1563 rtx in
[2], out
[2], insn
;
1566 bool reversed
= false;
1568 /* It is possible for reload to decide to overwrite a pointer with
1569 the value it points to. In that case we have to do the loads in
1570 the appropriate order so that the pointer is not destroyed too
1571 early. Also we must not generate a postmodify for that second
1572 load, or rws_access_regno will abort. */
1573 if (GET_CODE (operands
[1]) == MEM
1574 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1576 rtx base
= XEXP (operands
[1], 0);
1577 while (GET_CODE (base
) != REG
)
1578 base
= XEXP (base
, 0);
1580 if (REGNO (base
) == REGNO (operands
[0]))
1584 /* Another reason to do the moves in reversed order is if the first
1585 element of the target register pair is also the second element of
1586 the source register pair. */
1587 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1588 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1591 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1592 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1594 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1595 if (GET_CODE (EXP) == MEM \
1596 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1597 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1598 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1599 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1600 XEXP (XEXP (EXP, 0), 0), \
1603 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1604 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1605 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1607 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1608 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1609 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1612 emit_insn (fixup
[0]);
1614 emit_insn (fixup
[1]);
1616 #undef MAYBE_ADD_REG_INC_NOTE
1619 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1620 through memory plus an extra GR scratch register. Except that you can
1621 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1622 SECONDARY_RELOAD_CLASS, but not both.
1624 We got into problems in the first place by allowing a construct like
1625 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1626 This solution attempts to prevent this situation from occurring. When
1627 we see something like the above, we spill the inner register to memory. */
1630 spill_xfmode_operand (rtx in
, int force
)
1632 if (GET_CODE (in
) == SUBREG
1633 && GET_MODE (SUBREG_REG (in
)) == TImode
1634 && GET_CODE (SUBREG_REG (in
)) == REG
)
1636 rtx mem
= gen_mem_addressof (SUBREG_REG (in
), NULL_TREE
, /*rescan=*/true);
1637 return gen_rtx_MEM (XFmode
, copy_to_reg (XEXP (mem
, 0)));
1639 else if (force
&& GET_CODE (in
) == REG
)
1641 rtx mem
= gen_mem_addressof (in
, NULL_TREE
, /*rescan=*/true);
1642 return gen_rtx_MEM (XFmode
, copy_to_reg (XEXP (mem
, 0)));
1644 else if (GET_CODE (in
) == MEM
1645 && GET_CODE (XEXP (in
, 0)) == ADDRESSOF
)
1646 return change_address (in
, XFmode
, copy_to_reg (XEXP (in
, 0)));
1651 /* Emit comparison instruction if necessary, returning the expression
1652 that holds the compare result in the proper mode. */
1654 static GTY(()) rtx cmptf_libfunc
;
1657 ia64_expand_compare (enum rtx_code code
, enum machine_mode mode
)
1659 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1662 /* If we have a BImode input, then we already have a compare result, and
1663 do not need to emit another comparison. */
1664 if (GET_MODE (op0
) == BImode
)
1666 if ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1671 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1672 magic number as its third argument, that indicates what to do.
1673 The return value is an integer to be compared against zero. */
1674 else if (TARGET_HPUX
&& GET_MODE (op0
) == TFmode
)
1677 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1683 enum rtx_code ncode
;
1685 if (GET_MODE (op1
) != TFmode
)
1689 /* 1 = equal, 0 = not equal. Equality operators do
1690 not raise FP_INVALID when given an SNaN operand. */
1691 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1692 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1693 /* isunordered() from C99. */
1694 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1695 /* Relational operators raise FP_INVALID when given
1697 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1698 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1699 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1700 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1701 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1702 Expanders for buneq etc. weuld have to be added to ia64.md
1703 for this to be useful. */
1709 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1710 op0
, TFmode
, op1
, TFmode
,
1711 GEN_INT (magic
), DImode
);
1712 cmp
= gen_reg_rtx (BImode
);
1713 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1714 gen_rtx_fmt_ee (ncode
, BImode
,
1717 insns
= get_insns ();
1720 emit_libcall_block (insns
, cmp
, cmp
,
1721 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
));
1726 cmp
= gen_reg_rtx (BImode
);
1727 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1728 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1732 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1735 /* Emit the appropriate sequence for a call. */
1738 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
1743 addr
= XEXP (addr
, 0);
1744 addr
= convert_memory_address (DImode
, addr
);
1745 b0
= gen_rtx_REG (DImode
, R_BR (0));
1747 /* ??? Should do this for functions known to bind local too. */
1748 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1751 insn
= gen_sibcall_nogp (addr
);
1753 insn
= gen_call_nogp (addr
, b0
);
1755 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1756 insn
= emit_call_insn (insn
);
1761 insn
= gen_sibcall_gp (addr
);
1763 insn
= gen_call_gp (addr
, b0
);
1765 insn
= gen_call_value_gp (retval
, addr
, b0
);
1766 insn
= emit_call_insn (insn
);
1768 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1772 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1776 ia64_reload_gp (void)
1780 if (current_frame_info
.reg_save_gp
)
1781 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1784 HOST_WIDE_INT offset
;
1786 offset
= (current_frame_info
.spill_cfa_off
1787 + current_frame_info
.spill_size
);
1788 if (frame_pointer_needed
)
1790 tmp
= hard_frame_pointer_rtx
;
1795 tmp
= stack_pointer_rtx
;
1796 offset
= current_frame_info
.total_size
- offset
;
1799 if (CONST_OK_FOR_I (offset
))
1800 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1801 tmp
, GEN_INT (offset
)));
1804 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1805 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1806 pic_offset_table_rtx
, tmp
));
1809 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1812 emit_move_insn (pic_offset_table_rtx
, tmp
);
1816 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
1817 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
1820 bool is_desc
= false;
1822 /* If we find we're calling through a register, then we're actually
1823 calling through a descriptor, so load up the values. */
1824 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
1829 /* ??? We are currently constrained to *not* use peep2, because
1830 we can legitimately change the global lifetime of the GP
1831 (in the form of killing where previously live). This is
1832 because a call through a descriptor doesn't use the previous
1833 value of the GP, while a direct call does, and we do not
1834 commit to either form until the split here.
1836 That said, this means that we lack precise life info for
1837 whether ADDR is dead after this call. This is not terribly
1838 important, since we can fix things up essentially for free
1839 with the POST_DEC below, but it's nice to not use it when we
1840 can immediately tell it's not necessary. */
1841 addr_dead_p
= ((noreturn_p
|| sibcall_p
1842 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1844 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1846 /* Load the code address into scratch_b. */
1847 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1848 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1849 emit_move_insn (scratch_r
, tmp
);
1850 emit_move_insn (scratch_b
, scratch_r
);
1852 /* Load the GP address. If ADDR is not dead here, then we must
1853 revert the change made above via the POST_INCREMENT. */
1855 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1858 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1859 emit_move_insn (pic_offset_table_rtx
, tmp
);
1866 insn
= gen_sibcall_nogp (addr
);
1868 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1870 insn
= gen_call_nogp (addr
, retaddr
);
1871 emit_call_insn (insn
);
1873 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1877 /* Begin the assembly file. */
1880 ia64_file_start (void)
1882 default_file_start ();
1883 emit_safe_across_calls ();
1887 emit_safe_across_calls (void)
1889 unsigned int rs
, re
;
1896 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1900 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1904 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
1908 fputc (',', asm_out_file
);
1910 fprintf (asm_out_file
, "p%u", rs
);
1912 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
1916 fputc ('\n', asm_out_file
);
1919 /* Helper function for ia64_compute_frame_size: find an appropriate general
1920 register to spill some special register to. SPECIAL_SPILL_MASK contains
1921 bits in GR0 to GR31 that have already been allocated by this routine.
1922 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1925 find_gr_spill (int try_locals
)
1929 /* If this is a leaf function, first try an otherwise unused
1930 call-clobbered register. */
1931 if (current_function_is_leaf
)
1933 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1934 if (! regs_ever_live
[regno
]
1935 && call_used_regs
[regno
]
1936 && ! fixed_regs
[regno
]
1937 && ! global_regs
[regno
]
1938 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1940 current_frame_info
.gr_used_mask
|= 1 << regno
;
1947 regno
= current_frame_info
.n_local_regs
;
1948 /* If there is a frame pointer, then we can't use loc79, because
1949 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1950 reg_name switching code in ia64_expand_prologue. */
1951 if (regno
< (80 - frame_pointer_needed
))
1953 current_frame_info
.n_local_regs
= regno
+ 1;
1954 return LOC_REG (0) + regno
;
1958 /* Failed to find a general register to spill to. Must use stack. */
1962 /* In order to make for nice schedules, we try to allocate every temporary
1963 to a different register. We must of course stay away from call-saved,
1964 fixed, and global registers. We must also stay away from registers
1965 allocated in current_frame_info.gr_used_mask, since those include regs
1966 used all through the prologue.
1968 Any register allocated here must be used immediately. The idea is to
1969 aid scheduling, not to solve data flow problems. */
1971 static int last_scratch_gr_reg
;
1974 next_scratch_gr_reg (void)
1978 for (i
= 0; i
< 32; ++i
)
1980 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
1981 if (call_used_regs
[regno
]
1982 && ! fixed_regs
[regno
]
1983 && ! global_regs
[regno
]
1984 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1986 last_scratch_gr_reg
= regno
;
1991 /* There must be _something_ available. */
1995 /* Helper function for ia64_compute_frame_size, called through
1996 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1999 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2001 unsigned int regno
= REGNO (reg
);
2004 unsigned int i
, n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2005 for (i
= 0; i
< n
; ++i
)
2006 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2010 /* Returns the number of bytes offset between the frame pointer and the stack
2011 pointer for the current function. SIZE is the number of bytes of space
2012 needed for local variables. */
2015 ia64_compute_frame_size (HOST_WIDE_INT size
)
2017 HOST_WIDE_INT total_size
;
2018 HOST_WIDE_INT spill_size
= 0;
2019 HOST_WIDE_INT extra_spill_size
= 0;
2020 HOST_WIDE_INT pretend_args_size
;
2023 int spilled_gr_p
= 0;
2024 int spilled_fr_p
= 0;
2028 if (current_frame_info
.initialized
)
2031 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2032 CLEAR_HARD_REG_SET (mask
);
2034 /* Don't allocate scratches to the return register. */
2035 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2037 /* Don't allocate scratches to the EH scratch registers. */
2038 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2039 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2040 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2041 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2043 /* Find the size of the register stack frame. We have only 80 local
2044 registers, because we reserve 8 for the inputs and 8 for the
2047 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2048 since we'll be adjusting that down later. */
2049 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2050 for (; regno
>= LOC_REG (0); regno
--)
2051 if (regs_ever_live
[regno
])
2053 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2055 /* For functions marked with the syscall_linkage attribute, we must mark
2056 all eight input registers as in use, so that locals aren't visible to
2059 if (cfun
->machine
->n_varargs
> 0
2060 || lookup_attribute ("syscall_linkage",
2061 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2062 current_frame_info
.n_input_regs
= 8;
2065 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2066 if (regs_ever_live
[regno
])
2068 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2071 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2072 if (regs_ever_live
[regno
])
2074 i
= regno
- OUT_REG (0) + 1;
2076 /* When -p profiling, we need one output register for the mcount argument.
2077 Likewise for -a profiling for the bb_init_func argument. For -ax
2078 profiling, we need two output registers for the two bb_init_trace_func
2080 if (current_function_profile
)
2082 current_frame_info
.n_output_regs
= i
;
2084 /* ??? No rotating register support yet. */
2085 current_frame_info
.n_rotate_regs
= 0;
2087 /* Discover which registers need spilling, and how much room that
2088 will take. Begin with floating point and general registers,
2089 which will always wind up on the stack. */
2091 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2092 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2094 SET_HARD_REG_BIT (mask
, regno
);
2100 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2101 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2103 SET_HARD_REG_BIT (mask
, regno
);
2109 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2110 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2112 SET_HARD_REG_BIT (mask
, regno
);
2117 /* Now come all special registers that might get saved in other
2118 general registers. */
2120 if (frame_pointer_needed
)
2122 current_frame_info
.reg_fp
= find_gr_spill (1);
2123 /* If we did not get a register, then we take LOC79. This is guaranteed
2124 to be free, even if regs_ever_live is already set, because this is
2125 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2126 as we don't count loc79 above. */
2127 if (current_frame_info
.reg_fp
== 0)
2129 current_frame_info
.reg_fp
= LOC_REG (79);
2130 current_frame_info
.n_local_regs
++;
2134 if (! current_function_is_leaf
)
2136 /* Emit a save of BR0 if we call other functions. Do this even
2137 if this function doesn't return, as EH depends on this to be
2138 able to unwind the stack. */
2139 SET_HARD_REG_BIT (mask
, BR_REG (0));
2141 current_frame_info
.reg_save_b0
= find_gr_spill (1);
2142 if (current_frame_info
.reg_save_b0
== 0)
2148 /* Similarly for ar.pfs. */
2149 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2150 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2151 if (current_frame_info
.reg_save_ar_pfs
== 0)
2153 extra_spill_size
+= 8;
2157 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2158 registers are clobbered, so we fall back to the stack. */
2159 current_frame_info
.reg_save_gp
2160 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
2161 if (current_frame_info
.reg_save_gp
== 0)
2163 SET_HARD_REG_BIT (mask
, GR_REG (1));
2170 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
2172 SET_HARD_REG_BIT (mask
, BR_REG (0));
2177 if (regs_ever_live
[AR_PFS_REGNUM
])
2179 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2180 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2181 if (current_frame_info
.reg_save_ar_pfs
== 0)
2183 extra_spill_size
+= 8;
2189 /* Unwind descriptor hackery: things are most efficient if we allocate
2190 consecutive GR save registers for RP, PFS, FP in that order. However,
2191 it is absolutely critical that FP get the only hard register that's
2192 guaranteed to be free, so we allocated it first. If all three did
2193 happen to be allocated hard regs, and are consecutive, rearrange them
2194 into the preferred order now. */
2195 if (current_frame_info
.reg_fp
!= 0
2196 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
2197 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
2199 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
2200 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
2201 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
2204 /* See if we need to store the predicate register block. */
2205 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2206 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2208 if (regno
<= PR_REG (63))
2210 SET_HARD_REG_BIT (mask
, PR_REG (0));
2211 current_frame_info
.reg_save_pr
= find_gr_spill (1);
2212 if (current_frame_info
.reg_save_pr
== 0)
2214 extra_spill_size
+= 8;
2218 /* ??? Mark them all as used so that register renaming and such
2219 are free to use them. */
2220 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2221 regs_ever_live
[regno
] = 1;
2224 /* If we're forced to use st8.spill, we're forced to save and restore
2225 ar.unat as well. The check for existing liveness allows inline asm
2226 to touch ar.unat. */
2227 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2228 || regs_ever_live
[AR_UNAT_REGNUM
])
2230 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
2231 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2232 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
2233 if (current_frame_info
.reg_save_ar_unat
== 0)
2235 extra_spill_size
+= 8;
2240 if (regs_ever_live
[AR_LC_REGNUM
])
2242 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2243 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
2244 if (current_frame_info
.reg_save_ar_lc
== 0)
2246 extra_spill_size
+= 8;
2251 /* If we have an odd number of words of pretend arguments written to
2252 the stack, then the FR save area will be unaligned. We round the
2253 size of this area up to keep things 16 byte aligned. */
2255 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
2257 pretend_args_size
= current_function_pretend_args_size
;
2259 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2260 + current_function_outgoing_args_size
);
2261 total_size
= IA64_STACK_ALIGN (total_size
);
2263 /* We always use the 16-byte scratch area provided by the caller, but
2264 if we are a leaf function, there's no one to which we need to provide
2266 if (current_function_is_leaf
)
2267 total_size
= MAX (0, total_size
- 16);
2269 current_frame_info
.total_size
= total_size
;
2270 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2271 current_frame_info
.spill_size
= spill_size
;
2272 current_frame_info
.extra_spill_size
= extra_spill_size
;
2273 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2274 current_frame_info
.n_spilled
= n_spilled
;
2275 current_frame_info
.initialized
= reload_completed
;
2278 /* Compute the initial difference between the specified pair of registers. */
2281 ia64_initial_elimination_offset (int from
, int to
)
2283 HOST_WIDE_INT offset
;
2285 ia64_compute_frame_size (get_frame_size ());
2288 case FRAME_POINTER_REGNUM
:
2289 if (to
== HARD_FRAME_POINTER_REGNUM
)
2291 if (current_function_is_leaf
)
2292 offset
= -current_frame_info
.total_size
;
2294 offset
= -(current_frame_info
.total_size
2295 - current_function_outgoing_args_size
- 16);
2297 else if (to
== STACK_POINTER_REGNUM
)
2299 if (current_function_is_leaf
)
2302 offset
= 16 + current_function_outgoing_args_size
;
2308 case ARG_POINTER_REGNUM
:
2309 /* Arguments start above the 16 byte save area, unless stdarg
2310 in which case we store through the 16 byte save area. */
2311 if (to
== HARD_FRAME_POINTER_REGNUM
)
2312 offset
= 16 - current_function_pretend_args_size
;
2313 else if (to
== STACK_POINTER_REGNUM
)
2314 offset
= (current_frame_info
.total_size
2315 + 16 - current_function_pretend_args_size
);
2327 /* If there are more than a trivial number of register spills, we use
2328 two interleaved iterators so that we can get two memory references
2331 In order to simplify things in the prologue and epilogue expanders,
2332 we use helper functions to fix up the memory references after the
2333 fact with the appropriate offsets to a POST_MODIFY memory mode.
2334 The following data structure tracks the state of the two iterators
2335 while insns are being emitted. */
2337 struct spill_fill_data
2339 rtx init_after
; /* point at which to emit initializations */
2340 rtx init_reg
[2]; /* initial base register */
2341 rtx iter_reg
[2]; /* the iterator registers */
2342 rtx
*prev_addr
[2]; /* address of last memory use */
2343 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2344 HOST_WIDE_INT prev_off
[2]; /* last offset */
2345 int n_iter
; /* number of iterators in use */
2346 int next_iter
; /* next iterator to use */
2347 unsigned int save_gr_used_mask
;
2350 static struct spill_fill_data spill_fill_data
;
2353 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2357 spill_fill_data
.init_after
= get_last_insn ();
2358 spill_fill_data
.init_reg
[0] = init_reg
;
2359 spill_fill_data
.init_reg
[1] = init_reg
;
2360 spill_fill_data
.prev_addr
[0] = NULL
;
2361 spill_fill_data
.prev_addr
[1] = NULL
;
2362 spill_fill_data
.prev_insn
[0] = NULL
;
2363 spill_fill_data
.prev_insn
[1] = NULL
;
2364 spill_fill_data
.prev_off
[0] = cfa_off
;
2365 spill_fill_data
.prev_off
[1] = cfa_off
;
2366 spill_fill_data
.next_iter
= 0;
2367 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2369 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2370 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2372 int regno
= next_scratch_gr_reg ();
2373 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2374 current_frame_info
.gr_used_mask
|= 1 << regno
;
2379 finish_spill_pointers (void)
2381 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2385 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2387 int iter
= spill_fill_data
.next_iter
;
2388 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2389 rtx disp_rtx
= GEN_INT (disp
);
2392 if (spill_fill_data
.prev_addr
[iter
])
2394 if (CONST_OK_FOR_N (disp
))
2396 *spill_fill_data
.prev_addr
[iter
]
2397 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2398 gen_rtx_PLUS (DImode
,
2399 spill_fill_data
.iter_reg
[iter
],
2401 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2402 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2403 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2407 /* ??? Could use register post_modify for loads. */
2408 if (! CONST_OK_FOR_I (disp
))
2410 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2411 emit_move_insn (tmp
, disp_rtx
);
2414 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2415 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2418 /* Micro-optimization: if we've created a frame pointer, it's at
2419 CFA 0, which may allow the real iterator to be initialized lower,
2420 slightly increasing parallelism. Also, if there are few saves
2421 it may eliminate the iterator entirely. */
2423 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2424 && frame_pointer_needed
)
2426 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2427 set_mem_alias_set (mem
, get_varargs_alias_set ());
2435 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2436 spill_fill_data
.init_reg
[iter
]);
2441 if (! CONST_OK_FOR_I (disp
))
2443 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2444 emit_move_insn (tmp
, disp_rtx
);
2448 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2449 spill_fill_data
.init_reg
[iter
],
2456 /* Careful for being the first insn in a sequence. */
2457 if (spill_fill_data
.init_after
)
2458 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2461 rtx first
= get_insns ();
2463 insn
= emit_insn_before (seq
, first
);
2465 insn
= emit_insn (seq
);
2467 spill_fill_data
.init_after
= insn
;
2469 /* If DISP is 0, we may or may not have a further adjustment
2470 afterward. If we do, then the load/store insn may be modified
2471 to be a post-modify. If we don't, then this copy may be
2472 eliminated by copyprop_hardreg_forward, which makes this
2473 insn garbage, which runs afoul of the sanity check in
2474 propagate_one_insn. So mark this insn as legal to delete. */
2476 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2480 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2482 /* ??? Not all of the spills are for varargs, but some of them are.
2483 The rest of the spills belong in an alias set of their own. But
2484 it doesn't actually hurt to include them here. */
2485 set_mem_alias_set (mem
, get_varargs_alias_set ());
2487 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2488 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2490 if (++iter
>= spill_fill_data
.n_iter
)
2492 spill_fill_data
.next_iter
= iter
;
2498 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
2501 int iter
= spill_fill_data
.next_iter
;
2504 mem
= spill_restore_mem (reg
, cfa_off
);
2505 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2506 spill_fill_data
.prev_insn
[iter
] = insn
;
2513 RTX_FRAME_RELATED_P (insn
) = 1;
2515 /* Don't even pretend that the unwind code can intuit its way
2516 through a pair of interleaved post_modify iterators. Just
2517 provide the correct answer. */
2519 if (frame_pointer_needed
)
2521 base
= hard_frame_pointer_rtx
;
2526 base
= stack_pointer_rtx
;
2527 off
= current_frame_info
.total_size
- cfa_off
;
2531 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2532 gen_rtx_SET (VOIDmode
,
2533 gen_rtx_MEM (GET_MODE (reg
),
2534 plus_constant (base
, off
)),
2541 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
2543 int iter
= spill_fill_data
.next_iter
;
2546 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2547 GEN_INT (cfa_off
)));
2548 spill_fill_data
.prev_insn
[iter
] = insn
;
2551 /* Wrapper functions that discards the CONST_INT spill offset. These
2552 exist so that we can give gr_spill/gr_fill the offset they need and
2553 use a consistent function interface. */
2556 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2558 return gen_movdi (dest
, src
);
2562 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2564 return gen_fr_spill (dest
, src
);
2568 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2570 return gen_fr_restore (dest
, src
);
2573 /* Called after register allocation to add any instructions needed for the
2574 prologue. Using a prologue insn is favored compared to putting all of the
2575 instructions in output_function_prologue(), since it allows the scheduler
2576 to intermix instructions with the saves of the caller saved registers. In
2577 some cases, it might be necessary to emit a barrier instruction as the last
2578 insn to prevent such scheduling.
2580 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2581 so that the debug info generation code can handle them properly.
2583 The register save area is layed out like so:
2585 [ varargs spill area ]
2586 [ fr register spill area ]
2587 [ br register spill area ]
2588 [ ar register spill area ]
2589 [ pr register spill area ]
2590 [ gr register spill area ] */
2592 /* ??? Get inefficient code when the frame size is larger than can fit in an
2593 adds instruction. */
2596 ia64_expand_prologue (void)
2598 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2599 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2602 ia64_compute_frame_size (get_frame_size ());
2603 last_scratch_gr_reg
= 15;
2605 /* If there is no epilogue, then we don't need some prologue insns.
2606 We need to avoid emitting the dead prologue insns, because flow
2607 will complain about them. */
2612 for (e
= EXIT_BLOCK_PTR
->pred
; e
; e
= e
->pred_next
)
2613 if ((e
->flags
& EDGE_FAKE
) == 0
2614 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2616 epilogue_p
= (e
!= NULL
);
2621 /* Set the local, input, and output register names. We need to do this
2622 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2623 half. If we use in/loc/out register names, then we get assembler errors
2624 in crtn.S because there is no alloc insn or regstk directive in there. */
2625 if (! TARGET_REG_NAMES
)
2627 int inputs
= current_frame_info
.n_input_regs
;
2628 int locals
= current_frame_info
.n_local_regs
;
2629 int outputs
= current_frame_info
.n_output_regs
;
2631 for (i
= 0; i
< inputs
; i
++)
2632 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2633 for (i
= 0; i
< locals
; i
++)
2634 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2635 for (i
= 0; i
< outputs
; i
++)
2636 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2639 /* Set the frame pointer register name. The regnum is logically loc79,
2640 but of course we'll not have allocated that many locals. Rather than
2641 worrying about renumbering the existing rtxs, we adjust the name. */
2642 /* ??? This code means that we can never use one local register when
2643 there is a frame pointer. loc79 gets wasted in this case, as it is
2644 renamed to a register that will never be used. See also the try_locals
2645 code in find_gr_spill. */
2646 if (current_frame_info
.reg_fp
)
2648 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2649 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2650 = reg_names
[current_frame_info
.reg_fp
];
2651 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2654 /* We don't need an alloc instruction if we've used no outputs or locals. */
2655 if (current_frame_info
.n_local_regs
== 0
2656 && current_frame_info
.n_output_regs
== 0
2657 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2658 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2660 /* If there is no alloc, but there are input registers used, then we
2661 need a .regstk directive. */
2662 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2663 ar_pfs_save_reg
= NULL_RTX
;
2667 current_frame_info
.need_regstk
= 0;
2669 if (current_frame_info
.reg_save_ar_pfs
)
2670 regno
= current_frame_info
.reg_save_ar_pfs
;
2672 regno
= next_scratch_gr_reg ();
2673 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2675 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2676 GEN_INT (current_frame_info
.n_input_regs
),
2677 GEN_INT (current_frame_info
.n_local_regs
),
2678 GEN_INT (current_frame_info
.n_output_regs
),
2679 GEN_INT (current_frame_info
.n_rotate_regs
)));
2680 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2683 /* Set up frame pointer, stack pointer, and spill iterators. */
2685 n_varargs
= cfun
->machine
->n_varargs
;
2686 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2687 stack_pointer_rtx
, 0);
2689 if (frame_pointer_needed
)
2691 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2692 RTX_FRAME_RELATED_P (insn
) = 1;
2695 if (current_frame_info
.total_size
!= 0)
2697 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2700 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2701 offset
= frame_size_rtx
;
2704 regno
= next_scratch_gr_reg ();
2705 offset
= gen_rtx_REG (DImode
, regno
);
2706 emit_move_insn (offset
, frame_size_rtx
);
2709 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2710 stack_pointer_rtx
, offset
));
2712 if (! frame_pointer_needed
)
2714 RTX_FRAME_RELATED_P (insn
) = 1;
2715 if (GET_CODE (offset
) != CONST_INT
)
2718 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2719 gen_rtx_SET (VOIDmode
,
2721 gen_rtx_PLUS (DImode
,
2728 /* ??? At this point we must generate a magic insn that appears to
2729 modify the stack pointer, the frame pointer, and all spill
2730 iterators. This would allow the most scheduling freedom. For
2731 now, just hard stop. */
2732 emit_insn (gen_blockage ());
2735 /* Must copy out ar.unat before doing any integer spills. */
2736 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2738 if (current_frame_info
.reg_save_ar_unat
)
2740 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2743 alt_regno
= next_scratch_gr_reg ();
2744 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2745 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2748 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2749 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2750 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2752 /* Even if we're not going to generate an epilogue, we still
2753 need to save the register so that EH works. */
2754 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2755 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2758 ar_unat_save_reg
= NULL_RTX
;
2760 /* Spill all varargs registers. Do this before spilling any GR registers,
2761 since we want the UNAT bits for the GR registers to override the UNAT
2762 bits from varargs, which we don't care about. */
2765 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2767 reg
= gen_rtx_REG (DImode
, regno
);
2768 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2771 /* Locate the bottom of the register save area. */
2772 cfa_off
= (current_frame_info
.spill_cfa_off
2773 + current_frame_info
.spill_size
2774 + current_frame_info
.extra_spill_size
);
2776 /* Save the predicate register block either in a register or in memory. */
2777 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2779 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2780 if (current_frame_info
.reg_save_pr
!= 0)
2782 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2783 insn
= emit_move_insn (alt_reg
, reg
);
2785 /* ??? Denote pr spill/fill by a DImode move that modifies all
2786 64 hard registers. */
2787 RTX_FRAME_RELATED_P (insn
) = 1;
2789 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2790 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2793 /* Even if we're not going to generate an epilogue, we still
2794 need to save the register so that EH works. */
2796 emit_insn (gen_prologue_use (alt_reg
));
2800 alt_regno
= next_scratch_gr_reg ();
2801 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2802 insn
= emit_move_insn (alt_reg
, reg
);
2803 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2808 /* Handle AR regs in numerical order. All of them get special handling. */
2809 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2810 && current_frame_info
.reg_save_ar_unat
== 0)
2812 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2813 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2817 /* The alloc insn already copied ar.pfs into a general register. The
2818 only thing we have to do now is copy that register to a stack slot
2819 if we'd not allocated a local register for the job. */
2820 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2821 && current_frame_info
.reg_save_ar_pfs
== 0)
2823 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2824 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2828 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2830 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2831 if (current_frame_info
.reg_save_ar_lc
!= 0)
2833 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2834 insn
= emit_move_insn (alt_reg
, reg
);
2835 RTX_FRAME_RELATED_P (insn
) = 1;
2837 /* Even if we're not going to generate an epilogue, we still
2838 need to save the register so that EH works. */
2840 emit_insn (gen_prologue_use (alt_reg
));
2844 alt_regno
= next_scratch_gr_reg ();
2845 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2846 emit_move_insn (alt_reg
, reg
);
2847 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2852 if (current_frame_info
.reg_save_gp
)
2854 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2855 current_frame_info
.reg_save_gp
),
2856 pic_offset_table_rtx
);
2857 /* We don't know for sure yet if this is actually needed, since
2858 we've not split the PIC call patterns. If all of the calls
2859 are indirect, and not followed by any uses of the gp, then
2860 this save is dead. Allow it to go away. */
2862 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2865 /* We should now be at the base of the gr/br/fr spill area. */
2866 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2867 + current_frame_info
.spill_size
))
2870 /* Spill all general registers. */
2871 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2872 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2874 reg
= gen_rtx_REG (DImode
, regno
);
2875 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2879 /* Handle BR0 specially -- it may be getting stored permanently in
2880 some GR register. */
2881 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2883 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2884 if (current_frame_info
.reg_save_b0
!= 0)
2886 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2887 insn
= emit_move_insn (alt_reg
, reg
);
2888 RTX_FRAME_RELATED_P (insn
) = 1;
2890 /* Even if we're not going to generate an epilogue, we still
2891 need to save the register so that EH works. */
2893 emit_insn (gen_prologue_use (alt_reg
));
2897 alt_regno
= next_scratch_gr_reg ();
2898 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2899 emit_move_insn (alt_reg
, reg
);
2900 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2905 /* Spill the rest of the BR registers. */
2906 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2907 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2909 alt_regno
= next_scratch_gr_reg ();
2910 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2911 reg
= gen_rtx_REG (DImode
, regno
);
2912 emit_move_insn (alt_reg
, reg
);
2913 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2917 /* Align the frame and spill all FR registers. */
2918 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2919 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2923 reg
= gen_rtx_REG (XFmode
, regno
);
2924 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2928 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2931 finish_spill_pointers ();
2934 /* Called after register allocation to add any instructions needed for the
2935 epilogue. Using an epilogue insn is favored compared to putting all of the
2936 instructions in output_function_prologue(), since it allows the scheduler
2937 to intermix instructions with the saves of the caller saved registers. In
2938 some cases, it might be necessary to emit a barrier instruction as the last
2939 insn to prevent such scheduling. */
2942 ia64_expand_epilogue (int sibcall_p
)
2944 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2945 int regno
, alt_regno
, cfa_off
;
2947 ia64_compute_frame_size (get_frame_size ());
2949 /* If there is a frame pointer, then we use it instead of the stack
2950 pointer, so that the stack pointer does not need to be valid when
2951 the epilogue starts. See EXIT_IGNORE_STACK. */
2952 if (frame_pointer_needed
)
2953 setup_spill_pointers (current_frame_info
.n_spilled
,
2954 hard_frame_pointer_rtx
, 0);
2956 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2957 current_frame_info
.total_size
);
2959 if (current_frame_info
.total_size
!= 0)
2961 /* ??? At this point we must generate a magic insn that appears to
2962 modify the spill iterators and the frame pointer. This would
2963 allow the most scheduling freedom. For now, just hard stop. */
2964 emit_insn (gen_blockage ());
2967 /* Locate the bottom of the register save area. */
2968 cfa_off
= (current_frame_info
.spill_cfa_off
2969 + current_frame_info
.spill_size
2970 + current_frame_info
.extra_spill_size
);
2972 /* Restore the predicate registers. */
2973 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2975 if (current_frame_info
.reg_save_pr
!= 0)
2976 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2979 alt_regno
= next_scratch_gr_reg ();
2980 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2981 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2984 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2985 emit_move_insn (reg
, alt_reg
);
2988 /* Restore the application registers. */
2990 /* Load the saved unat from the stack, but do not restore it until
2991 after the GRs have been restored. */
2992 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2994 if (current_frame_info
.reg_save_ar_unat
!= 0)
2996 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2999 alt_regno
= next_scratch_gr_reg ();
3000 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3001 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3002 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3007 ar_unat_save_reg
= NULL_RTX
;
3009 if (current_frame_info
.reg_save_ar_pfs
!= 0)
3011 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
3012 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3013 emit_move_insn (reg
, alt_reg
);
3015 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3017 alt_regno
= next_scratch_gr_reg ();
3018 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3019 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3021 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3022 emit_move_insn (reg
, alt_reg
);
3025 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3027 if (current_frame_info
.reg_save_ar_lc
!= 0)
3028 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
3031 alt_regno
= next_scratch_gr_reg ();
3032 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3033 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3036 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3037 emit_move_insn (reg
, alt_reg
);
3040 /* We should now be at the base of the gr/br/fr spill area. */
3041 if (cfa_off
!= (current_frame_info
.spill_cfa_off
3042 + current_frame_info
.spill_size
))
3045 /* The GP may be stored on the stack in the prologue, but it's
3046 never restored in the epilogue. Skip the stack slot. */
3047 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3050 /* Restore all general registers. */
3051 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3052 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3054 reg
= gen_rtx_REG (DImode
, regno
);
3055 do_restore (gen_gr_restore
, reg
, cfa_off
);
3059 /* Restore the branch registers. Handle B0 specially, as it may
3060 have gotten stored in some GR register. */
3061 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3063 if (current_frame_info
.reg_save_b0
!= 0)
3064 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3067 alt_regno
= next_scratch_gr_reg ();
3068 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3069 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3072 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3073 emit_move_insn (reg
, alt_reg
);
3076 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3077 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3079 alt_regno
= next_scratch_gr_reg ();
3080 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3081 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3083 reg
= gen_rtx_REG (DImode
, regno
);
3084 emit_move_insn (reg
, alt_reg
);
3087 /* Restore floating point registers. */
3088 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3089 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3093 reg
= gen_rtx_REG (XFmode
, regno
);
3094 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
3098 /* Restore ar.unat for real. */
3099 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3101 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3102 emit_move_insn (reg
, ar_unat_save_reg
);
3105 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
3108 finish_spill_pointers ();
3110 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
3112 /* ??? At this point we must generate a magic insn that appears to
3113 modify the spill iterators, the stack pointer, and the frame
3114 pointer. This would allow the most scheduling freedom. For now,
3116 emit_insn (gen_blockage ());
3119 if (cfun
->machine
->ia64_eh_epilogue_sp
)
3120 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
3121 else if (frame_pointer_needed
)
3123 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3124 RTX_FRAME_RELATED_P (insn
) = 1;
3126 else if (current_frame_info
.total_size
)
3128 rtx offset
, frame_size_rtx
;
3130 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
3131 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
3132 offset
= frame_size_rtx
;
3135 regno
= next_scratch_gr_reg ();
3136 offset
= gen_rtx_REG (DImode
, regno
);
3137 emit_move_insn (offset
, frame_size_rtx
);
3140 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
3143 RTX_FRAME_RELATED_P (insn
) = 1;
3144 if (GET_CODE (offset
) != CONST_INT
)
3147 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3148 gen_rtx_SET (VOIDmode
,
3150 gen_rtx_PLUS (DImode
,
3157 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
3158 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
3161 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
3164 int fp
= GR_REG (2);
3165 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3166 first available call clobbered register. If there was a frame_pointer
3167 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3168 so we have to make sure we're using the string "r2" when emitting
3169 the register name for the assembler. */
3170 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
3171 fp
= HARD_FRAME_POINTER_REGNUM
;
3173 /* We must emit an alloc to force the input registers to become output
3174 registers. Otherwise, if the callee tries to pass its parameters
3175 through to another call without an intervening alloc, then these
3177 /* ??? We don't need to preserve all input registers. We only need to
3178 preserve those input registers used as arguments to the sibling call.
3179 It is unclear how to compute that number here. */
3180 if (current_frame_info
.n_input_regs
!= 0)
3181 emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
3182 const0_rtx
, const0_rtx
,
3183 GEN_INT (current_frame_info
.n_input_regs
),
3188 /* Return 1 if br.ret can do all the work required to return from a
3192 ia64_direct_return (void)
3194 if (reload_completed
&& ! frame_pointer_needed
)
3196 ia64_compute_frame_size (get_frame_size ());
3198 return (current_frame_info
.total_size
== 0
3199 && current_frame_info
.n_spilled
== 0
3200 && current_frame_info
.reg_save_b0
== 0
3201 && current_frame_info
.reg_save_pr
== 0
3202 && current_frame_info
.reg_save_ar_pfs
== 0
3203 && current_frame_info
.reg_save_ar_unat
== 0
3204 && current_frame_info
.reg_save_ar_lc
== 0);
3209 /* Return the magic cookie that we use to hold the return address
3210 during early compilation. */
3213 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3217 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3220 /* Split this value after reload, now that we know where the return
3221 address is saved. */
3224 ia64_split_return_addr_rtx (rtx dest
)
3228 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3230 if (current_frame_info
.reg_save_b0
!= 0)
3231 src
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3237 /* Compute offset from CFA for BR0. */
3238 /* ??? Must be kept in sync with ia64_expand_prologue. */
3239 off
= (current_frame_info
.spill_cfa_off
3240 + current_frame_info
.spill_size
);
3241 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3242 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3245 /* Convert CFA offset to a register based offset. */
3246 if (frame_pointer_needed
)
3247 src
= hard_frame_pointer_rtx
;
3250 src
= stack_pointer_rtx
;
3251 off
+= current_frame_info
.total_size
;
3254 /* Load address into scratch register. */
3255 if (CONST_OK_FOR_I (off
))
3256 emit_insn (gen_adddi3 (dest
, src
, GEN_INT (off
)));
3259 emit_move_insn (dest
, GEN_INT (off
));
3260 emit_insn (gen_adddi3 (dest
, src
, dest
));
3263 src
= gen_rtx_MEM (Pmode
, dest
);
3267 src
= gen_rtx_REG (DImode
, BR_REG (0));
3269 emit_move_insn (dest
, src
);
3273 ia64_hard_regno_rename_ok (int from
, int to
)
3275 /* Don't clobber any of the registers we reserved for the prologue. */
3276 if (to
== current_frame_info
.reg_fp
3277 || to
== current_frame_info
.reg_save_b0
3278 || to
== current_frame_info
.reg_save_pr
3279 || to
== current_frame_info
.reg_save_ar_pfs
3280 || to
== current_frame_info
.reg_save_ar_unat
3281 || to
== current_frame_info
.reg_save_ar_lc
)
3284 if (from
== current_frame_info
.reg_fp
3285 || from
== current_frame_info
.reg_save_b0
3286 || from
== current_frame_info
.reg_save_pr
3287 || from
== current_frame_info
.reg_save_ar_pfs
3288 || from
== current_frame_info
.reg_save_ar_unat
3289 || from
== current_frame_info
.reg_save_ar_lc
)
3292 /* Don't use output registers outside the register frame. */
3293 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3296 /* Retain even/oddness on predicate register pairs. */
3297 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3298 return (from
& 1) == (to
& 1);
3303 /* Target hook for assembling integer objects. Handle word-sized
3304 aligned objects and detect the cases when @fptr is needed. */
3307 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3309 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3311 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3312 && GET_CODE (x
) == SYMBOL_REF
3313 && SYMBOL_REF_FUNCTION_P (x
))
3315 if (POINTER_SIZE
== 32)
3316 fputs ("\tdata4\t@fptr(", asm_out_file
);
3318 fputs ("\tdata8\t@fptr(", asm_out_file
);
3319 output_addr_const (asm_out_file
, x
);
3320 fputs (")\n", asm_out_file
);
3323 return default_assemble_integer (x
, size
, aligned_p
);
3326 /* Emit the function prologue. */
3329 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3331 int mask
, grsave
, grsave_prev
;
3333 if (current_frame_info
.need_regstk
)
3334 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3335 current_frame_info
.n_input_regs
,
3336 current_frame_info
.n_local_regs
,
3337 current_frame_info
.n_output_regs
,
3338 current_frame_info
.n_rotate_regs
);
3340 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3343 /* Emit the .prologue directive. */
3346 grsave
= grsave_prev
= 0;
3347 if (current_frame_info
.reg_save_b0
!= 0)
3350 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3352 if (current_frame_info
.reg_save_ar_pfs
!= 0
3353 && (grsave_prev
== 0
3354 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3357 if (grsave_prev
== 0)
3358 grsave
= current_frame_info
.reg_save_ar_pfs
;
3359 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3361 if (current_frame_info
.reg_fp
!= 0
3362 && (grsave_prev
== 0
3363 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3366 if (grsave_prev
== 0)
3367 grsave
= HARD_FRAME_POINTER_REGNUM
;
3368 grsave_prev
= current_frame_info
.reg_fp
;
3370 if (current_frame_info
.reg_save_pr
!= 0
3371 && (grsave_prev
== 0
3372 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3375 if (grsave_prev
== 0)
3376 grsave
= current_frame_info
.reg_save_pr
;
3379 if (mask
&& TARGET_GNU_AS
)
3380 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3381 ia64_dbx_register_number (grsave
));
3383 fputs ("\t.prologue\n", file
);
3385 /* Emit a .spill directive, if necessary, to relocate the base of
3386 the register spill area. */
3387 if (current_frame_info
.spill_cfa_off
!= -16)
3388 fprintf (file
, "\t.spill %ld\n",
3389 (long) (current_frame_info
.spill_cfa_off
3390 + current_frame_info
.spill_size
));
3393 /* Emit the .body directive at the scheduled end of the prologue. */
3396 ia64_output_function_end_prologue (FILE *file
)
3398 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3401 fputs ("\t.body\n", file
);
3404 /* Emit the function epilogue. */
3407 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3408 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3412 if (current_frame_info
.reg_fp
)
3414 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3415 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3416 = reg_names
[current_frame_info
.reg_fp
];
3417 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3419 if (! TARGET_REG_NAMES
)
3421 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3422 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3423 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3424 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3425 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3426 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3429 current_frame_info
.initialized
= 0;
3433 ia64_dbx_register_number (int regno
)
3435 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3436 from its home at loc79 to something inside the register frame. We
3437 must perform the same renumbering here for the debug info. */
3438 if (current_frame_info
.reg_fp
)
3440 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3441 regno
= current_frame_info
.reg_fp
;
3442 else if (regno
== current_frame_info
.reg_fp
)
3443 regno
= HARD_FRAME_POINTER_REGNUM
;
3446 if (IN_REGNO_P (regno
))
3447 return 32 + regno
- IN_REG (0);
3448 else if (LOC_REGNO_P (regno
))
3449 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3450 else if (OUT_REGNO_P (regno
))
3451 return (32 + current_frame_info
.n_input_regs
3452 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3458 ia64_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
3460 rtx addr_reg
, eight
= GEN_INT (8);
3462 /* The Intel assembler requires that the global __ia64_trampoline symbol
3463 be declared explicitly */
3466 static bool declared_ia64_trampoline
= false;
3468 if (!declared_ia64_trampoline
)
3470 declared_ia64_trampoline
= true;
3471 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
3472 "__ia64_trampoline");
3476 /* Load up our iterator. */
3477 addr_reg
= gen_reg_rtx (Pmode
);
3478 emit_move_insn (addr_reg
, addr
);
3480 /* The first two words are the fake descriptor:
3481 __ia64_trampoline, ADDR+16. */
3482 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3483 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3484 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3486 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3487 copy_to_reg (plus_constant (addr
, 16)));
3488 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3490 /* The third word is the target descriptor. */
3491 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3492 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3494 /* The fourth word is the static chain. */
3495 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3498 /* Do any needed setup for a variadic function. CUM has not been updated
3499 for the last named argument which has type TYPE and mode MODE.
3501 We generate the actual spill instructions during prologue generation. */
3504 ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3505 tree type
, int * pretend_size
,
3506 int second_time ATTRIBUTE_UNUSED
)
3508 CUMULATIVE_ARGS next_cum
= *cum
;
3510 /* Skip the current argument. */
3511 ia64_function_arg_advance (&next_cum
, mode
, type
, 1);
3513 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
3515 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
3516 *pretend_size
= n
* UNITS_PER_WORD
;
3517 cfun
->machine
->n_varargs
= n
;
3521 /* Check whether TYPE is a homogeneous floating point aggregate. If
3522 it is, return the mode of the floating point type that appears
3523 in all leafs. If it is not, return VOIDmode.
3525 An aggregate is a homogeneous floating point aggregate is if all
3526 fields/elements in it have the same floating point type (e.g,
3527 SFmode). 128-bit quad-precision floats are excluded. */
3529 static enum machine_mode
3530 hfa_element_mode (tree type
, int nested
)
3532 enum machine_mode element_mode
= VOIDmode
;
3533 enum machine_mode mode
;
3534 enum tree_code code
= TREE_CODE (type
);
3535 int know_element_mode
= 0;
3540 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3541 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3542 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3543 case FILE_TYPE
: case SET_TYPE
: case LANG_TYPE
:
3547 /* Fortran complex types are supposed to be HFAs, so we need to handle
3548 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3551 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3552 && TYPE_MODE (type
) != TCmode
)
3553 return GET_MODE_INNER (TYPE_MODE (type
));
3558 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3559 mode if this is contained within an aggregate. */
3560 if (nested
&& TYPE_MODE (type
) != TFmode
)
3561 return TYPE_MODE (type
);
3566 return hfa_element_mode (TREE_TYPE (type
), 1);
3570 case QUAL_UNION_TYPE
:
3571 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3573 if (TREE_CODE (t
) != FIELD_DECL
)
3576 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3577 if (know_element_mode
)
3579 if (mode
!= element_mode
)
3582 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3586 know_element_mode
= 1;
3587 element_mode
= mode
;
3590 return element_mode
;
3593 /* If we reach here, we probably have some front-end specific type
3594 that the backend doesn't know about. This can happen via the
3595 aggregate_value_p call in init_function_start. All we can do is
3596 ignore unknown tree types. */
3603 /* Return the number of words required to hold a quantity of TYPE and MODE
3604 when passed as an argument. */
3606 ia64_function_arg_words (tree type
, enum machine_mode mode
)
3610 if (mode
== BLKmode
)
3611 words
= int_size_in_bytes (type
);
3613 words
= GET_MODE_SIZE (mode
);
3615 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
3618 /* Return the number of registers that should be skipped so the current
3619 argument (described by TYPE and WORDS) will be properly aligned.
3621 Integer and float arguments larger than 8 bytes start at the next
3622 even boundary. Aggregates larger than 8 bytes start at the next
3623 even boundary if the aggregate has 16 byte alignment. Note that
3624 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3625 but are still to be aligned in registers.
3627 ??? The ABI does not specify how to handle aggregates with
3628 alignment from 9 to 15 bytes, or greater than 16. We handle them
3629 all as if they had 16 byte alignment. Such aggregates can occur
3630 only if gcc extensions are used. */
3632 ia64_function_arg_offset (CUMULATIVE_ARGS
*cum
, tree type
, int words
)
3634 if ((cum
->words
& 1) == 0)
3638 && TREE_CODE (type
) != INTEGER_TYPE
3639 && TREE_CODE (type
) != REAL_TYPE
)
3640 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
3645 /* Return rtx for register where argument is passed, or zero if it is passed
3647 /* ??? 128-bit quad-precision floats are always passed in general
3651 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
3652 int named
, int incoming
)
3654 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3655 int words
= ia64_function_arg_words (type
, mode
);
3656 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3657 enum machine_mode hfa_mode
= VOIDmode
;
3659 /* If all argument slots are used, then it must go on the stack. */
3660 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3663 /* Check for and handle homogeneous FP aggregates. */
3665 hfa_mode
= hfa_element_mode (type
, 0);
3667 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3668 and unprototyped hfas are passed specially. */
3669 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3673 int fp_regs
= cum
->fp_regs
;
3674 int int_regs
= cum
->words
+ offset
;
3675 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3679 /* If prototyped, pass it in FR regs then GR regs.
3680 If not prototyped, pass it in both FR and GR regs.
3682 If this is an SFmode aggregate, then it is possible to run out of
3683 FR regs while GR regs are still left. In that case, we pass the
3684 remaining part in the GR regs. */
3686 /* Fill the FP regs. We do this always. We stop if we reach the end
3687 of the argument, the last FP register, or the last argument slot. */
3689 byte_size
= ((mode
== BLKmode
)
3690 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3691 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3693 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3694 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3696 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3697 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3701 args_byte_size
+= hfa_size
;
3705 /* If no prototype, then the whole thing must go in GR regs. */
3706 if (! cum
->prototype
)
3708 /* If this is an SFmode aggregate, then we might have some left over
3709 that needs to go in GR regs. */
3710 else if (byte_size
!= offset
)
3711 int_regs
+= offset
/ UNITS_PER_WORD
;
3713 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3715 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3717 enum machine_mode gr_mode
= DImode
;
3718 unsigned int gr_size
;
3720 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3721 then this goes in a GR reg left adjusted/little endian, right
3722 adjusted/big endian. */
3723 /* ??? Currently this is handled wrong, because 4-byte hunks are
3724 always right adjusted/little endian. */
3727 /* If we have an even 4 byte hunk because the aggregate is a
3728 multiple of 4 bytes in size, then this goes in a GR reg right
3729 adjusted/little endian. */
3730 else if (byte_size
- offset
== 4)
3733 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3734 gen_rtx_REG (gr_mode
, (basereg
3738 gr_size
= GET_MODE_SIZE (gr_mode
);
3740 if (gr_size
== UNITS_PER_WORD
3741 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
3743 else if (gr_size
> UNITS_PER_WORD
)
3744 int_regs
+= gr_size
/ UNITS_PER_WORD
;
3747 /* If we ended up using just one location, just return that one loc, but
3748 change the mode back to the argument mode. */
3750 return gen_rtx_REG (mode
, REGNO (XEXP (loc
[0], 0)));
3752 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3755 /* Integral and aggregates go in general registers. If we have run out of
3756 FR registers, then FP values must also go in general registers. This can
3757 happen when we have a SFmode HFA. */
3758 else if (mode
== TFmode
|| mode
== TCmode
3759 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3761 int byte_size
= ((mode
== BLKmode
)
3762 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3763 if (BYTES_BIG_ENDIAN
3764 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3765 && byte_size
< UNITS_PER_WORD
3768 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3769 gen_rtx_REG (DImode
,
3770 (basereg
+ cum
->words
3773 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3776 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3780 /* If there is a prototype, then FP values go in a FR register when
3781 named, and in a GR register when unnamed. */
3782 else if (cum
->prototype
)
3785 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3786 /* In big-endian mode, an anonymous SFmode value must be represented
3787 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3788 the value into the high half of the general register. */
3789 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
3790 return gen_rtx_PARALLEL (mode
,
3792 gen_rtx_EXPR_LIST (VOIDmode
,
3793 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
3796 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3798 /* If there is no prototype, then FP values go in both FR and GR
3802 /* See comment above. */
3803 enum machine_mode inner_mode
=
3804 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
3806 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3807 gen_rtx_REG (mode
, (FR_ARG_FIRST
3810 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3811 gen_rtx_REG (inner_mode
,
3812 (basereg
+ cum
->words
3816 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3820 /* Return number of words, at the beginning of the argument, that must be
3821 put in registers. 0 is the argument is entirely in registers or entirely
3825 ia64_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3826 tree type
, int named ATTRIBUTE_UNUSED
)
3828 int words
= ia64_function_arg_words (type
, mode
);
3829 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3831 /* If all argument slots are used, then it must go on the stack. */
3832 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3835 /* It doesn't matter whether the argument goes in FR or GR regs. If
3836 it fits within the 8 argument slots, then it goes entirely in
3837 registers. If it extends past the last argument slot, then the rest
3838 goes on the stack. */
3840 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3843 return MAX_ARGUMENT_SLOTS
- cum
->words
- offset
;
3846 /* Update CUM to point after this argument. This is patterned after
3847 ia64_function_arg. */
3850 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3851 tree type
, int named
)
3853 int words
= ia64_function_arg_words (type
, mode
);
3854 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3855 enum machine_mode hfa_mode
= VOIDmode
;
3857 /* If all arg slots are already full, then there is nothing to do. */
3858 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3861 cum
->words
+= words
+ offset
;
3863 /* Check for and handle homogeneous FP aggregates. */
3865 hfa_mode
= hfa_element_mode (type
, 0);
3867 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3868 and unprototyped hfas are passed specially. */
3869 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3871 int fp_regs
= cum
->fp_regs
;
3872 /* This is the original value of cum->words + offset. */
3873 int int_regs
= cum
->words
- words
;
3874 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3878 /* If prototyped, pass it in FR regs then GR regs.
3879 If not prototyped, pass it in both FR and GR regs.
3881 If this is an SFmode aggregate, then it is possible to run out of
3882 FR regs while GR regs are still left. In that case, we pass the
3883 remaining part in the GR regs. */
3885 /* Fill the FP regs. We do this always. We stop if we reach the end
3886 of the argument, the last FP register, or the last argument slot. */
3888 byte_size
= ((mode
== BLKmode
)
3889 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3890 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3892 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3893 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3896 args_byte_size
+= hfa_size
;
3900 cum
->fp_regs
= fp_regs
;
3903 /* Integral and aggregates go in general registers. If we have run out of
3904 FR registers, then FP values must also go in general registers. This can
3905 happen when we have a SFmode HFA. */
3906 else if (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
)
3907 cum
->int_regs
= cum
->words
;
3909 /* If there is a prototype, then FP values go in a FR register when
3910 named, and in a GR register when unnamed. */
3911 else if (cum
->prototype
)
3914 cum
->int_regs
= cum
->words
;
3916 /* ??? Complex types should not reach here. */
3917 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3919 /* If there is no prototype, then FP values go in both FR and GR
3923 /* ??? Complex types should not reach here. */
3924 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3925 cum
->int_regs
= cum
->words
;
3929 /* Variable sized types are passed by reference. */
3930 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3933 ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3934 enum machine_mode mode ATTRIBUTE_UNUSED
,
3935 tree type
, int named ATTRIBUTE_UNUSED
)
3937 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
3940 /* True if it is OK to do sibling call optimization for the specified
3941 call expression EXP. DECL will be the called function, or NULL if
3942 this is an indirect call. */
3944 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3946 /* We must always return with our current GP. This means we can
3947 only sibcall to functions defined in the current module. */
3948 return decl
&& (*targetm
.binds_local_p
) (decl
);
3952 /* Implement va_arg. */
3955 ia64_va_arg (tree valist
, tree type
)
3959 /* Variable sized types are passed by reference. */
3960 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
3962 rtx addr
= force_reg (ptr_mode
,
3963 std_expand_builtin_va_arg (valist
, build_pointer_type (type
)));
3964 #ifdef POINTERS_EXTEND_UNSIGNED
3965 addr
= convert_memory_address (Pmode
, addr
);
3967 return gen_rtx_MEM (ptr_mode
, addr
);
3970 /* Aggregate arguments with alignment larger than 8 bytes start at
3971 the next even boundary. Integer and floating point arguments
3972 do so if they are larger than 8 bytes, whether or not they are
3973 also aligned larger than 8 bytes. */
3974 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
3975 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3977 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
3978 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
3979 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3980 build_int_2 (-2 * UNITS_PER_WORD
, -1));
3981 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
3982 TREE_SIDE_EFFECTS (t
) = 1;
3983 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3986 return std_expand_builtin_va_arg (valist
, type
);
3989 /* Return 1 if function return value returned in memory. Return 0 if it is
3993 ia64_return_in_memory (tree valtype
, tree fntype ATTRIBUTE_UNUSED
)
3995 enum machine_mode mode
;
3996 enum machine_mode hfa_mode
;
3997 HOST_WIDE_INT byte_size
;
3999 mode
= TYPE_MODE (valtype
);
4000 byte_size
= GET_MODE_SIZE (mode
);
4001 if (mode
== BLKmode
)
4003 byte_size
= int_size_in_bytes (valtype
);
4008 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4010 hfa_mode
= hfa_element_mode (valtype
, 0);
4011 if (hfa_mode
!= VOIDmode
)
4013 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4015 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
4020 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
4026 /* Return rtx for register that holds the function return value. */
4029 ia64_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4031 enum machine_mode mode
;
4032 enum machine_mode hfa_mode
;
4034 mode
= TYPE_MODE (valtype
);
4035 hfa_mode
= hfa_element_mode (valtype
, 0);
4037 if (hfa_mode
!= VOIDmode
)
4045 hfa_size
= GET_MODE_SIZE (hfa_mode
);
4046 byte_size
= ((mode
== BLKmode
)
4047 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
4049 for (i
= 0; offset
< byte_size
; i
++)
4051 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4052 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
4058 return XEXP (loc
[0], 0);
4060 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4062 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
4063 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
4066 if (BYTES_BIG_ENDIAN
4067 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
4075 bytesize
= int_size_in_bytes (valtype
);
4076 for (i
= 0; offset
< bytesize
; i
++)
4078 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4079 gen_rtx_REG (DImode
,
4082 offset
+= UNITS_PER_WORD
;
4084 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4087 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4091 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
4092 We need to emit DTP-relative relocations. */
4095 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4099 fputs ("\tdata8.ua\t@dtprel(", file
);
4100 output_addr_const (file
, x
);
4104 /* Print a memory address as an operand to reference that memory location. */
4106 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4107 also call this from ia64_print_operand for memory addresses. */
4110 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
4111 rtx address ATTRIBUTE_UNUSED
)
4115 /* Print an operand to an assembler instruction.
4116 C Swap and print a comparison operator.
4117 D Print an FP comparison operator.
4118 E Print 32 - constant, for SImode shifts as extract.
4119 e Print 64 - constant, for DImode rotates.
4120 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4121 a floating point register emitted normally.
4122 I Invert a predicate register by adding 1.
4123 J Select the proper predicate register for a condition.
4124 j Select the inverse predicate register for a condition.
4125 O Append .acq for volatile load.
4126 P Postincrement of a MEM.
4127 Q Append .rel for volatile store.
4128 S Shift amount for shladd instruction.
4129 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4130 for Intel assembler.
4131 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4132 for Intel assembler.
4133 r Print register name, or constant 0 as r0. HP compatibility for
4136 ia64_print_operand (FILE * file
, rtx x
, int code
)
4143 /* Handled below. */
4148 enum rtx_code c
= swap_condition (GET_CODE (x
));
4149 fputs (GET_RTX_NAME (c
), file
);
4154 switch (GET_CODE (x
))
4166 str
= GET_RTX_NAME (GET_CODE (x
));
4173 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
4177 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
4181 if (x
== CONST0_RTX (GET_MODE (x
)))
4182 str
= reg_names
[FR_REG (0)];
4183 else if (x
== CONST1_RTX (GET_MODE (x
)))
4184 str
= reg_names
[FR_REG (1)];
4185 else if (GET_CODE (x
) == REG
)
4186 str
= reg_names
[REGNO (x
)];
4193 fputs (reg_names
[REGNO (x
) + 1], file
);
4199 unsigned int regno
= REGNO (XEXP (x
, 0));
4200 if (GET_CODE (x
) == EQ
)
4204 fputs (reg_names
[regno
], file
);
4209 if (MEM_VOLATILE_P (x
))
4210 fputs(".acq", file
);
4215 HOST_WIDE_INT value
;
4217 switch (GET_CODE (XEXP (x
, 0)))
4223 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
4224 if (GET_CODE (x
) == CONST_INT
)
4226 else if (GET_CODE (x
) == REG
)
4228 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
4236 value
= GET_MODE_SIZE (GET_MODE (x
));
4240 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
4244 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
4249 if (MEM_VOLATILE_P (x
))
4250 fputs(".rel", file
);
4254 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4258 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4260 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
4266 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4268 const char *prefix
= "0x";
4269 if (INTVAL (x
) & 0x80000000)
4271 fprintf (file
, "0xffffffff");
4274 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
4280 /* If this operand is the constant zero, write it as register zero.
4281 Any register, zero, or CONST_INT value is OK here. */
4282 if (GET_CODE (x
) == REG
)
4283 fputs (reg_names
[REGNO (x
)], file
);
4284 else if (x
== CONST0_RTX (GET_MODE (x
)))
4286 else if (GET_CODE (x
) == CONST_INT
)
4287 output_addr_const (file
, x
);
4289 output_operand_lossage ("invalid %%r value");
4296 /* For conditional branches, returns or calls, substitute
4297 sptk, dptk, dpnt, or spnt for %s. */
4298 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4301 int pred_val
= INTVAL (XEXP (x
, 0));
4303 /* Guess top and bottom 10% statically predicted. */
4304 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4306 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4308 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4313 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4318 fputs (which
, file
);
4323 x
= current_insn_predicate
;
4326 unsigned int regno
= REGNO (XEXP (x
, 0));
4327 if (GET_CODE (x
) == EQ
)
4329 fprintf (file
, "(%s) ", reg_names
[regno
]);
4334 output_operand_lossage ("ia64_print_operand: unknown code");
4338 switch (GET_CODE (x
))
4340 /* This happens for the spill/restore instructions. */
4345 /* ... fall through ... */
4348 fputs (reg_names
[REGNO (x
)], file
);
4353 rtx addr
= XEXP (x
, 0);
4354 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
4355 addr
= XEXP (addr
, 0);
4356 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4361 output_addr_const (file
, x
);
4368 /* Compute a (partial) cost for rtx X. Return true if the complete
4369 cost has been computed, and false if subexpressions should be
4370 scanned. In either case, *TOTAL contains the cost result. */
4371 /* ??? This is incomplete. */
4374 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4382 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4385 if (CONST_OK_FOR_I (INTVAL (x
)))
4387 else if (CONST_OK_FOR_J (INTVAL (x
)))
4390 *total
= COSTS_N_INSNS (1);
4393 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4396 *total
= COSTS_N_INSNS (1);
4401 *total
= COSTS_N_INSNS (1);
4407 *total
= COSTS_N_INSNS (3);
4411 /* For multiplies wider than HImode, we have to go to the FPU,
4412 which normally involves copies. Plus there's the latency
4413 of the multiply itself, and the latency of the instructions to
4414 transfer integer regs to FP regs. */
4415 /* ??? Check for FP mode. */
4416 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4417 *total
= COSTS_N_INSNS (10);
4419 *total
= COSTS_N_INSNS (2);
4427 *total
= COSTS_N_INSNS (1);
4434 /* We make divide expensive, so that divide-by-constant will be
4435 optimized to a multiply. */
4436 *total
= COSTS_N_INSNS (60);
4444 /* Calculate the cost of moving data from a register in class FROM to
4445 one in class TO, using MODE. */
4448 ia64_register_move_cost (enum machine_mode mode
, enum reg_class from
,
4451 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4452 if (to
== ADDL_REGS
)
4454 if (from
== ADDL_REGS
)
4457 /* All costs are symmetric, so reduce cases by putting the
4458 lower number class as the destination. */
4461 enum reg_class tmp
= to
;
4462 to
= from
, from
= tmp
;
4465 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4466 so that we get secondary memory reloads. Between FR_REGS,
4467 we have to make this at least as expensive as MEMORY_MOVE_COST
4468 to avoid spectacularly poor register class preferencing. */
4471 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4472 return MEMORY_MOVE_COST (mode
, to
, 0);
4480 /* Moving between PR registers takes two insns. */
4481 if (from
== PR_REGS
)
4483 /* Moving between PR and anything but GR is impossible. */
4484 if (from
!= GR_REGS
)
4485 return MEMORY_MOVE_COST (mode
, to
, 0);
4489 /* Moving between BR and anything but GR is impossible. */
4490 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4491 return MEMORY_MOVE_COST (mode
, to
, 0);
4496 /* Moving between AR and anything but GR is impossible. */
4497 if (from
!= GR_REGS
)
4498 return MEMORY_MOVE_COST (mode
, to
, 0);
4503 case GR_AND_FR_REGS
:
4504 case GR_AND_BR_REGS
:
4515 /* This function returns the register class required for a secondary
4516 register when copying between one of the registers in CLASS, and X,
4517 using MODE. A return value of NO_REGS means that no secondary register
4521 ia64_secondary_reload_class (enum reg_class
class,
4522 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4526 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4527 regno
= true_regnum (x
);
4534 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4535 interaction. We end up with two pseudos with overlapping lifetimes
4536 both of which are equiv to the same constant, and both which need
4537 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4538 changes depending on the path length, which means the qty_first_reg
4539 check in make_regs_eqv can give different answers at different times.
4540 At some point I'll probably need a reload_indi pattern to handle
4543 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4544 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4545 non-general registers for good measure. */
4546 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4549 /* This is needed if a pseudo used as a call_operand gets spilled to a
4551 if (GET_CODE (x
) == MEM
)
4556 /* Need to go through general registers to get to other class regs. */
4557 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4560 /* This can happen when a paradoxical subreg is an operand to the
4562 /* ??? This shouldn't be necessary after instruction scheduling is
4563 enabled, because paradoxical subregs are not accepted by
4564 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4565 stop the paradoxical subreg stupidity in the *_operand functions
4567 if (GET_CODE (x
) == MEM
4568 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4569 || GET_MODE (x
) == QImode
))
4572 /* This can happen because of the ior/and/etc patterns that accept FP
4573 registers as operands. If the third operand is a constant, then it
4574 needs to be reloaded into a FP register. */
4575 if (GET_CODE (x
) == CONST_INT
)
4578 /* This can happen because of register elimination in a muldi3 insn.
4579 E.g. `26107 * (unsigned long)&u'. */
4580 if (GET_CODE (x
) == PLUS
)
4585 /* ??? This happens if we cse/gcse a BImode value across a call,
4586 and the function has a nonlocal goto. This is because global
4587 does not allocate call crossing pseudos to hard registers when
4588 current_function_has_nonlocal_goto is true. This is relatively
4589 common for C++ programs that use exceptions. To reproduce,
4590 return NO_REGS and compile libstdc++. */
4591 if (GET_CODE (x
) == MEM
)
4594 /* This can happen when we take a BImode subreg of a DImode value,
4595 and that DImode value winds up in some non-GR register. */
4596 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4608 /* Emit text to declare externally defined variables and functions, because
4609 the Intel assembler does not support undefined externals. */
4612 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
4614 int save_referenced
;
4616 /* GNU as does not need anything here, but the HP linker does need
4617 something for external functions. */
4621 || TREE_CODE (decl
) != FUNCTION_DECL
4622 || strstr (name
, "__builtin_") == name
))
4625 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4626 the linker when we do this, so we need to be careful not to do this for
4627 builtin functions which have no library equivalent. Unfortunately, we
4628 can't tell here whether or not a function will actually be called by
4629 expand_expr, so we pull in library functions even if we may not need
4631 if (! strcmp (name
, "__builtin_next_arg")
4632 || ! strcmp (name
, "alloca")
4633 || ! strcmp (name
, "__builtin_constant_p")
4634 || ! strcmp (name
, "__builtin_args_info"))
4638 ia64_hpux_add_extern_decl (decl
);
4641 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4643 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4644 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4645 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4646 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4647 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4651 /* Parse the -mfixed-range= option string. */
4654 fix_range (const char *const_str
)
4657 char *str
, *dash
, *comma
;
4659 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4660 REG2 are either register names or register numbers. The effect
4661 of this option is to mark the registers in the range from REG1 to
4662 REG2 as ``fixed'' so they won't be used by the compiler. This is
4663 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4665 i
= strlen (const_str
);
4666 str
= (char *) alloca (i
+ 1);
4667 memcpy (str
, const_str
, i
+ 1);
4671 dash
= strchr (str
, '-');
4674 warning ("value of -mfixed-range must have form REG1-REG2");
4679 comma
= strchr (dash
+ 1, ',');
4683 first
= decode_reg_name (str
);
4686 warning ("unknown register name: %s", str
);
4690 last
= decode_reg_name (dash
+ 1);
4693 warning ("unknown register name: %s", dash
+ 1);
4701 warning ("%s-%s is an empty range", str
, dash
+ 1);
4705 for (i
= first
; i
<= last
; ++i
)
4706 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4716 static struct machine_function
*
4717 ia64_init_machine_status (void)
4719 return ggc_alloc_cleared (sizeof (struct machine_function
));
4722 /* Handle TARGET_OPTIONS switches. */
4725 ia64_override_options (void)
4729 const char *const name
; /* processor name or nickname. */
4730 const enum processor_type processor
;
4732 const processor_alias_table
[] =
4734 {"itanium", PROCESSOR_ITANIUM
},
4735 {"itanium1", PROCESSOR_ITANIUM
},
4736 {"merced", PROCESSOR_ITANIUM
},
4737 {"itanium2", PROCESSOR_ITANIUM2
},
4738 {"mckinley", PROCESSOR_ITANIUM2
},
4741 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4744 if (TARGET_AUTO_PIC
)
4745 target_flags
|= MASK_CONST_GP
;
4747 if (TARGET_INLINE_FLOAT_DIV_LAT
&& TARGET_INLINE_FLOAT_DIV_THR
)
4749 if ((target_flags_explicit
& MASK_INLINE_FLOAT_DIV_LAT
)
4750 && (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
))
4752 warning ("cannot optimize floating point division for both latency and throughput");
4753 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4757 if (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
)
4758 target_flags
&= ~MASK_INLINE_FLOAT_DIV_LAT
;
4760 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4764 if (TARGET_INLINE_INT_DIV_LAT
&& TARGET_INLINE_INT_DIV_THR
)
4766 if ((target_flags_explicit
& MASK_INLINE_INT_DIV_LAT
)
4767 && (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
))
4769 warning ("cannot optimize integer division for both latency and throughput");
4770 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4774 if (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
)
4775 target_flags
&= ~MASK_INLINE_INT_DIV_LAT
;
4777 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4781 if (TARGET_INLINE_SQRT_LAT
&& TARGET_INLINE_SQRT_THR
)
4783 if ((target_flags_explicit
& MASK_INLINE_SQRT_LAT
)
4784 && (target_flags_explicit
& MASK_INLINE_SQRT_THR
))
4786 warning ("cannot optimize square root for both latency and throughput");
4787 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4791 if (target_flags_explicit
& MASK_INLINE_SQRT_THR
)
4792 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4794 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4798 if (TARGET_INLINE_SQRT_LAT
)
4800 warning ("not yet implemented: latency-optimized inline square root");
4801 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4804 if (ia64_fixed_range_string
)
4805 fix_range (ia64_fixed_range_string
);
4807 if (ia64_tls_size_string
)
4810 unsigned long tmp
= strtoul (ia64_tls_size_string
, &end
, 10);
4811 if (*end
|| (tmp
!= 14 && tmp
!= 22 && tmp
!= 64))
4812 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string
);
4814 ia64_tls_size
= tmp
;
4817 if (!ia64_tune_string
)
4818 ia64_tune_string
= "itanium2";
4820 for (i
= 0; i
< pta_size
; i
++)
4821 if (! strcmp (ia64_tune_string
, processor_alias_table
[i
].name
))
4823 ia64_tune
= processor_alias_table
[i
].processor
;
4828 error ("bad value (%s) for -tune= switch", ia64_tune_string
);
4830 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4831 flag_schedule_insns_after_reload
= 0;
4833 /* Variable tracking should be run after all optimizations which change order
4834 of insns. It also needs a valid CFG. */
4835 ia64_flag_var_tracking
= flag_var_tracking
;
4836 flag_var_tracking
= 0;
4838 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4840 init_machine_status
= ia64_init_machine_status
;
4843 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
4844 static enum attr_type
ia64_safe_type (rtx
);
4846 static enum attr_itanium_class
4847 ia64_safe_itanium_class (rtx insn
)
4849 if (recog_memoized (insn
) >= 0)
4850 return get_attr_itanium_class (insn
);
4852 return ITANIUM_CLASS_UNKNOWN
;
4855 static enum attr_type
4856 ia64_safe_type (rtx insn
)
4858 if (recog_memoized (insn
) >= 0)
4859 return get_attr_type (insn
);
4861 return TYPE_UNKNOWN
;
4864 /* The following collection of routines emit instruction group stop bits as
4865 necessary to avoid dependencies. */
4867 /* Need to track some additional registers as far as serialization is
4868 concerned so we can properly handle br.call and br.ret. We could
4869 make these registers visible to gcc, but since these registers are
4870 never explicitly used in gcc generated code, it seems wasteful to
4871 do so (plus it would make the call and return patterns needlessly
4873 #define REG_RP (BR_REG (0))
4874 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4875 /* This is used for volatile asms which may require a stop bit immediately
4876 before and after them. */
4877 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4878 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4879 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4881 /* For each register, we keep track of how it has been written in the
4882 current instruction group.
4884 If a register is written unconditionally (no qualifying predicate),
4885 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4887 If a register is written if its qualifying predicate P is true, we
4888 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4889 may be written again by the complement of P (P^1) and when this happens,
4890 WRITE_COUNT gets set to 2.
4892 The result of this is that whenever an insn attempts to write a register
4893 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4895 If a predicate register is written by a floating-point insn, we set
4896 WRITTEN_BY_FP to true.
4898 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4899 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4901 struct reg_write_state
4903 unsigned int write_count
: 2;
4904 unsigned int first_pred
: 16;
4905 unsigned int written_by_fp
: 1;
4906 unsigned int written_by_and
: 1;
4907 unsigned int written_by_or
: 1;
4910 /* Cumulative info for the current instruction group. */
4911 struct reg_write_state rws_sum
[NUM_REGS
];
4912 /* Info for the current instruction. This gets copied to rws_sum after a
4913 stop bit is emitted. */
4914 struct reg_write_state rws_insn
[NUM_REGS
];
4916 /* Indicates whether this is the first instruction after a stop bit,
4917 in which case we don't need another stop bit. Without this, we hit
4918 the abort in ia64_variable_issue when scheduling an alloc. */
4919 static int first_instruction
;
4921 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4922 RTL for one instruction. */
4925 unsigned int is_write
: 1; /* Is register being written? */
4926 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
4927 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
4928 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
4929 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
4930 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
4933 static void rws_update (struct reg_write_state
*, int, struct reg_flags
, int);
4934 static int rws_access_regno (int, struct reg_flags
, int);
4935 static int rws_access_reg (rtx
, struct reg_flags
, int);
4936 static void update_set_flags (rtx
, struct reg_flags
*, int *, rtx
*);
4937 static int set_src_needs_barrier (rtx
, struct reg_flags
, int, rtx
);
4938 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
4939 static void init_insn_group_barriers (void);
4940 static int group_barrier_needed_p (rtx
);
4941 static int safe_group_barrier_needed_p (rtx
);
4943 /* Update *RWS for REGNO, which is being written by the current instruction,
4944 with predicate PRED, and associated register flags in FLAGS. */
4947 rws_update (struct reg_write_state
*rws
, int regno
, struct reg_flags flags
, int pred
)
4950 rws
[regno
].write_count
++;
4952 rws
[regno
].write_count
= 2;
4953 rws
[regno
].written_by_fp
|= flags
.is_fp
;
4954 /* ??? Not tracking and/or across differing predicates. */
4955 rws
[regno
].written_by_and
= flags
.is_and
;
4956 rws
[regno
].written_by_or
= flags
.is_or
;
4957 rws
[regno
].first_pred
= pred
;
4960 /* Handle an access to register REGNO of type FLAGS using predicate register
4961 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4962 a dependency with an earlier instruction in the same group. */
4965 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
4967 int need_barrier
= 0;
4969 if (regno
>= NUM_REGS
)
4972 if (! PR_REGNO_P (regno
))
4973 flags
.is_and
= flags
.is_or
= 0;
4979 /* One insn writes same reg multiple times? */
4980 if (rws_insn
[regno
].write_count
> 0)
4983 /* Update info for current instruction. */
4984 rws_update (rws_insn
, regno
, flags
, pred
);
4985 write_count
= rws_sum
[regno
].write_count
;
4987 switch (write_count
)
4990 /* The register has not been written yet. */
4991 rws_update (rws_sum
, regno
, flags
, pred
);
4995 /* The register has been written via a predicate. If this is
4996 not a complementary predicate, then we need a barrier. */
4997 /* ??? This assumes that P and P+1 are always complementary
4998 predicates for P even. */
4999 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5001 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5003 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5005 rws_update (rws_sum
, regno
, flags
, pred
);
5009 /* The register has been unconditionally written already. We
5011 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5013 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5017 rws_sum
[regno
].written_by_and
= flags
.is_and
;
5018 rws_sum
[regno
].written_by_or
= flags
.is_or
;
5027 if (flags
.is_branch
)
5029 /* Branches have several RAW exceptions that allow to avoid
5032 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
5033 /* RAW dependencies on branch regs are permissible as long
5034 as the writer is a non-branch instruction. Since we
5035 never generate code that uses a branch register written
5036 by a branch instruction, handling this case is
5040 if (REGNO_REG_CLASS (regno
) == PR_REGS
5041 && ! rws_sum
[regno
].written_by_fp
)
5042 /* The predicates of a branch are available within the
5043 same insn group as long as the predicate was written by
5044 something other than a floating-point instruction. */
5048 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5050 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5053 switch (rws_sum
[regno
].write_count
)
5056 /* The register has not been written yet. */
5060 /* The register has been written via a predicate. If this is
5061 not a complementary predicate, then we need a barrier. */
5062 /* ??? This assumes that P and P+1 are always complementary
5063 predicates for P even. */
5064 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5069 /* The register has been unconditionally written already. We
5079 return need_barrier
;
5083 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
5085 int regno
= REGNO (reg
);
5086 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
5089 return rws_access_regno (regno
, flags
, pred
);
5092 int need_barrier
= 0;
5094 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
5095 return need_barrier
;
5099 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5100 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5103 update_set_flags (rtx x
, struct reg_flags
*pflags
, int *ppred
, rtx
*pcond
)
5105 rtx src
= SET_SRC (x
);
5109 switch (GET_CODE (src
))
5115 if (SET_DEST (x
) == pc_rtx
)
5116 /* X is a conditional branch. */
5120 int is_complemented
= 0;
5122 /* X is a conditional move. */
5123 rtx cond
= XEXP (src
, 0);
5124 if (GET_CODE (cond
) == EQ
)
5125 is_complemented
= 1;
5126 cond
= XEXP (cond
, 0);
5127 if (GET_CODE (cond
) != REG
5128 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5131 if (XEXP (src
, 1) == SET_DEST (x
)
5132 || XEXP (src
, 2) == SET_DEST (x
))
5134 /* X is a conditional move that conditionally writes the
5137 /* We need another complement in this case. */
5138 if (XEXP (src
, 1) == SET_DEST (x
))
5139 is_complemented
= ! is_complemented
;
5141 *ppred
= REGNO (cond
);
5142 if (is_complemented
)
5146 /* ??? If this is a conditional write to the dest, then this
5147 instruction does not actually read one source. This probably
5148 doesn't matter, because that source is also the dest. */
5149 /* ??? Multiple writes to predicate registers are allowed
5150 if they are all AND type compares, or if they are all OR
5151 type compares. We do not generate such instructions
5154 /* ... fall through ... */
5157 if (COMPARISON_P (src
)
5158 && GET_MODE_CLASS (GET_MODE (XEXP (src
, 0))) == MODE_FLOAT
)
5159 /* Set pflags->is_fp to 1 so that we know we're dealing
5160 with a floating point comparison when processing the
5161 destination of the SET. */
5164 /* Discover if this is a parallel comparison. We only handle
5165 and.orcm and or.andcm at present, since we must retain a
5166 strict inverse on the predicate pair. */
5167 else if (GET_CODE (src
) == AND
)
5169 else if (GET_CODE (src
) == IOR
)
5176 /* Subroutine of rtx_needs_barrier; this function determines whether the
5177 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5178 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5182 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
, rtx cond
)
5184 int need_barrier
= 0;
5186 rtx src
= SET_SRC (x
);
5188 if (GET_CODE (src
) == CALL
)
5189 /* We don't need to worry about the result registers that
5190 get written by subroutine call. */
5191 return rtx_needs_barrier (src
, flags
, pred
);
5192 else if (SET_DEST (x
) == pc_rtx
)
5194 /* X is a conditional branch. */
5195 /* ??? This seems redundant, as the caller sets this bit for
5197 flags
.is_branch
= 1;
5198 return rtx_needs_barrier (src
, flags
, pred
);
5201 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
5203 /* This instruction unconditionally uses a predicate register. */
5205 need_barrier
|= rws_access_reg (cond
, flags
, 0);
5208 if (GET_CODE (dst
) == ZERO_EXTRACT
)
5210 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
5211 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
5212 dst
= XEXP (dst
, 0);
5214 return need_barrier
;
5217 /* Handle an access to rtx X of type FLAGS using predicate register
5218 PRED. Return 1 if this access creates a dependency with an earlier
5219 instruction in the same group. */
5222 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
5225 int is_complemented
= 0;
5226 int need_barrier
= 0;
5227 const char *format_ptr
;
5228 struct reg_flags new_flags
;
5236 switch (GET_CODE (x
))
5239 update_set_flags (x
, &new_flags
, &pred
, &cond
);
5240 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
, cond
);
5241 if (GET_CODE (SET_SRC (x
)) != CALL
)
5243 new_flags
.is_write
= 1;
5244 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
5249 new_flags
.is_write
= 0;
5250 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5252 /* Avoid multiple register writes, in case this is a pattern with
5253 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5254 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
5256 new_flags
.is_write
= 1;
5257 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
5258 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
5259 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5264 /* X is a predicated instruction. */
5266 cond
= COND_EXEC_TEST (x
);
5269 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
5271 if (GET_CODE (cond
) == EQ
)
5272 is_complemented
= 1;
5273 cond
= XEXP (cond
, 0);
5274 if (GET_CODE (cond
) != REG
5275 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5277 pred
= REGNO (cond
);
5278 if (is_complemented
)
5281 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
5282 return need_barrier
;
5286 /* Clobber & use are for earlier compiler-phases only. */
5291 /* We always emit stop bits for traditional asms. We emit stop bits
5292 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5293 if (GET_CODE (x
) != ASM_OPERANDS
5294 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
5296 /* Avoid writing the register multiple times if we have multiple
5297 asm outputs. This avoids an abort in rws_access_reg. */
5298 if (! rws_insn
[REG_VOLATILE
].write_count
)
5300 new_flags
.is_write
= 1;
5301 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5306 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5307 We can not just fall through here since then we would be confused
5308 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5309 traditional asms unlike their normal usage. */
5311 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5312 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5317 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5319 rtx pat
= XVECEXP (x
, 0, i
);
5320 if (GET_CODE (pat
) == SET
)
5322 update_set_flags (pat
, &new_flags
, &pred
, &cond
);
5323 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
, cond
);
5325 else if (GET_CODE (pat
) == USE
5326 || GET_CODE (pat
) == CALL
5327 || GET_CODE (pat
) == ASM_OPERANDS
)
5328 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5329 else if (GET_CODE (pat
) != CLOBBER
&& GET_CODE (pat
) != RETURN
)
5332 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5334 rtx pat
= XVECEXP (x
, 0, i
);
5335 if (GET_CODE (pat
) == SET
)
5337 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5339 new_flags
.is_write
= 1;
5340 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5344 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5345 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5353 if (REGNO (x
) == AR_UNAT_REGNUM
)
5355 for (i
= 0; i
< 64; ++i
)
5356 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5359 need_barrier
= rws_access_reg (x
, flags
, pred
);
5363 /* Find the regs used in memory address computation. */
5364 new_flags
.is_write
= 0;
5365 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5368 case CONST_INT
: case CONST_DOUBLE
:
5369 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5372 /* Operators with side-effects. */
5373 case POST_INC
: case POST_DEC
:
5374 if (GET_CODE (XEXP (x
, 0)) != REG
)
5377 new_flags
.is_write
= 0;
5378 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5379 new_flags
.is_write
= 1;
5380 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5384 if (GET_CODE (XEXP (x
, 0)) != REG
)
5387 new_flags
.is_write
= 0;
5388 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5389 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5390 new_flags
.is_write
= 1;
5391 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5394 /* Handle common unary and binary ops for efficiency. */
5395 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5396 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5397 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5398 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5399 case NE
: case EQ
: case GE
: case GT
: case LE
:
5400 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5401 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5402 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5405 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5406 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5407 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5408 case SQRT
: case FFS
: case POPCOUNT
:
5409 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5413 switch (XINT (x
, 1))
5415 case UNSPEC_LTOFF_DTPMOD
:
5416 case UNSPEC_LTOFF_DTPREL
:
5418 case UNSPEC_LTOFF_TPREL
:
5420 case UNSPEC_PRED_REL_MUTEX
:
5421 case UNSPEC_PIC_CALL
:
5423 case UNSPEC_FETCHADD_ACQ
:
5424 case UNSPEC_BSP_VALUE
:
5425 case UNSPEC_FLUSHRS
:
5426 case UNSPEC_BUNDLE_SELECTOR
:
5429 case UNSPEC_GR_SPILL
:
5430 case UNSPEC_GR_RESTORE
:
5432 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5433 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5435 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5436 new_flags
.is_write
= (XINT (x
, 1) == 1);
5437 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5442 case UNSPEC_FR_SPILL
:
5443 case UNSPEC_FR_RESTORE
:
5444 case UNSPEC_GETF_EXP
:
5445 case UNSPEC_SETF_EXP
:
5447 case UNSPEC_FR_SQRT_RECIP_APPROX
:
5448 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5451 case UNSPEC_FR_RECIP_APPROX
:
5452 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5453 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5456 case UNSPEC_CMPXCHG_ACQ
:
5457 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5458 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5466 case UNSPEC_VOLATILE
:
5467 switch (XINT (x
, 1))
5470 /* Alloc must always be the first instruction of a group.
5471 We force this by always returning true. */
5472 /* ??? We might get better scheduling if we explicitly check for
5473 input/local/output register dependencies, and modify the
5474 scheduler so that alloc is always reordered to the start of
5475 the current group. We could then eliminate all of the
5476 first_instruction code. */
5477 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5479 new_flags
.is_write
= 1;
5480 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5483 case UNSPECV_SET_BSP
:
5487 case UNSPECV_BLOCKAGE
:
5488 case UNSPECV_INSN_GROUP_BARRIER
:
5490 case UNSPECV_PSAC_ALL
:
5491 case UNSPECV_PSAC_NORMAL
:
5500 new_flags
.is_write
= 0;
5501 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5502 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5504 new_flags
.is_write
= 1;
5505 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5506 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5510 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5511 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5512 switch (format_ptr
[i
])
5514 case '0': /* unused field */
5515 case 'i': /* integer */
5516 case 'n': /* note */
5517 case 'w': /* wide integer */
5518 case 's': /* pointer to string */
5519 case 'S': /* optional pointer to string */
5523 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5528 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5529 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5538 return need_barrier
;
5541 /* Clear out the state for group_barrier_needed_p at the start of a
5542 sequence of insns. */
5545 init_insn_group_barriers (void)
5547 memset (rws_sum
, 0, sizeof (rws_sum
));
5548 first_instruction
= 1;
5551 /* Given the current state, recorded by previous calls to this function,
5552 determine whether a group barrier (a stop bit) is necessary before INSN.
5553 Return nonzero if so. */
5556 group_barrier_needed_p (rtx insn
)
5559 int need_barrier
= 0;
5560 struct reg_flags flags
;
5562 memset (&flags
, 0, sizeof (flags
));
5563 switch (GET_CODE (insn
))
5569 /* A barrier doesn't imply an instruction group boundary. */
5573 memset (rws_insn
, 0, sizeof (rws_insn
));
5577 flags
.is_branch
= 1;
5578 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5579 memset (rws_insn
, 0, sizeof (rws_insn
));
5581 /* Don't bundle a call following another call. */
5582 if ((pat
= prev_active_insn (insn
))
5583 && GET_CODE (pat
) == CALL_INSN
)
5589 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5593 flags
.is_branch
= 1;
5595 /* Don't bundle a jump following a call. */
5596 if ((pat
= prev_active_insn (insn
))
5597 && GET_CODE (pat
) == CALL_INSN
)
5605 if (GET_CODE (PATTERN (insn
)) == USE
5606 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5607 /* Don't care about USE and CLOBBER "insns"---those are used to
5608 indicate to the optimizer that it shouldn't get rid of
5609 certain operations. */
5612 pat
= PATTERN (insn
);
5614 /* Ug. Hack hacks hacked elsewhere. */
5615 switch (recog_memoized (insn
))
5617 /* We play dependency tricks with the epilogue in order
5618 to get proper schedules. Undo this for dv analysis. */
5619 case CODE_FOR_epilogue_deallocate_stack
:
5620 case CODE_FOR_prologue_allocate_stack
:
5621 pat
= XVECEXP (pat
, 0, 0);
5624 /* The pattern we use for br.cloop confuses the code above.
5625 The second element of the vector is representative. */
5626 case CODE_FOR_doloop_end_internal
:
5627 pat
= XVECEXP (pat
, 0, 1);
5630 /* Doesn't generate code. */
5631 case CODE_FOR_pred_rel_mutex
:
5632 case CODE_FOR_prologue_use
:
5639 memset (rws_insn
, 0, sizeof (rws_insn
));
5640 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5642 /* Check to see if the previous instruction was a volatile
5645 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5652 if (first_instruction
&& INSN_P (insn
)
5653 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5654 && GET_CODE (PATTERN (insn
)) != USE
5655 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5658 first_instruction
= 0;
5661 return need_barrier
;
5664 /* Like group_barrier_needed_p, but do not clobber the current state. */
5667 safe_group_barrier_needed_p (rtx insn
)
5669 struct reg_write_state rws_saved
[NUM_REGS
];
5670 int saved_first_instruction
;
5673 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5674 saved_first_instruction
= first_instruction
;
5676 t
= group_barrier_needed_p (insn
);
5678 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5679 first_instruction
= saved_first_instruction
;
5684 /* Scan the current function and insert stop bits as necessary to
5685 eliminate dependencies. This function assumes that a final
5686 instruction scheduling pass has been run which has already
5687 inserted most of the necessary stop bits. This function only
5688 inserts new ones at basic block boundaries, since these are
5689 invisible to the scheduler. */
5692 emit_insn_group_barriers (FILE *dump
)
5696 int insns_since_last_label
= 0;
5698 init_insn_group_barriers ();
5700 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5702 if (GET_CODE (insn
) == CODE_LABEL
)
5704 if (insns_since_last_label
)
5706 insns_since_last_label
= 0;
5708 else if (GET_CODE (insn
) == NOTE
5709 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5711 if (insns_since_last_label
)
5713 insns_since_last_label
= 0;
5715 else if (GET_CODE (insn
) == INSN
5716 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5717 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5719 init_insn_group_barriers ();
5722 else if (INSN_P (insn
))
5724 insns_since_last_label
= 1;
5726 if (group_barrier_needed_p (insn
))
5731 fprintf (dump
, "Emitting stop before label %d\n",
5732 INSN_UID (last_label
));
5733 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5736 init_insn_group_barriers ();
5744 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5745 This function has to emit all necessary group barriers. */
5748 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
5752 init_insn_group_barriers ();
5754 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5756 if (GET_CODE (insn
) == BARRIER
)
5758 rtx last
= prev_active_insn (insn
);
5762 if (GET_CODE (last
) == JUMP_INSN
5763 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5764 last
= prev_active_insn (last
);
5765 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5766 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5768 init_insn_group_barriers ();
5770 else if (INSN_P (insn
))
5772 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5773 init_insn_group_barriers ();
5774 else if (group_barrier_needed_p (insn
))
5776 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5777 init_insn_group_barriers ();
5778 group_barrier_needed_p (insn
);
5785 static int errata_find_address_regs (rtx
*, void *);
5786 static void errata_emit_nops (rtx
);
5787 static void fixup_errata (void);
5789 /* This structure is used to track some details about the previous insns
5790 groups so we can determine if it may be necessary to insert NOPs to
5791 workaround hardware errata. */
5794 HARD_REG_SET p_reg_set
;
5795 HARD_REG_SET gr_reg_conditionally_set
;
5798 /* Index into the last_group array. */
5799 static int group_idx
;
5801 /* Called through for_each_rtx; determines if a hard register that was
5802 conditionally set in the previous group is used as an address register.
5803 It ensures that for_each_rtx returns 1 in that case. */
5805 errata_find_address_regs (rtx
*xp
, void *data ATTRIBUTE_UNUSED
)
5808 if (GET_CODE (x
) != MEM
)
5811 if (GET_CODE (x
) == POST_MODIFY
)
5813 if (GET_CODE (x
) == REG
)
5815 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5816 if (TEST_HARD_REG_BIT (prev_group
->gr_reg_conditionally_set
,
5824 /* Called for each insn; this function keeps track of the state in
5825 last_group and emits additional NOPs if necessary to work around
5826 an Itanium A/B step erratum. */
5828 errata_emit_nops (rtx insn
)
5830 struct group
*this_group
= last_group
+ group_idx
;
5831 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5832 rtx pat
= PATTERN (insn
);
5833 rtx cond
= GET_CODE (pat
) == COND_EXEC
? COND_EXEC_TEST (pat
) : 0;
5834 rtx real_pat
= cond
? COND_EXEC_CODE (pat
) : pat
;
5835 enum attr_type type
;
5838 if (GET_CODE (real_pat
) == USE
5839 || GET_CODE (real_pat
) == CLOBBER
5840 || GET_CODE (real_pat
) == ASM_INPUT
5841 || GET_CODE (real_pat
) == ADDR_VEC
5842 || GET_CODE (real_pat
) == ADDR_DIFF_VEC
5843 || asm_noperands (PATTERN (insn
)) >= 0)
5846 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5849 if (GET_CODE (set
) == PARALLEL
)
5852 set
= XVECEXP (real_pat
, 0, 0);
5853 for (i
= 1; i
< XVECLEN (real_pat
, 0); i
++)
5854 if (GET_CODE (XVECEXP (real_pat
, 0, i
)) != USE
5855 && GET_CODE (XVECEXP (real_pat
, 0, i
)) != CLOBBER
)
5862 if (set
&& GET_CODE (set
) != SET
)
5865 type
= get_attr_type (insn
);
5868 && set
&& REG_P (SET_DEST (set
)) && PR_REGNO_P (REGNO (SET_DEST (set
))))
5869 SET_HARD_REG_BIT (this_group
->p_reg_set
, REGNO (SET_DEST (set
)));
5871 if ((type
== TYPE_M
|| type
== TYPE_A
) && cond
&& set
5872 && REG_P (SET_DEST (set
))
5873 && GET_CODE (SET_SRC (set
)) != PLUS
5874 && GET_CODE (SET_SRC (set
)) != MINUS
5875 && (GET_CODE (SET_SRC (set
)) != ASHIFT
5876 || !shladd_operand (XEXP (SET_SRC (set
), 1), VOIDmode
))
5877 && (GET_CODE (SET_SRC (set
)) != MEM
5878 || GET_CODE (XEXP (SET_SRC (set
), 0)) != POST_MODIFY
)
5879 && GENERAL_REGNO_P (REGNO (SET_DEST (set
))))
5881 if (!COMPARISON_P (cond
)
5882 || !REG_P (XEXP (cond
, 0)))
5885 if (TEST_HARD_REG_BIT (prev_group
->p_reg_set
, REGNO (XEXP (cond
, 0))))
5886 SET_HARD_REG_BIT (this_group
->gr_reg_conditionally_set
, REGNO (SET_DEST (set
)));
5888 if (for_each_rtx (&real_pat
, errata_find_address_regs
, NULL
))
5890 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5891 emit_insn_before (gen_nop (), insn
);
5892 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5894 memset (last_group
, 0, sizeof last_group
);
5898 /* Emit extra nops if they are required to work around hardware errata. */
5905 if (! TARGET_B_STEP
)
5909 memset (last_group
, 0, sizeof last_group
);
5911 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5916 if (ia64_safe_type (insn
) == TYPE_S
)
5919 memset (last_group
+ group_idx
, 0, sizeof last_group
[group_idx
]);
5922 errata_emit_nops (insn
);
5927 /* Instruction scheduling support. */
5929 #define NR_BUNDLES 10
5931 /* A list of names of all available bundles. */
5933 static const char *bundle_name
[NR_BUNDLES
] =
5939 #if NR_BUNDLES == 10
5949 /* Nonzero if we should insert stop bits into the schedule. */
5951 int ia64_final_schedule
= 0;
5953 /* Codes of the corresponding quieryied units: */
5955 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5956 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5958 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5959 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5961 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5963 /* The following variable value is an insn group barrier. */
5965 static rtx dfa_stop_insn
;
5967 /* The following variable value is the last issued insn. */
5969 static rtx last_scheduled_insn
;
5971 /* The following variable value is size of the DFA state. */
5973 static size_t dfa_state_size
;
5975 /* The following variable value is pointer to a DFA state used as
5976 temporary variable. */
5978 static state_t temp_dfa_state
= NULL
;
5980 /* The following variable value is DFA state after issuing the last
5983 static state_t prev_cycle_state
= NULL
;
5985 /* The following array element values are TRUE if the corresponding
5986 insn requires to add stop bits before it. */
5988 static char *stops_p
;
5990 /* The following variable is used to set up the mentioned above array. */
5992 static int stop_before_p
= 0;
5994 /* The following variable value is length of the arrays `clocks' and
5997 static int clocks_length
;
5999 /* The following array element values are cycles on which the
6000 corresponding insn will be issued. The array is used only for
6005 /* The following array element values are numbers of cycles should be
6006 added to improve insn scheduling for MM_insns for Itanium1. */
6008 static int *add_cycles
;
6010 static rtx
ia64_single_set (rtx
);
6011 static void ia64_emit_insn_before (rtx
, rtx
);
6013 /* Map a bundle number to its pseudo-op. */
6016 get_bundle_name (int b
)
6018 return bundle_name
[b
];
6022 /* Return the maximum number of instructions a cpu can issue. */
6025 ia64_issue_rate (void)
6030 /* Helper function - like single_set, but look inside COND_EXEC. */
6033 ia64_single_set (rtx insn
)
6035 rtx x
= PATTERN (insn
), ret
;
6036 if (GET_CODE (x
) == COND_EXEC
)
6037 x
= COND_EXEC_CODE (x
);
6038 if (GET_CODE (x
) == SET
)
6041 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6042 Although they are not classical single set, the second set is there just
6043 to protect it from moving past FP-relative stack accesses. */
6044 switch (recog_memoized (insn
))
6046 case CODE_FOR_prologue_allocate_stack
:
6047 case CODE_FOR_epilogue_deallocate_stack
:
6048 ret
= XVECEXP (x
, 0, 0);
6052 ret
= single_set_2 (insn
, x
);
6059 /* Adjust the cost of a scheduling dependency. Return the new cost of
6060 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6063 ia64_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
6065 enum attr_itanium_class dep_class
;
6066 enum attr_itanium_class insn_class
;
6068 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
6071 insn_class
= ia64_safe_itanium_class (insn
);
6072 dep_class
= ia64_safe_itanium_class (dep_insn
);
6073 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
6074 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
6080 /* Like emit_insn_before, but skip cycle_display notes.
6081 ??? When cycle display notes are implemented, update this. */
6084 ia64_emit_insn_before (rtx insn
, rtx before
)
6086 emit_insn_before (insn
, before
);
6089 /* The following function marks insns who produce addresses for load
6090 and store insns. Such insns will be placed into M slots because it
6091 decrease latency time for Itanium1 (see function
6092 `ia64_produce_address_p' and the DFA descriptions). */
6095 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
6097 rtx insn
, link
, next
, next_tail
;
6099 next_tail
= NEXT_INSN (tail
);
6100 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6103 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6105 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
6107 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
6109 next
= XEXP (link
, 0);
6110 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
6111 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
6112 && ia64_st_address_bypass_p (insn
, next
))
6114 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
6115 || ia64_safe_itanium_class (next
)
6116 == ITANIUM_CLASS_FLD
)
6117 && ia64_ld_address_bypass_p (insn
, next
))
6120 insn
->call
= link
!= 0;
6124 /* We're beginning a new block. Initialize data structures as necessary. */
6127 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
6128 int sched_verbose ATTRIBUTE_UNUSED
,
6129 int max_ready ATTRIBUTE_UNUSED
)
6131 #ifdef ENABLE_CHECKING
6134 if (reload_completed
)
6135 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6136 insn
!= current_sched_info
->next_tail
;
6137 insn
= NEXT_INSN (insn
))
6138 if (SCHED_GROUP_P (insn
))
6141 last_scheduled_insn
= NULL_RTX
;
6142 init_insn_group_barriers ();
6145 /* We are about to being issuing insns for this clock cycle.
6146 Override the default sort algorithm to better slot instructions. */
6149 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
6150 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
,
6154 int n_ready
= *pn_ready
;
6155 rtx
*e_ready
= ready
+ n_ready
;
6159 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
6161 if (reorder_type
== 0)
6163 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6165 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6166 if (insnp
< e_ready
)
6169 enum attr_type t
= ia64_safe_type (insn
);
6170 if (t
== TYPE_UNKNOWN
)
6172 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6173 || asm_noperands (PATTERN (insn
)) >= 0)
6175 rtx lowest
= ready
[n_asms
];
6176 ready
[n_asms
] = insn
;
6182 rtx highest
= ready
[n_ready
- 1];
6183 ready
[n_ready
- 1] = insn
;
6190 if (n_asms
< n_ready
)
6192 /* Some normal insns to process. Skip the asms. */
6196 else if (n_ready
> 0)
6200 if (ia64_final_schedule
)
6203 int nr_need_stop
= 0;
6205 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6206 if (safe_group_barrier_needed_p (*insnp
))
6209 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
6211 if (reorder_type
== 0)
6214 /* Move down everything that needs a stop bit, preserving
6216 while (insnp
-- > ready
+ deleted
)
6217 while (insnp
>= ready
+ deleted
)
6220 if (! safe_group_barrier_needed_p (insn
))
6222 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
6233 /* We are about to being issuing insns for this clock cycle. Override
6234 the default sort algorithm to better slot instructions. */
6237 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
6240 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
6241 pn_ready
, clock_var
, 0);
6244 /* Like ia64_sched_reorder, but called after issuing each insn.
6245 Override the default sort algorithm to better slot instructions. */
6248 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
6249 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
6250 int *pn_ready
, int clock_var
)
6252 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
6253 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
6254 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
6258 /* We are about to issue INSN. Return the number of insns left on the
6259 ready queue that can be issued this cycle. */
6262 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
6263 int sched_verbose ATTRIBUTE_UNUSED
,
6264 rtx insn ATTRIBUTE_UNUSED
,
6265 int can_issue_more ATTRIBUTE_UNUSED
)
6267 last_scheduled_insn
= insn
;
6268 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
6269 if (reload_completed
)
6271 if (group_barrier_needed_p (insn
))
6273 if (GET_CODE (insn
) == CALL_INSN
)
6274 init_insn_group_barriers ();
6275 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6281 /* We are choosing insn from the ready queue. Return nonzero if INSN
6285 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
6287 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6289 return (!reload_completed
6290 || !safe_group_barrier_needed_p (insn
));
6293 /* The following variable value is pseudo-insn used by the DFA insn
6294 scheduler to change the DFA state when the simulated clock is
6297 static rtx dfa_pre_cycle_insn
;
6299 /* We are about to being issuing INSN. Return nonzero if we can not
6300 issue it on given cycle CLOCK and return zero if we should not sort
6301 the ready queue on the next clock start. */
6304 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
6305 int clock
, int *sort_p
)
6307 int setup_clocks_p
= FALSE
;
6309 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6311 if ((reload_completed
&& safe_group_barrier_needed_p (insn
))
6312 || (last_scheduled_insn
6313 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6314 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6315 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6317 init_insn_group_barriers ();
6318 if (verbose
&& dump
)
6319 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6320 last_clock
== clock
? " + cycle advance" : "");
6322 if (last_clock
== clock
)
6324 state_transition (curr_state
, dfa_stop_insn
);
6325 if (TARGET_EARLY_STOP_BITS
)
6326 *sort_p
= (last_scheduled_insn
== NULL_RTX
6327 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6332 else if (reload_completed
)
6333 setup_clocks_p
= TRUE
;
6334 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6335 state_transition (curr_state
, dfa_stop_insn
);
6336 state_transition (curr_state
, dfa_pre_cycle_insn
);
6337 state_transition (curr_state
, NULL
);
6339 else if (reload_completed
)
6340 setup_clocks_p
= TRUE
;
6341 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
)
6343 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6345 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6350 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6351 if (REG_NOTE_KIND (link
) == 0)
6353 enum attr_itanium_class dep_class
;
6354 rtx dep_insn
= XEXP (link
, 0);
6356 dep_class
= ia64_safe_itanium_class (dep_insn
);
6357 if ((dep_class
== ITANIUM_CLASS_MMMUL
6358 || dep_class
== ITANIUM_CLASS_MMSHF
)
6359 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6361 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6362 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6365 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6373 /* The following page contains abstract data `bundle states' which are
6374 used for bundling insns (inserting nops and template generation). */
6376 /* The following describes state of insn bundling. */
6380 /* Unique bundle state number to identify them in the debugging
6383 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6384 /* number nops before and after the insn */
6385 short before_nops_num
, after_nops_num
;
6386 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6388 int cost
; /* cost of the state in cycles */
6389 int accumulated_insns_num
; /* number of all previous insns including
6390 nops. L is considered as 2 insns */
6391 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6392 struct bundle_state
*next
; /* next state with the same insn_num */
6393 struct bundle_state
*originator
; /* originator (previous insn state) */
6394 /* All bundle states are in the following chain. */
6395 struct bundle_state
*allocated_states_chain
;
6396 /* The DFA State after issuing the insn and the nops. */
6400 /* The following is map insn number to the corresponding bundle state. */
6402 static struct bundle_state
**index_to_bundle_states
;
6404 /* The unique number of next bundle state. */
6406 static int bundle_states_num
;
6408 /* All allocated bundle states are in the following chain. */
6410 static struct bundle_state
*allocated_bundle_states_chain
;
6412 /* All allocated but not used bundle states are in the following
6415 static struct bundle_state
*free_bundle_state_chain
;
6418 /* The following function returns a free bundle state. */
6420 static struct bundle_state
*
6421 get_free_bundle_state (void)
6423 struct bundle_state
*result
;
6425 if (free_bundle_state_chain
!= NULL
)
6427 result
= free_bundle_state_chain
;
6428 free_bundle_state_chain
= result
->next
;
6432 result
= xmalloc (sizeof (struct bundle_state
));
6433 result
->dfa_state
= xmalloc (dfa_state_size
);
6434 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6435 allocated_bundle_states_chain
= result
;
6437 result
->unique_num
= bundle_states_num
++;
6442 /* The following function frees given bundle state. */
6445 free_bundle_state (struct bundle_state
*state
)
6447 state
->next
= free_bundle_state_chain
;
6448 free_bundle_state_chain
= state
;
6451 /* Start work with abstract data `bundle states'. */
6454 initiate_bundle_states (void)
6456 bundle_states_num
= 0;
6457 free_bundle_state_chain
= NULL
;
6458 allocated_bundle_states_chain
= NULL
;
6461 /* Finish work with abstract data `bundle states'. */
6464 finish_bundle_states (void)
6466 struct bundle_state
*curr_state
, *next_state
;
6468 for (curr_state
= allocated_bundle_states_chain
;
6470 curr_state
= next_state
)
6472 next_state
= curr_state
->allocated_states_chain
;
6473 free (curr_state
->dfa_state
);
6478 /* Hash table of the bundle states. The key is dfa_state and insn_num
6479 of the bundle states. */
6481 static htab_t bundle_state_table
;
6483 /* The function returns hash of BUNDLE_STATE. */
6486 bundle_state_hash (const void *bundle_state
)
6488 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6491 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6492 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6493 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6494 return result
+ state
->insn_num
;
6497 /* The function returns nonzero if the bundle state keys are equal. */
6500 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
6502 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6503 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6505 return (state1
->insn_num
== state2
->insn_num
6506 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6507 dfa_state_size
) == 0);
6510 /* The function inserts the BUNDLE_STATE into the hash table. The
6511 function returns nonzero if the bundle has been inserted into the
6512 table. The table contains the best bundle state with given key. */
6515 insert_bundle_state (struct bundle_state
*bundle_state
)
6519 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6520 if (*entry_ptr
== NULL
)
6522 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6523 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6524 *entry_ptr
= (void *) bundle_state
;
6527 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6528 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6529 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6530 > bundle_state
->accumulated_insns_num
6531 || (((struct bundle_state
*)
6532 *entry_ptr
)->accumulated_insns_num
6533 == bundle_state
->accumulated_insns_num
6534 && ((struct bundle_state
*)
6535 *entry_ptr
)->branch_deviation
6536 > bundle_state
->branch_deviation
))))
6539 struct bundle_state temp
;
6541 temp
= *(struct bundle_state
*) *entry_ptr
;
6542 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6543 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6544 *bundle_state
= temp
;
6549 /* Start work with the hash table. */
6552 initiate_bundle_state_table (void)
6554 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6558 /* Finish work with the hash table. */
6561 finish_bundle_state_table (void)
6563 htab_delete (bundle_state_table
);
6568 /* The following variable is a insn `nop' used to check bundle states
6569 with different number of inserted nops. */
6571 static rtx ia64_nop
;
6573 /* The following function tries to issue NOPS_NUM nops for the current
6574 state without advancing processor cycle. If it failed, the
6575 function returns FALSE and frees the current state. */
6578 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
6582 for (i
= 0; i
< nops_num
; i
++)
6583 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6585 free_bundle_state (curr_state
);
6591 /* The following function tries to issue INSN for the current
6592 state without advancing processor cycle. If it failed, the
6593 function returns FALSE and frees the current state. */
6596 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
6598 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6600 free_bundle_state (curr_state
);
6606 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6607 starting with ORIGINATOR without advancing processor cycle. If
6608 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6609 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6610 If it was successful, the function creates new bundle state and
6611 insert into the hash table and into `index_to_bundle_states'. */
6614 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
6615 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
6617 struct bundle_state
*curr_state
;
6619 curr_state
= get_free_bundle_state ();
6620 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6621 curr_state
->insn
= insn
;
6622 curr_state
->insn_num
= originator
->insn_num
+ 1;
6623 curr_state
->cost
= originator
->cost
;
6624 curr_state
->originator
= originator
;
6625 curr_state
->before_nops_num
= before_nops_num
;
6626 curr_state
->after_nops_num
= 0;
6627 curr_state
->accumulated_insns_num
6628 = originator
->accumulated_insns_num
+ before_nops_num
;
6629 curr_state
->branch_deviation
= originator
->branch_deviation
;
6630 if (insn
== NULL_RTX
)
6632 else if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6634 if (GET_MODE (insn
) == TImode
)
6636 if (!try_issue_nops (curr_state
, before_nops_num
))
6638 if (!try_issue_insn (curr_state
, insn
))
6640 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6641 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6642 && curr_state
->accumulated_insns_num
% 3 != 0)
6644 free_bundle_state (curr_state
);
6648 else if (GET_MODE (insn
) != TImode
)
6650 if (!try_issue_nops (curr_state
, before_nops_num
))
6652 if (!try_issue_insn (curr_state
, insn
))
6654 curr_state
->accumulated_insns_num
++;
6655 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6656 || asm_noperands (PATTERN (insn
)) >= 0)
6658 if (ia64_safe_type (insn
) == TYPE_L
)
6659 curr_state
->accumulated_insns_num
++;
6663 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6664 state_transition (curr_state
->dfa_state
, NULL
);
6666 if (!try_issue_nops (curr_state
, before_nops_num
))
6668 if (!try_issue_insn (curr_state
, insn
))
6670 curr_state
->accumulated_insns_num
++;
6671 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6672 || asm_noperands (PATTERN (insn
)) >= 0)
6674 /* Finish bundle containing asm insn. */
6675 curr_state
->after_nops_num
6676 = 3 - curr_state
->accumulated_insns_num
% 3;
6677 curr_state
->accumulated_insns_num
6678 += 3 - curr_state
->accumulated_insns_num
% 3;
6680 else if (ia64_safe_type (insn
) == TYPE_L
)
6681 curr_state
->accumulated_insns_num
++;
6683 if (ia64_safe_type (insn
) == TYPE_B
)
6684 curr_state
->branch_deviation
6685 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6686 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6688 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6691 struct bundle_state
*curr_state1
;
6692 struct bundle_state
*allocated_states_chain
;
6694 curr_state1
= get_free_bundle_state ();
6695 dfa_state
= curr_state1
->dfa_state
;
6696 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6697 *curr_state1
= *curr_state
;
6698 curr_state1
->dfa_state
= dfa_state
;
6699 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6700 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6702 curr_state
= curr_state1
;
6704 if (!try_issue_nops (curr_state
,
6705 3 - curr_state
->accumulated_insns_num
% 3))
6707 curr_state
->after_nops_num
6708 = 3 - curr_state
->accumulated_insns_num
% 3;
6709 curr_state
->accumulated_insns_num
6710 += 3 - curr_state
->accumulated_insns_num
% 3;
6712 if (!insert_bundle_state (curr_state
))
6713 free_bundle_state (curr_state
);
6717 /* The following function returns position in the two window bundle
6721 get_max_pos (state_t state
)
6723 if (cpu_unit_reservation_p (state
, pos_6
))
6725 else if (cpu_unit_reservation_p (state
, pos_5
))
6727 else if (cpu_unit_reservation_p (state
, pos_4
))
6729 else if (cpu_unit_reservation_p (state
, pos_3
))
6731 else if (cpu_unit_reservation_p (state
, pos_2
))
6733 else if (cpu_unit_reservation_p (state
, pos_1
))
6739 /* The function returns code of a possible template for given position
6740 and state. The function should be called only with 2 values of
6741 position equal to 3 or 6. */
6744 get_template (state_t state
, int pos
)
6749 if (cpu_unit_reservation_p (state
, _0mii_
))
6751 else if (cpu_unit_reservation_p (state
, _0mmi_
))
6753 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6755 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6757 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6759 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6761 else if (cpu_unit_reservation_p (state
, _0mib_
))
6763 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6765 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6767 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6772 if (cpu_unit_reservation_p (state
, _1mii_
))
6774 else if (cpu_unit_reservation_p (state
, _1mmi_
))
6776 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6778 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6780 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6782 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6784 else if (cpu_unit_reservation_p (state
, _1mib_
))
6786 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6788 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6790 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6799 /* The following function returns an insn important for insn bundling
6800 followed by INSN and before TAIL. */
6803 get_next_important_insn (rtx insn
, rtx tail
)
6805 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6807 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6808 && GET_CODE (PATTERN (insn
)) != USE
6809 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6814 /* The following function does insn bundling. Bundling means
6815 inserting templates and nop insns to fit insn groups into permitted
6816 templates. Instruction scheduling uses NDFA (non-deterministic
6817 finite automata) encoding informations about the templates and the
6818 inserted nops. Nondeterminism of the automata permits follows
6819 all possible insn sequences very fast.
6821 Unfortunately it is not possible to get information about inserting
6822 nop insns and used templates from the automata states. The
6823 automata only says that we can issue an insn possibly inserting
6824 some nops before it and using some template. Therefore insn
6825 bundling in this function is implemented by using DFA
6826 (deterministic finite automata). We follows all possible insn
6827 sequences by inserting 0-2 nops (that is what the NDFA describe for
6828 insn scheduling) before/after each insn being bundled. We know the
6829 start of simulated processor cycle from insn scheduling (insn
6830 starting a new cycle has TImode).
6832 Simple implementation of insn bundling would create enormous
6833 number of possible insn sequences satisfying information about new
6834 cycle ticks taken from the insn scheduling. To make the algorithm
6835 practical we use dynamic programming. Each decision (about
6836 inserting nops and implicitly about previous decisions) is described
6837 by structure bundle_state (see above). If we generate the same
6838 bundle state (key is automaton state after issuing the insns and
6839 nops for it), we reuse already generated one. As consequence we
6840 reject some decisions which can not improve the solution and
6841 reduce memory for the algorithm.
6843 When we reach the end of EBB (extended basic block), we choose the
6844 best sequence and then, moving back in EBB, insert templates for
6845 the best alternative. The templates are taken from querying
6846 automaton state for each insn in chosen bundle states.
6848 So the algorithm makes two (forward and backward) passes through
6849 EBB. There is an additional forward pass through EBB for Itanium1
6850 processor. This pass inserts more nops to make dependency between
6851 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6854 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
6856 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6857 rtx insn
, next_insn
;
6859 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6860 int pos
= 0, max_pos
, template0
, template1
;
6863 enum attr_type type
;
6866 /* Count insns in the EBB. */
6867 for (insn
= NEXT_INSN (prev_head_insn
);
6868 insn
&& insn
!= tail
;
6869 insn
= NEXT_INSN (insn
))
6875 dfa_clean_insn_cache ();
6876 initiate_bundle_state_table ();
6877 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6878 * sizeof (struct bundle_state
*));
6879 /* First (forward) pass -- generation of bundle states. */
6880 curr_state
= get_free_bundle_state ();
6881 curr_state
->insn
= NULL
;
6882 curr_state
->before_nops_num
= 0;
6883 curr_state
->after_nops_num
= 0;
6884 curr_state
->insn_num
= 0;
6885 curr_state
->cost
= 0;
6886 curr_state
->accumulated_insns_num
= 0;
6887 curr_state
->branch_deviation
= 0;
6888 curr_state
->next
= NULL
;
6889 curr_state
->originator
= NULL
;
6890 state_reset (curr_state
->dfa_state
);
6891 index_to_bundle_states
[0] = curr_state
;
6893 /* Shift cycle mark if it is put on insn which could be ignored. */
6894 for (insn
= NEXT_INSN (prev_head_insn
);
6896 insn
= NEXT_INSN (insn
))
6898 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6899 || GET_CODE (PATTERN (insn
)) == USE
6900 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6901 && GET_MODE (insn
) == TImode
)
6903 PUT_MODE (insn
, VOIDmode
);
6904 for (next_insn
= NEXT_INSN (insn
);
6906 next_insn
= NEXT_INSN (next_insn
))
6907 if (INSN_P (next_insn
)
6908 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6909 && GET_CODE (PATTERN (next_insn
)) != USE
6910 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6912 PUT_MODE (next_insn
, TImode
);
6916 /* Froward pass: generation of bundle states. */
6917 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6922 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6923 || GET_CODE (PATTERN (insn
)) == USE
6924 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6926 type
= ia64_safe_type (insn
);
6927 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6929 index_to_bundle_states
[insn_num
] = NULL
;
6930 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6932 curr_state
= next_state
)
6934 pos
= curr_state
->accumulated_insns_num
% 3;
6935 next_state
= curr_state
->next
;
6936 /* We must fill up the current bundle in order to start a
6937 subsequent asm insn in a new bundle. Asm insn is always
6938 placed in a separate bundle. */
6940 = (next_insn
!= NULL_RTX
6941 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6942 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6943 /* We may fill up the current bundle if it is the cycle end
6944 without a group barrier. */
6946 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6947 || (GET_MODE (next_insn
) == TImode
6948 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6949 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6951 /* We need to insert 2 nops for cases like M_MII. To
6952 guarantee issuing all insns on the same cycle for
6953 Itanium 1, we need to issue 2 nops after the first M
6954 insn (MnnMII where n is a nop insn). */
6955 || (type
== TYPE_M
&& ia64_tune
== PROCESSOR_ITANIUM
6956 && !bundle_end_p
&& pos
== 1))
6957 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6959 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6961 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6964 if (index_to_bundle_states
[insn_num
] == NULL
)
6966 for (curr_state
= index_to_bundle_states
[insn_num
];
6968 curr_state
= curr_state
->next
)
6969 if (verbose
>= 2 && dump
)
6971 /* This structure is taken from generated code of the
6972 pipeline hazard recognizer (see file insn-attrtab.c).
6973 Please don't forget to change the structure if a new
6974 automaton is added to .md file. */
6977 unsigned short one_automaton_state
;
6978 unsigned short oneb_automaton_state
;
6979 unsigned short two_automaton_state
;
6980 unsigned short twob_automaton_state
;
6985 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6986 curr_state
->unique_num
,
6987 (curr_state
->originator
== NULL
6988 ? -1 : curr_state
->originator
->unique_num
),
6990 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6991 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6992 (ia64_tune
== PROCESSOR_ITANIUM
6993 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6994 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6998 if (index_to_bundle_states
[insn_num
] == NULL
)
6999 /* We should find a solution because the 2nd insn scheduling has
7002 /* Find a state corresponding to the best insn sequence. */
7004 for (curr_state
= index_to_bundle_states
[insn_num
];
7006 curr_state
= curr_state
->next
)
7007 /* We are just looking at the states with fully filled up last
7008 bundle. The first we prefer insn sequences with minimal cost
7009 then with minimal inserted nops and finally with branch insns
7010 placed in the 3rd slots. */
7011 if (curr_state
->accumulated_insns_num
% 3 == 0
7012 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
7013 || (best_state
->cost
== curr_state
->cost
7014 && (curr_state
->accumulated_insns_num
7015 < best_state
->accumulated_insns_num
7016 || (curr_state
->accumulated_insns_num
7017 == best_state
->accumulated_insns_num
7018 && curr_state
->branch_deviation
7019 < best_state
->branch_deviation
)))))
7020 best_state
= curr_state
;
7021 /* Second (backward) pass: adding nops and templates. */
7022 insn_num
= best_state
->before_nops_num
;
7023 template0
= template1
= -1;
7024 for (curr_state
= best_state
;
7025 curr_state
->originator
!= NULL
;
7026 curr_state
= curr_state
->originator
)
7028 insn
= curr_state
->insn
;
7029 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7030 || asm_noperands (PATTERN (insn
)) >= 0);
7032 if (verbose
>= 2 && dump
)
7036 unsigned short one_automaton_state
;
7037 unsigned short oneb_automaton_state
;
7038 unsigned short two_automaton_state
;
7039 unsigned short twob_automaton_state
;
7044 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7045 curr_state
->unique_num
,
7046 (curr_state
->originator
== NULL
7047 ? -1 : curr_state
->originator
->unique_num
),
7049 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
7050 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
7051 (ia64_tune
== PROCESSOR_ITANIUM
7052 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
7053 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
7056 /* Find the position in the current bundle window. The window can
7057 contain at most two bundles. Two bundle window means that
7058 the processor will make two bundle rotation. */
7059 max_pos
= get_max_pos (curr_state
->dfa_state
);
7061 /* The following (negative template number) means that the
7062 processor did one bundle rotation. */
7063 || (max_pos
== 3 && template0
< 0))
7065 /* We are at the end of the window -- find template(s) for
7069 template0
= get_template (curr_state
->dfa_state
, 3);
7072 template1
= get_template (curr_state
->dfa_state
, 3);
7073 template0
= get_template (curr_state
->dfa_state
, 6);
7076 if (max_pos
> 3 && template1
< 0)
7077 /* It may happen when we have the stop inside a bundle. */
7081 template1
= get_template (curr_state
->dfa_state
, 3);
7085 /* Emit nops after the current insn. */
7086 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
7089 emit_insn_after (nop
, insn
);
7095 /* We are at the start of a bundle: emit the template
7096 (it should be defined). */
7099 b
= gen_bundle_selector (GEN_INT (template0
));
7100 ia64_emit_insn_before (b
, nop
);
7101 /* If we have two bundle window, we make one bundle
7102 rotation. Otherwise template0 will be undefined
7103 (negative value). */
7104 template0
= template1
;
7108 /* Move the position backward in the window. Group barrier has
7109 no slot. Asm insn takes all bundle. */
7110 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7111 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7112 && asm_noperands (PATTERN (insn
)) < 0)
7114 /* Long insn takes 2 slots. */
7115 if (ia64_safe_type (insn
) == TYPE_L
)
7120 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7121 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7122 && asm_noperands (PATTERN (insn
)) < 0)
7124 /* The current insn is at the bundle start: emit the
7128 b
= gen_bundle_selector (GEN_INT (template0
));
7129 ia64_emit_insn_before (b
, insn
);
7130 b
= PREV_INSN (insn
);
7132 /* See comment above in analogous place for emitting nops
7134 template0
= template1
;
7137 /* Emit nops after the current insn. */
7138 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
7141 ia64_emit_insn_before (nop
, insn
);
7142 nop
= PREV_INSN (insn
);
7149 /* See comment above in analogous place for emitting nops
7153 b
= gen_bundle_selector (GEN_INT (template0
));
7154 ia64_emit_insn_before (b
, insn
);
7155 b
= PREV_INSN (insn
);
7157 template0
= template1
;
7162 if (ia64_tune
== PROCESSOR_ITANIUM
)
7163 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7164 Itanium1 has a strange design, if the distance between an insn
7165 and dependent MM-insn is less 4 then we have a 6 additional
7166 cycles stall. So we make the distance equal to 4 cycles if it
7168 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
7173 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
7174 || GET_CODE (PATTERN (insn
)) == USE
7175 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
7177 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
7178 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
7179 /* We found a MM-insn which needs additional cycles. */
7185 /* Now we are searching for a template of the bundle in
7186 which the MM-insn is placed and the position of the
7187 insn in the bundle (0, 1, 2). Also we are searching
7188 for that there is a stop before the insn. */
7189 last
= prev_active_insn (insn
);
7190 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
7192 last
= prev_active_insn (last
);
7194 for (;; last
= prev_active_insn (last
))
7195 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
7197 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
7199 /* The insn is in MLX bundle. Change the template
7200 onto MFI because we will add nops before the
7201 insn. It simplifies subsequent code a lot. */
7203 = gen_bundle_selector (const2_rtx
); /* -> MFI */
7206 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7208 /* Some check of correctness: the stop is not at the
7209 bundle start, there are no more 3 insns in the bundle,
7210 and the MM-insn is not at the start of bundle with
7212 if ((pred_stop_p
&& n
== 0) || n
> 2
7213 || (template0
== 9 && n
!= 0))
7215 /* Put nops after the insn in the bundle. */
7216 for (j
= 3 - n
; j
> 0; j
--)
7217 ia64_emit_insn_before (gen_nop (), insn
);
7218 /* It takes into account that we will add more N nops
7219 before the insn lately -- please see code below. */
7220 add_cycles
[INSN_UID (insn
)]--;
7221 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
7222 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7225 add_cycles
[INSN_UID (insn
)]--;
7226 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
7228 /* Insert "MII;" template. */
7229 ia64_emit_insn_before (gen_bundle_selector (const0_rtx
),
7231 ia64_emit_insn_before (gen_nop (), insn
);
7232 ia64_emit_insn_before (gen_nop (), insn
);
7235 /* To decrease code size, we use "MI;I;"
7237 ia64_emit_insn_before
7238 (gen_insn_group_barrier (GEN_INT (3)), insn
);
7241 ia64_emit_insn_before (gen_nop (), insn
);
7242 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7245 /* Put the MM-insn in the same slot of a bundle with the
7246 same template as the original one. */
7247 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
7249 /* To put the insn in the same slot, add necessary number
7251 for (j
= n
; j
> 0; j
--)
7252 ia64_emit_insn_before (gen_nop (), insn
);
7253 /* Put the stop if the original bundle had it. */
7255 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7259 free (index_to_bundle_states
);
7260 finish_bundle_state_table ();
7262 dfa_clean_insn_cache ();
7265 /* The following function is called at the end of scheduling BB or
7266 EBB. After reload, it inserts stop bits and does insn bundling. */
7269 ia64_sched_finish (FILE *dump
, int sched_verbose
)
7272 fprintf (dump
, "// Finishing schedule.\n");
7273 if (!reload_completed
)
7275 if (reload_completed
)
7277 final_emit_insn_group_barriers (dump
);
7278 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
7279 current_sched_info
->next_tail
);
7280 if (sched_verbose
&& dump
)
7281 fprintf (dump
, "// finishing %d-%d\n",
7282 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
7283 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
7289 /* The following function inserts stop bits in scheduled BB or EBB. */
7292 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7295 int need_barrier_p
= 0;
7296 rtx prev_insn
= NULL_RTX
;
7298 init_insn_group_barriers ();
7300 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7301 insn
!= current_sched_info
->next_tail
;
7302 insn
= NEXT_INSN (insn
))
7304 if (GET_CODE (insn
) == BARRIER
)
7306 rtx last
= prev_active_insn (insn
);
7310 if (GET_CODE (last
) == JUMP_INSN
7311 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
7312 last
= prev_active_insn (last
);
7313 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7314 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7316 init_insn_group_barriers ();
7318 prev_insn
= NULL_RTX
;
7320 else if (INSN_P (insn
))
7322 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7324 init_insn_group_barriers ();
7326 prev_insn
= NULL_RTX
;
7328 else if (need_barrier_p
|| group_barrier_needed_p (insn
))
7330 if (TARGET_EARLY_STOP_BITS
)
7335 last
!= current_sched_info
->prev_head
;
7336 last
= PREV_INSN (last
))
7337 if (INSN_P (last
) && GET_MODE (last
) == TImode
7338 && stops_p
[INSN_UID (last
)])
7340 if (last
== current_sched_info
->prev_head
)
7342 last
= prev_active_insn (last
);
7344 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7345 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7347 init_insn_group_barriers ();
7348 for (last
= NEXT_INSN (last
);
7350 last
= NEXT_INSN (last
))
7352 group_barrier_needed_p (last
);
7356 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7358 init_insn_group_barriers ();
7360 group_barrier_needed_p (insn
);
7361 prev_insn
= NULL_RTX
;
7363 else if (recog_memoized (insn
) >= 0)
7365 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7366 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7367 || asm_noperands (PATTERN (insn
)) >= 0);
7374 /* If the following function returns TRUE, we will use the the DFA
7378 ia64_use_dfa_pipeline_interface (void)
7383 /* If the following function returns TRUE, we will use the the DFA
7387 ia64_first_cycle_multipass_dfa_lookahead (void)
7389 return (reload_completed
? 6 : 4);
7392 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7395 ia64_init_dfa_pre_cycle_insn (void)
7397 if (temp_dfa_state
== NULL
)
7399 dfa_state_size
= state_size ();
7400 temp_dfa_state
= xmalloc (dfa_state_size
);
7401 prev_cycle_state
= xmalloc (dfa_state_size
);
7403 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7404 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7405 recog_memoized (dfa_pre_cycle_insn
);
7406 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7407 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7408 recog_memoized (dfa_stop_insn
);
7411 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7412 used by the DFA insn scheduler. */
7415 ia64_dfa_pre_cycle_insn (void)
7417 return dfa_pre_cycle_insn
;
7420 /* The following function returns TRUE if PRODUCER (of type ilog or
7421 ld) produces address for CONSUMER (of type st or stf). */
7424 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
7428 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7430 dest
= ia64_single_set (producer
);
7431 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7432 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7434 if (GET_CODE (reg
) == SUBREG
)
7435 reg
= SUBREG_REG (reg
);
7436 dest
= ia64_single_set (consumer
);
7437 if (dest
== NULL_RTX
|| (mem
= SET_DEST (dest
)) == NULL_RTX
7438 || GET_CODE (mem
) != MEM
)
7440 return reg_mentioned_p (reg
, mem
);
7443 /* The following function returns TRUE if PRODUCER (of type ilog or
7444 ld) produces address for CONSUMER (of type ld or fld). */
7447 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
7449 rtx dest
, src
, reg
, mem
;
7451 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7453 dest
= ia64_single_set (producer
);
7454 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7455 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7457 if (GET_CODE (reg
) == SUBREG
)
7458 reg
= SUBREG_REG (reg
);
7459 src
= ia64_single_set (consumer
);
7460 if (src
== NULL_RTX
|| (mem
= SET_SRC (src
)) == NULL_RTX
)
7462 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7463 mem
= XVECEXP (mem
, 0, 0);
7464 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7465 mem
= XEXP (mem
, 0);
7467 /* Note that LO_SUM is used for GOT loads. */
7468 if (GET_CODE (mem
) != LO_SUM
&& GET_CODE (mem
) != MEM
)
7471 return reg_mentioned_p (reg
, mem
);
7474 /* The following function returns TRUE if INSN produces address for a
7475 load/store insn. We will place such insns into M slot because it
7476 decreases its latency time. */
7479 ia64_produce_address_p (rtx insn
)
7485 /* Emit pseudo-ops for the assembler to describe predicate relations.
7486 At present this assumes that we only consider predicate pairs to
7487 be mutex, and that the assembler can deduce proper values from
7488 straight-line code. */
7491 emit_predicate_relation_info (void)
7495 FOR_EACH_BB_REVERSE (bb
)
7498 rtx head
= BB_HEAD (bb
);
7500 /* We only need such notes at code labels. */
7501 if (GET_CODE (head
) != CODE_LABEL
)
7503 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7504 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7505 head
= NEXT_INSN (head
);
7507 for (r
= PR_REG (0); r
< PR_REG (64); r
+= 2)
7508 if (REGNO_REG_SET_P (bb
->global_live_at_start
, r
))
7510 rtx p
= gen_rtx_REG (BImode
, r
);
7511 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7512 if (head
== BB_END (bb
))
7518 /* Look for conditional calls that do not return, and protect predicate
7519 relations around them. Otherwise the assembler will assume the call
7520 returns, and complain about uses of call-clobbered predicates after
7522 FOR_EACH_BB_REVERSE (bb
)
7524 rtx insn
= BB_HEAD (bb
);
7528 if (GET_CODE (insn
) == CALL_INSN
7529 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7530 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7532 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7533 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7534 if (BB_HEAD (bb
) == insn
)
7536 if (BB_END (bb
) == insn
)
7540 if (insn
== BB_END (bb
))
7542 insn
= NEXT_INSN (insn
);
7547 /* Perform machine dependent operations on the rtl chain INSNS. */
7552 /* We are freeing block_for_insn in the toplev to keep compatibility
7553 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7554 compute_bb_for_insn ();
7556 /* If optimizing, we'll have split before scheduling. */
7558 split_all_insns (0);
7560 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7561 non-optimizing bootstrap. */
7562 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7564 if (ia64_flag_schedule_insns2
)
7566 timevar_push (TV_SCHED2
);
7567 ia64_final_schedule
= 1;
7569 initiate_bundle_states ();
7570 ia64_nop
= make_insn_raw (gen_nop ());
7571 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7572 recog_memoized (ia64_nop
);
7573 clocks_length
= get_max_uid () + 1;
7574 stops_p
= xcalloc (1, clocks_length
);
7575 if (ia64_tune
== PROCESSOR_ITANIUM
)
7577 clocks
= xcalloc (clocks_length
, sizeof (int));
7578 add_cycles
= xcalloc (clocks_length
, sizeof (int));
7580 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7582 pos_1
= get_cpu_unit_code ("2_1");
7583 pos_2
= get_cpu_unit_code ("2_2");
7584 pos_3
= get_cpu_unit_code ("2_3");
7585 pos_4
= get_cpu_unit_code ("2_4");
7586 pos_5
= get_cpu_unit_code ("2_5");
7587 pos_6
= get_cpu_unit_code ("2_6");
7588 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7589 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7590 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7591 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7592 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7593 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7594 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7595 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7596 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7597 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7598 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7599 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7600 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7601 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7602 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7603 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7604 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7605 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7606 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7607 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7611 pos_1
= get_cpu_unit_code ("1_1");
7612 pos_2
= get_cpu_unit_code ("1_2");
7613 pos_3
= get_cpu_unit_code ("1_3");
7614 pos_4
= get_cpu_unit_code ("1_4");
7615 pos_5
= get_cpu_unit_code ("1_5");
7616 pos_6
= get_cpu_unit_code ("1_6");
7617 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7618 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7619 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7620 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7621 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7622 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7623 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7624 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7625 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7626 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7627 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7628 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7629 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7630 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7631 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7632 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7633 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7634 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7635 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7636 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7638 schedule_ebbs (dump_file
);
7639 finish_bundle_states ();
7640 if (ia64_tune
== PROCESSOR_ITANIUM
)
7646 emit_insn_group_barriers (dump_file
);
7648 ia64_final_schedule
= 0;
7649 timevar_pop (TV_SCHED2
);
7652 emit_all_insn_group_barriers (dump_file
);
7654 /* A call must not be the last instruction in a function, so that the
7655 return address is still within the function, so that unwinding works
7656 properly. Note that IA-64 differs from dwarf2 on this point. */
7657 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7662 insn
= get_last_insn ();
7663 if (! INSN_P (insn
))
7664 insn
= prev_active_insn (insn
);
7665 if (GET_CODE (insn
) == INSN
7666 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7667 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7670 insn
= prev_active_insn (insn
);
7672 if (GET_CODE (insn
) == CALL_INSN
)
7675 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7676 emit_insn (gen_break_f ());
7677 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7682 emit_predicate_relation_info ();
7684 if (ia64_flag_var_tracking
)
7686 timevar_push (TV_VAR_TRACKING
);
7687 variable_tracking_main ();
7688 timevar_pop (TV_VAR_TRACKING
);
7692 /* Return true if REGNO is used by the epilogue. */
7695 ia64_epilogue_uses (int regno
)
7700 /* With a call to a function in another module, we will write a new
7701 value to "gp". After returning from such a call, we need to make
7702 sure the function restores the original gp-value, even if the
7703 function itself does not use the gp anymore. */
7704 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
7706 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7707 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7708 /* For functions defined with the syscall_linkage attribute, all
7709 input registers are marked as live at all function exits. This
7710 prevents the register allocator from using the input registers,
7711 which in turn makes it possible to restart a system call after
7712 an interrupt without having to save/restore the input registers.
7713 This also prevents kernel data from leaking to application code. */
7714 return lookup_attribute ("syscall_linkage",
7715 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7718 /* Conditional return patterns can't represent the use of `b0' as
7719 the return address, so we force the value live this way. */
7723 /* Likewise for ar.pfs, which is used by br.ret. */
7731 /* Return true if REGNO is used by the frame unwinder. */
7734 ia64_eh_uses (int regno
)
7736 if (! reload_completed
)
7739 if (current_frame_info
.reg_save_b0
7740 && regno
== current_frame_info
.reg_save_b0
)
7742 if (current_frame_info
.reg_save_pr
7743 && regno
== current_frame_info
.reg_save_pr
)
7745 if (current_frame_info
.reg_save_ar_pfs
7746 && regno
== current_frame_info
.reg_save_ar_pfs
)
7748 if (current_frame_info
.reg_save_ar_unat
7749 && regno
== current_frame_info
.reg_save_ar_unat
)
7751 if (current_frame_info
.reg_save_ar_lc
7752 && regno
== current_frame_info
.reg_save_ar_lc
)
7758 /* Return true if this goes in small data/bss. */
7760 /* ??? We could also support own long data here. Generating movl/add/ld8
7761 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7762 code faster because there is one less load. This also includes incomplete
7763 types which can't go in sdata/sbss. */
7766 ia64_in_small_data_p (tree exp
)
7768 if (TARGET_NO_SDATA
)
7771 /* We want to merge strings, so we never consider them small data. */
7772 if (TREE_CODE (exp
) == STRING_CST
)
7775 /* Functions are never small data. */
7776 if (TREE_CODE (exp
) == FUNCTION_DECL
)
7779 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7781 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7782 if (strcmp (section
, ".sdata") == 0
7783 || strcmp (section
, ".sbss") == 0)
7788 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7790 /* If this is an incomplete type with size 0, then we can't put it
7791 in sdata because it might be too big when completed. */
7792 if (size
> 0 && size
<= ia64_section_threshold
)
7799 /* Output assembly directives for prologue regions. */
7801 /* The current basic block number. */
7803 static bool last_block
;
7805 /* True if we need a copy_state command at the start of the next block. */
7807 static bool need_copy_state
;
7809 /* The function emits unwind directives for the start of an epilogue. */
7812 process_epilogue (void)
7814 /* If this isn't the last block of the function, then we need to label the
7815 current state, and copy it back in at the start of the next block. */
7819 fprintf (asm_out_file
, "\t.label_state 1\n");
7820 need_copy_state
= true;
7823 fprintf (asm_out_file
, "\t.restore sp\n");
7826 /* This function processes a SET pattern looking for specific patterns
7827 which result in emitting an assembly directive required for unwinding. */
7830 process_set (FILE *asm_out_file
, rtx pat
)
7832 rtx src
= SET_SRC (pat
);
7833 rtx dest
= SET_DEST (pat
);
7834 int src_regno
, dest_regno
;
7836 /* Look for the ALLOC insn. */
7837 if (GET_CODE (src
) == UNSPEC_VOLATILE
7838 && XINT (src
, 1) == UNSPECV_ALLOC
7839 && GET_CODE (dest
) == REG
)
7841 dest_regno
= REGNO (dest
);
7843 /* If this isn't the final destination for ar.pfs, the alloc
7844 shouldn't have been marked frame related. */
7845 if (dest_regno
!= current_frame_info
.reg_save_ar_pfs
)
7848 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7849 ia64_dbx_register_number (dest_regno
));
7853 /* Look for SP = .... */
7854 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7856 if (GET_CODE (src
) == PLUS
)
7858 rtx op0
= XEXP (src
, 0);
7859 rtx op1
= XEXP (src
, 1);
7860 if (op0
== dest
&& GET_CODE (op1
) == CONST_INT
)
7862 if (INTVAL (op1
) < 0)
7863 fprintf (asm_out_file
, "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
7866 process_epilogue ();
7871 else if (GET_CODE (src
) == REG
7872 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
7873 process_epilogue ();
7880 /* Register move we need to look at. */
7881 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7883 src_regno
= REGNO (src
);
7884 dest_regno
= REGNO (dest
);
7889 /* Saving return address pointer. */
7890 if (dest_regno
!= current_frame_info
.reg_save_b0
)
7892 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7893 ia64_dbx_register_number (dest_regno
));
7897 if (dest_regno
!= current_frame_info
.reg_save_pr
)
7899 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7900 ia64_dbx_register_number (dest_regno
));
7903 case AR_UNAT_REGNUM
:
7904 if (dest_regno
!= current_frame_info
.reg_save_ar_unat
)
7906 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7907 ia64_dbx_register_number (dest_regno
));
7911 if (dest_regno
!= current_frame_info
.reg_save_ar_lc
)
7913 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7914 ia64_dbx_register_number (dest_regno
));
7917 case STACK_POINTER_REGNUM
:
7918 if (dest_regno
!= HARD_FRAME_POINTER_REGNUM
7919 || ! frame_pointer_needed
)
7921 fprintf (asm_out_file
, "\t.vframe r%d\n",
7922 ia64_dbx_register_number (dest_regno
));
7926 /* Everything else should indicate being stored to memory. */
7931 /* Memory store we need to look at. */
7932 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7938 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7940 base
= XEXP (dest
, 0);
7943 else if (GET_CODE (XEXP (dest
, 0)) == PLUS
7944 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
)
7946 base
= XEXP (XEXP (dest
, 0), 0);
7947 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7952 if (base
== hard_frame_pointer_rtx
)
7954 saveop
= ".savepsp";
7957 else if (base
== stack_pointer_rtx
)
7962 src_regno
= REGNO (src
);
7966 if (current_frame_info
.reg_save_b0
!= 0)
7968 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7972 if (current_frame_info
.reg_save_pr
!= 0)
7974 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7978 if (current_frame_info
.reg_save_ar_lc
!= 0)
7980 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7984 if (current_frame_info
.reg_save_ar_pfs
!= 0)
7986 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7989 case AR_UNAT_REGNUM
:
7990 if (current_frame_info
.reg_save_ar_unat
!= 0)
7992 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
7999 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
8000 1 << (src_regno
- GR_REG (4)));
8008 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
8009 1 << (src_regno
- BR_REG (1)));
8016 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
8017 1 << (src_regno
- FR_REG (2)));
8020 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
8021 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
8022 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
8023 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
8024 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
8025 1 << (src_regno
- FR_REG (12)));
8037 /* This function looks at a single insn and emits any directives
8038 required to unwind this insn. */
8040 process_for_unwind_directive (FILE *asm_out_file
, rtx insn
)
8042 if (flag_unwind_tables
8043 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
8047 if (GET_CODE (insn
) == NOTE
8048 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
8050 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
8052 /* Restore unwind state from immediately before the epilogue. */
8053 if (need_copy_state
)
8055 fprintf (asm_out_file
, "\t.body\n");
8056 fprintf (asm_out_file
, "\t.copy_state 1\n");
8057 need_copy_state
= false;
8061 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
8064 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
8066 pat
= XEXP (pat
, 0);
8068 pat
= PATTERN (insn
);
8070 switch (GET_CODE (pat
))
8073 process_set (asm_out_file
, pat
);
8079 int limit
= XVECLEN (pat
, 0);
8080 for (par_index
= 0; par_index
< limit
; par_index
++)
8082 rtx x
= XVECEXP (pat
, 0, par_index
);
8083 if (GET_CODE (x
) == SET
)
8084 process_set (asm_out_file
, x
);
8097 ia64_init_builtins (void)
8099 tree psi_type_node
= build_pointer_type (integer_type_node
);
8100 tree pdi_type_node
= build_pointer_type (long_integer_type_node
);
8102 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
8103 tree si_ftype_psi_si_si
8104 = build_function_type_list (integer_type_node
,
8105 psi_type_node
, integer_type_node
,
8106 integer_type_node
, NULL_TREE
);
8108 /* __sync_val_compare_and_swap_di */
8109 tree di_ftype_pdi_di_di
8110 = build_function_type_list (long_integer_type_node
,
8111 pdi_type_node
, long_integer_type_node
,
8112 long_integer_type_node
, NULL_TREE
);
8113 /* __sync_bool_compare_and_swap_di */
8114 tree si_ftype_pdi_di_di
8115 = build_function_type_list (integer_type_node
,
8116 pdi_type_node
, long_integer_type_node
,
8117 long_integer_type_node
, NULL_TREE
);
8118 /* __sync_synchronize */
8119 tree void_ftype_void
8120 = build_function_type (void_type_node
, void_list_node
);
8122 /* __sync_lock_test_and_set_si */
8123 tree si_ftype_psi_si
8124 = build_function_type_list (integer_type_node
,
8125 psi_type_node
, integer_type_node
, NULL_TREE
);
8127 /* __sync_lock_test_and_set_di */
8128 tree di_ftype_pdi_di
8129 = build_function_type_list (long_integer_type_node
,
8130 pdi_type_node
, long_integer_type_node
,
8133 /* __sync_lock_release_si */
8135 = build_function_type_list (void_type_node
, psi_type_node
, NULL_TREE
);
8137 /* __sync_lock_release_di */
8139 = build_function_type_list (void_type_node
, pdi_type_node
, NULL_TREE
);
8144 /* The __fpreg type. */
8145 fpreg_type
= make_node (REAL_TYPE
);
8146 /* ??? The back end should know to load/save __fpreg variables using
8147 the ldf.fill and stf.spill instructions. */
8148 TYPE_PRECISION (fpreg_type
) = 96;
8149 layout_type (fpreg_type
);
8150 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
8152 /* The __float80 type. */
8153 float80_type
= make_node (REAL_TYPE
);
8154 TYPE_PRECISION (float80_type
) = 96;
8155 layout_type (float80_type
);
8156 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
8158 /* The __float128 type. */
8161 tree float128_type
= make_node (REAL_TYPE
);
8162 TYPE_PRECISION (float128_type
) = 128;
8163 layout_type (float128_type
);
8164 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
8167 /* Under HPUX, this is a synonym for "long double". */
8168 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
8171 #define def_builtin(name, type, code) \
8172 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
8174 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si
,
8175 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
);
8176 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di
,
8177 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
);
8178 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si
,
8179 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
);
8180 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di
,
8181 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
);
8183 def_builtin ("__sync_synchronize", void_ftype_void
,
8184 IA64_BUILTIN_SYNCHRONIZE
);
8186 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si
,
8187 IA64_BUILTIN_LOCK_TEST_AND_SET_SI
);
8188 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di
,
8189 IA64_BUILTIN_LOCK_TEST_AND_SET_DI
);
8190 def_builtin ("__sync_lock_release_si", void_ftype_psi
,
8191 IA64_BUILTIN_LOCK_RELEASE_SI
);
8192 def_builtin ("__sync_lock_release_di", void_ftype_pdi
,
8193 IA64_BUILTIN_LOCK_RELEASE_DI
);
8195 def_builtin ("__builtin_ia64_bsp",
8196 build_function_type (ptr_type_node
, void_list_node
),
8199 def_builtin ("__builtin_ia64_flushrs",
8200 build_function_type (void_type_node
, void_list_node
),
8201 IA64_BUILTIN_FLUSHRS
);
8203 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si
,
8204 IA64_BUILTIN_FETCH_AND_ADD_SI
);
8205 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si
,
8206 IA64_BUILTIN_FETCH_AND_SUB_SI
);
8207 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si
,
8208 IA64_BUILTIN_FETCH_AND_OR_SI
);
8209 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si
,
8210 IA64_BUILTIN_FETCH_AND_AND_SI
);
8211 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si
,
8212 IA64_BUILTIN_FETCH_AND_XOR_SI
);
8213 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si
,
8214 IA64_BUILTIN_FETCH_AND_NAND_SI
);
8216 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si
,
8217 IA64_BUILTIN_ADD_AND_FETCH_SI
);
8218 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si
,
8219 IA64_BUILTIN_SUB_AND_FETCH_SI
);
8220 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si
,
8221 IA64_BUILTIN_OR_AND_FETCH_SI
);
8222 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si
,
8223 IA64_BUILTIN_AND_AND_FETCH_SI
);
8224 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si
,
8225 IA64_BUILTIN_XOR_AND_FETCH_SI
);
8226 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si
,
8227 IA64_BUILTIN_NAND_AND_FETCH_SI
);
8229 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di
,
8230 IA64_BUILTIN_FETCH_AND_ADD_DI
);
8231 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di
,
8232 IA64_BUILTIN_FETCH_AND_SUB_DI
);
8233 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di
,
8234 IA64_BUILTIN_FETCH_AND_OR_DI
);
8235 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di
,
8236 IA64_BUILTIN_FETCH_AND_AND_DI
);
8237 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di
,
8238 IA64_BUILTIN_FETCH_AND_XOR_DI
);
8239 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di
,
8240 IA64_BUILTIN_FETCH_AND_NAND_DI
);
8242 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di
,
8243 IA64_BUILTIN_ADD_AND_FETCH_DI
);
8244 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di
,
8245 IA64_BUILTIN_SUB_AND_FETCH_DI
);
8246 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di
,
8247 IA64_BUILTIN_OR_AND_FETCH_DI
);
8248 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di
,
8249 IA64_BUILTIN_AND_AND_FETCH_DI
);
8250 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di
,
8251 IA64_BUILTIN_XOR_AND_FETCH_DI
);
8252 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di
,
8253 IA64_BUILTIN_NAND_AND_FETCH_DI
);
8258 /* Expand fetch_and_op intrinsics. The basic code sequence is:
8266 cmpxchgsz.acq tmp = [ptr], tmp
8267 } while (tmp != ret)
8271 ia64_expand_fetch_and_op (optab binoptab
, enum machine_mode mode
,
8272 tree arglist
, rtx target
)
8274 rtx ret
, label
, tmp
, ccv
, insn
, mem
, value
;
8277 arg0
= TREE_VALUE (arglist
);
8278 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8279 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8280 #ifdef POINTERS_EXTEND_UNSIGNED
8281 if (GET_MODE(mem
) != Pmode
)
8282 mem
= convert_memory_address (Pmode
, mem
);
8284 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8286 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8287 MEM_VOLATILE_P (mem
) = 1;
8289 if (target
&& register_operand (target
, mode
))
8292 ret
= gen_reg_rtx (mode
);
8294 emit_insn (gen_mf ());
8296 /* Special case for fetchadd instructions. */
8297 if (binoptab
== add_optab
&& fetchadd_operand (value
, VOIDmode
))
8300 insn
= gen_fetchadd_acq_si (ret
, mem
, value
);
8302 insn
= gen_fetchadd_acq_di (ret
, mem
, value
);
8307 tmp
= gen_reg_rtx (mode
);
8308 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8309 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8310 emit_move_insn (tmp
, mem
);
8312 label
= gen_label_rtx ();
8314 emit_move_insn (ret
, tmp
);
8315 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8317 /* Perform the specific operation. Special case NAND by noticing
8318 one_cmpl_optab instead. */
8319 if (binoptab
== one_cmpl_optab
)
8321 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8322 binoptab
= and_optab
;
8324 tmp
= expand_binop (mode
, binoptab
, tmp
, value
, tmp
, 1, OPTAB_WIDEN
);
8327 insn
= gen_cmpxchg_acq_si (tmp
, mem
, tmp
, ccv
);
8329 insn
= gen_cmpxchg_acq_di (tmp
, mem
, tmp
, ccv
);
8332 emit_cmp_and_jump_insns (tmp
, ret
, NE
, 0, mode
, 1, label
);
8337 /* Expand op_and_fetch intrinsics. The basic code sequence is:
8344 ret = tmp <op> value;
8345 cmpxchgsz.acq tmp = [ptr], ret
8346 } while (tmp != old)
8350 ia64_expand_op_and_fetch (optab binoptab
, enum machine_mode mode
,
8351 tree arglist
, rtx target
)
8353 rtx old
, label
, tmp
, ret
, ccv
, insn
, mem
, value
;
8356 arg0
= TREE_VALUE (arglist
);
8357 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8358 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8359 #ifdef POINTERS_EXTEND_UNSIGNED
8360 if (GET_MODE(mem
) != Pmode
)
8361 mem
= convert_memory_address (Pmode
, mem
);
8364 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8366 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8367 MEM_VOLATILE_P (mem
) = 1;
8369 if (target
&& ! register_operand (target
, mode
))
8372 emit_insn (gen_mf ());
8373 tmp
= gen_reg_rtx (mode
);
8374 old
= gen_reg_rtx (mode
);
8375 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8376 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8378 emit_move_insn (tmp
, mem
);
8380 label
= gen_label_rtx ();
8382 emit_move_insn (old
, tmp
);
8383 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8385 /* Perform the specific operation. Special case NAND by noticing
8386 one_cmpl_optab instead. */
8387 if (binoptab
== one_cmpl_optab
)
8389 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8390 binoptab
= and_optab
;
8392 ret
= expand_binop (mode
, binoptab
, tmp
, value
, target
, 1, OPTAB_WIDEN
);
8395 insn
= gen_cmpxchg_acq_si (tmp
, mem
, ret
, ccv
);
8397 insn
= gen_cmpxchg_acq_di (tmp
, mem
, ret
, ccv
);
8400 emit_cmp_and_jump_insns (tmp
, old
, NE
, 0, mode
, 1, label
);
8405 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8409 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8412 For bool_ it's the same except return ret == oldval.
8416 ia64_expand_compare_and_swap (enum machine_mode rmode
, enum machine_mode mode
,
8417 int boolp
, tree arglist
, rtx target
)
8419 tree arg0
, arg1
, arg2
;
8420 rtx mem
, old
, new, ccv
, tmp
, insn
;
8422 arg0
= TREE_VALUE (arglist
);
8423 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8424 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8425 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8426 old
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8427 new = expand_expr (arg2
, NULL_RTX
, mode
, 0);
8429 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8430 MEM_VOLATILE_P (mem
) = 1;
8432 if (GET_MODE (old
) != mode
)
8433 old
= convert_to_mode (mode
, old
, /*unsignedp=*/1);
8434 if (GET_MODE (new) != mode
)
8435 new = convert_to_mode (mode
, new, /*unsignedp=*/1);
8437 if (! register_operand (old
, mode
))
8438 old
= copy_to_mode_reg (mode
, old
);
8439 if (! register_operand (new, mode
))
8440 new = copy_to_mode_reg (mode
, new);
8442 if (! boolp
&& target
&& register_operand (target
, mode
))
8445 tmp
= gen_reg_rtx (mode
);
8447 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8448 convert_move (ccv
, old
, /*unsignedp=*/1);
8449 emit_insn (gen_mf ());
8451 insn
= gen_cmpxchg_acq_si (tmp
, mem
, new, ccv
);
8453 insn
= gen_cmpxchg_acq_di (tmp
, mem
, new, ccv
);
8459 target
= gen_reg_rtx (rmode
);
8460 return emit_store_flag_force (target
, EQ
, tmp
, old
, mode
, 1, 1);
8466 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8469 ia64_expand_lock_test_and_set (enum machine_mode mode
, tree arglist
,
8473 rtx mem
, new, ret
, insn
;
8475 arg0
= TREE_VALUE (arglist
);
8476 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8477 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8478 new = expand_expr (arg1
, NULL_RTX
, mode
, 0);
8480 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8481 MEM_VOLATILE_P (mem
) = 1;
8482 if (! register_operand (new, mode
))
8483 new = copy_to_mode_reg (mode
, new);
8485 if (target
&& register_operand (target
, mode
))
8488 ret
= gen_reg_rtx (mode
);
8491 insn
= gen_xchgsi (ret
, mem
, new);
8493 insn
= gen_xchgdi (ret
, mem
, new);
8499 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8502 ia64_expand_lock_release (enum machine_mode mode
, tree arglist
,
8503 rtx target ATTRIBUTE_UNUSED
)
8508 arg0
= TREE_VALUE (arglist
);
8509 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8511 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8512 MEM_VOLATILE_P (mem
) = 1;
8514 emit_move_insn (mem
, const0_rtx
);
8520 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8521 enum machine_mode mode ATTRIBUTE_UNUSED
,
8522 int ignore ATTRIBUTE_UNUSED
)
8524 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8525 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8526 tree arglist
= TREE_OPERAND (exp
, 1);
8527 enum machine_mode rmode
= VOIDmode
;
8531 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8532 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8537 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8538 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8539 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8540 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8541 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8542 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8543 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8544 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8545 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8546 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8547 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8548 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8549 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8550 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8554 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8559 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8564 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8565 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8566 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8567 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8568 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8569 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8570 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8571 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8572 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8573 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8574 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8575 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8576 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8577 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8587 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8588 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8589 return ia64_expand_compare_and_swap (rmode
, mode
, 1, arglist
,
8592 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8593 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8594 return ia64_expand_compare_and_swap (rmode
, mode
, 0, arglist
,
8597 case IA64_BUILTIN_SYNCHRONIZE
:
8598 emit_insn (gen_mf ());
8601 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8602 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8603 return ia64_expand_lock_test_and_set (mode
, arglist
, target
);
8605 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8606 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8607 return ia64_expand_lock_release (mode
, arglist
, target
);
8609 case IA64_BUILTIN_BSP
:
8610 if (! target
|| ! register_operand (target
, DImode
))
8611 target
= gen_reg_rtx (DImode
);
8612 emit_insn (gen_bsp_value (target
));
8613 #ifdef POINTERS_EXTEND_UNSIGNED
8614 target
= convert_memory_address (ptr_mode
, target
);
8618 case IA64_BUILTIN_FLUSHRS
:
8619 emit_insn (gen_flushrs ());
8622 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8623 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8624 return ia64_expand_fetch_and_op (add_optab
, mode
, arglist
, target
);
8626 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8627 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8628 return ia64_expand_fetch_and_op (sub_optab
, mode
, arglist
, target
);
8630 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8631 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8632 return ia64_expand_fetch_and_op (ior_optab
, mode
, arglist
, target
);
8634 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8635 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8636 return ia64_expand_fetch_and_op (and_optab
, mode
, arglist
, target
);
8638 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8639 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8640 return ia64_expand_fetch_and_op (xor_optab
, mode
, arglist
, target
);
8642 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8643 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8644 return ia64_expand_fetch_and_op (one_cmpl_optab
, mode
, arglist
, target
);
8646 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8647 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8648 return ia64_expand_op_and_fetch (add_optab
, mode
, arglist
, target
);
8650 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8651 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8652 return ia64_expand_op_and_fetch (sub_optab
, mode
, arglist
, target
);
8654 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8655 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8656 return ia64_expand_op_and_fetch (ior_optab
, mode
, arglist
, target
);
8658 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8659 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8660 return ia64_expand_op_and_fetch (and_optab
, mode
, arglist
, target
);
8662 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8663 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8664 return ia64_expand_op_and_fetch (xor_optab
, mode
, arglist
, target
);
8666 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8667 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8668 return ia64_expand_op_and_fetch (one_cmpl_optab
, mode
, arglist
, target
);
8677 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8678 most significant bits of the stack slot. */
8681 ia64_hpux_function_arg_padding (enum machine_mode mode
, tree type
)
8683 /* Exception to normal case for structures/unions/etc. */
8685 if (type
&& AGGREGATE_TYPE_P (type
)
8686 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8689 /* Fall back to the default. */
8690 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8693 /* Linked list of all external functions that are to be emitted by GCC.
8694 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8695 order to avoid putting out names that are never really used. */
8697 struct extern_func_list
GTY(())
8699 struct extern_func_list
*next
;
8703 static GTY(()) struct extern_func_list
*extern_func_head
;
8706 ia64_hpux_add_extern_decl (tree decl
)
8708 struct extern_func_list
*p
= ggc_alloc (sizeof (struct extern_func_list
));
8711 p
->next
= extern_func_head
;
8712 extern_func_head
= p
;
8715 /* Print out the list of used global functions. */
8718 ia64_hpux_file_end (void)
8720 struct extern_func_list
*p
;
8722 for (p
= extern_func_head
; p
; p
= p
->next
)
8724 tree decl
= p
->decl
;
8725 tree id
= DECL_ASSEMBLER_NAME (decl
);
8730 if (!TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (id
))
8732 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8734 TREE_ASM_WRITTEN (decl
) = 1;
8735 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
8736 fputs (TYPE_ASM_OP
, asm_out_file
);
8737 assemble_name (asm_out_file
, name
);
8738 fprintf (asm_out_file
, "," TYPE_OPERAND_FMT
"\n", "function");
8742 extern_func_head
= 0;
8745 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8746 modes of word_mode and larger. */
8749 ia64_init_libfuncs (void)
8751 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
8752 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
8753 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
8754 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
8757 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8760 ia64_hpux_init_libfuncs (void)
8762 ia64_init_libfuncs ();
8764 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
8765 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
8766 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
8767 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
8768 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
8769 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
8770 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
8771 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
8773 /* ia64_expand_compare uses this. */
8774 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
8776 /* These should never be used. */
8777 set_optab_libfunc (eq_optab
, TFmode
, 0);
8778 set_optab_libfunc (ne_optab
, TFmode
, 0);
8779 set_optab_libfunc (gt_optab
, TFmode
, 0);
8780 set_optab_libfunc (ge_optab
, TFmode
, 0);
8781 set_optab_libfunc (lt_optab
, TFmode
, 0);
8782 set_optab_libfunc (le_optab
, TFmode
, 0);
8784 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
8785 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
8786 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
8787 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
8788 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
8789 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
8791 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
8792 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
8793 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
8794 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
8796 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
8797 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
8800 /* Rename the division and modulus functions in VMS. */
8803 ia64_vms_init_libfuncs (void)
8805 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
8806 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
8807 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
8808 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
8809 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
8810 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
8811 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
8812 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
8815 /* Switch to the section to which we should output X. The only thing
8816 special we do here is to honor small data. */
8819 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
8820 unsigned HOST_WIDE_INT align
)
8822 if (GET_MODE_SIZE (mode
) > 0
8823 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8826 default_elf_select_rtx_section (mode
, x
, align
);
8829 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8830 Pretend flag_pic is always set. */
8833 ia64_rwreloc_select_section (tree exp
, int reloc
, unsigned HOST_WIDE_INT align
)
8835 default_elf_select_section_1 (exp
, reloc
, align
, true);
8839 ia64_rwreloc_unique_section (tree decl
, int reloc
)
8841 default_unique_section_1 (decl
, reloc
, true);
8845 ia64_rwreloc_select_rtx_section (enum machine_mode mode
, rtx x
,
8846 unsigned HOST_WIDE_INT align
)
8848 int save_pic
= flag_pic
;
8850 ia64_select_rtx_section (mode
, x
, align
);
8851 flag_pic
= save_pic
;
8855 ia64_rwreloc_section_type_flags (tree decl
, const char *name
, int reloc
)
8857 return default_section_type_flags_1 (decl
, name
, reloc
, true);
8860 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8861 structure type and that the address of that type should be passed
8862 in out0, rather than in r8. */
8865 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
8867 tree ret_type
= TREE_TYPE (fntype
);
8869 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8870 as the structure return address parameter, if the return value
8871 type has a non-trivial copy constructor or destructor. It is not
8872 clear if this same convention should be used for other
8873 programming languages. Until G++ 3.4, we incorrectly used r8 for
8874 these return values. */
8875 return (abi_version_at_least (2)
8877 && TYPE_MODE (ret_type
) == BLKmode
8878 && TREE_ADDRESSABLE (ret_type
)
8879 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
8882 /* Output the assembler code for a thunk function. THUNK_DECL is the
8883 declaration for the thunk function itself, FUNCTION is the decl for
8884 the target function. DELTA is an immediate constant offset to be
8885 added to THIS. If VCALL_OFFSET is nonzero, the word at
8886 *(*this + vcall_offset) should be added to THIS. */
8889 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8890 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8893 rtx
this, insn
, funexp
;
8894 unsigned int this_parmno
;
8895 unsigned int this_regno
;
8897 reload_completed
= 1;
8898 epilogue_completed
= 1;
8901 /* Set things up as ia64_expand_prologue might. */
8902 last_scratch_gr_reg
= 15;
8904 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8905 current_frame_info
.spill_cfa_off
= -16;
8906 current_frame_info
.n_input_regs
= 1;
8907 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8909 /* Mark the end of the (empty) prologue. */
8910 emit_note (NOTE_INSN_PROLOGUE_END
);
8912 /* Figure out whether "this" will be the first parameter (the
8913 typical case) or the second parameter (as happens when the
8914 virtual function returns certain class objects). */
8916 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
8918 this_regno
= IN_REG (this_parmno
);
8919 if (!TARGET_REG_NAMES
)
8920 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
8922 this = gen_rtx_REG (Pmode
, this_regno
);
8925 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
8926 REG_POINTER (tmp
) = 1;
8927 if (delta
&& CONST_OK_FOR_I (delta
))
8929 emit_insn (gen_ptr_extend_plus_imm (this, tmp
, GEN_INT (delta
)));
8933 emit_insn (gen_ptr_extend (this, tmp
));
8936 /* Apply the constant offset, if required. */
8939 rtx delta_rtx
= GEN_INT (delta
);
8941 if (!CONST_OK_FOR_I (delta
))
8943 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8944 emit_move_insn (tmp
, delta_rtx
);
8947 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8950 /* Apply the offset from the vtable, if required. */
8953 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8954 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8958 rtx t
= gen_rtx_REG (ptr_mode
, 2);
8959 REG_POINTER (t
) = 1;
8960 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this));
8961 if (CONST_OK_FOR_I (vcall_offset
))
8963 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
,
8968 emit_insn (gen_ptr_extend (tmp
, t
));
8971 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8975 if (!CONST_OK_FOR_J (vcall_offset
))
8977 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
8978 emit_move_insn (tmp2
, vcall_offset_rtx
);
8979 vcall_offset_rtx
= tmp2
;
8981 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
8985 emit_move_insn (gen_rtx_REG (ptr_mode
, 2),
8986 gen_rtx_MEM (ptr_mode
, tmp
));
8988 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
8990 emit_insn (gen_adddi3 (this, this, tmp
));
8993 /* Generate a tail call to the target function. */
8994 if (! TREE_USED (function
))
8996 assemble_external (function
);
8997 TREE_USED (function
) = 1;
8999 funexp
= XEXP (DECL_RTL (function
), 0);
9000 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9001 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
9002 insn
= get_last_insn ();
9003 SIBLING_CALL_P (insn
) = 1;
9005 /* Code generation for calls relies on splitting. */
9006 reload_completed
= 1;
9007 epilogue_completed
= 1;
9008 try_split (PATTERN (insn
), insn
, 0);
9012 /* Run just enough of rest_of_compilation to get the insns emitted.
9013 There's not really enough bulk here to make other passes such as
9014 instruction scheduling worth while. Note that use_thunk calls
9015 assemble_start_function and assemble_end_function. */
9017 insn_locators_initialize ();
9018 emit_all_insn_group_barriers (NULL
);
9019 insn
= get_insns ();
9020 shorten_branches (insn
);
9021 final_start_function (insn
, file
, 1);
9022 final (insn
, file
, 1, 0);
9023 final_end_function ();
9025 reload_completed
= 0;
9026 epilogue_completed
= 0;
9030 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9033 ia64_struct_value_rtx (tree fntype
,
9034 int incoming ATTRIBUTE_UNUSED
)
9036 if (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
))
9038 return gen_rtx_REG (Pmode
, GR_REG (8));
9041 #include "gt-ia64.h"