gcc/config/mips/mips-fixed.md

   1 ;; Copyright (C) 2007-2022 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19 ;; This file contains MIPS instructions that support fixed-point operations.
  20
  21 ;; All supported fixed-point modes
  22 (define_mode_iterator FIXED [(QQ "") (HQ "") (SQ "") (DQ "TARGET_64BIT")
  23                              (UQQ "") (UHQ "") (USQ "") (UDQ "TARGET_64BIT")
  24                              (HA "") (SA "") (DA "TARGET_64BIT")
  25                              (UHA "") (USA "") (UDA "TARGET_64BIT")])
  26
  27 ;; For signed add/sub with saturation
  28 (define_mode_iterator ADDSUB [(HQ "") (SQ "") (HA "") (SA "") (V2HQ "")
  29                               (V2HA "")])
  30 (define_mode_attr addsubfmt [(HQ "ph") (SQ "w") (HA "ph") (SA "w")
  31                              (V2HQ "ph") (V2HA "ph")])
  32
  33 ;; For unsigned add/sub with saturation
  34 (define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
  35                                (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
  36                                (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
  37 (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
  38                               (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])
  39
  40 ;; For signed multiplication with saturation
  41 (define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
  42                             (SQ "ISA_HAS_DSPR2")])
  43 (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])
  44
  45 (define_insn "add<mode>3"
  46   [(set (match_operand:FIXED 0 "register_operand" "=d")
  47         (plus:FIXED (match_operand:FIXED 1 "register_operand" "d")
  48                     (match_operand:FIXED 2 "register_operand" "d")))]
  49   ""
  50   "<d>addu\t%0,%1,%2"
  51   [(set_attr "type" "arith")
  52    (set_attr "mode" "<IMODE>")])
  53
  54 (define_insn "usadd<mode>3"
  55   [(set (match_operand:UADDSUB 0 "register_operand" "=d")
  56         (us_plus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
  57                          (match_operand:UADDSUB 2 "register_operand" "d")))
  58    (set (reg:CCDSP CCDSP_OU_REGNUM)
  59         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
  60   ""
  61   "addu_s.<uaddsubfmt>\t%0,%1,%2"
  62   [(set_attr "type" "arith")
  63    (set_attr "mode" "<IMODE>")])
  64
  65 (define_insn "ssadd<mode>3"
  66   [(set (match_operand:ADDSUB 0 "register_operand" "=d")
  67         (ss_plus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
  68                         (match_operand:ADDSUB 2 "register_operand" "d")))
  69    (set (reg:CCDSP CCDSP_OU_REGNUM)
  70         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))]
  71   "ISA_HAS_DSP"
  72   "addq_s.<addsubfmt>\t%0,%1,%2"
  73   [(set_attr "type" "arith")
  74    (set_attr "mode" "<IMODE>")])
  75
  76 (define_insn "sub<mode>3"
  77   [(set (match_operand:FIXED 0 "register_operand" "=d")
  78         (minus:FIXED (match_operand:FIXED 1 "register_operand" "d")
  79                      (match_operand:FIXED 2 "register_operand" "d")))]
  80   ""
  81   "<d>subu\t%0,%1,%2"
  82   [(set_attr "type" "arith")
  83    (set_attr "mode" "<IMODE>")])
  84
  85 (define_insn "ussub<mode>3"
  86   [(set (match_operand:UADDSUB 0 "register_operand" "=d")
  87         (us_minus:UADDSUB (match_operand:UADDSUB 1 "register_operand" "d")
  88                           (match_operand:UADDSUB 2 "register_operand" "d")))
  89    (set (reg:CCDSP CCDSP_OU_REGNUM)
  90         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
  91   ""
  92   "subu_s.<uaddsubfmt>\t%0,%1,%2"
  93   [(set_attr "type" "arith")
  94    (set_attr "mode" "<IMODE>")])
  95
  96 (define_insn "sssub<mode>3"
  97   [(set (match_operand:ADDSUB 0 "register_operand" "=d")
  98         (ss_minus:ADDSUB (match_operand:ADDSUB 1 "register_operand" "d")
  99                          (match_operand:ADDSUB 2 "register_operand" "d")))
 100    (set (reg:CCDSP CCDSP_OU_REGNUM)
 101         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))]
 102   "ISA_HAS_DSP"
 103   "subq_s.<addsubfmt>\t%0,%1,%2"
 104   [(set_attr "type" "arith")
 105    (set_attr "mode" "<IMODE>")])
 106
 107 (define_insn "ssmul<mode>3"
 108   [(set (match_operand:MULQ 0 "register_operand" "=d")
 109         (ss_mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
 110                       (match_operand:MULQ 2 "register_operand" "d")))
 111    (set (reg:CCDSP CCDSP_OU_REGNUM)
 112         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
 113    (clobber (match_scratch:DI 3 "=x"))]
 114   ""
 115   "mulq_rs.<mulqfmt>\t%0,%1,%2"
 116   [(set_attr "type"     "imul3")
 117    (set_attr "mode"     "<IMODE>")])
 118
 119 (define_insn "ssmaddsqdq4"
 120   [(set (match_operand:DQ 0 "register_operand" "=a")
 121         (ss_plus:DQ
 122         (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
 123                                    "register_operand" "d"))
 124                     (sat_fract:DQ (match_operand:SQ 2
 125                                    "register_operand" "d")))
 126         (match_operand:DQ 3 "register_operand" "0")))
 127    (set (reg:CCDSP CCDSP_OU_REGNUM)
 128         (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 129                       UNSPEC_DPAQ_SA_L_W))]
 130   "ISA_HAS_DSP && !TARGET_64BIT"
 131   "dpaq_sa.l.w\t%q0,%1,%2"
 132   [(set_attr "type" "imadd")
 133    (set_attr "mode" "SI")])
 134
 135 (define_insn "ssmsubsqdq4"
 136   [(set (match_operand:DQ 0 "register_operand" "=a")
 137         (ss_minus:DQ
 138          (match_operand:DQ 3 "register_operand" "0")
 139          (ss_mult:DQ (sat_fract:DQ (match_operand:SQ 1
 140                                     "register_operand" "d"))
 141                      (sat_fract:DQ (match_operand:SQ 2
 142                                     "register_operand" "d")))))
 143    (set (reg:CCDSP CCDSP_OU_REGNUM)
 144         (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 145                       UNSPEC_DPSQ_SA_L_W))]
 146   "ISA_HAS_DSP && !TARGET_64BIT"
 147   "dpsq_sa.l.w\t%q0,%1,%2"
 148   [(set_attr "type" "imadd")
 149    (set_attr "mode" "SI")])