1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
33 #include "stringpool.h"
39 #include "diagnostic-core.h"
40 #include "insn-attr.h"
42 #include "fold-const.h"
43 #include "stor-layout.h"
51 #include "common/common-target.h"
52 #include "langhooks.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Return nonzero if there is a bypass for the output of
61 OUT_INSN and the fp store IN_INSN. */
63 pa_fpstore_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
65 machine_mode store_mode
;
66 machine_mode other_mode
;
69 if (recog_memoized (in_insn
) < 0
70 || (get_attr_type (in_insn
) != TYPE_FPSTORE
71 && get_attr_type (in_insn
) != TYPE_FPSTORE_LOAD
)
72 || recog_memoized (out_insn
) < 0)
75 store_mode
= GET_MODE (SET_SRC (PATTERN (in_insn
)));
77 set
= single_set (out_insn
);
81 other_mode
= GET_MODE (SET_SRC (set
));
83 return (GET_MODE_SIZE (store_mode
) == GET_MODE_SIZE (other_mode
));
87 #ifndef DO_FRAME_NOTES
88 #ifdef INCOMING_RETURN_ADDR_RTX
89 #define DO_FRAME_NOTES 1
91 #define DO_FRAME_NOTES 0
95 static void pa_option_override (void);
96 static void copy_reg_pointer (rtx
, rtx
);
97 static void fix_range (const char *);
98 static int hppa_register_move_cost (machine_mode mode
, reg_class_t
,
100 static int hppa_address_cost (rtx
, machine_mode mode
, addr_space_t
, bool);
101 static bool hppa_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
102 static inline rtx
force_mode (machine_mode
, rtx
);
103 static void pa_reorg (void);
104 static void pa_combine_instructions (void);
105 static int pa_can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, int, rtx
,
107 static bool forward_branch_p (rtx_insn
*);
108 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT
, unsigned *);
109 static void compute_zdepdi_operands (unsigned HOST_WIDE_INT
, unsigned *);
110 static int compute_cpymem_length (rtx_insn
*);
111 static int compute_clrmem_length (rtx_insn
*);
112 static bool pa_assemble_integer (rtx
, unsigned int, int);
113 static void remove_useless_addtr_insns (int);
114 static void store_reg (int, HOST_WIDE_INT
, int);
115 static void store_reg_modify (int, int, HOST_WIDE_INT
);
116 static void load_reg (int, HOST_WIDE_INT
, int);
117 static void set_reg_plus_d (int, int, HOST_WIDE_INT
, int);
118 static rtx
pa_function_value (const_tree
, const_tree
, bool);
119 static rtx
pa_libcall_value (machine_mode
, const_rtx
);
120 static bool pa_function_value_regno_p (const unsigned int);
121 static void pa_output_function_prologue (FILE *) ATTRIBUTE_UNUSED
;
122 static void pa_linux_output_function_prologue (FILE *) ATTRIBUTE_UNUSED
;
123 static void update_total_code_bytes (unsigned int);
124 static void pa_output_function_epilogue (FILE *);
125 static int pa_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
126 static int pa_issue_rate (void);
127 static int pa_reloc_rw_mask (void);
128 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED
;
129 static section
*pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED
;
130 static section
*pa_select_section (tree
, int, unsigned HOST_WIDE_INT
)
132 static void pa_encode_section_info (tree
, rtx
, int);
133 static const char *pa_strip_name_encoding (const char *);
134 static bool pa_function_ok_for_sibcall (tree
, tree
);
135 static void pa_globalize_label (FILE *, const char *)
137 static void pa_asm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
138 HOST_WIDE_INT
, tree
);
139 #if !defined(USE_COLLECT2)
140 static void pa_asm_out_constructor (rtx
, int);
141 static void pa_asm_out_destructor (rtx
, int);
143 static void pa_init_builtins (void);
144 static rtx
pa_expand_builtin (tree
, rtx
, rtx
, machine_mode mode
, int);
145 static rtx
hppa_builtin_saveregs (void);
146 static void hppa_va_start (tree
, rtx
);
147 static tree
hppa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
148 static bool pa_scalar_mode_supported_p (scalar_mode
);
149 static bool pa_commutative_p (const_rtx x
, int outer_code
);
150 static void copy_fp_args (rtx_insn
*) ATTRIBUTE_UNUSED
;
151 static int length_fp_args (rtx_insn
*) ATTRIBUTE_UNUSED
;
152 static rtx
hppa_legitimize_address (rtx
, rtx
, machine_mode
);
153 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED
;
154 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED
;
155 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED
;
156 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED
;
157 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED
;
158 static void pa_som_file_start (void) ATTRIBUTE_UNUSED
;
159 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED
;
160 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED
;
161 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED
;
162 static void output_deferred_plabels (void);
163 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED
;
164 static void pa_file_end (void);
165 static void pa_init_libfuncs (void);
166 static rtx
pa_struct_value_rtx (tree
, int);
167 static bool pa_pass_by_reference (cumulative_args_t
,
168 const function_arg_info
&);
169 static int pa_arg_partial_bytes (cumulative_args_t
, const function_arg_info
&);
170 static void pa_function_arg_advance (cumulative_args_t
,
171 const function_arg_info
&);
172 static rtx
pa_function_arg (cumulative_args_t
, const function_arg_info
&);
173 static pad_direction
pa_function_arg_padding (machine_mode
, const_tree
);
174 static unsigned int pa_function_arg_boundary (machine_mode
, const_tree
);
175 static struct machine_function
* pa_init_machine_status (void);
176 static reg_class_t
pa_secondary_reload (bool, rtx
, reg_class_t
,
178 secondary_reload_info
*);
179 static bool pa_secondary_memory_needed (machine_mode
,
180 reg_class_t
, reg_class_t
);
181 static void pa_extra_live_on_entry (bitmap
);
182 static machine_mode
pa_promote_function_mode (const_tree
,
186 static void pa_asm_trampoline_template (FILE *);
187 static void pa_trampoline_init (rtx
, tree
, rtx
);
188 static rtx
pa_trampoline_adjust_address (rtx
);
189 static rtx
pa_delegitimize_address (rtx
);
190 static bool pa_print_operand_punct_valid_p (unsigned char);
191 static rtx
pa_internal_arg_pointer (void);
192 static bool pa_can_eliminate (const int, const int);
193 static void pa_conditional_register_usage (void);
194 static machine_mode
pa_c_mode_for_suffix (char);
195 static section
*pa_function_section (tree
, enum node_frequency
, bool, bool);
196 static bool pa_cannot_force_const_mem (machine_mode
, rtx
);
197 static bool pa_legitimate_constant_p (machine_mode
, rtx
);
198 static unsigned int pa_section_type_flags (tree
, const char *, int);
199 static bool pa_legitimate_address_p (machine_mode
, rtx
, bool);
200 static bool pa_callee_copies (cumulative_args_t
, const function_arg_info
&);
201 static unsigned int pa_hard_regno_nregs (unsigned int, machine_mode
);
202 static bool pa_hard_regno_mode_ok (unsigned int, machine_mode
);
203 static bool pa_modes_tieable_p (machine_mode
, machine_mode
);
204 static bool pa_can_change_mode_class (machine_mode
, machine_mode
, reg_class_t
);
205 static HOST_WIDE_INT
pa_starting_frame_offset (void);
207 /* The following extra sections are only used for SOM. */
208 static GTY(()) section
*som_readonly_data_section
;
209 static GTY(()) section
*som_one_only_readonly_data_section
;
210 static GTY(()) section
*som_one_only_data_section
;
211 static GTY(()) section
*som_tm_clone_table_section
;
213 /* Counts for the number of callee-saved general and floating point
214 registers which were saved by the current function's prologue. */
215 static int gr_saved
, fr_saved
;
217 /* Boolean indicating whether the return pointer was saved by the
218 current function's prologue. */
219 static bool rp_saved
;
221 static rtx
find_addr_reg (rtx
);
223 /* Keep track of the number of bytes we have output in the CODE subspace
224 during this compilation so we'll know when to emit inline long-calls. */
225 unsigned long total_code_bytes
;
227 /* The last address of the previous function plus the number of bytes in
228 associated thunks that have been output. This is used to determine if
229 a thunk can use an IA-relative branch to reach its target function. */
230 static unsigned int last_address
;
232 /* Variables to handle plabels that we discover are necessary at assembly
233 output time. They are output after the current function. */
234 struct GTY(()) deferred_plabel
239 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel
*
241 static size_t n_deferred_plabels
= 0;
243 /* Initialize the GCC target structure. */
245 #undef TARGET_OPTION_OVERRIDE
246 #define TARGET_OPTION_OVERRIDE pa_option_override
248 #undef TARGET_ASM_ALIGNED_HI_OP
249 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
250 #undef TARGET_ASM_ALIGNED_SI_OP
251 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
252 #undef TARGET_ASM_ALIGNED_DI_OP
253 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
254 #undef TARGET_ASM_UNALIGNED_HI_OP
255 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
256 #undef TARGET_ASM_UNALIGNED_SI_OP
257 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
258 #undef TARGET_ASM_UNALIGNED_DI_OP
259 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
260 #undef TARGET_ASM_INTEGER
261 #define TARGET_ASM_INTEGER pa_assemble_integer
263 #undef TARGET_ASM_FUNCTION_EPILOGUE
264 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
266 #undef TARGET_FUNCTION_VALUE
267 #define TARGET_FUNCTION_VALUE pa_function_value
268 #undef TARGET_LIBCALL_VALUE
269 #define TARGET_LIBCALL_VALUE pa_libcall_value
270 #undef TARGET_FUNCTION_VALUE_REGNO_P
271 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
273 #undef TARGET_LEGITIMIZE_ADDRESS
274 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
276 #undef TARGET_SCHED_ADJUST_COST
277 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
278 #undef TARGET_SCHED_ISSUE_RATE
279 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
281 #undef TARGET_ENCODE_SECTION_INFO
282 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
283 #undef TARGET_STRIP_NAME_ENCODING
284 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
286 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
287 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
289 #undef TARGET_COMMUTATIVE_P
290 #define TARGET_COMMUTATIVE_P pa_commutative_p
292 #undef TARGET_ASM_OUTPUT_MI_THUNK
293 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
297 #undef TARGET_ASM_FILE_END
298 #define TARGET_ASM_FILE_END pa_file_end
300 #undef TARGET_ASM_RELOC_RW_MASK
301 #define TARGET_ASM_RELOC_RW_MASK pa_reloc_rw_mask
303 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
304 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
306 #if !defined(USE_COLLECT2)
307 #undef TARGET_ASM_CONSTRUCTOR
308 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
309 #undef TARGET_ASM_DESTRUCTOR
310 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
313 #undef TARGET_INIT_BUILTINS
314 #define TARGET_INIT_BUILTINS pa_init_builtins
316 #undef TARGET_EXPAND_BUILTIN
317 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
319 #undef TARGET_REGISTER_MOVE_COST
320 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
321 #undef TARGET_RTX_COSTS
322 #define TARGET_RTX_COSTS hppa_rtx_costs
323 #undef TARGET_ADDRESS_COST
324 #define TARGET_ADDRESS_COST hppa_address_cost
326 #undef TARGET_MACHINE_DEPENDENT_REORG
327 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
329 #undef TARGET_INIT_LIBFUNCS
330 #define TARGET_INIT_LIBFUNCS pa_init_libfuncs
332 #undef TARGET_PROMOTE_FUNCTION_MODE
333 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
334 #undef TARGET_PROMOTE_PROTOTYPES
335 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
337 #undef TARGET_STRUCT_VALUE_RTX
338 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
339 #undef TARGET_RETURN_IN_MEMORY
340 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
341 #undef TARGET_MUST_PASS_IN_STACK
342 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
343 #undef TARGET_PASS_BY_REFERENCE
344 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
345 #undef TARGET_CALLEE_COPIES
346 #define TARGET_CALLEE_COPIES pa_callee_copies
347 #undef TARGET_ARG_PARTIAL_BYTES
348 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
349 #undef TARGET_FUNCTION_ARG
350 #define TARGET_FUNCTION_ARG pa_function_arg
351 #undef TARGET_FUNCTION_ARG_ADVANCE
352 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
353 #undef TARGET_FUNCTION_ARG_PADDING
354 #define TARGET_FUNCTION_ARG_PADDING pa_function_arg_padding
355 #undef TARGET_FUNCTION_ARG_BOUNDARY
356 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
358 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
359 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
360 #undef TARGET_EXPAND_BUILTIN_VA_START
361 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
362 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
363 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
365 #undef TARGET_SCALAR_MODE_SUPPORTED_P
366 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
368 #undef TARGET_CANNOT_FORCE_CONST_MEM
369 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
371 #undef TARGET_SECONDARY_RELOAD
372 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
373 #undef TARGET_SECONDARY_MEMORY_NEEDED
374 #define TARGET_SECONDARY_MEMORY_NEEDED pa_secondary_memory_needed
376 #undef TARGET_EXTRA_LIVE_ON_ENTRY
377 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
379 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
380 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
381 #undef TARGET_TRAMPOLINE_INIT
382 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
383 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
384 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
385 #undef TARGET_DELEGITIMIZE_ADDRESS
386 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
387 #undef TARGET_INTERNAL_ARG_POINTER
388 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
389 #undef TARGET_CAN_ELIMINATE
390 #define TARGET_CAN_ELIMINATE pa_can_eliminate
391 #undef TARGET_CONDITIONAL_REGISTER_USAGE
392 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
393 #undef TARGET_C_MODE_FOR_SUFFIX
394 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
395 #undef TARGET_ASM_FUNCTION_SECTION
396 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
398 #undef TARGET_LEGITIMATE_CONSTANT_P
399 #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p
400 #undef TARGET_SECTION_TYPE_FLAGS
401 #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
402 #undef TARGET_LEGITIMATE_ADDRESS_P
403 #define TARGET_LEGITIMATE_ADDRESS_P pa_legitimate_address_p
406 #define TARGET_LRA_P hook_bool_void_false
408 #undef TARGET_HARD_REGNO_NREGS
409 #define TARGET_HARD_REGNO_NREGS pa_hard_regno_nregs
410 #undef TARGET_HARD_REGNO_MODE_OK
411 #define TARGET_HARD_REGNO_MODE_OK pa_hard_regno_mode_ok
412 #undef TARGET_MODES_TIEABLE_P
413 #define TARGET_MODES_TIEABLE_P pa_modes_tieable_p
415 #undef TARGET_CAN_CHANGE_MODE_CLASS
416 #define TARGET_CAN_CHANGE_MODE_CLASS pa_can_change_mode_class
418 #undef TARGET_CONSTANT_ALIGNMENT
419 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
421 #undef TARGET_STARTING_FRAME_OFFSET
422 #define TARGET_STARTING_FRAME_OFFSET pa_starting_frame_offset
424 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
425 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
427 struct gcc_target targetm
= TARGET_INITIALIZER
;
429 /* Parse the -mfixed-range= option string. */
432 fix_range (const char *const_str
)
435 char *str
, *dash
, *comma
;
437 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
438 REG2 are either register names or register numbers. The effect
439 of this option is to mark the registers in the range from REG1 to
440 REG2 as ``fixed'' so they won't be used by the compiler. This is
441 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
443 i
= strlen (const_str
);
444 str
= (char *) alloca (i
+ 1);
445 memcpy (str
, const_str
, i
+ 1);
449 dash
= strchr (str
, '-');
452 warning (0, "value of %<-mfixed-range%> must have form REG1-REG2");
457 comma
= strchr (dash
+ 1, ',');
461 first
= decode_reg_name (str
);
464 warning (0, "unknown register name: %s", str
);
468 last
= decode_reg_name (dash
+ 1);
471 warning (0, "unknown register name: %s", dash
+ 1);
479 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
483 for (i
= first
; i
<= last
; ++i
)
484 fixed_regs
[i
] = call_used_regs
[i
] = 1;
493 /* Check if all floating point registers have been fixed. */
494 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
499 target_flags
|= MASK_DISABLE_FPREGS
;
502 /* Implement the TARGET_OPTION_OVERRIDE hook. */
505 pa_option_override (void)
508 cl_deferred_option
*opt
;
509 vec
<cl_deferred_option
> *v
510 = (vec
<cl_deferred_option
> *) pa_deferred_options
;
513 FOR_EACH_VEC_ELT (*v
, i
, opt
)
515 switch (opt
->opt_index
)
517 case OPT_mfixed_range_
:
518 fix_range (opt
->arg
);
526 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
528 warning (0, "PIC code generation is not supported in the portable runtime model");
531 if (flag_pic
&& TARGET_FAST_INDIRECT_CALLS
)
533 warning (0, "PIC code generation is not compatible with fast indirect calls");
536 if (! TARGET_GAS
&& write_symbols
!= NO_DEBUG
)
538 warning (0, "%<-g%> is only supported when using GAS on this processor");
539 warning (0, "%<-g%> option disabled");
540 write_symbols
= NO_DEBUG
;
543 /* We only support the "big PIC" model now. And we always generate PIC
544 code when in 64bit mode. */
545 if (flag_pic
== 1 || TARGET_64BIT
)
548 /* Disable -freorder-blocks-and-partition as we don't support hot and
549 cold partitioning. */
550 if (flag_reorder_blocks_and_partition
)
552 inform (input_location
,
553 "%<-freorder-blocks-and-partition%> does not work "
554 "on this architecture");
555 flag_reorder_blocks_and_partition
= 0;
556 flag_reorder_blocks
= 1;
559 /* We can't guarantee that .dword is available for 32-bit targets. */
560 if (UNITS_PER_WORD
== 4)
561 targetm
.asm_out
.aligned_op
.di
= NULL
;
563 /* The unaligned ops are only available when using GAS. */
566 targetm
.asm_out
.unaligned_op
.hi
= NULL
;
567 targetm
.asm_out
.unaligned_op
.si
= NULL
;
568 targetm
.asm_out
.unaligned_op
.di
= NULL
;
571 init_machine_status
= pa_init_machine_status
;
576 PA_BUILTIN_COPYSIGNQ
,
579 PA_BUILTIN_HUGE_VALQ
,
583 static GTY(()) tree pa_builtins
[(int) PA_BUILTIN_max
];
586 pa_init_builtins (void)
588 #ifdef DONT_HAVE_FPUTC_UNLOCKED
590 tree decl
= builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED
);
591 set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED
, decl
,
592 builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED
));
599 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITE
)) != NULL_TREE
)
600 set_user_assembler_name (decl
, "_Isfinite");
601 if ((decl
= builtin_decl_explicit (BUILT_IN_FINITEF
)) != NULL_TREE
)
602 set_user_assembler_name (decl
, "_Isfinitef");
606 if (HPUX_LONG_DOUBLE_LIBRARY
)
610 /* Under HPUX, the __float128 type is a synonym for "long double". */
611 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
614 /* TFmode support builtins. */
615 ftype
= build_function_type_list (long_double_type_node
,
616 long_double_type_node
,
618 decl
= add_builtin_function ("__builtin_fabsq", ftype
,
619 PA_BUILTIN_FABSQ
, BUILT_IN_MD
,
620 "_U_Qfabs", NULL_TREE
);
621 TREE_READONLY (decl
) = 1;
622 pa_builtins
[PA_BUILTIN_FABSQ
] = decl
;
624 ftype
= build_function_type_list (long_double_type_node
,
625 long_double_type_node
,
626 long_double_type_node
,
628 decl
= add_builtin_function ("__builtin_copysignq", ftype
,
629 PA_BUILTIN_COPYSIGNQ
, BUILT_IN_MD
,
630 "_U_Qfcopysign", NULL_TREE
);
631 TREE_READONLY (decl
) = 1;
632 pa_builtins
[PA_BUILTIN_COPYSIGNQ
] = decl
;
634 ftype
= build_function_type_list (long_double_type_node
, NULL_TREE
);
635 decl
= add_builtin_function ("__builtin_infq", ftype
,
636 PA_BUILTIN_INFQ
, BUILT_IN_MD
,
638 pa_builtins
[PA_BUILTIN_INFQ
] = decl
;
640 decl
= add_builtin_function ("__builtin_huge_valq", ftype
,
641 PA_BUILTIN_HUGE_VALQ
, BUILT_IN_MD
,
643 pa_builtins
[PA_BUILTIN_HUGE_VALQ
] = decl
;
648 pa_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
649 machine_mode mode ATTRIBUTE_UNUSED
,
650 int ignore ATTRIBUTE_UNUSED
)
652 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
653 unsigned int fcode
= DECL_MD_FUNCTION_CODE (fndecl
);
657 case PA_BUILTIN_FABSQ
:
658 case PA_BUILTIN_COPYSIGNQ
:
659 return expand_call (exp
, target
, ignore
);
661 case PA_BUILTIN_INFQ
:
662 case PA_BUILTIN_HUGE_VALQ
:
664 machine_mode target_mode
= TYPE_MODE (TREE_TYPE (exp
));
669 tmp
= const_double_from_real_value (inf
, target_mode
);
671 tmp
= validize_mem (force_const_mem (target_mode
, tmp
));
674 target
= gen_reg_rtx (target_mode
);
676 emit_move_insn (target
, tmp
);
687 /* Function to init struct machine_function.
688 This will be called, via a pointer variable,
689 from push_function_context. */
691 static struct machine_function
*
692 pa_init_machine_status (void)
694 return ggc_cleared_alloc
<machine_function
> ();
697 /* If FROM is a probable pointer register, mark TO as a probable
698 pointer register with the same pointer alignment as FROM. */
701 copy_reg_pointer (rtx to
, rtx from
)
703 if (REG_POINTER (from
))
704 mark_reg_pointer (to
, REGNO_POINTER_ALIGN (REGNO (from
)));
707 /* Return 1 if X contains a symbolic expression. We know these
708 expressions will have one of a few well defined forms, so
709 we need only check those forms. */
711 pa_symbolic_expression_p (rtx x
)
714 /* Strip off any HIGH. */
715 if (GET_CODE (x
) == HIGH
)
718 return symbolic_operand (x
, VOIDmode
);
721 /* Accept any constant that can be moved in one instruction into a
724 pa_cint_ok_for_move (unsigned HOST_WIDE_INT ival
)
726 /* OK if ldo, ldil, or zdepi, can be used. */
727 return (VAL_14_BITS_P (ival
)
728 || pa_ldil_cint_p (ival
)
729 || pa_zdepi_cint_p (ival
));
732 /* True iff ldil can be used to load this CONST_INT. The least
733 significant 11 bits of the value must be zero and the value must
734 not change sign when extended from 32 to 64 bits. */
736 pa_ldil_cint_p (unsigned HOST_WIDE_INT ival
)
738 unsigned HOST_WIDE_INT x
;
740 x
= ival
& (((unsigned HOST_WIDE_INT
) -1 << 31) | 0x7ff);
741 return x
== 0 || x
== ((unsigned HOST_WIDE_INT
) -1 << 31);
744 /* True iff zdepi can be used to generate this CONST_INT.
745 zdepi first sign extends a 5-bit signed number to a given field
746 length, then places this field anywhere in a zero. */
748 pa_zdepi_cint_p (unsigned HOST_WIDE_INT x
)
750 unsigned HOST_WIDE_INT lsb_mask
, t
;
752 /* This might not be obvious, but it's at least fast.
753 This function is critical; we don't have the time loops would take. */
755 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
756 /* Return true iff t is a power of two. */
757 return ((t
& (t
- 1)) == 0);
760 /* True iff depi or extru can be used to compute (reg & mask).
761 Accept bit pattern like these:
766 pa_and_mask_p (unsigned HOST_WIDE_INT mask
)
769 mask
+= mask
& -mask
;
770 return (mask
& (mask
- 1)) == 0;
773 /* True iff depi can be used to compute (reg | MASK). */
775 pa_ior_mask_p (unsigned HOST_WIDE_INT mask
)
777 mask
+= mask
& -mask
;
778 return (mask
& (mask
- 1)) == 0;
781 /* Legitimize PIC addresses. If the address is already
782 position-independent, we return ORIG. Newly generated
783 position-independent addresses go to REG. If we need more
784 than one register, we lose. */
787 legitimize_pic_address (rtx orig
, machine_mode mode
, rtx reg
)
791 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig
));
793 /* Labels need special handling. */
794 if (pic_label_operand (orig
, mode
))
798 /* We do not want to go through the movXX expanders here since that
799 would create recursion.
801 Nor do we really want to call a generator for a named pattern
802 since that requires multiple patterns if we want to support
805 So instead we just emit the raw set, which avoids the movXX
806 expanders completely. */
807 mark_reg_pointer (reg
, BITS_PER_UNIT
);
808 insn
= emit_insn (gen_rtx_SET (reg
, orig
));
810 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
811 add_reg_note (insn
, REG_EQUAL
, orig
);
813 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
814 and update LABEL_NUSES because this is not done automatically. */
815 if (reload_in_progress
|| reload_completed
)
817 /* Extract LABEL_REF. */
818 if (GET_CODE (orig
) == CONST
)
819 orig
= XEXP (XEXP (orig
, 0), 0);
820 /* Extract CODE_LABEL. */
821 orig
= XEXP (orig
, 0);
822 add_reg_note (insn
, REG_LABEL_OPERAND
, orig
);
823 /* Make sure we have label and not a note. */
825 LABEL_NUSES (orig
)++;
827 crtl
->uses_pic_offset_table
= 1;
830 if (GET_CODE (orig
) == SYMBOL_REF
)
837 /* Before reload, allocate a temporary register for the intermediate
838 result. This allows the sequence to be deleted when the final
839 result is unused and the insns are trivially dead. */
840 tmp_reg
= ((reload_in_progress
|| reload_completed
)
841 ? reg
: gen_reg_rtx (Pmode
));
843 if (function_label_operand (orig
, VOIDmode
))
845 /* Force function label into memory in word mode. */
846 orig
= XEXP (force_const_mem (word_mode
, orig
), 0);
847 /* Load plabel address from DLT. */
848 emit_move_insn (tmp_reg
,
849 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
850 gen_rtx_HIGH (word_mode
, orig
)));
852 = gen_const_mem (Pmode
,
853 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
854 gen_rtx_UNSPEC (Pmode
,
857 emit_move_insn (reg
, pic_ref
);
858 /* Now load address of function descriptor. */
859 pic_ref
= gen_rtx_MEM (Pmode
, reg
);
863 /* Load symbol reference from DLT. */
864 emit_move_insn (tmp_reg
,
865 gen_rtx_PLUS (word_mode
, pic_offset_table_rtx
,
866 gen_rtx_HIGH (word_mode
, orig
)));
868 = gen_const_mem (Pmode
,
869 gen_rtx_LO_SUM (Pmode
, tmp_reg
,
870 gen_rtx_UNSPEC (Pmode
,
875 crtl
->uses_pic_offset_table
= 1;
876 mark_reg_pointer (reg
, BITS_PER_UNIT
);
877 insn
= emit_move_insn (reg
, pic_ref
);
879 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
880 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
884 else if (GET_CODE (orig
) == CONST
)
888 if (GET_CODE (XEXP (orig
, 0)) == PLUS
889 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
893 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
895 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
896 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
897 base
== reg
? 0 : reg
);
899 if (GET_CODE (orig
) == CONST_INT
)
901 if (INT_14_BITS (orig
))
902 return plus_constant (Pmode
, base
, INTVAL (orig
));
903 orig
= force_reg (Pmode
, orig
);
905 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
906 /* Likewise, should we set special REG_NOTEs here? */
912 static GTY(()) rtx gen_tls_tga
;
915 gen_tls_get_addr (void)
918 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
923 hppa_tls_call (rtx arg
)
927 ret
= gen_reg_rtx (Pmode
);
928 emit_library_call_value (gen_tls_get_addr (), ret
,
929 LCT_CONST
, Pmode
, arg
, Pmode
);
935 legitimize_tls_address (rtx addr
)
937 rtx ret
, tmp
, t1
, t2
, tp
;
940 /* Currently, we can't handle anything but a SYMBOL_REF. */
941 if (GET_CODE (addr
) != SYMBOL_REF
)
944 switch (SYMBOL_REF_TLS_MODEL (addr
))
946 case TLS_MODEL_GLOBAL_DYNAMIC
:
947 tmp
= gen_reg_rtx (Pmode
);
949 emit_insn (gen_tgd_load_pic (tmp
, addr
));
951 emit_insn (gen_tgd_load (tmp
, addr
));
952 ret
= hppa_tls_call (tmp
);
955 case TLS_MODEL_LOCAL_DYNAMIC
:
956 ret
= gen_reg_rtx (Pmode
);
957 tmp
= gen_reg_rtx (Pmode
);
960 emit_insn (gen_tld_load_pic (tmp
, addr
));
962 emit_insn (gen_tld_load (tmp
, addr
));
963 t1
= hppa_tls_call (tmp
);
966 t2
= gen_reg_rtx (Pmode
);
967 emit_libcall_block (insn
, t2
, t1
,
968 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
970 emit_insn (gen_tld_offset_load (ret
, addr
, t2
));
973 case TLS_MODEL_INITIAL_EXEC
:
974 tp
= gen_reg_rtx (Pmode
);
975 tmp
= gen_reg_rtx (Pmode
);
976 ret
= gen_reg_rtx (Pmode
);
977 emit_insn (gen_tp_load (tp
));
979 emit_insn (gen_tie_load_pic (tmp
, addr
));
981 emit_insn (gen_tie_load (tmp
, addr
));
982 emit_move_insn (ret
, gen_rtx_PLUS (Pmode
, tp
, tmp
));
985 case TLS_MODEL_LOCAL_EXEC
:
986 tp
= gen_reg_rtx (Pmode
);
987 ret
= gen_reg_rtx (Pmode
);
988 emit_insn (gen_tp_load (tp
));
989 emit_insn (gen_tle_load (ret
, addr
, tp
));
999 /* Helper for hppa_legitimize_address. Given X, return true if it
1000 is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
1002 This respectively represent canonical shift-add rtxs or scaled
1003 memory addresses. */
1005 mem_shadd_or_shadd_rtx_p (rtx x
)
1007 return ((GET_CODE (x
) == ASHIFT
1008 || GET_CODE (x
) == MULT
)
1009 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1010 && ((GET_CODE (x
) == ASHIFT
1011 && pa_shadd_constant_p (INTVAL (XEXP (x
, 1))))
1012 || (GET_CODE (x
) == MULT
1013 && pa_mem_shadd_constant_p (INTVAL (XEXP (x
, 1))))));
1016 /* Try machine-dependent ways of modifying an illegitimate address
1017 to be legitimate. If we find one, return the new, valid address.
1018 This macro is used in only one place: `memory_address' in explow.c.
1020 OLDX is the address as it was before break_out_memory_refs was called.
1021 In some cases it is useful to look at this to decide what needs to be done.
1023 It is always safe for this macro to do nothing. It exists to recognize
1024 opportunities to optimize the output.
1026 For the PA, transform:
1028 memory(X + <large int>)
1032 if (<large int> & mask) >= 16
1033 Y = (<large int> & ~mask) + mask + 1 Round up.
1035 Y = (<large int> & ~mask) Round down.
1037 memory (Z + (<large int> - Y));
1039 This is for CSE to find several similar references, and only use one Z.
1041 X can either be a SYMBOL_REF or REG, but because combine cannot
1042 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1043 D will not fit in 14 bits.
1045 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1048 MODE_INT references allow displacements which fit in 14 bits, so use
1051 This relies on the fact that most mode MODE_FLOAT references will use FP
1052 registers and most mode MODE_INT references will use integer registers.
1053 (In the rare case of an FP register used in an integer MODE, we depend
1054 on secondary reloads to clean things up.)
1057 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1058 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1059 addressing modes to be used).
1061 Note that the addresses passed into hppa_legitimize_address always
1062 come from a MEM, so we only have to match the MULT form on incoming
1063 addresses. But to be future proof we also match the ASHIFT form.
1065 However, this routine always places those shift-add sequences into
1066 registers, so we have to generate the ASHIFT form as our output.
1068 Put X and Z into registers. Then put the entire expression into
1072 hppa_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1077 /* We need to canonicalize the order of operands in unscaled indexed
1078 addresses since the code that checks if an address is valid doesn't
1079 always try both orders. */
1080 if (!TARGET_NO_SPACE_REGS
1081 && GET_CODE (x
) == PLUS
1082 && GET_MODE (x
) == Pmode
1083 && REG_P (XEXP (x
, 0))
1084 && REG_P (XEXP (x
, 1))
1085 && REG_POINTER (XEXP (x
, 0))
1086 && !REG_POINTER (XEXP (x
, 1)))
1087 return gen_rtx_PLUS (Pmode
, XEXP (x
, 1), XEXP (x
, 0));
1089 if (tls_referenced_p (x
))
1090 return legitimize_tls_address (x
);
1092 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
1094 /* Strip off CONST. */
1095 if (GET_CODE (x
) == CONST
)
1098 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1099 That should always be safe. */
1100 if (GET_CODE (x
) == PLUS
1101 && GET_CODE (XEXP (x
, 0)) == REG
1102 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
1104 rtx reg
= force_reg (Pmode
, XEXP (x
, 1));
1105 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg
, XEXP (x
, 0)));
1108 /* Note we must reject symbols which represent function addresses
1109 since the assembler/linker can't handle arithmetic on plabels. */
1110 if (GET_CODE (x
) == PLUS
1111 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1112 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1113 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
1114 || GET_CODE (XEXP (x
, 0)) == REG
))
1116 rtx int_part
, ptr_reg
;
1118 int offset
= INTVAL (XEXP (x
, 1));
1121 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
1122 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
1124 /* Choose which way to round the offset. Round up if we
1125 are >= halfway to the next boundary. */
1126 if ((offset
& mask
) >= ((mask
+ 1) / 2))
1127 newoffset
= (offset
& ~ mask
) + mask
+ 1;
1129 newoffset
= (offset
& ~ mask
);
1131 /* If the newoffset will not fit in 14 bits (ldo), then
1132 handling this would take 4 or 5 instructions (2 to load
1133 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1134 add the new offset and the SYMBOL_REF.) Combine cannot
1135 handle 4->2 or 5->2 combinations, so do not create
1137 if (! VAL_14_BITS_P (newoffset
)
1138 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
1140 rtx const_part
= plus_constant (Pmode
, XEXP (x
, 0), newoffset
);
1143 gen_rtx_HIGH (Pmode
, const_part
));
1146 gen_rtx_LO_SUM (Pmode
,
1147 tmp_reg
, const_part
));
1151 if (! VAL_14_BITS_P (newoffset
))
1152 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
1154 int_part
= GEN_INT (newoffset
);
1156 ptr_reg
= force_reg (Pmode
,
1157 gen_rtx_PLUS (Pmode
,
1158 force_reg (Pmode
, XEXP (x
, 0)),
1161 return plus_constant (Pmode
, ptr_reg
, offset
- newoffset
);
1164 /* Handle (plus (mult (a) (mem_shadd_constant)) (b)). */
1166 if (GET_CODE (x
) == PLUS
1167 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1168 && (OBJECT_P (XEXP (x
, 1))
1169 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1170 && GET_CODE (XEXP (x
, 1)) != CONST
)
1172 /* If we were given a MULT, we must fix the constant
1173 as we're going to create the ASHIFT form. */
1174 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1175 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1176 shift_val
= exact_log2 (shift_val
);
1180 if (GET_CODE (reg1
) != REG
)
1181 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1183 reg2
= XEXP (XEXP (x
, 0), 0);
1184 if (GET_CODE (reg2
) != REG
)
1185 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1187 return force_reg (Pmode
,
1188 gen_rtx_PLUS (Pmode
,
1189 gen_rtx_ASHIFT (Pmode
, reg2
,
1190 GEN_INT (shift_val
)),
1194 /* Similarly for (plus (plus (mult (a) (mem_shadd_constant)) (b)) (c)).
1196 Only do so for floating point modes since this is more speculative
1197 and we lose if it's an integer store. */
1198 if (GET_CODE (x
) == PLUS
1199 && GET_CODE (XEXP (x
, 0)) == PLUS
1200 && mem_shadd_or_shadd_rtx_p (XEXP (XEXP (x
, 0), 0))
1201 && (mode
== SFmode
|| mode
== DFmode
))
1203 int shift_val
= INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1));
1205 /* If we were given a MULT, we must fix the constant
1206 as we're going to create the ASHIFT form. */
1207 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
1208 shift_val
= exact_log2 (shift_val
);
1210 /* Try and figure out what to use as a base register. */
1211 rtx reg1
, reg2
, base
, idx
;
1213 reg1
= XEXP (XEXP (x
, 0), 1);
1218 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1219 then pa_emit_move_sequence will turn on REG_POINTER so we'll know
1220 it's a base register below. */
1221 if (GET_CODE (reg1
) != REG
)
1222 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1224 if (GET_CODE (reg2
) != REG
)
1225 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1227 /* Figure out what the base and index are. */
1229 if (GET_CODE (reg1
) == REG
1230 && REG_POINTER (reg1
))
1233 idx
= gen_rtx_PLUS (Pmode
,
1234 gen_rtx_ASHIFT (Pmode
,
1235 XEXP (XEXP (XEXP (x
, 0), 0), 0),
1236 GEN_INT (shift_val
)),
1239 else if (GET_CODE (reg2
) == REG
1240 && REG_POINTER (reg2
))
1249 /* If the index adds a large constant, try to scale the
1250 constant so that it can be loaded with only one insn. */
1251 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1252 && VAL_14_BITS_P (INTVAL (XEXP (idx
, 1))
1253 / INTVAL (XEXP (XEXP (idx
, 0), 1)))
1254 && INTVAL (XEXP (idx
, 1)) % INTVAL (XEXP (XEXP (idx
, 0), 1)) == 0)
1256 /* Divide the CONST_INT by the scale factor, then add it to A. */
1257 int val
= INTVAL (XEXP (idx
, 1));
1258 val
/= (1 << shift_val
);
1260 reg1
= XEXP (XEXP (idx
, 0), 0);
1261 if (GET_CODE (reg1
) != REG
)
1262 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1264 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, reg1
, GEN_INT (val
)));
1266 /* We can now generate a simple scaled indexed address. */
1269 (Pmode
, gen_rtx_PLUS (Pmode
,
1270 gen_rtx_ASHIFT (Pmode
, reg1
,
1271 GEN_INT (shift_val
)),
1275 /* If B + C is still a valid base register, then add them. */
1276 if (GET_CODE (XEXP (idx
, 1)) == CONST_INT
1277 && INTVAL (XEXP (idx
, 1)) <= 4096
1278 && INTVAL (XEXP (idx
, 1)) >= -4096)
1282 reg1
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, XEXP (idx
, 1)));
1284 reg2
= XEXP (XEXP (idx
, 0), 0);
1285 if (GET_CODE (reg2
) != CONST_INT
)
1286 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1288 return force_reg (Pmode
,
1289 gen_rtx_PLUS (Pmode
,
1290 gen_rtx_ASHIFT (Pmode
, reg2
,
1291 GEN_INT (shift_val
)),
1295 /* Get the index into a register, then add the base + index and
1296 return a register holding the result. */
1298 /* First get A into a register. */
1299 reg1
= XEXP (XEXP (idx
, 0), 0);
1300 if (GET_CODE (reg1
) != REG
)
1301 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1303 /* And get B into a register. */
1304 reg2
= XEXP (idx
, 1);
1305 if (GET_CODE (reg2
) != REG
)
1306 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1308 reg1
= force_reg (Pmode
,
1309 gen_rtx_PLUS (Pmode
,
1310 gen_rtx_ASHIFT (Pmode
, reg1
,
1311 GEN_INT (shift_val
)),
1314 /* Add the result to our base register and return. */
1315 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, base
, reg1
));
1319 /* Uh-oh. We might have an address for x[n-100000]. This needs
1320 special handling to avoid creating an indexed memory address
1321 with x-100000 as the base.
1323 If the constant part is small enough, then it's still safe because
1324 there is a guard page at the beginning and end of the data segment.
1326 Scaled references are common enough that we want to try and rearrange the
1327 terms so that we can use indexing for these addresses too. Only
1328 do the optimization for floatint point modes. */
1330 if (GET_CODE (x
) == PLUS
1331 && pa_symbolic_expression_p (XEXP (x
, 1)))
1333 /* Ugly. We modify things here so that the address offset specified
1334 by the index expression is computed first, then added to x to form
1335 the entire address. */
1337 rtx regx1
, regx2
, regy1
, regy2
, y
;
1339 /* Strip off any CONST. */
1341 if (GET_CODE (y
) == CONST
)
1344 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1346 /* See if this looks like
1347 (plus (mult (reg) (mem_shadd_const))
1348 (const (plus (symbol_ref) (const_int))))
1350 Where const_int is small. In that case the const
1351 expression is a valid pointer for indexing.
1353 If const_int is big, but can be divided evenly by shadd_const
1354 and added to (reg). This allows more scaled indexed addresses. */
1355 if (GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1356 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1357 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1358 && INTVAL (XEXP (y
, 1)) >= -4096
1359 && INTVAL (XEXP (y
, 1)) <= 4095)
1361 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1363 /* If we were given a MULT, we must fix the constant
1364 as we're going to create the ASHIFT form. */
1365 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1366 shift_val
= exact_log2 (shift_val
);
1371 if (GET_CODE (reg1
) != REG
)
1372 reg1
= force_reg (Pmode
, force_operand (reg1
, 0));
1374 reg2
= XEXP (XEXP (x
, 0), 0);
1375 if (GET_CODE (reg2
) != REG
)
1376 reg2
= force_reg (Pmode
, force_operand (reg2
, 0));
1380 gen_rtx_PLUS (Pmode
,
1381 gen_rtx_ASHIFT (Pmode
,
1383 GEN_INT (shift_val
)),
1386 else if ((mode
== DFmode
|| mode
== SFmode
)
1387 && GET_CODE (XEXP (y
, 0)) == SYMBOL_REF
1388 && mem_shadd_or_shadd_rtx_p (XEXP (x
, 0))
1389 && GET_CODE (XEXP (y
, 1)) == CONST_INT
1390 && INTVAL (XEXP (y
, 1)) % (1 << INTVAL (XEXP (XEXP (x
, 0), 1))) == 0)
1392 int shift_val
= INTVAL (XEXP (XEXP (x
, 0), 1));
1394 /* If we were given a MULT, we must fix the constant
1395 as we're going to create the ASHIFT form. */
1396 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1397 shift_val
= exact_log2 (shift_val
);
1400 = force_reg (Pmode
, GEN_INT (INTVAL (XEXP (y
, 1))
1401 / INTVAL (XEXP (XEXP (x
, 0), 1))));
1402 regx2
= XEXP (XEXP (x
, 0), 0);
1403 if (GET_CODE (regx2
) != REG
)
1404 regx2
= force_reg (Pmode
, force_operand (regx2
, 0));
1405 regx2
= force_reg (Pmode
, gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1409 gen_rtx_PLUS (Pmode
,
1410 gen_rtx_ASHIFT (Pmode
, regx2
,
1411 GEN_INT (shift_val
)),
1412 force_reg (Pmode
, XEXP (y
, 0))));
1414 else if (GET_CODE (XEXP (y
, 1)) == CONST_INT
1415 && INTVAL (XEXP (y
, 1)) >= -4096
1416 && INTVAL (XEXP (y
, 1)) <= 4095)
1418 /* This is safe because of the guard page at the
1419 beginning and end of the data space. Just
1420 return the original address. */
1425 /* Doesn't look like one we can optimize. */
1426 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1427 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1428 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1429 regx1
= force_reg (Pmode
,
1430 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
,
1432 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1440 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1442 Compute extra cost of moving data between one register class
1445 Make moves from SAR so expensive they should never happen. We used to
1446 have 0xffff here, but that generates overflow in rare cases.
1448 Copies involving a FP register and a non-FP register are relatively
1449 expensive because they must go through memory.
1451 Other copies are reasonably cheap. */
1454 hppa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1455 reg_class_t from
, reg_class_t to
)
1457 if (from
== SHIFT_REGS
)
1459 else if (to
== SHIFT_REGS
&& FP_REG_CLASS_P (from
))
1461 else if ((FP_REG_CLASS_P (from
) && ! FP_REG_CLASS_P (to
))
1462 || (FP_REG_CLASS_P (to
) && ! FP_REG_CLASS_P (from
)))
1468 /* For the HPPA, REG and REG+CONST is cost 0
1469 and addresses involving symbolic constants are cost 2.
1471 PIC addresses are very expensive.
1473 It is no coincidence that this has the same structure
1474 as pa_legitimate_address_p. */
1477 hppa_address_cost (rtx X
, machine_mode mode ATTRIBUTE_UNUSED
,
1478 addr_space_t as ATTRIBUTE_UNUSED
,
1479 bool speed ATTRIBUTE_UNUSED
)
1481 switch (GET_CODE (X
))
1494 /* Compute a (partial) cost for rtx X. Return true if the complete
1495 cost has been computed, and false if subexpressions should be
1496 scanned. In either case, *TOTAL contains the cost result. */
1499 hppa_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
1500 int opno ATTRIBUTE_UNUSED
,
1501 int *total
, bool speed ATTRIBUTE_UNUSED
)
1504 int code
= GET_CODE (x
);
1509 if (INTVAL (x
) == 0)
1511 else if (INT_14_BITS (x
))
1528 if ((x
== CONST0_RTX (DFmode
) || x
== CONST0_RTX (SFmode
))
1529 && outer_code
!= SET
)
1536 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1538 *total
= COSTS_N_INSNS (3);
1542 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1543 factor
= GET_MODE_SIZE (mode
) / 4;
1547 if (TARGET_PA_11
&& !TARGET_DISABLE_FPREGS
&& !TARGET_SOFT_FLOAT
)
1548 *total
= factor
* factor
* COSTS_N_INSNS (8);
1550 *total
= factor
* factor
* COSTS_N_INSNS (20);
1554 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1556 *total
= COSTS_N_INSNS (14);
1564 /* A mode size N times larger than SImode needs O(N*N) more insns. */
1565 factor
= GET_MODE_SIZE (mode
) / 4;
1569 *total
= factor
* factor
* COSTS_N_INSNS (60);
1572 case PLUS
: /* this includes shNadd insns */
1574 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1576 *total
= COSTS_N_INSNS (3);
1580 /* A size N times larger than UNITS_PER_WORD needs N times as
1581 many insns, taking N times as long. */
1582 factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
1585 *total
= factor
* COSTS_N_INSNS (1);
1591 *total
= COSTS_N_INSNS (1);
1599 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1600 new rtx with the correct mode. */
1602 force_mode (machine_mode mode
, rtx orig
)
1604 if (mode
== GET_MODE (orig
))
1607 gcc_assert (REGNO (orig
) < FIRST_PSEUDO_REGISTER
);
1609 return gen_rtx_REG (mode
, REGNO (orig
));
1612 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1615 pa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1617 return tls_referenced_p (x
);
1620 /* Emit insns to move operands[1] into operands[0].
1622 Return 1 if we have written out everything that needs to be done to
1623 do the move. Otherwise, return 0 and the caller will emit the move
1626 Note SCRATCH_REG may not be in the proper mode depending on how it
1627 will be used. This routine is responsible for creating a new copy
1628 of SCRATCH_REG in the proper mode. */
1631 pa_emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
1633 register rtx operand0
= operands
[0];
1634 register rtx operand1
= operands
[1];
1637 /* We can only handle indexed addresses in the destination operand
1638 of floating point stores. Thus, we need to break out indexed
1639 addresses from the destination operand. */
1640 if (GET_CODE (operand0
) == MEM
&& IS_INDEX_ADDR_P (XEXP (operand0
, 0)))
1642 gcc_assert (can_create_pseudo_p ());
1644 tem
= copy_to_mode_reg (Pmode
, XEXP (operand0
, 0));
1645 operand0
= replace_equiv_address (operand0
, tem
);
1648 /* On targets with non-equivalent space registers, break out unscaled
1649 indexed addresses from the source operand before the final CSE.
1650 We have to do this because the REG_POINTER flag is not correctly
1651 carried through various optimization passes and CSE may substitute
1652 a pseudo without the pointer set for one with the pointer set. As
1653 a result, we loose various opportunities to create insns with
1654 unscaled indexed addresses. */
1655 if (!TARGET_NO_SPACE_REGS
1656 && !cse_not_expected
1657 && GET_CODE (operand1
) == MEM
1658 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1659 && REG_P (XEXP (XEXP (operand1
, 0), 0))
1660 && REG_P (XEXP (XEXP (operand1
, 0), 1)))
1662 = replace_equiv_address (operand1
,
1663 copy_to_mode_reg (Pmode
, XEXP (operand1
, 0)));
1666 && reload_in_progress
&& GET_CODE (operand0
) == REG
1667 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1668 operand0
= reg_equiv_mem (REGNO (operand0
));
1669 else if (scratch_reg
1670 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
1671 && GET_CODE (SUBREG_REG (operand0
)) == REG
1672 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
1674 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1675 the code which tracks sets/uses for delete_output_reload. */
1676 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
1677 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
1678 SUBREG_BYTE (operand0
));
1679 operand0
= alter_subreg (&temp
, true);
1683 && reload_in_progress
&& GET_CODE (operand1
) == REG
1684 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
1685 operand1
= reg_equiv_mem (REGNO (operand1
));
1686 else if (scratch_reg
1687 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
1688 && GET_CODE (SUBREG_REG (operand1
)) == REG
1689 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
1691 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1692 the code which tracks sets/uses for delete_output_reload. */
1693 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
1694 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
1695 SUBREG_BYTE (operand1
));
1696 operand1
= alter_subreg (&temp
, true);
1699 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
1700 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
1701 != XEXP (operand0
, 0)))
1702 operand0
= replace_equiv_address (operand0
, tem
);
1704 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
1705 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
1706 != XEXP (operand1
, 0)))
1707 operand1
= replace_equiv_address (operand1
, tem
);
1709 /* Handle secondary reloads for loads/stores of FP registers from
1710 REG+D addresses where D does not fit in 5 or 14 bits, including
1711 (subreg (mem (addr))) cases, and reloads for other unsupported
1714 && FP_REG_P (operand0
)
1715 && (MEM_P (operand1
)
1716 || (GET_CODE (operand1
) == SUBREG
1717 && MEM_P (XEXP (operand1
, 0)))))
1721 if (GET_CODE (op1
) == SUBREG
)
1722 op1
= XEXP (op1
, 0);
1724 if (reg_plus_base_memory_operand (op1
, GET_MODE (op1
)))
1728 && INT_14_BITS (XEXP (XEXP (op1
, 0), 1)))
1729 && !INT_5_BITS (XEXP (XEXP (op1
, 0), 1)))
1731 /* SCRATCH_REG will hold an address and maybe the actual data.
1732 We want it in WORD_MODE regardless of what mode it was
1733 originally given to us. */
1734 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1736 /* D might not fit in 14 bits either; for such cases load D
1737 into scratch reg. */
1738 if (!INT_14_BITS (XEXP (XEXP (op1
, 0), 1)))
1740 emit_move_insn (scratch_reg
, XEXP (XEXP (op1
, 0), 1));
1741 emit_move_insn (scratch_reg
,
1742 gen_rtx_fmt_ee (GET_CODE (XEXP (op1
, 0)),
1744 XEXP (XEXP (op1
, 0), 0),
1748 emit_move_insn (scratch_reg
, XEXP (op1
, 0));
1749 op1
= replace_equiv_address (op1
, scratch_reg
);
1752 else if ((!INT14_OK_STRICT
&& symbolic_memory_operand (op1
, VOIDmode
))
1753 || IS_LO_SUM_DLT_ADDR_P (XEXP (op1
, 0))
1754 || IS_INDEX_ADDR_P (XEXP (op1
, 0)))
1756 /* Load memory address into SCRATCH_REG. */
1757 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1758 emit_move_insn (scratch_reg
, XEXP (op1
, 0));
1759 op1
= replace_equiv_address (op1
, scratch_reg
);
1761 emit_insn (gen_rtx_SET (operand0
, op1
));
1764 else if (scratch_reg
1765 && FP_REG_P (operand1
)
1766 && (MEM_P (operand0
)
1767 || (GET_CODE (operand0
) == SUBREG
1768 && MEM_P (XEXP (operand0
, 0)))))
1772 if (GET_CODE (op0
) == SUBREG
)
1773 op0
= XEXP (op0
, 0);
1775 if (reg_plus_base_memory_operand (op0
, GET_MODE (op0
)))
1779 && INT_14_BITS (XEXP (XEXP (op0
, 0), 1)))
1780 && !INT_5_BITS (XEXP (XEXP (op0
, 0), 1)))
1782 /* SCRATCH_REG will hold an address and maybe the actual data.
1783 We want it in WORD_MODE regardless of what mode it was
1784 originally given to us. */
1785 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1787 /* D might not fit in 14 bits either; for such cases load D
1788 into scratch reg. */
1789 if (!INT_14_BITS (XEXP (XEXP (op0
, 0), 1)))
1791 emit_move_insn (scratch_reg
, XEXP (XEXP (op0
, 0), 1));
1792 emit_move_insn (scratch_reg
,
1793 gen_rtx_fmt_ee (GET_CODE (XEXP (op0
, 0)),
1795 XEXP (XEXP (op0
, 0), 0),
1799 emit_move_insn (scratch_reg
, XEXP (op0
, 0));
1800 op0
= replace_equiv_address (op0
, scratch_reg
);
1803 else if ((!INT14_OK_STRICT
&& symbolic_memory_operand (op0
, VOIDmode
))
1804 || IS_LO_SUM_DLT_ADDR_P (XEXP (op0
, 0))
1805 || IS_INDEX_ADDR_P (XEXP (op0
, 0)))
1807 /* Load memory address into SCRATCH_REG. */
1808 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1809 emit_move_insn (scratch_reg
, XEXP (op0
, 0));
1810 op0
= replace_equiv_address (op0
, scratch_reg
);
1812 emit_insn (gen_rtx_SET (op0
, operand1
));
1815 /* Handle secondary reloads for loads of FP registers from constant
1816 expressions by forcing the constant into memory. For the most part,
1817 this is only necessary for SImode and DImode.
1819 Use scratch_reg to hold the address of the memory location. */
1820 else if (scratch_reg
1821 && CONSTANT_P (operand1
)
1822 && FP_REG_P (operand0
))
1824 rtx const_mem
, xoperands
[2];
1826 if (operand1
== CONST0_RTX (mode
))
1828 emit_insn (gen_rtx_SET (operand0
, operand1
));
1832 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1833 it in WORD_MODE regardless of what mode it was originally given
1835 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1837 /* Force the constant into memory and put the address of the
1838 memory location into scratch_reg. */
1839 const_mem
= force_const_mem (mode
, operand1
);
1840 xoperands
[0] = scratch_reg
;
1841 xoperands
[1] = XEXP (const_mem
, 0);
1842 pa_emit_move_sequence (xoperands
, Pmode
, 0);
1844 /* Now load the destination register. */
1845 emit_insn (gen_rtx_SET (operand0
,
1846 replace_equiv_address (const_mem
, scratch_reg
)));
1849 /* Handle secondary reloads for SAR. These occur when trying to load
1850 the SAR from memory or a constant. */
1851 else if (scratch_reg
1852 && GET_CODE (operand0
) == REG
1853 && REGNO (operand0
) < FIRST_PSEUDO_REGISTER
1854 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
1855 && (GET_CODE (operand1
) == MEM
|| GET_CODE (operand1
) == CONST_INT
))
1857 /* D might not fit in 14 bits either; for such cases load D into
1859 if (GET_CODE (operand1
) == MEM
1860 && !memory_address_p (GET_MODE (operand0
), XEXP (operand1
, 0)))
1862 /* We are reloading the address into the scratch register, so we
1863 want to make sure the scratch register is a full register. */
1864 scratch_reg
= force_mode (word_mode
, scratch_reg
);
1866 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
1867 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
,
1870 XEXP (XEXP (operand1
, 0),
1874 /* Now we are going to load the scratch register from memory,
1875 we want to load it in the same width as the original MEM,
1876 which must be the same as the width of the ultimate destination,
1878 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1880 emit_move_insn (scratch_reg
,
1881 replace_equiv_address (operand1
, scratch_reg
));
1885 /* We want to load the scratch register using the same mode as
1886 the ultimate destination. */
1887 scratch_reg
= force_mode (GET_MODE (operand0
), scratch_reg
);
1889 emit_move_insn (scratch_reg
, operand1
);
1892 /* And emit the insn to set the ultimate destination. We know that
1893 the scratch register has the same mode as the destination at this
1895 emit_move_insn (operand0
, scratch_reg
);
1899 /* Handle the most common case: storing into a register. */
1900 if (register_operand (operand0
, mode
))
1902 /* Legitimize TLS symbol references. This happens for references
1903 that aren't a legitimate constant. */
1904 if (PA_SYMBOL_REF_TLS_P (operand1
))
1905 operand1
= legitimize_tls_address (operand1
);
1907 if (register_operand (operand1
, mode
)
1908 || (GET_CODE (operand1
) == CONST_INT
1909 && pa_cint_ok_for_move (UINTVAL (operand1
)))
1910 || (operand1
== CONST0_RTX (mode
))
1911 || (GET_CODE (operand1
) == HIGH
1912 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
1913 /* Only `general_operands' can come here, so MEM is ok. */
1914 || GET_CODE (operand1
) == MEM
)
1916 /* Various sets are created during RTL generation which don't
1917 have the REG_POINTER flag correctly set. After the CSE pass,
1918 instruction recognition can fail if we don't consistently
1919 set this flag when performing register copies. This should
1920 also improve the opportunities for creating insns that use
1921 unscaled indexing. */
1922 if (REG_P (operand0
) && REG_P (operand1
))
1924 if (REG_POINTER (operand1
)
1925 && !REG_POINTER (operand0
)
1926 && !HARD_REGISTER_P (operand0
))
1927 copy_reg_pointer (operand0
, operand1
);
1930 /* When MEMs are broken out, the REG_POINTER flag doesn't
1931 get set. In some cases, we can set the REG_POINTER flag
1932 from the declaration for the MEM. */
1933 if (REG_P (operand0
)
1934 && GET_CODE (operand1
) == MEM
1935 && !REG_POINTER (operand0
))
1937 tree decl
= MEM_EXPR (operand1
);
1939 /* Set the register pointer flag and register alignment
1940 if the declaration for this memory reference is a
1946 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1948 if (TREE_CODE (decl
) == COMPONENT_REF
)
1949 decl
= TREE_OPERAND (decl
, 1);
1951 type
= TREE_TYPE (decl
);
1952 type
= strip_array_types (type
);
1954 if (POINTER_TYPE_P (type
))
1955 mark_reg_pointer (operand0
, BITS_PER_UNIT
);
1959 emit_insn (gen_rtx_SET (operand0
, operand1
));
1963 else if (GET_CODE (operand0
) == MEM
)
1965 if (mode
== DFmode
&& operand1
== CONST0_RTX (mode
)
1966 && !(reload_in_progress
|| reload_completed
))
1968 rtx temp
= gen_reg_rtx (DFmode
);
1970 emit_insn (gen_rtx_SET (temp
, operand1
));
1971 emit_insn (gen_rtx_SET (operand0
, temp
));
1974 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
1976 /* Run this case quickly. */
1977 emit_insn (gen_rtx_SET (operand0
, operand1
));
1980 if (! (reload_in_progress
|| reload_completed
))
1982 operands
[0] = validize_mem (operand0
);
1983 operands
[1] = operand1
= force_reg (mode
, operand1
);
1987 /* Simplify the source if we need to.
1988 Note we do have to handle function labels here, even though we do
1989 not consider them legitimate constants. Loop optimizations can
1990 call the emit_move_xxx with one as a source. */
1991 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1992 || (GET_CODE (operand1
) == HIGH
1993 && symbolic_operand (XEXP (operand1
, 0), mode
))
1994 || function_label_operand (operand1
, VOIDmode
)
1995 || tls_referenced_p (operand1
))
1999 if (GET_CODE (operand1
) == HIGH
)
2002 operand1
= XEXP (operand1
, 0);
2004 if (symbolic_operand (operand1
, mode
))
2006 /* Argh. The assembler and linker can't handle arithmetic
2009 So we force the plabel into memory, load operand0 from
2010 the memory location, then add in the constant part. */
2011 if ((GET_CODE (operand1
) == CONST
2012 && GET_CODE (XEXP (operand1
, 0)) == PLUS
2013 && function_label_operand (XEXP (XEXP (operand1
, 0), 0),
2015 || function_label_operand (operand1
, VOIDmode
))
2017 rtx temp
, const_part
;
2019 /* Figure out what (if any) scratch register to use. */
2020 if (reload_in_progress
|| reload_completed
)
2022 scratch_reg
= scratch_reg
? scratch_reg
: operand0
;
2023 /* SCRATCH_REG will hold an address and maybe the actual
2024 data. We want it in WORD_MODE regardless of what mode it
2025 was originally given to us. */
2026 scratch_reg
= force_mode (word_mode
, scratch_reg
);
2029 scratch_reg
= gen_reg_rtx (Pmode
);
2031 if (GET_CODE (operand1
) == CONST
)
2033 /* Save away the constant part of the expression. */
2034 const_part
= XEXP (XEXP (operand1
, 0), 1);
2035 gcc_assert (GET_CODE (const_part
) == CONST_INT
);
2037 /* Force the function label into memory. */
2038 temp
= force_const_mem (mode
, XEXP (XEXP (operand1
, 0), 0));
2042 /* No constant part. */
2043 const_part
= NULL_RTX
;
2045 /* Force the function label into memory. */
2046 temp
= force_const_mem (mode
, operand1
);
2050 /* Get the address of the memory location. PIC-ify it if
2052 temp
= XEXP (temp
, 0);
2054 temp
= legitimize_pic_address (temp
, mode
, scratch_reg
);
2056 /* Put the address of the memory location into our destination
2059 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
2061 /* Now load from the memory location into our destination
2063 operands
[1] = gen_rtx_MEM (Pmode
, operands
[0]);
2064 pa_emit_move_sequence (operands
, mode
, scratch_reg
);
2066 /* And add back in the constant part. */
2067 if (const_part
!= NULL_RTX
)
2068 expand_inc (operand0
, const_part
);
2078 if (reload_in_progress
|| reload_completed
)
2080 temp
= scratch_reg
? scratch_reg
: operand0
;
2081 /* TEMP will hold an address and maybe the actual
2082 data. We want it in WORD_MODE regardless of what mode it
2083 was originally given to us. */
2084 temp
= force_mode (word_mode
, temp
);
2087 temp
= gen_reg_rtx (Pmode
);
2089 /* Force (const (plus (symbol) (const_int))) to memory
2090 if the const_int will not fit in 14 bits. Although
2091 this requires a relocation, the instruction sequence
2092 needed to load the value is shorter. */
2093 if (GET_CODE (operand1
) == CONST
2094 && GET_CODE (XEXP (operand1
, 0)) == PLUS
2095 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
2096 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1)))
2098 rtx x
, m
= force_const_mem (mode
, operand1
);
2100 x
= legitimize_pic_address (XEXP (m
, 0), mode
, temp
);
2101 x
= replace_equiv_address (m
, x
);
2102 insn
= emit_move_insn (operand0
, x
);
2106 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
2107 if (REG_P (operand0
) && REG_P (operands
[1]))
2108 copy_reg_pointer (operand0
, operands
[1]);
2109 insn
= emit_move_insn (operand0
, operands
[1]);
2112 /* Put a REG_EQUAL note on this insn. */
2113 set_unique_reg_note (insn
, REG_EQUAL
, operand1
);
2115 /* On the HPPA, references to data space are supposed to use dp,
2116 register 27, but showing it in the RTL inhibits various cse
2117 and loop optimizations. */
2122 if (reload_in_progress
|| reload_completed
)
2124 temp
= scratch_reg
? scratch_reg
: operand0
;
2125 /* TEMP will hold an address and maybe the actual
2126 data. We want it in WORD_MODE regardless of what mode it
2127 was originally given to us. */
2128 temp
= force_mode (word_mode
, temp
);
2131 temp
= gen_reg_rtx (mode
);
2133 /* Loading a SYMBOL_REF into a register makes that register
2134 safe to be used as the base in an indexed address.
2136 Don't mark hard registers though. That loses. */
2137 if (GET_CODE (operand0
) == REG
2138 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2139 mark_reg_pointer (operand0
, BITS_PER_UNIT
);
2140 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
2141 mark_reg_pointer (temp
, BITS_PER_UNIT
);
2144 set
= gen_rtx_SET (operand0
, temp
);
2146 set
= gen_rtx_SET (operand0
,
2147 gen_rtx_LO_SUM (mode
, temp
, operand1
));
2149 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, operand1
)));
2155 else if (tls_referenced_p (operand1
))
2160 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
2162 addend
= XEXP (XEXP (tmp
, 0), 1);
2163 tmp
= XEXP (XEXP (tmp
, 0), 0);
2166 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
2167 tmp
= legitimize_tls_address (tmp
);
2170 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
2171 tmp
= force_operand (tmp
, operands
[0]);
2175 else if (GET_CODE (operand1
) != CONST_INT
2176 || !pa_cint_ok_for_move (UINTVAL (operand1
)))
2181 HOST_WIDE_INT value
= 0;
2182 HOST_WIDE_INT insv
= 0;
2185 if (GET_CODE (operand1
) == CONST_INT
)
2186 value
= INTVAL (operand1
);
2189 && GET_CODE (operand1
) == CONST_INT
2190 && HOST_BITS_PER_WIDE_INT
> 32
2191 && GET_MODE_BITSIZE (GET_MODE (operand0
)) > 32)
2195 /* Extract the low order 32 bits of the value and sign extend.
2196 If the new value is the same as the original value, we can
2197 can use the original value as-is. If the new value is
2198 different, we use it and insert the most-significant 32-bits
2199 of the original value into the final result. */
2200 nval
= ((value
& (((HOST_WIDE_INT
) 2 << 31) - 1))
2201 ^ ((HOST_WIDE_INT
) 1 << 31)) - ((HOST_WIDE_INT
) 1 << 31);
2204 #if HOST_BITS_PER_WIDE_INT > 32
2205 insv
= value
>= 0 ? value
>> 32 : ~(~value
>> 32);
2209 operand1
= GEN_INT (nval
);
2213 if (reload_in_progress
|| reload_completed
)
2214 temp
= scratch_reg
? scratch_reg
: operand0
;
2216 temp
= gen_reg_rtx (mode
);
2218 /* We don't directly split DImode constants on 32-bit targets
2219 because PLUS uses an 11-bit immediate and the insn sequence
2220 generated is not as efficient as the one using HIGH/LO_SUM. */
2221 if (GET_CODE (operand1
) == CONST_INT
2222 && GET_MODE_BITSIZE (mode
) <= BITS_PER_WORD
2223 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
2226 /* Directly break constant into high and low parts. This
2227 provides better optimization opportunities because various
2228 passes recognize constants split with PLUS but not LO_SUM.
2229 We use a 14-bit signed low part except when the addition
2230 of 0x4000 to the high part might change the sign of the
2232 HOST_WIDE_INT low
= value
& 0x3fff;
2233 HOST_WIDE_INT high
= value
& ~ 0x3fff;
2237 if (high
== 0x7fffc000 || (mode
== HImode
&& high
== 0x4000))
2245 emit_insn (gen_rtx_SET (temp
, GEN_INT (high
)));
2246 operands
[1] = gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2250 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, operand1
)));
2251 operands
[1] = gen_rtx_LO_SUM (mode
, temp
, operand1
);
2254 insn
= emit_move_insn (operands
[0], operands
[1]);
2256 /* Now insert the most significant 32 bits of the value
2257 into the register. When we don't have a second register
2258 available, it could take up to nine instructions to load
2259 a 64-bit integer constant. Prior to reload, we force
2260 constants that would take more than three instructions
2261 to load to the constant pool. During and after reload,
2262 we have to handle all possible values. */
2265 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2266 register and the value to be inserted is outside the
2267 range that can be loaded with three depdi instructions. */
2268 if (temp
!= operand0
&& (insv
>= 16384 || insv
< -16384))
2270 operand1
= GEN_INT (insv
);
2272 emit_insn (gen_rtx_SET (temp
,
2273 gen_rtx_HIGH (mode
, operand1
)));
2274 emit_move_insn (temp
, gen_rtx_LO_SUM (mode
, temp
, operand1
));
2276 insn
= emit_insn (gen_insvdi (operand0
, GEN_INT (32),
2279 insn
= emit_insn (gen_insvsi (operand0
, GEN_INT (32),
2284 int len
= 5, pos
= 27;
2286 /* Insert the bits using the depdi instruction. */
2289 HOST_WIDE_INT v5
= ((insv
& 31) ^ 16) - 16;
2290 HOST_WIDE_INT sign
= v5
< 0;
2292 /* Left extend the insertion. */
2293 insv
= (insv
>= 0 ? insv
>> len
: ~(~insv
>> len
));
2294 while (pos
> 0 && (insv
& 1) == sign
)
2296 insv
= (insv
>= 0 ? insv
>> 1 : ~(~insv
>> 1));
2302 insn
= emit_insn (gen_insvdi (operand0
,
2307 insn
= emit_insn (gen_insvsi (operand0
,
2312 len
= pos
> 0 && pos
< 5 ? pos
: 5;
2318 set_unique_reg_note (insn
, REG_EQUAL
, op1
);
2323 /* Now have insn-emit do whatever it normally does. */
2327 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2328 it will need a link/runtime reloc). */
2331 pa_reloc_needed (tree exp
)
2335 switch (TREE_CODE (exp
))
2340 case POINTER_PLUS_EXPR
:
2343 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2344 reloc
|= pa_reloc_needed (TREE_OPERAND (exp
, 1));
2348 case NON_LVALUE_EXPR
:
2349 reloc
= pa_reloc_needed (TREE_OPERAND (exp
, 0));
2355 unsigned HOST_WIDE_INT ix
;
2357 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp
), ix
, value
)
2359 reloc
|= pa_reloc_needed (value
);
2373 /* Return the best assembler insn template
2374 for moving operands[1] into operands[0] as a fullword. */
2376 pa_singlemove_string (rtx
*operands
)
2378 HOST_WIDE_INT intval
;
2380 if (GET_CODE (operands
[0]) == MEM
)
2381 return "stw %r1,%0";
2382 if (GET_CODE (operands
[1]) == MEM
)
2384 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2388 gcc_assert (GET_MODE (operands
[1]) == SFmode
);
2390 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2392 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands
[1]), i
);
2394 operands
[1] = GEN_INT (i
);
2395 /* Fall through to CONST_INT case. */
2397 if (GET_CODE (operands
[1]) == CONST_INT
)
2399 intval
= INTVAL (operands
[1]);
2401 if (VAL_14_BITS_P (intval
))
2403 else if ((intval
& 0x7ff) == 0)
2404 return "ldil L'%1,%0";
2405 else if (pa_zdepi_cint_p (intval
))
2406 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2408 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2410 return "copy %1,%0";
2414 /* Compute position (in OP[1]) and width (in OP[2])
2415 useful for copying IMM to a register using the zdepi
2416 instructions. Store the immediate value to insert in OP[0]. */
2418 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2422 /* Find the least significant set bit in IMM. */
2423 for (lsb
= 0; lsb
< 32; lsb
++)
2430 /* Choose variants based on *sign* of the 5-bit field. */
2431 if ((imm
& 0x10) == 0)
2432 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
2435 /* Find the width of the bitstring in IMM. */
2436 for (len
= 5; len
< 32 - lsb
; len
++)
2438 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2442 /* Sign extend IMM as a 5-bit value. */
2443 imm
= (imm
& 0xf) - 0x10;
2451 /* Compute position (in OP[1]) and width (in OP[2])
2452 useful for copying IMM to a register using the depdi,z
2453 instructions. Store the immediate value to insert in OP[0]. */
2456 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm
, unsigned *op
)
2458 int lsb
, len
, maxlen
;
2460 maxlen
= MIN (HOST_BITS_PER_WIDE_INT
, 64);
2462 /* Find the least significant set bit in IMM. */
2463 for (lsb
= 0; lsb
< maxlen
; lsb
++)
2470 /* Choose variants based on *sign* of the 5-bit field. */
2471 if ((imm
& 0x10) == 0)
2472 len
= (lsb
<= maxlen
- 4) ? 4 : maxlen
- lsb
;
2475 /* Find the width of the bitstring in IMM. */
2476 for (len
= 5; len
< maxlen
- lsb
; len
++)
2478 if ((imm
& ((unsigned HOST_WIDE_INT
) 1 << len
)) == 0)
2482 /* Extend length if host is narrow and IMM is negative. */
2483 if (HOST_BITS_PER_WIDE_INT
== 32 && len
== maxlen
- lsb
)
2486 /* Sign extend IMM as a 5-bit value. */
2487 imm
= (imm
& 0xf) - 0x10;
2495 /* Output assembler code to perform a doubleword move insn
2496 with operands OPERANDS. */
2499 pa_output_move_double (rtx
*operands
)
2501 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
2503 rtx addreg0
= 0, addreg1
= 0;
2506 /* First classify both operands. */
2508 if (REG_P (operands
[0]))
2510 else if (offsettable_memref_p (operands
[0]))
2512 else if (GET_CODE (operands
[0]) == MEM
)
2517 if (REG_P (operands
[1]))
2519 else if (CONSTANT_P (operands
[1]))
2521 else if (offsettable_memref_p (operands
[1]))
2523 else if (GET_CODE (operands
[1]) == MEM
)
2528 /* Check for the cases that the operand constraints are not
2529 supposed to allow to happen. */
2530 gcc_assert (optype0
== REGOP
|| optype1
== REGOP
);
2532 /* Handle copies between general and floating registers. */
2534 if (optype0
== REGOP
&& optype1
== REGOP
2535 && FP_REG_P (operands
[0]) ^ FP_REG_P (operands
[1]))
2537 if (FP_REG_P (operands
[0]))
2539 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands
);
2540 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands
);
2541 return "{fldds|fldd} -16(%%sp),%0";
2545 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands
);
2546 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands
);
2547 return "{ldws|ldw} -12(%%sp),%R0";
2551 /* Handle auto decrementing and incrementing loads and stores
2552 specifically, since the structure of the function doesn't work
2553 for them without major modification. Do it better when we learn
2554 this port about the general inc/dec addressing of PA.
2555 (This was written by tege. Chide him if it doesn't work.) */
2557 if (optype0
== MEMOP
)
2559 /* We have to output the address syntax ourselves, since print_operand
2560 doesn't deal with the addresses we want to use. Fix this later. */
2562 rtx addr
= XEXP (operands
[0], 0);
2563 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2565 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2567 operands
[0] = XEXP (addr
, 0);
2568 gcc_assert (GET_CODE (operands
[1]) == REG
2569 && GET_CODE (operands
[0]) == REG
);
2571 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2573 /* No overlap between high target register and address
2574 register. (We do this in a non-obvious way to
2575 save a register file writeback) */
2576 if (GET_CODE (addr
) == POST_INC
)
2577 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2578 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2580 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2582 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[1], 0);
2584 operands
[0] = XEXP (addr
, 0);
2585 gcc_assert (GET_CODE (operands
[1]) == REG
2586 && GET_CODE (operands
[0]) == REG
);
2588 gcc_assert (!reg_overlap_mentioned_p (high_reg
, addr
));
2589 /* No overlap between high target register and address
2590 register. (We do this in a non-obvious way to save a
2591 register file writeback) */
2592 if (GET_CODE (addr
) == PRE_INC
)
2593 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2594 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2597 if (optype1
== MEMOP
)
2599 /* We have to output the address syntax ourselves, since print_operand
2600 doesn't deal with the addresses we want to use. Fix this later. */
2602 rtx addr
= XEXP (operands
[1], 0);
2603 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
2605 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2607 operands
[1] = XEXP (addr
, 0);
2608 gcc_assert (GET_CODE (operands
[0]) == REG
2609 && GET_CODE (operands
[1]) == REG
);
2611 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2613 /* No overlap between high target register and address
2614 register. (We do this in a non-obvious way to
2615 save a register file writeback) */
2616 if (GET_CODE (addr
) == POST_INC
)
2617 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2618 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2622 /* This is an undefined situation. We should load into the
2623 address register *and* update that register. Probably
2624 we don't need to handle this at all. */
2625 if (GET_CODE (addr
) == POST_INC
)
2626 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2627 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2630 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
2632 rtx high_reg
= gen_rtx_SUBREG (SImode
, operands
[0], 0);
2634 operands
[1] = XEXP (addr
, 0);
2635 gcc_assert (GET_CODE (operands
[0]) == REG
2636 && GET_CODE (operands
[1]) == REG
);
2638 if (!reg_overlap_mentioned_p (high_reg
, addr
))
2640 /* No overlap between high target register and address
2641 register. (We do this in a non-obvious way to
2642 save a register file writeback) */
2643 if (GET_CODE (addr
) == PRE_INC
)
2644 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2645 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2649 /* This is an undefined situation. We should load into the
2650 address register *and* update that register. Probably
2651 we don't need to handle this at all. */
2652 if (GET_CODE (addr
) == PRE_INC
)
2653 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2654 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2657 else if (GET_CODE (addr
) == PLUS
2658 && GET_CODE (XEXP (addr
, 0)) == MULT
)
2662 /* Load address into left half of destination register. */
2663 xoperands
[0] = gen_rtx_SUBREG (SImode
, operands
[0], 0);
2664 xoperands
[1] = XEXP (addr
, 1);
2665 xoperands
[2] = XEXP (XEXP (addr
, 0), 0);
2666 xoperands
[3] = XEXP (XEXP (addr
, 0), 1);
2667 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2669 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2671 else if (GET_CODE (addr
) == PLUS
2672 && REG_P (XEXP (addr
, 0))
2673 && REG_P (XEXP (addr
, 1)))
2677 /* Load address into left half of destination register. */
2678 xoperands
[0] = gen_rtx_SUBREG (SImode
, operands
[0], 0);
2679 xoperands
[1] = XEXP (addr
, 0);
2680 xoperands
[2] = XEXP (addr
, 1);
2681 output_asm_insn ("{addl|add,l} %1,%2,%0",
2683 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2687 /* If an operand is an unoffsettable memory ref, find a register
2688 we can increment temporarily to make it refer to the second word. */
2690 if (optype0
== MEMOP
)
2691 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2693 if (optype1
== MEMOP
)
2694 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2696 /* Ok, we can do one word at a time.
2697 Normally we do the low-numbered word first.
2699 In either case, set up in LATEHALF the operands to use
2700 for the high-numbered word and in some cases alter the
2701 operands in OPERANDS to be suitable for the low-numbered word. */
2703 if (optype0
== REGOP
)
2704 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2705 else if (optype0
== OFFSOP
)
2706 latehalf
[0] = adjust_address_nv (operands
[0], SImode
, 4);
2708 latehalf
[0] = operands
[0];
2710 if (optype1
== REGOP
)
2711 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2712 else if (optype1
== OFFSOP
)
2713 latehalf
[1] = adjust_address_nv (operands
[1], SImode
, 4);
2714 else if (optype1
== CNSTOP
)
2716 if (GET_CODE (operands
[1]) == HIGH
)
2718 operands
[1] = XEXP (operands
[1], 0);
2721 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2724 latehalf
[1] = operands
[1];
2726 /* If the first move would clobber the source of the second one,
2727 do them in the other order.
2729 This can happen in two cases:
2731 mem -> register where the first half of the destination register
2732 is the same register used in the memory's address. Reload
2733 can create such insns.
2735 mem in this case will be either register indirect or register
2736 indirect plus a valid offset.
2738 register -> register move where REGNO(dst) == REGNO(src + 1)
2739 someone (Tim/Tege?) claimed this can happen for parameter loads.
2741 Handle mem -> register case first. */
2742 if (optype0
== REGOP
2743 && (optype1
== MEMOP
|| optype1
== OFFSOP
)
2744 && refers_to_regno_p (REGNO (operands
[0]), operands
[1]))
2746 /* Do the late half first. */
2748 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2749 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2753 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2754 return pa_singlemove_string (operands
);
2757 /* Now handle register -> register case. */
2758 if (optype0
== REGOP
&& optype1
== REGOP
2759 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
2761 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2762 return pa_singlemove_string (operands
);
2765 /* Normal case: do the two words, low-numbered first. */
2767 output_asm_insn (pa_singlemove_string (operands
), operands
);
2769 /* Make any unoffsettable addresses point at high-numbered word. */
2771 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
2773 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
2775 /* Do high-numbered word. */
2777 output_asm_insn ("ldil L'%1,%0", latehalf
);
2779 output_asm_insn (pa_singlemove_string (latehalf
), latehalf
);
2781 /* Undo the adds we just did. */
2783 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
2785 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
2791 pa_output_fp_move_double (rtx
*operands
)
2793 if (FP_REG_P (operands
[0]))
2795 if (FP_REG_P (operands
[1])
2796 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
2797 output_asm_insn ("fcpy,dbl %f1,%0", operands
);
2799 output_asm_insn ("fldd%F1 %1,%0", operands
);
2801 else if (FP_REG_P (operands
[1]))
2803 output_asm_insn ("fstd%F0 %1,%0", operands
);
2809 gcc_assert (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])));
2811 /* This is a pain. You have to be prepared to deal with an
2812 arbitrary address here including pre/post increment/decrement.
2814 so avoid this in the MD. */
2815 gcc_assert (GET_CODE (operands
[0]) == REG
);
2817 xoperands
[1] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2818 xoperands
[0] = operands
[0];
2819 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
2824 /* Return a REG that occurs in ADDR with coefficient 1.
2825 ADDR can be effectively incremented by incrementing REG. */
2828 find_addr_reg (rtx addr
)
2830 while (GET_CODE (addr
) == PLUS
)
2832 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2833 addr
= XEXP (addr
, 0);
2834 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2835 addr
= XEXP (addr
, 1);
2836 else if (CONSTANT_P (XEXP (addr
, 0)))
2837 addr
= XEXP (addr
, 1);
2838 else if (CONSTANT_P (XEXP (addr
, 1)))
2839 addr
= XEXP (addr
, 0);
2843 gcc_assert (GET_CODE (addr
) == REG
);
2847 /* Emit code to perform a block move.
2849 OPERANDS[0] is the destination pointer as a REG, clobbered.
2850 OPERANDS[1] is the source pointer as a REG, clobbered.
2851 OPERANDS[2] is a register for temporary storage.
2852 OPERANDS[3] is a register for temporary storage.
2853 OPERANDS[4] is the size as a CONST_INT
2854 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2855 OPERANDS[6] is another temporary register. */
2858 pa_output_block_move (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
2860 int align
= INTVAL (operands
[5]);
2861 unsigned long n_bytes
= INTVAL (operands
[4]);
2863 /* We can't move more than a word at a time because the PA
2864 has no longer integer move insns. (Could use fp mem ops?) */
2865 if (align
> (TARGET_64BIT
? 8 : 4))
2866 align
= (TARGET_64BIT
? 8 : 4);
2868 /* Note that we know each loop below will execute at least twice
2869 (else we would have open-coded the copy). */
2873 /* Pre-adjust the loop counter. */
2874 operands
[4] = GEN_INT (n_bytes
- 16);
2875 output_asm_insn ("ldi %4,%2", operands
);
2878 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2879 output_asm_insn ("ldd,ma 8(%1),%6", operands
);
2880 output_asm_insn ("std,ma %3,8(%0)", operands
);
2881 output_asm_insn ("addib,>= -16,%2,.-12", operands
);
2882 output_asm_insn ("std,ma %6,8(%0)", operands
);
2884 /* Handle the residual. There could be up to 7 bytes of
2885 residual to copy! */
2886 if (n_bytes
% 16 != 0)
2888 operands
[4] = GEN_INT (n_bytes
% 8);
2889 if (n_bytes
% 16 >= 8)
2890 output_asm_insn ("ldd,ma 8(%1),%3", operands
);
2891 if (n_bytes
% 8 != 0)
2892 output_asm_insn ("ldd 0(%1),%6", operands
);
2893 if (n_bytes
% 16 >= 8)
2894 output_asm_insn ("std,ma %3,8(%0)", operands
);
2895 if (n_bytes
% 8 != 0)
2896 output_asm_insn ("stdby,e %6,%4(%0)", operands
);
2901 /* Pre-adjust the loop counter. */
2902 operands
[4] = GEN_INT (n_bytes
- 8);
2903 output_asm_insn ("ldi %4,%2", operands
);
2906 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2907 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands
);
2908 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2909 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
2910 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands
);
2912 /* Handle the residual. There could be up to 7 bytes of
2913 residual to copy! */
2914 if (n_bytes
% 8 != 0)
2916 operands
[4] = GEN_INT (n_bytes
% 4);
2917 if (n_bytes
% 8 >= 4)
2918 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands
);
2919 if (n_bytes
% 4 != 0)
2920 output_asm_insn ("ldw 0(%1),%6", operands
);
2921 if (n_bytes
% 8 >= 4)
2922 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands
);
2923 if (n_bytes
% 4 != 0)
2924 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands
);
2929 /* Pre-adjust the loop counter. */
2930 operands
[4] = GEN_INT (n_bytes
- 4);
2931 output_asm_insn ("ldi %4,%2", operands
);
2934 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2935 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands
);
2936 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2937 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
2938 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands
);
2940 /* Handle the residual. */
2941 if (n_bytes
% 4 != 0)
2943 if (n_bytes
% 4 >= 2)
2944 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands
);
2945 if (n_bytes
% 2 != 0)
2946 output_asm_insn ("ldb 0(%1),%6", operands
);
2947 if (n_bytes
% 4 >= 2)
2948 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands
);
2949 if (n_bytes
% 2 != 0)
2950 output_asm_insn ("stb %6,0(%0)", operands
);
2955 /* Pre-adjust the loop counter. */
2956 operands
[4] = GEN_INT (n_bytes
- 2);
2957 output_asm_insn ("ldi %4,%2", operands
);
2960 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands
);
2961 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands
);
2962 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands
);
2963 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
2964 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands
);
2966 /* Handle the residual. */
2967 if (n_bytes
% 2 != 0)
2969 output_asm_insn ("ldb 0(%1),%3", operands
);
2970 output_asm_insn ("stb %3,0(%0)", operands
);
2979 /* Count the number of insns necessary to handle this block move.
2981 Basic structure is the same as emit_block_move, except that we
2982 count insns rather than emit them. */
2985 compute_cpymem_length (rtx_insn
*insn
)
2987 rtx pat
= PATTERN (insn
);
2988 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 7), 0));
2989 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
2990 unsigned int n_insns
= 0;
2992 /* We can't move more than four bytes at a time because the PA
2993 has no longer integer move insns. (Could use fp mem ops?) */
2994 if (align
> (TARGET_64BIT
? 8 : 4))
2995 align
= (TARGET_64BIT
? 8 : 4);
2997 /* The basic copying loop. */
3001 if (n_bytes
% (2 * align
) != 0)
3003 if ((n_bytes
% (2 * align
)) >= align
)
3006 if ((n_bytes
% align
) != 0)
3010 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3014 /* Emit code to perform a block clear.
3016 OPERANDS[0] is the destination pointer as a REG, clobbered.
3017 OPERANDS[1] is a register for temporary storage.
3018 OPERANDS[2] is the size as a CONST_INT
3019 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
3022 pa_output_block_clear (rtx
*operands
, int size_is_constant ATTRIBUTE_UNUSED
)
3024 int align
= INTVAL (operands
[3]);
3025 unsigned long n_bytes
= INTVAL (operands
[2]);
3027 /* We can't clear more than a word at a time because the PA
3028 has no longer integer move insns. */
3029 if (align
> (TARGET_64BIT
? 8 : 4))
3030 align
= (TARGET_64BIT
? 8 : 4);
3032 /* Note that we know each loop below will execute at least twice
3033 (else we would have open-coded the copy). */
3037 /* Pre-adjust the loop counter. */
3038 operands
[2] = GEN_INT (n_bytes
- 16);
3039 output_asm_insn ("ldi %2,%1", operands
);
3042 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3043 output_asm_insn ("addib,>= -16,%1,.-4", operands
);
3044 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3046 /* Handle the residual. There could be up to 7 bytes of
3047 residual to copy! */
3048 if (n_bytes
% 16 != 0)
3050 operands
[2] = GEN_INT (n_bytes
% 8);
3051 if (n_bytes
% 16 >= 8)
3052 output_asm_insn ("std,ma %%r0,8(%0)", operands
);
3053 if (n_bytes
% 8 != 0)
3054 output_asm_insn ("stdby,e %%r0,%2(%0)", operands
);
3059 /* Pre-adjust the loop counter. */
3060 operands
[2] = GEN_INT (n_bytes
- 8);
3061 output_asm_insn ("ldi %2,%1", operands
);
3064 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3065 output_asm_insn ("addib,>= -8,%1,.-4", operands
);
3066 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3068 /* Handle the residual. There could be up to 7 bytes of
3069 residual to copy! */
3070 if (n_bytes
% 8 != 0)
3072 operands
[2] = GEN_INT (n_bytes
% 4);
3073 if (n_bytes
% 8 >= 4)
3074 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands
);
3075 if (n_bytes
% 4 != 0)
3076 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands
);
3081 /* Pre-adjust the loop counter. */
3082 operands
[2] = GEN_INT (n_bytes
- 4);
3083 output_asm_insn ("ldi %2,%1", operands
);
3086 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3087 output_asm_insn ("addib,>= -4,%1,.-4", operands
);
3088 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3090 /* Handle the residual. */
3091 if (n_bytes
% 4 != 0)
3093 if (n_bytes
% 4 >= 2)
3094 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands
);
3095 if (n_bytes
% 2 != 0)
3096 output_asm_insn ("stb %%r0,0(%0)", operands
);
3101 /* Pre-adjust the loop counter. */
3102 operands
[2] = GEN_INT (n_bytes
- 2);
3103 output_asm_insn ("ldi %2,%1", operands
);
3106 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3107 output_asm_insn ("addib,>= -2,%1,.-4", operands
);
3108 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands
);
3110 /* Handle the residual. */
3111 if (n_bytes
% 2 != 0)
3112 output_asm_insn ("stb %%r0,0(%0)", operands
);
3121 /* Count the number of insns necessary to handle this block move.
3123 Basic structure is the same as emit_block_move, except that we
3124 count insns rather than emit them. */
3127 compute_clrmem_length (rtx_insn
*insn
)
3129 rtx pat
= PATTERN (insn
);
3130 unsigned int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 4), 0));
3131 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 3), 0));
3132 unsigned int n_insns
= 0;
3134 /* We can't clear more than a word at a time because the PA
3135 has no longer integer move insns. */
3136 if (align
> (TARGET_64BIT
? 8 : 4))
3137 align
= (TARGET_64BIT
? 8 : 4);
3139 /* The basic loop. */
3143 if (n_bytes
% (2 * align
) != 0)
3145 if ((n_bytes
% (2 * align
)) >= align
)
3148 if ((n_bytes
% align
) != 0)
3152 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3158 pa_output_and (rtx
*operands
)
3160 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3162 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3163 int ls0
, ls1
, ms0
, p
, len
;
3165 for (ls0
= 0; ls0
< 32; ls0
++)
3166 if ((mask
& (1 << ls0
)) == 0)
3169 for (ls1
= ls0
; ls1
< 32; ls1
++)
3170 if ((mask
& (1 << ls1
)) != 0)
3173 for (ms0
= ls1
; ms0
< 32; ms0
++)
3174 if ((mask
& (1 << ms0
)) == 0)
3177 gcc_assert (ms0
== 32);
3185 operands
[2] = GEN_INT (len
);
3186 return "{extru|extrw,u} %1,31,%2,%0";
3190 /* We could use this `depi' for the case above as well, but `depi'
3191 requires one more register file access than an `extru'. */
3196 operands
[2] = GEN_INT (p
);
3197 operands
[3] = GEN_INT (len
);
3198 return "{depi|depwi} 0,%2,%3,%0";
3202 return "and %1,%2,%0";
3205 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3206 storing the result in operands[0]. */
3208 pa_output_64bit_and (rtx
*operands
)
3210 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
3212 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3213 int ls0
, ls1
, ms0
, p
, len
;
3215 for (ls0
= 0; ls0
< HOST_BITS_PER_WIDE_INT
; ls0
++)
3216 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls0
)) == 0)
3219 for (ls1
= ls0
; ls1
< HOST_BITS_PER_WIDE_INT
; ls1
++)
3220 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ls1
)) != 0)
3223 for (ms0
= ls1
; ms0
< HOST_BITS_PER_WIDE_INT
; ms0
++)
3224 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << ms0
)) == 0)
3227 gcc_assert (ms0
== HOST_BITS_PER_WIDE_INT
);
3229 if (ls1
== HOST_BITS_PER_WIDE_INT
)
3235 operands
[2] = GEN_INT (len
);
3236 return "extrd,u %1,63,%2,%0";
3240 /* We could use this `depi' for the case above as well, but `depi'
3241 requires one more register file access than an `extru'. */
3246 operands
[2] = GEN_INT (p
);
3247 operands
[3] = GEN_INT (len
);
3248 return "depdi 0,%2,%3,%0";
3252 return "and %1,%2,%0";
3256 pa_output_ior (rtx
*operands
)
3258 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3259 int bs0
, bs1
, p
, len
;
3261 if (INTVAL (operands
[2]) == 0)
3262 return "copy %1,%0";
3264 for (bs0
= 0; bs0
< 32; bs0
++)
3265 if ((mask
& (1 << bs0
)) != 0)
3268 for (bs1
= bs0
; bs1
< 32; bs1
++)
3269 if ((mask
& (1 << bs1
)) == 0)
3272 gcc_assert (bs1
== 32 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3277 operands
[2] = GEN_INT (p
);
3278 operands
[3] = GEN_INT (len
);
3279 return "{depi|depwi} -1,%2,%3,%0";
3282 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3283 storing the result in operands[0]. */
3285 pa_output_64bit_ior (rtx
*operands
)
3287 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
3288 int bs0
, bs1
, p
, len
;
3290 if (INTVAL (operands
[2]) == 0)
3291 return "copy %1,%0";
3293 for (bs0
= 0; bs0
< HOST_BITS_PER_WIDE_INT
; bs0
++)
3294 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs0
)) != 0)
3297 for (bs1
= bs0
; bs1
< HOST_BITS_PER_WIDE_INT
; bs1
++)
3298 if ((mask
& ((unsigned HOST_WIDE_INT
) 1 << bs1
)) == 0)
3301 gcc_assert (bs1
== HOST_BITS_PER_WIDE_INT
3302 || ((unsigned HOST_WIDE_INT
) 1 << bs1
) > mask
);
3307 operands
[2] = GEN_INT (p
);
3308 operands
[3] = GEN_INT (len
);
3309 return "depdi -1,%2,%3,%0";
3312 /* Target hook for assembling integer objects. This code handles
3313 aligned SI and DI integers specially since function references
3314 must be preceded by P%. */
3317 pa_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3322 /* When we have a SYMBOL_REF with a SYMBOL_REF_DECL, we need to call
3323 call assemble_external and set the SYMBOL_REF_DECL to NULL before
3324 calling output_addr_const. Otherwise, it may call assemble_external
3325 in the midst of outputing the assembler code for the SYMBOL_REF.
3326 We restore the SYMBOL_REF_DECL after the output is done. */
3327 if (GET_CODE (x
) == SYMBOL_REF
)
3329 decl
= SYMBOL_REF_DECL (x
);
3332 assemble_external (decl
);
3333 SET_SYMBOL_REF_DECL (x
, NULL
);
3337 if (size
== UNITS_PER_WORD
3339 && function_label_operand (x
, VOIDmode
))
3341 fputs (size
== 8? "\t.dword\t" : "\t.word\t", asm_out_file
);
3343 /* We don't want an OPD when generating fast indirect calls. */
3344 if (!TARGET_FAST_INDIRECT_CALLS
)
3345 fputs ("P%", asm_out_file
);
3347 output_addr_const (asm_out_file
, x
);
3348 fputc ('\n', asm_out_file
);
3352 result
= default_assemble_integer (x
, size
, aligned_p
);
3355 SET_SYMBOL_REF_DECL (x
, decl
);
3360 /* Output an ascii string. */
3362 pa_output_ascii (FILE *file
, const char *p
, int size
)
3366 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
3368 /* The HP assembler can only take strings of 256 characters at one
3369 time. This is a limitation on input line length, *not* the
3370 length of the string. Sigh. Even worse, it seems that the
3371 restriction is in number of input characters (see \xnn &
3372 \whatever). So we have to do this very carefully. */
3374 fputs ("\t.STRING \"", file
);
3377 for (i
= 0; i
< size
; i
+= 4)
3381 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
3383 register unsigned int c
= (unsigned char) p
[i
+ io
];
3385 if (c
== '\"' || c
== '\\')
3386 partial_output
[co
++] = '\\';
3387 if (c
>= ' ' && c
< 0177)
3388 partial_output
[co
++] = c
;
3392 partial_output
[co
++] = '\\';
3393 partial_output
[co
++] = 'x';
3394 hexd
= c
/ 16 - 0 + '0';
3396 hexd
-= '9' - 'a' + 1;
3397 partial_output
[co
++] = hexd
;
3398 hexd
= c
% 16 - 0 + '0';
3400 hexd
-= '9' - 'a' + 1;
3401 partial_output
[co
++] = hexd
;
3404 if (chars_output
+ co
> 243)
3406 fputs ("\"\n\t.STRING \"", file
);
3409 fwrite (partial_output
, 1, (size_t) co
, file
);
3413 fputs ("\"\n", file
);
3416 /* Try to rewrite floating point comparisons & branches to avoid
3417 useless add,tr insns.
3419 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3420 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3421 first attempt to remove useless add,tr insns. It is zero
3422 for the second pass as reorg sometimes leaves bogus REG_DEAD
3425 When CHECK_NOTES is zero we can only eliminate add,tr insns
3426 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3429 remove_useless_addtr_insns (int check_notes
)
3432 static int pass
= 0;
3434 /* This is fairly cheap, so always run it when optimizing. */
3438 int fbranch_count
= 0;
3440 /* Walk all the insns in this function looking for fcmp & fbranch
3441 instructions. Keep track of how many of each we find. */
3442 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3446 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3447 if (! NONJUMP_INSN_P (insn
) && ! JUMP_P (insn
))
3450 tmp
= PATTERN (insn
);
3452 /* It must be a set. */
3453 if (GET_CODE (tmp
) != SET
)
3456 /* If the destination is CCFP, then we've found an fcmp insn. */
3457 tmp
= SET_DEST (tmp
);
3458 if (GET_CODE (tmp
) == REG
&& REGNO (tmp
) == 0)
3464 tmp
= PATTERN (insn
);
3465 /* If this is an fbranch instruction, bump the fbranch counter. */
3466 if (GET_CODE (tmp
) == SET
3467 && SET_DEST (tmp
) == pc_rtx
3468 && GET_CODE (SET_SRC (tmp
)) == IF_THEN_ELSE
3469 && GET_CODE (XEXP (SET_SRC (tmp
), 0)) == NE
3470 && GET_CODE (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == REG
3471 && REGNO (XEXP (XEXP (SET_SRC (tmp
), 0), 0)) == 0)
3479 /* Find all floating point compare + branch insns. If possible,
3480 reverse the comparison & the branch to avoid add,tr insns. */
3481 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3486 /* Ignore anything that isn't an INSN. */
3487 if (! NONJUMP_INSN_P (insn
))
3490 tmp
= PATTERN (insn
);
3492 /* It must be a set. */
3493 if (GET_CODE (tmp
) != SET
)
3496 /* The destination must be CCFP, which is register zero. */
3497 tmp
= SET_DEST (tmp
);
3498 if (GET_CODE (tmp
) != REG
|| REGNO (tmp
) != 0)
3501 /* INSN should be a set of CCFP.
3503 See if the result of this insn is used in a reversed FP
3504 conditional branch. If so, reverse our condition and
3505 the branch. Doing so avoids useless add,tr insns. */
3506 next
= next_insn (insn
);
3509 /* Jumps, calls and labels stop our search. */
3510 if (JUMP_P (next
) || CALL_P (next
) || LABEL_P (next
))
3513 /* As does another fcmp insn. */
3514 if (NONJUMP_INSN_P (next
)
3515 && GET_CODE (PATTERN (next
)) == SET
3516 && GET_CODE (SET_DEST (PATTERN (next
))) == REG
3517 && REGNO (SET_DEST (PATTERN (next
))) == 0)
3520 next
= next_insn (next
);
3523 /* Is NEXT_INSN a branch? */
3524 if (next
&& JUMP_P (next
))
3526 rtx pattern
= PATTERN (next
);
3528 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3529 and CCFP dies, then reverse our conditional and the branch
3530 to avoid the add,tr. */
3531 if (GET_CODE (pattern
) == SET
3532 && SET_DEST (pattern
) == pc_rtx
3533 && GET_CODE (SET_SRC (pattern
)) == IF_THEN_ELSE
3534 && GET_CODE (XEXP (SET_SRC (pattern
), 0)) == NE
3535 && GET_CODE (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == REG
3536 && REGNO (XEXP (XEXP (SET_SRC (pattern
), 0), 0)) == 0
3537 && GET_CODE (XEXP (SET_SRC (pattern
), 1)) == PC
3538 && (fcmp_count
== fbranch_count
3540 && find_regno_note (next
, REG_DEAD
, 0))))
3542 /* Reverse the branch. */
3543 tmp
= XEXP (SET_SRC (pattern
), 1);
3544 XEXP (SET_SRC (pattern
), 1) = XEXP (SET_SRC (pattern
), 2);
3545 XEXP (SET_SRC (pattern
), 2) = tmp
;
3546 INSN_CODE (next
) = -1;
3548 /* Reverse our condition. */
3549 tmp
= PATTERN (insn
);
3550 PUT_CODE (XEXP (tmp
, 1),
3551 (reverse_condition_maybe_unordered
3552 (GET_CODE (XEXP (tmp
, 1)))));
3562 /* You may have trouble believing this, but this is the 32 bit HP-PA
3567 Variable arguments (optional; any number may be allocated)
3569 SP-(4*(N+9)) arg word N
3574 Fixed arguments (must be allocated; may remain unused)
3583 SP-32 External Data Pointer (DP)
3585 SP-24 External/stub RP (RP')
3589 SP-8 Calling Stub RP (RP'')
3594 SP-0 Stack Pointer (points to next available address)
3598 /* This function saves registers as follows. Registers marked with ' are
3599 this function's registers (as opposed to the previous function's).
3600 If a frame_pointer isn't needed, r4 is saved as a general register;
3601 the space for the frame pointer is still allocated, though, to keep
3607 SP (FP') Previous FP
3608 SP + 4 Alignment filler (sigh)
3609 SP + 8 Space for locals reserved here.
3613 SP + n All call saved register used.
3617 SP + o All call saved fp registers used.
3621 SP + p (SP') points to next available address.
3625 /* Global variables set by output_function_prologue(). */
3626 /* Size of frame. Need to know this to emit return insns from
3628 static HOST_WIDE_INT actual_fsize
, local_fsize
;
3629 static int save_fregs
;
3631 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3632 Handle case where DISP > 8k by using the add_high_const patterns.
3634 Note in DISP > 8k case, we will leave the high part of the address
3635 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3638 store_reg (int reg
, HOST_WIDE_INT disp
, int base
)
3640 rtx dest
, src
, basereg
;
3643 src
= gen_rtx_REG (word_mode
, reg
);
3644 basereg
= gen_rtx_REG (Pmode
, base
);
3645 if (VAL_14_BITS_P (disp
))
3647 dest
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
3648 insn
= emit_move_insn (dest
, src
);
3650 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3652 rtx delta
= GEN_INT (disp
);
3653 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3655 emit_move_insn (tmpreg
, delta
);
3656 insn
= emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3659 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3660 gen_rtx_SET (tmpreg
,
3661 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3662 RTX_FRAME_RELATED_P (insn
) = 1;
3664 dest
= gen_rtx_MEM (word_mode
, tmpreg
);
3665 insn
= emit_move_insn (dest
, src
);
3669 rtx delta
= GEN_INT (disp
);
3670 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
3671 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3673 emit_move_insn (tmpreg
, high
);
3674 dest
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3675 insn
= emit_move_insn (dest
, src
);
3677 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3678 gen_rtx_SET (gen_rtx_MEM (word_mode
,
3679 gen_rtx_PLUS (word_mode
,
3686 RTX_FRAME_RELATED_P (insn
) = 1;
3689 /* Emit RTL to store REG at the memory location specified by BASE and then
3690 add MOD to BASE. MOD must be <= 8k. */
3693 store_reg_modify (int base
, int reg
, HOST_WIDE_INT mod
)
3695 rtx basereg
, srcreg
, delta
;
3698 gcc_assert (VAL_14_BITS_P (mod
));
3700 basereg
= gen_rtx_REG (Pmode
, base
);
3701 srcreg
= gen_rtx_REG (word_mode
, reg
);
3702 delta
= GEN_INT (mod
);
3704 insn
= emit_insn (gen_post_store (basereg
, srcreg
, delta
));
3707 RTX_FRAME_RELATED_P (insn
) = 1;
3709 /* RTX_FRAME_RELATED_P must be set on each frame related set
3710 in a parallel with more than one element. */
3711 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 0)) = 1;
3712 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn
), 0, 1)) = 1;
3716 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3717 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3718 whether to add a frame note or not.
3720 In the DISP > 8k case, we leave the high part of the address in %r1.
3721 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3724 set_reg_plus_d (int reg
, int base
, HOST_WIDE_INT disp
, int note
)
3728 if (VAL_14_BITS_P (disp
))
3730 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3731 plus_constant (Pmode
,
3732 gen_rtx_REG (Pmode
, base
), disp
));
3734 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
3736 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3737 rtx delta
= GEN_INT (disp
);
3738 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3740 emit_move_insn (tmpreg
, delta
);
3741 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3742 gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
3744 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3745 gen_rtx_SET (tmpreg
,
3746 gen_rtx_PLUS (Pmode
, basereg
, delta
)));
3750 rtx basereg
= gen_rtx_REG (Pmode
, base
);
3751 rtx delta
= GEN_INT (disp
);
3752 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
3754 emit_move_insn (tmpreg
,
3755 gen_rtx_PLUS (Pmode
, basereg
,
3756 gen_rtx_HIGH (Pmode
, delta
)));
3757 insn
= emit_move_insn (gen_rtx_REG (Pmode
, reg
),
3758 gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
3761 if (DO_FRAME_NOTES
&& note
)
3762 RTX_FRAME_RELATED_P (insn
) = 1;
3766 pa_compute_frame_size (poly_int64 size
, int *fregs_live
)
3771 /* The code in pa_expand_prologue and pa_expand_epilogue must
3772 be consistent with the rounding and size calculation done here.
3773 Change them at the same time. */
3775 /* We do our own stack alignment. First, round the size of the
3776 stack locals up to a word boundary. */
3777 size
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3779 /* Space for previous frame pointer + filler. If any frame is
3780 allocated, we need to add in the TARGET_STARTING_FRAME_OFFSET. We
3781 waste some space here for the sake of HP compatibility. The
3782 first slot is only used when the frame pointer is needed. */
3783 if (size
|| frame_pointer_needed
)
3784 size
+= pa_starting_frame_offset ();
3786 /* If the current function calls __builtin_eh_return, then we need
3787 to allocate stack space for registers that will hold data for
3788 the exception handler. */
3789 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
3793 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
3795 size
+= i
* UNITS_PER_WORD
;
3798 /* Account for space used by the callee general register saves. */
3799 for (i
= 18, j
= frame_pointer_needed
? 4 : 3; i
>= j
; i
--)
3800 if (df_regs_ever_live_p (i
))
3801 size
+= UNITS_PER_WORD
;
3803 /* Account for space used by the callee floating point register saves. */
3804 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
3805 if (df_regs_ever_live_p (i
)
3806 || (!TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
3810 /* We always save both halves of the FP register, so always
3811 increment the frame size by 8 bytes. */
3815 /* If any of the floating registers are saved, account for the
3816 alignment needed for the floating point register save block. */
3819 size
= (size
+ 7) & ~7;
3824 /* The various ABIs include space for the outgoing parameters in the
3825 size of the current function's stack frame. We don't need to align
3826 for the outgoing arguments as their alignment is set by the final
3827 rounding for the frame as a whole. */
3828 size
+= crtl
->outgoing_args_size
;
3830 /* Allocate space for the fixed frame marker. This space must be
3831 allocated for any function that makes calls or allocates
3833 if (!crtl
->is_leaf
|| size
)
3834 size
+= TARGET_64BIT
? 48 : 32;
3836 /* Finally, round to the preferred stack boundary. */
3837 return ((size
+ PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
3838 & ~(PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
3841 /* Output function label, and associated .PROC and .CALLINFO statements. */
3844 pa_output_function_label (FILE *file
)
3846 /* The function's label and associated .PROC must never be
3847 separated and must be output *after* any profiling declarations
3848 to avoid changing spaces/subspaces within a procedure. */
3849 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
3850 fputs ("\t.PROC\n", file
);
3852 /* pa_expand_prologue does the dirty work now. We just need
3853 to output the assembler directives which denote the start
3855 fprintf (file
, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC
, actual_fsize
);
3857 fputs (",NO_CALLS", file
);
3859 fputs (",CALLS", file
);
3861 fputs (",SAVE_RP", file
);
3863 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3864 at the beginning of the frame and that it is used as the frame
3865 pointer for the frame. We do this because our current frame
3866 layout doesn't conform to that specified in the HP runtime
3867 documentation and we need a way to indicate to programs such as
3868 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3869 isn't used by HP compilers but is supported by the assembler.
3870 However, SAVE_SP is supposed to indicate that the previous stack
3871 pointer has been saved in the frame marker. */
3872 if (frame_pointer_needed
)
3873 fputs (",SAVE_SP", file
);
3875 /* Pass on information about the number of callee register saves
3876 performed in the prologue.
3878 The compiler is supposed to pass the highest register number
3879 saved, the assembler then has to adjust that number before
3880 entering it into the unwind descriptor (to account for any
3881 caller saved registers with lower register numbers than the
3882 first callee saved register). */
3884 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
3887 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
3889 fputs ("\n\t.ENTRY\n", file
);
3892 /* Output function prologue. */
3895 pa_output_function_prologue (FILE *file
)
3897 pa_output_function_label (file
);
3898 remove_useless_addtr_insns (0);
3901 /* The label is output by ASM_DECLARE_FUNCTION_NAME on linux. */
3904 pa_linux_output_function_prologue (FILE *file ATTRIBUTE_UNUSED
)
3906 remove_useless_addtr_insns (0);
3910 pa_expand_prologue (void)
3912 int merge_sp_adjust_with_store
= 0;
3913 HOST_WIDE_INT size
= get_frame_size ();
3914 HOST_WIDE_INT offset
;
3923 /* Compute total size for frame pointer, filler, locals and rounding to
3924 the next word boundary. Similar code appears in pa_compute_frame_size
3925 and must be changed in tandem with this code. */
3926 local_fsize
= (size
+ UNITS_PER_WORD
- 1) & ~(UNITS_PER_WORD
- 1);
3927 if (local_fsize
|| frame_pointer_needed
)
3928 local_fsize
+= pa_starting_frame_offset ();
3930 actual_fsize
= pa_compute_frame_size (size
, &save_fregs
);
3931 if (flag_stack_usage_info
)
3932 current_function_static_stack_size
= actual_fsize
;
3934 /* Compute a few things we will use often. */
3935 tmpreg
= gen_rtx_REG (word_mode
, 1);
3937 /* Save RP first. The calling conventions manual states RP will
3938 always be stored into the caller's frame at sp - 20 or sp - 16
3939 depending on which ABI is in use. */
3940 if (df_regs_ever_live_p (2) || crtl
->calls_eh_return
)
3942 store_reg (2, TARGET_64BIT
? -16 : -20, STACK_POINTER_REGNUM
);
3948 /* Allocate the local frame and set up the frame pointer if needed. */
3949 if (actual_fsize
!= 0)
3951 if (frame_pointer_needed
)
3953 /* Copy the old frame pointer temporarily into %r1. Set up the
3954 new stack pointer, then store away the saved old frame pointer
3955 into the stack at sp and at the same time update the stack
3956 pointer by actual_fsize bytes. Two versions, first
3957 handles small (<8k) frames. The second handles large (>=8k)
3959 insn
= emit_move_insn (tmpreg
, hard_frame_pointer_rtx
);
3961 RTX_FRAME_RELATED_P (insn
) = 1;
3963 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
3965 RTX_FRAME_RELATED_P (insn
) = 1;
3967 if (VAL_14_BITS_P (actual_fsize
))
3968 store_reg_modify (STACK_POINTER_REGNUM
, 1, actual_fsize
);
3971 /* It is incorrect to store the saved frame pointer at *sp,
3972 then increment sp (writes beyond the current stack boundary).
3974 So instead use stwm to store at *sp and post-increment the
3975 stack pointer as an atomic operation. Then increment sp to
3976 finish allocating the new frame. */
3977 HOST_WIDE_INT adjust1
= 8192 - 64;
3978 HOST_WIDE_INT adjust2
= actual_fsize
- adjust1
;
3980 store_reg_modify (STACK_POINTER_REGNUM
, 1, adjust1
);
3981 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
3985 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3986 we need to store the previous stack pointer (frame pointer)
3987 into the frame marker on targets that use the HP unwind
3988 library. This allows the HP unwind library to be used to
3989 unwind GCC frames. However, we are not fully compatible
3990 with the HP library because our frame layout differs from
3991 that specified in the HP runtime specification.
3993 We don't want a frame note on this instruction as the frame
3994 marker moves during dynamic stack allocation.
3996 This instruction also serves as a blockage to prevent
3997 register spills from being scheduled before the stack
3998 pointer is raised. This is necessary as we store
3999 registers using the frame pointer as a base register,
4000 and the frame pointer is set before sp is raised. */
4001 if (TARGET_HPUX_UNWIND_LIBRARY
)
4003 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
,
4004 GEN_INT (TARGET_64BIT
? -8 : -4));
4006 emit_move_insn (gen_rtx_MEM (word_mode
, addr
),
4007 hard_frame_pointer_rtx
);
4010 emit_insn (gen_blockage ());
4012 /* no frame pointer needed. */
4015 /* In some cases we can perform the first callee register save
4016 and allocating the stack frame at the same time. If so, just
4017 make a note of it and defer allocating the frame until saving
4018 the callee registers. */
4019 if (VAL_14_BITS_P (actual_fsize
) && local_fsize
== 0)
4020 merge_sp_adjust_with_store
= 1;
4021 /* Cannot optimize. Adjust the stack frame by actual_fsize
4024 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4029 /* Normal register save.
4031 Do not save the frame pointer in the frame_pointer_needed case. It
4032 was done earlier. */
4033 if (frame_pointer_needed
)
4035 offset
= local_fsize
;
4037 /* Saving the EH return data registers in the frame is the simplest
4038 way to get the frame unwind information emitted. We put them
4039 just before the general registers. */
4040 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4042 unsigned int i
, regno
;
4046 regno
= EH_RETURN_DATA_REGNO (i
);
4047 if (regno
== INVALID_REGNUM
)
4050 store_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
4051 offset
+= UNITS_PER_WORD
;
4055 for (i
= 18; i
>= 4; i
--)
4056 if (df_regs_ever_live_p (i
) && !call_used_or_fixed_reg_p (i
))
4058 store_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
4059 offset
+= UNITS_PER_WORD
;
4062 /* Account for %r3 which is saved in a special place. */
4065 /* No frame pointer needed. */
4068 offset
= local_fsize
- actual_fsize
;
4070 /* Saving the EH return data registers in the frame is the simplest
4071 way to get the frame unwind information emitted. */
4072 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4074 unsigned int i
, regno
;
4078 regno
= EH_RETURN_DATA_REGNO (i
);
4079 if (regno
== INVALID_REGNUM
)
4082 /* If merge_sp_adjust_with_store is nonzero, then we can
4083 optimize the first save. */
4084 if (merge_sp_adjust_with_store
)
4086 store_reg_modify (STACK_POINTER_REGNUM
, regno
, -offset
);
4087 merge_sp_adjust_with_store
= 0;
4090 store_reg (regno
, offset
, STACK_POINTER_REGNUM
);
4091 offset
+= UNITS_PER_WORD
;
4095 for (i
= 18; i
>= 3; i
--)
4096 if (df_regs_ever_live_p (i
) && !call_used_or_fixed_reg_p (i
))
4098 /* If merge_sp_adjust_with_store is nonzero, then we can
4099 optimize the first GR save. */
4100 if (merge_sp_adjust_with_store
)
4102 store_reg_modify (STACK_POINTER_REGNUM
, i
, -offset
);
4103 merge_sp_adjust_with_store
= 0;
4106 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
4107 offset
+= UNITS_PER_WORD
;
4111 /* If we wanted to merge the SP adjustment with a GR save, but we never
4112 did any GR saves, then just emit the adjustment here. */
4113 if (merge_sp_adjust_with_store
)
4114 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4118 /* The hppa calling conventions say that %r19, the pic offset
4119 register, is saved at sp - 32 (in this function's frame)
4120 when generating PIC code. FIXME: What is the correct thing
4121 to do for functions which make no calls and allocate no
4122 frame? Do we need to allocate a frame, or can we just omit
4123 the save? For now we'll just omit the save.
4125 We don't want a note on this insn as the frame marker can
4126 move if there is a dynamic stack allocation. */
4127 if (flag_pic
&& actual_fsize
!= 0 && !TARGET_64BIT
)
4129 rtx addr
= gen_rtx_PLUS (word_mode
, stack_pointer_rtx
, GEN_INT (-32));
4131 emit_move_insn (gen_rtx_MEM (word_mode
, addr
), pic_offset_table_rtx
);
4135 /* Align pointer properly (doubleword boundary). */
4136 offset
= (offset
+ 7) & ~7;
4138 /* Floating point register store. */
4143 /* First get the frame or stack pointer to the start of the FP register
4145 if (frame_pointer_needed
)
4147 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4148 base
= hard_frame_pointer_rtx
;
4152 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4153 base
= stack_pointer_rtx
;
4156 /* Now actually save the FP registers. */
4157 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4159 if (df_regs_ever_live_p (i
)
4160 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4164 addr
= gen_rtx_MEM (DFmode
,
4165 gen_rtx_POST_INC (word_mode
, tmpreg
));
4166 reg
= gen_rtx_REG (DFmode
, i
);
4167 insn
= emit_move_insn (addr
, reg
);
4170 RTX_FRAME_RELATED_P (insn
) = 1;
4173 rtx mem
= gen_rtx_MEM (DFmode
,
4174 plus_constant (Pmode
, base
,
4176 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4177 gen_rtx_SET (mem
, reg
));
4181 rtx meml
= gen_rtx_MEM (SFmode
,
4182 plus_constant (Pmode
, base
,
4184 rtx memr
= gen_rtx_MEM (SFmode
,
4185 plus_constant (Pmode
, base
,
4187 rtx regl
= gen_rtx_REG (SFmode
, i
);
4188 rtx regr
= gen_rtx_REG (SFmode
, i
+ 1);
4189 rtx setl
= gen_rtx_SET (meml
, regl
);
4190 rtx setr
= gen_rtx_SET (memr
, regr
);
4193 RTX_FRAME_RELATED_P (setl
) = 1;
4194 RTX_FRAME_RELATED_P (setr
) = 1;
4195 vec
= gen_rtvec (2, setl
, setr
);
4196 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4197 gen_rtx_SEQUENCE (VOIDmode
, vec
));
4200 offset
+= GET_MODE_SIZE (DFmode
);
4207 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4208 Handle case where DISP > 8k by using the add_high_const patterns. */
4211 load_reg (int reg
, HOST_WIDE_INT disp
, int base
)
4213 rtx dest
= gen_rtx_REG (word_mode
, reg
);
4214 rtx basereg
= gen_rtx_REG (Pmode
, base
);
4217 if (VAL_14_BITS_P (disp
))
4218 src
= gen_rtx_MEM (word_mode
, plus_constant (Pmode
, basereg
, disp
));
4219 else if (TARGET_64BIT
&& !VAL_32_BITS_P (disp
))
4221 rtx delta
= GEN_INT (disp
);
4222 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4224 emit_move_insn (tmpreg
, delta
);
4225 if (TARGET_DISABLE_INDEXING
)
4227 emit_move_insn (tmpreg
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4228 src
= gen_rtx_MEM (word_mode
, tmpreg
);
4231 src
= gen_rtx_MEM (word_mode
, gen_rtx_PLUS (Pmode
, tmpreg
, basereg
));
4235 rtx delta
= GEN_INT (disp
);
4236 rtx high
= gen_rtx_PLUS (Pmode
, basereg
, gen_rtx_HIGH (Pmode
, delta
));
4237 rtx tmpreg
= gen_rtx_REG (Pmode
, 1);
4239 emit_move_insn (tmpreg
, high
);
4240 src
= gen_rtx_MEM (word_mode
, gen_rtx_LO_SUM (Pmode
, tmpreg
, delta
));
4243 emit_move_insn (dest
, src
);
4246 /* Update the total code bytes output to the text section. */
4249 update_total_code_bytes (unsigned int nbytes
)
4251 if ((TARGET_PORTABLE_RUNTIME
|| !TARGET_GAS
|| !TARGET_SOM
)
4252 && !IN_NAMED_SECTION_P (cfun
->decl
))
4254 unsigned int old_total
= total_code_bytes
;
4256 total_code_bytes
+= nbytes
;
4258 /* Be prepared to handle overflows. */
4259 if (old_total
> total_code_bytes
)
4260 total_code_bytes
= UINT_MAX
;
4264 /* This function generates the assembly code for function exit.
4265 Args are as for output_function_prologue ().
4267 The function epilogue should not depend on the current stack
4268 pointer! It should use the frame pointer only. This is mandatory
4269 because of alloca; we also take advantage of it to omit stack
4270 adjustments before returning. */
4273 pa_output_function_epilogue (FILE *file
)
4275 rtx_insn
*insn
= get_last_insn ();
4278 /* pa_expand_epilogue does the dirty work now. We just need
4279 to output the assembler directives which denote the end
4282 To make debuggers happy, emit a nop if the epilogue was completely
4283 eliminated due to a volatile call as the last insn in the
4284 current function. That way the return address (in %r2) will
4285 always point to a valid instruction in the current function. */
4287 /* Get the last real insn. */
4289 insn
= prev_real_insn (insn
);
4291 /* If it is a sequence, then look inside. */
4292 if (insn
&& NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4293 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))-> insn (0);
4295 /* If insn is a CALL_INSN, then it must be a call to a volatile
4296 function (otherwise there would be epilogue insns). */
4297 if (insn
&& CALL_P (insn
))
4299 fputs ("\tnop\n", file
);
4305 fputs ("\t.EXIT\n\t.PROCEND\n", file
);
4307 if (TARGET_SOM
&& TARGET_GAS
)
4309 /* We are done with this subspace except possibly for some additional
4310 debug information. Forget that we are in this subspace to ensure
4311 that the next function is output in its own subspace. */
4313 cfun
->machine
->in_nsubspa
= 2;
4316 /* Thunks do their own insn accounting. */
4320 if (INSN_ADDRESSES_SET_P ())
4322 last_address
= extra_nop
? 4 : 0;
4323 insn
= get_last_nonnote_insn ();
4326 last_address
+= INSN_ADDRESSES (INSN_UID (insn
));
4328 last_address
+= insn_default_length (insn
);
4330 last_address
= ((last_address
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
4331 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
4334 last_address
= UINT_MAX
;
4336 /* Finally, update the total number of code bytes output so far. */
4337 update_total_code_bytes (last_address
);
4341 pa_expand_epilogue (void)
4344 HOST_WIDE_INT offset
;
4345 HOST_WIDE_INT ret_off
= 0;
4347 int merge_sp_adjust_with_load
= 0;
4349 /* We will use this often. */
4350 tmpreg
= gen_rtx_REG (word_mode
, 1);
4352 /* Try to restore RP early to avoid load/use interlocks when
4353 RP gets used in the return (bv) instruction. This appears to still
4354 be necessary even when we schedule the prologue and epilogue. */
4357 ret_off
= TARGET_64BIT
? -16 : -20;
4358 if (frame_pointer_needed
)
4360 load_reg (2, ret_off
, HARD_FRAME_POINTER_REGNUM
);
4365 /* No frame pointer, and stack is smaller than 8k. */
4366 if (VAL_14_BITS_P (ret_off
- actual_fsize
))
4368 load_reg (2, ret_off
- actual_fsize
, STACK_POINTER_REGNUM
);
4374 /* General register restores. */
4375 if (frame_pointer_needed
)
4377 offset
= local_fsize
;
4379 /* If the current function calls __builtin_eh_return, then we need
4380 to restore the saved EH data registers. */
4381 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4383 unsigned int i
, regno
;
4387 regno
= EH_RETURN_DATA_REGNO (i
);
4388 if (regno
== INVALID_REGNUM
)
4391 load_reg (regno
, offset
, HARD_FRAME_POINTER_REGNUM
);
4392 offset
+= UNITS_PER_WORD
;
4396 for (i
= 18; i
>= 4; i
--)
4397 if (df_regs_ever_live_p (i
) && !call_used_or_fixed_reg_p (i
))
4399 load_reg (i
, offset
, HARD_FRAME_POINTER_REGNUM
);
4400 offset
+= UNITS_PER_WORD
;
4405 offset
= local_fsize
- actual_fsize
;
4407 /* If the current function calls __builtin_eh_return, then we need
4408 to restore the saved EH data registers. */
4409 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4411 unsigned int i
, regno
;
4415 regno
= EH_RETURN_DATA_REGNO (i
);
4416 if (regno
== INVALID_REGNUM
)
4419 /* Only for the first load.
4420 merge_sp_adjust_with_load holds the register load
4421 with which we will merge the sp adjustment. */
4422 if (merge_sp_adjust_with_load
== 0
4424 && VAL_14_BITS_P (-actual_fsize
))
4425 merge_sp_adjust_with_load
= regno
;
4427 load_reg (regno
, offset
, STACK_POINTER_REGNUM
);
4428 offset
+= UNITS_PER_WORD
;
4432 for (i
= 18; i
>= 3; i
--)
4434 if (df_regs_ever_live_p (i
) && !call_used_or_fixed_reg_p (i
))
4436 /* Only for the first load.
4437 merge_sp_adjust_with_load holds the register load
4438 with which we will merge the sp adjustment. */
4439 if (merge_sp_adjust_with_load
== 0
4441 && VAL_14_BITS_P (-actual_fsize
))
4442 merge_sp_adjust_with_load
= i
;
4444 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
4445 offset
+= UNITS_PER_WORD
;
4450 /* Align pointer properly (doubleword boundary). */
4451 offset
= (offset
+ 7) & ~7;
4453 /* FP register restores. */
4456 /* Adjust the register to index off of. */
4457 if (frame_pointer_needed
)
4458 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM
, offset
, 0);
4460 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
, 0);
4462 /* Actually do the restores now. */
4463 for (i
= FP_SAVED_REG_LAST
; i
>= FP_SAVED_REG_FIRST
; i
-= FP_REG_STEP
)
4464 if (df_regs_ever_live_p (i
)
4465 || (! TARGET_64BIT
&& df_regs_ever_live_p (i
+ 1)))
4467 rtx src
= gen_rtx_MEM (DFmode
,
4468 gen_rtx_POST_INC (word_mode
, tmpreg
));
4469 rtx dest
= gen_rtx_REG (DFmode
, i
);
4470 emit_move_insn (dest
, src
);
4474 /* Emit a blockage insn here to keep these insns from being moved to
4475 an earlier spot in the epilogue, or into the main instruction stream.
4477 This is necessary as we must not cut the stack back before all the
4478 restores are finished. */
4479 emit_insn (gen_blockage ());
4481 /* Reset stack pointer (and possibly frame pointer). The stack
4482 pointer is initially set to fp + 64 to avoid a race condition. */
4483 if (frame_pointer_needed
)
4485 rtx delta
= GEN_INT (-64);
4487 set_reg_plus_d (STACK_POINTER_REGNUM
, HARD_FRAME_POINTER_REGNUM
, 64, 0);
4488 emit_insn (gen_pre_load (hard_frame_pointer_rtx
,
4489 stack_pointer_rtx
, delta
));
4491 /* If we were deferring a callee register restore, do it now. */
4492 else if (merge_sp_adjust_with_load
)
4494 rtx delta
= GEN_INT (-actual_fsize
);
4495 rtx dest
= gen_rtx_REG (word_mode
, merge_sp_adjust_with_load
);
4497 emit_insn (gen_pre_load (dest
, stack_pointer_rtx
, delta
));
4499 else if (actual_fsize
!= 0)
4500 set_reg_plus_d (STACK_POINTER_REGNUM
, STACK_POINTER_REGNUM
,
4503 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4504 frame greater than 8k), do so now. */
4506 load_reg (2, ret_off
, STACK_POINTER_REGNUM
);
4508 if (DO_FRAME_NOTES
&& crtl
->calls_eh_return
)
4510 rtx sa
= EH_RETURN_STACKADJ_RTX
;
4512 emit_insn (gen_blockage ());
4513 emit_insn (TARGET_64BIT
4514 ? gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
)
4515 : gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, sa
));
4520 pa_can_use_return_insn (void)
4522 if (!reload_completed
)
4525 if (frame_pointer_needed
)
4528 if (df_regs_ever_live_p (2))
4534 return pa_compute_frame_size (get_frame_size (), 0) == 0;
4538 hppa_pic_save_rtx (void)
4540 return get_hard_reg_initial_val (word_mode
, PIC_OFFSET_TABLE_REGNUM
);
4543 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4544 #define NO_DEFERRED_PROFILE_COUNTERS 0
4548 /* Vector of funcdef numbers. */
4549 static vec
<int> funcdef_nos
;
4551 /* Output deferred profile counters. */
4553 output_deferred_profile_counters (void)
4558 if (funcdef_nos
.is_empty ())
4561 switch_to_section (data_section
);
4562 align
= MIN (BIGGEST_ALIGNMENT
, LONG_TYPE_SIZE
);
4563 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (align
/ BITS_PER_UNIT
));
4565 for (i
= 0; funcdef_nos
.iterate (i
, &n
); i
++)
4567 targetm
.asm_out
.internal_label (asm_out_file
, "LP", n
);
4568 assemble_integer (const0_rtx
, LONG_TYPE_SIZE
/ BITS_PER_UNIT
, align
, 1);
4571 funcdef_nos
.release ();
4575 hppa_profile_hook (int label_no
)
4577 rtx_code_label
*label_rtx
= gen_label_rtx ();
4578 int reg_parm_stack_space
= REG_PARM_STACK_SPACE (NULL_TREE
);
4579 rtx arg_bytes
, begin_label_rtx
, mcount
, sym
;
4580 rtx_insn
*call_insn
;
4581 char begin_label_name
[16];
4582 bool use_mcount_pcrel_call
;
4584 /* Set up call destination. */
4585 sym
= gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
4586 pa_encode_label (sym
);
4587 mcount
= gen_rtx_MEM (Pmode
, sym
);
4589 /* If we can reach _mcount with a pc-relative call, we can optimize
4590 loading the address of the current function. This requires linker
4591 long branch stub support. */
4592 if (!TARGET_PORTABLE_RUNTIME
4593 && !TARGET_LONG_CALLS
4594 && (TARGET_SOM
|| flag_function_sections
))
4595 use_mcount_pcrel_call
= TRUE
;
4597 use_mcount_pcrel_call
= FALSE
;
4599 ASM_GENERATE_INTERNAL_LABEL (begin_label_name
, FUNC_BEGIN_PROLOG_LABEL
,
4601 begin_label_rtx
= gen_rtx_SYMBOL_REF (SImode
, ggc_strdup (begin_label_name
));
4603 emit_move_insn (gen_rtx_REG (word_mode
, 26), gen_rtx_REG (word_mode
, 2));
4605 if (!use_mcount_pcrel_call
)
4607 /* The address of the function is loaded into %r25 with an instruction-
4608 relative sequence that avoids the use of relocations. We use SImode
4609 for the address of the function in both 32 and 64-bit code to avoid
4610 having to provide DImode versions of the lcla2 pattern. */
4612 emit_insn (gen_lcla2 (gen_rtx_REG (SImode
, 25), label_rtx
));
4614 emit_insn (gen_lcla1 (gen_rtx_REG (SImode
, 25), label_rtx
));
4617 if (!NO_DEFERRED_PROFILE_COUNTERS
)
4619 rtx count_label_rtx
, addr
, r24
;
4620 char count_label_name
[16];
4622 funcdef_nos
.safe_push (label_no
);
4623 ASM_GENERATE_INTERNAL_LABEL (count_label_name
, "LP", label_no
);
4624 count_label_rtx
= gen_rtx_SYMBOL_REF (Pmode
,
4625 ggc_strdup (count_label_name
));
4627 addr
= force_reg (Pmode
, count_label_rtx
);
4628 r24
= gen_rtx_REG (Pmode
, 24);
4629 emit_move_insn (r24
, addr
);
4631 arg_bytes
= GEN_INT (TARGET_64BIT
? 24 : 12);
4632 if (use_mcount_pcrel_call
)
4633 call_insn
= emit_call_insn (gen_call_mcount (mcount
, arg_bytes
,
4636 call_insn
= emit_call_insn (gen_call (mcount
, arg_bytes
));
4638 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), r24
);
4642 arg_bytes
= GEN_INT (TARGET_64BIT
? 16 : 8);
4643 if (use_mcount_pcrel_call
)
4644 call_insn
= emit_call_insn (gen_call_mcount (mcount
, arg_bytes
,
4647 call_insn
= emit_call_insn (gen_call (mcount
, arg_bytes
));
4650 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 25));
4651 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), gen_rtx_REG (SImode
, 26));
4653 /* Indicate the _mcount call cannot throw, nor will it execute a
4655 make_reg_eh_region_note_nothrow_nononlocal (call_insn
);
4657 /* Allocate space for fixed arguments. */
4658 if (reg_parm_stack_space
> crtl
->outgoing_args_size
)
4659 crtl
->outgoing_args_size
= reg_parm_stack_space
;
4662 /* Fetch the return address for the frame COUNT steps up from
4663 the current frame, after the prologue. FRAMEADDR is the
4664 frame pointer of the COUNT frame.
4666 We want to ignore any export stub remnants here. To handle this,
4667 we examine the code at the return address, and if it is an export
4668 stub, we return a memory rtx for the stub return address stored
4671 The value returned is used in two different ways:
4673 1. To find a function's caller.
4675 2. To change the return address for a function.
4677 This function handles most instances of case 1; however, it will
4678 fail if there are two levels of stubs to execute on the return
4679 path. The only way I believe that can happen is if the return value
4680 needs a parameter relocation, which never happens for C code.
4682 This function handles most instances of case 2; however, it will
4683 fail if we did not originally have stub code on the return path
4684 but will need stub code on the new return path. This can happen if
4685 the caller & callee are both in the main program, but the new
4686 return location is in a shared library. */
4689 pa_return_addr_rtx (int count
, rtx frameaddr
)
4696 /* The instruction stream at the return address of a PA1.X export stub is:
4698 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4699 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4700 0x00011820 | stub+16: mtsp r1,sr0
4701 0xe0400002 | stub+20: be,n 0(sr0,rp)
4703 0xe0400002 must be specified as -532676606 so that it won't be
4704 rejected as an invalid immediate operand on 64-bit hosts.
4706 The instruction stream at the return address of a PA2.0 export stub is:
4708 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4709 0xe840d002 | stub+12: bve,n (rp)
4712 HOST_WIDE_INT insns
[4];
4718 rp
= get_hard_reg_initial_val (Pmode
, 2);
4720 if (TARGET_64BIT
|| TARGET_NO_SPACE_REGS
)
4723 /* If there is no export stub then just use the value saved from
4724 the return pointer register. */
4726 saved_rp
= gen_reg_rtx (Pmode
);
4727 emit_move_insn (saved_rp
, rp
);
4729 /* Get pointer to the instruction stream. We have to mask out the
4730 privilege level from the two low order bits of the return address
4731 pointer here so that ins will point to the start of the first
4732 instruction that would have been executed if we returned. */
4733 ins
= copy_to_reg (gen_rtx_AND (Pmode
, rp
, MASK_RETURN_ADDR
));
4734 label
= gen_label_rtx ();
4738 insns
[0] = 0x4bc23fd1;
4739 insns
[1] = -398405630;
4744 insns
[0] = 0x4bc23fd1;
4745 insns
[1] = 0x004010a1;
4746 insns
[2] = 0x00011820;
4747 insns
[3] = -532676606;
4751 /* Check the instruction stream at the normal return address for the
4752 export stub. If it is an export stub, than our return address is
4753 really in -24[frameaddr]. */
4755 for (i
= 0; i
< len
; i
++)
4757 rtx op0
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, ins
, i
* 4));
4758 rtx op1
= GEN_INT (insns
[i
]);
4759 emit_cmp_and_jump_insns (op0
, op1
, NE
, NULL
, SImode
, 0, label
);
4762 /* Here we know that our return address points to an export
4763 stub. We don't want to return the address of the export stub,
4764 but rather the return address of the export stub. That return
4765 address is stored at -24[frameaddr]. */
4767 emit_move_insn (saved_rp
,
4769 memory_address (Pmode
,
4770 plus_constant (Pmode
, frameaddr
,
4779 pa_emit_bcond_fp (rtx operands
[])
4781 enum rtx_code code
= GET_CODE (operands
[0]);
4782 rtx operand0
= operands
[1];
4783 rtx operand1
= operands
[2];
4784 rtx label
= operands
[3];
4786 emit_insn (gen_rtx_SET (gen_rtx_REG (CCFPmode
, 0),
4787 gen_rtx_fmt_ee (code
, CCFPmode
, operand0
, operand1
)));
4789 emit_jump_insn (gen_rtx_SET (pc_rtx
,
4790 gen_rtx_IF_THEN_ELSE (VOIDmode
,
4793 gen_rtx_REG (CCFPmode
, 0),
4795 gen_rtx_LABEL_REF (VOIDmode
, label
),
4800 /* Adjust the cost of a scheduling dependency. Return the new cost of
4801 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4804 pa_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
4807 enum attr_type attr_type
;
4809 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4810 true dependencies as they are described with bypasses now. */
4811 if (pa_cpu
>= PROCESSOR_8000
|| dep_type
== 0)
4814 if (! recog_memoized (insn
))
4817 attr_type
= get_attr_type (insn
);
4822 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4825 if (attr_type
== TYPE_FPLOAD
)
4827 rtx pat
= PATTERN (insn
);
4828 rtx dep_pat
= PATTERN (dep_insn
);
4829 if (GET_CODE (pat
) == PARALLEL
)
4831 /* This happens for the fldXs,mb patterns. */
4832 pat
= XVECEXP (pat
, 0, 0);
4834 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4835 /* If this happens, we have to extend this to schedule
4836 optimally. Return 0 for now. */
4839 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4841 if (! recog_memoized (dep_insn
))
4843 switch (get_attr_type (dep_insn
))
4850 case TYPE_FPSQRTSGL
:
4851 case TYPE_FPSQRTDBL
:
4852 /* A fpload can't be issued until one cycle before a
4853 preceding arithmetic operation has finished if
4854 the target of the fpload is any of the sources
4855 (or destination) of the arithmetic operation. */
4856 return insn_default_latency (dep_insn
) - 1;
4863 else if (attr_type
== TYPE_FPALU
)
4865 rtx pat
= PATTERN (insn
);
4866 rtx dep_pat
= PATTERN (dep_insn
);
4867 if (GET_CODE (pat
) == PARALLEL
)
4869 /* This happens for the fldXs,mb patterns. */
4870 pat
= XVECEXP (pat
, 0, 0);
4872 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4873 /* If this happens, we have to extend this to schedule
4874 optimally. Return 0 for now. */
4877 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
4879 if (! recog_memoized (dep_insn
))
4881 switch (get_attr_type (dep_insn
))
4885 case TYPE_FPSQRTSGL
:
4886 case TYPE_FPSQRTDBL
:
4887 /* An ALU flop can't be issued until two cycles before a
4888 preceding divide or sqrt operation has finished if
4889 the target of the ALU flop is any of the sources
4890 (or destination) of the divide or sqrt operation. */
4891 return insn_default_latency (dep_insn
) - 2;
4899 /* For other anti dependencies, the cost is 0. */
4902 case REG_DEP_OUTPUT
:
4903 /* Output dependency; DEP_INSN writes a register that INSN writes some
4905 if (attr_type
== TYPE_FPLOAD
)
4907 rtx pat
= PATTERN (insn
);
4908 rtx dep_pat
= PATTERN (dep_insn
);
4909 if (GET_CODE (pat
) == PARALLEL
)
4911 /* This happens for the fldXs,mb patterns. */
4912 pat
= XVECEXP (pat
, 0, 0);
4914 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4915 /* If this happens, we have to extend this to schedule
4916 optimally. Return 0 for now. */
4919 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4921 if (! recog_memoized (dep_insn
))
4923 switch (get_attr_type (dep_insn
))
4930 case TYPE_FPSQRTSGL
:
4931 case TYPE_FPSQRTDBL
:
4932 /* A fpload can't be issued until one cycle before a
4933 preceding arithmetic operation has finished if
4934 the target of the fpload is the destination of the
4935 arithmetic operation.
4937 Exception: For PA7100LC, PA7200 and PA7300, the cost
4938 is 3 cycles, unless they bundle together. We also
4939 pay the penalty if the second insn is a fpload. */
4940 return insn_default_latency (dep_insn
) - 1;
4947 else if (attr_type
== TYPE_FPALU
)
4949 rtx pat
= PATTERN (insn
);
4950 rtx dep_pat
= PATTERN (dep_insn
);
4951 if (GET_CODE (pat
) == PARALLEL
)
4953 /* This happens for the fldXs,mb patterns. */
4954 pat
= XVECEXP (pat
, 0, 0);
4956 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
4957 /* If this happens, we have to extend this to schedule
4958 optimally. Return 0 for now. */
4961 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
4963 if (! recog_memoized (dep_insn
))
4965 switch (get_attr_type (dep_insn
))
4969 case TYPE_FPSQRTSGL
:
4970 case TYPE_FPSQRTDBL
:
4971 /* An ALU flop can't be issued until two cycles before a
4972 preceding divide or sqrt operation has finished if
4973 the target of the ALU flop is also the target of
4974 the divide or sqrt operation. */
4975 return insn_default_latency (dep_insn
) - 2;
4983 /* For other output dependencies, the cost is 0. */
4991 /* The 700 can only issue a single insn at a time.
4992 The 7XXX processors can issue two insns at a time.
4993 The 8000 can issue 4 insns at a time. */
4995 pa_issue_rate (void)
4999 case PROCESSOR_700
: return 1;
5000 case PROCESSOR_7100
: return 2;
5001 case PROCESSOR_7100LC
: return 2;
5002 case PROCESSOR_7200
: return 2;
5003 case PROCESSOR_7300
: return 2;
5004 case PROCESSOR_8000
: return 4;
5013 /* Return any length plus adjustment needed by INSN which already has
5014 its length computed as LENGTH. Return LENGTH if no adjustment is
5017 Also compute the length of an inline block move here as it is too
5018 complicated to express as a length attribute in pa.md. */
5020 pa_adjust_insn_length (rtx_insn
*insn
, int length
)
5022 rtx pat
= PATTERN (insn
);
5024 /* If length is negative or undefined, provide initial length. */
5025 if ((unsigned int) length
>= INT_MAX
)
5027 if (GET_CODE (pat
) == SEQUENCE
)
5028 insn
= as_a
<rtx_insn
*> (XVECEXP (pat
, 0, 0));
5030 switch (get_attr_type (insn
))
5033 length
= pa_attr_length_millicode_call (insn
);
5036 length
= pa_attr_length_call (insn
, 0);
5039 length
= pa_attr_length_call (insn
, 1);
5042 length
= pa_attr_length_indirect_call (insn
);
5044 case TYPE_SH_FUNC_ADRS
:
5045 length
= pa_attr_length_millicode_call (insn
) + 20;
5052 /* Block move pattern. */
5053 if (NONJUMP_INSN_P (insn
)
5054 && GET_CODE (pat
) == PARALLEL
5055 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
5056 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
5057 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
5058 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
5059 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
5060 length
+= compute_cpymem_length (insn
) - 4;
5061 /* Block clear pattern. */
5062 else if (NONJUMP_INSN_P (insn
)
5063 && GET_CODE (pat
) == PARALLEL
5064 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
5065 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
5066 && XEXP (XVECEXP (pat
, 0, 0), 1) == const0_rtx
5067 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
)
5068 length
+= compute_clrmem_length (insn
) - 4;
5069 /* Conditional branch with an unfilled delay slot. */
5070 else if (JUMP_P (insn
) && ! simplejump_p (insn
))
5072 /* Adjust a short backwards conditional with an unfilled delay slot. */
5073 if (GET_CODE (pat
) == SET
5075 && JUMP_LABEL (insn
) != NULL_RTX
5076 && ! forward_branch_p (insn
))
5078 else if (GET_CODE (pat
) == PARALLEL
5079 && get_attr_type (insn
) == TYPE_PARALLEL_BRANCH
5082 /* Adjust dbra insn with short backwards conditional branch with
5083 unfilled delay slot -- only for case where counter is in a
5084 general register register. */
5085 else if (GET_CODE (pat
) == PARALLEL
5086 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
5087 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
5088 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
5090 && ! forward_branch_p (insn
))
5096 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
5099 pa_print_operand_punct_valid_p (unsigned char code
)
5110 /* Print operand X (an rtx) in assembler syntax to file FILE.
5111 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5112 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5115 pa_print_operand (FILE *file
, rtx x
, int code
)
5120 /* Output a 'nop' if there's nothing for the delay slot. */
5121 if (dbr_sequence_length () == 0)
5122 fputs ("\n\tnop", file
);
5125 /* Output a nullification completer if there's nothing for the */
5126 /* delay slot or nullification is requested. */
5127 if (dbr_sequence_length () == 0 ||
5129 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
5133 /* Print out the second register name of a register pair.
5134 I.e., R (6) => 7. */
5135 fputs (reg_names
[REGNO (x
) + 1], file
);
5138 /* A register or zero. */
5140 || (x
== CONST0_RTX (DFmode
))
5141 || (x
== CONST0_RTX (SFmode
)))
5143 fputs ("%r0", file
);
5149 /* A register or zero (floating point). */
5151 || (x
== CONST0_RTX (DFmode
))
5152 || (x
== CONST0_RTX (SFmode
)))
5154 fputs ("%fr0", file
);
5163 xoperands
[0] = XEXP (XEXP (x
, 0), 0);
5164 xoperands
[1] = XVECEXP (XEXP (XEXP (x
, 0), 1), 0, 0);
5165 pa_output_global_address (file
, xoperands
[1], 0);
5166 fprintf (file
, "(%s)", reg_names
[REGNO (xoperands
[0])]);
5170 case 'C': /* Plain (C)ondition */
5172 switch (GET_CODE (x
))
5175 fputs ("=", file
); break;
5177 fputs ("<>", file
); break;
5179 fputs (">", file
); break;
5181 fputs (">=", file
); break;
5183 fputs (">>=", file
); break;
5185 fputs (">>", file
); break;
5187 fputs ("<", file
); break;
5189 fputs ("<=", file
); break;
5191 fputs ("<<=", file
); break;
5193 fputs ("<<", file
); break;
5198 case 'N': /* Condition, (N)egated */
5199 switch (GET_CODE (x
))
5202 fputs ("<>", file
); break;
5204 fputs ("=", file
); break;
5206 fputs ("<=", file
); break;
5208 fputs ("<", file
); break;
5210 fputs ("<<", file
); break;
5212 fputs ("<<=", file
); break;
5214 fputs (">=", file
); break;
5216 fputs (">", file
); break;
5218 fputs (">>", file
); break;
5220 fputs (">>=", file
); break;
5225 /* For floating point comparisons. Note that the output
5226 predicates are the complement of the desired mode. The
5227 conditions for GT, GE, LT, LE and LTGT cause an invalid
5228 operation exception if the result is unordered and this
5229 exception is enabled in the floating-point status register. */
5231 switch (GET_CODE (x
))
5234 fputs ("!=", file
); break;
5236 fputs ("=", file
); break;
5238 fputs ("!>", file
); break;
5240 fputs ("!>=", file
); break;
5242 fputs ("!<", file
); break;
5244 fputs ("!<=", file
); break;
5246 fputs ("!<>", file
); break;
5248 fputs ("!?<=", file
); break;
5250 fputs ("!?<", file
); break;
5252 fputs ("!?>=", file
); break;
5254 fputs ("!?>", file
); break;
5256 fputs ("!?=", file
); break;
5258 fputs ("!?", file
); break;
5260 fputs ("?", file
); break;
5265 case 'S': /* Condition, operands are (S)wapped. */
5266 switch (GET_CODE (x
))
5269 fputs ("=", file
); break;
5271 fputs ("<>", file
); break;
5273 fputs ("<", file
); break;
5275 fputs ("<=", file
); break;
5277 fputs ("<<=", file
); break;
5279 fputs ("<<", file
); break;
5281 fputs (">", file
); break;
5283 fputs (">=", file
); break;
5285 fputs (">>=", file
); break;
5287 fputs (">>", file
); break;
5292 case 'B': /* Condition, (B)oth swapped and negate. */
5293 switch (GET_CODE (x
))
5296 fputs ("<>", file
); break;
5298 fputs ("=", file
); break;
5300 fputs (">=", file
); break;
5302 fputs (">", file
); break;
5304 fputs (">>", file
); break;
5306 fputs (">>=", file
); break;
5308 fputs ("<=", file
); break;
5310 fputs ("<", file
); break;
5312 fputs ("<<", file
); break;
5314 fputs ("<<=", file
); break;
5320 gcc_assert (GET_CODE (x
) == CONST_INT
);
5321 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~INTVAL (x
));
5324 gcc_assert (GET_CODE (x
) == CONST_INT
);
5325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - (INTVAL (x
) & 63));
5328 gcc_assert (GET_CODE (x
) == CONST_INT
);
5329 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - (INTVAL (x
) & 31));
5332 gcc_assert (GET_CODE (x
) == CONST_INT
5333 && (INTVAL (x
) == 1 || INTVAL (x
) == 2 || INTVAL (x
) == 3));
5334 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5337 gcc_assert (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0);
5338 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
5341 gcc_assert (GET_CODE (x
) == CONST_INT
);
5342 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 63 - (INTVAL (x
) & 63));
5345 gcc_assert (GET_CODE (x
) == CONST_INT
);
5346 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 31 - (INTVAL (x
) & 31));
5349 if (GET_CODE (x
) == CONST_INT
)
5354 switch (GET_CODE (XEXP (x
, 0)))
5358 if (ASSEMBLER_DIALECT
== 0)
5359 fputs ("s,mb", file
);
5361 fputs (",mb", file
);
5365 if (ASSEMBLER_DIALECT
== 0)
5366 fputs ("s,ma", file
);
5368 fputs (",ma", file
);
5371 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5372 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5374 if (ASSEMBLER_DIALECT
== 0)
5377 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5378 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5380 if (ASSEMBLER_DIALECT
== 0)
5381 fputs ("x,s", file
);
5385 else if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5389 if (code
== 'F' && ASSEMBLER_DIALECT
== 0)
5395 pa_output_global_address (file
, x
, 0);
5398 pa_output_global_address (file
, x
, 1);
5400 case 0: /* Don't do anything special */
5405 compute_zdepwi_operands (INTVAL (x
), op
);
5406 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5412 compute_zdepdi_operands (INTVAL (x
), op
);
5413 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
5417 /* We can get here from a .vtable_inherit due to our
5418 CONSTANT_ADDRESS_P rejecting perfectly good constant
5424 if (GET_CODE (x
) == REG
)
5426 fputs (reg_names
[REGNO (x
)], file
);
5427 if (TARGET_64BIT
&& FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4)
5433 && GET_MODE_SIZE (GET_MODE (x
)) <= 4
5434 && (REGNO (x
) & 1) == 0)
5437 else if (GET_CODE (x
) == MEM
)
5439 int size
= GET_MODE_SIZE (GET_MODE (x
));
5440 rtx base
= NULL_RTX
;
5441 switch (GET_CODE (XEXP (x
, 0)))
5445 base
= XEXP (XEXP (x
, 0), 0);
5446 fprintf (file
, "-%d(%s)", size
, reg_names
[REGNO (base
)]);
5450 base
= XEXP (XEXP (x
, 0), 0);
5451 fprintf (file
, "%d(%s)", size
, reg_names
[REGNO (base
)]);
5454 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
)
5455 fprintf (file
, "%s(%s)",
5456 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 0), 0))],
5457 reg_names
[REGNO (XEXP (XEXP (x
, 0), 1))]);
5458 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == MULT
)
5459 fprintf (file
, "%s(%s)",
5460 reg_names
[REGNO (XEXP (XEXP (XEXP (x
, 0), 1), 0))],
5461 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
5462 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
5463 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
)
5465 /* Because the REG_POINTER flag can get lost during reload,
5466 pa_legitimate_address_p canonicalizes the order of the
5467 index and base registers in the combined move patterns. */
5468 rtx base
= XEXP (XEXP (x
, 0), 1);
5469 rtx index
= XEXP (XEXP (x
, 0), 0);
5471 fprintf (file
, "%s(%s)",
5472 reg_names
[REGNO (index
)], reg_names
[REGNO (base
)]);
5475 output_address (GET_MODE (x
), XEXP (x
, 0));
5478 output_address (GET_MODE (x
), XEXP (x
, 0));
5483 output_addr_const (file
, x
);
5486 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5489 pa_output_global_address (FILE *file
, rtx x
, int round_constant
)
5492 /* Imagine (high (const (plus ...))). */
5493 if (GET_CODE (x
) == HIGH
)
5496 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
, VOIDmode
))
5497 output_addr_const (file
, x
);
5498 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
5500 output_addr_const (file
, x
);
5501 fputs ("-$global$", file
);
5503 else if (GET_CODE (x
) == CONST
)
5505 const char *sep
= "";
5506 int offset
= 0; /* assembler wants -$global$ at end */
5507 rtx base
= NULL_RTX
;
5509 switch (GET_CODE (XEXP (XEXP (x
, 0), 0)))
5513 base
= XEXP (XEXP (x
, 0), 0);
5514 output_addr_const (file
, base
);
5517 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
5523 switch (GET_CODE (XEXP (XEXP (x
, 0), 1)))
5527 base
= XEXP (XEXP (x
, 0), 1);
5528 output_addr_const (file
, base
);
5531 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
5537 /* How bogus. The compiler is apparently responsible for
5538 rounding the constant if it uses an LR field selector.
5540 The linker and/or assembler seem a better place since
5541 they have to do this kind of thing already.
5543 If we fail to do this, HP's optimizing linker may eliminate
5544 an addil, but not update the ldw/stw/ldo instruction that
5545 uses the result of the addil. */
5547 offset
= ((offset
+ 0x1000) & ~0x1fff);
5549 switch (GET_CODE (XEXP (x
, 0)))
5562 gcc_assert (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
);
5570 if (!read_only_operand (base
, VOIDmode
) && !flag_pic
)
5571 fputs ("-$global$", file
);
5573 fprintf (file
, "%s%d", sep
, offset
);
5576 output_addr_const (file
, x
);
5579 /* Output boilerplate text to appear at the beginning of the file.
5580 There are several possible versions. */
5581 #define aputs(x) fputs(x, asm_out_file)
5583 pa_file_start_level (void)
5586 aputs ("\t.LEVEL 2.0w\n");
5587 else if (TARGET_PA_20
)
5588 aputs ("\t.LEVEL 2.0\n");
5589 else if (TARGET_PA_11
)
5590 aputs ("\t.LEVEL 1.1\n");
5592 aputs ("\t.LEVEL 1.0\n");
5596 pa_file_start_space (int sortspace
)
5598 aputs ("\t.SPACE $PRIVATE$");
5601 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31");
5603 aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31");
5604 aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5605 "\n\t.SPACE $TEXT$");
5608 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5609 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5613 pa_file_start_file (int want_version
)
5615 if (write_symbols
!= NO_DEBUG
)
5617 output_file_directive (asm_out_file
, main_input_filename
);
5619 aputs ("\t.version\t\"01.01\"\n");
5624 pa_file_start_mcount (const char *aswhat
)
5627 fprintf (asm_out_file
, "\t.IMPORT _mcount,%s\n", aswhat
);
5631 pa_elf_file_start (void)
5633 pa_file_start_level ();
5634 pa_file_start_mcount ("ENTRY");
5635 pa_file_start_file (0);
5639 pa_som_file_start (void)
5641 pa_file_start_level ();
5642 pa_file_start_space (0);
5643 aputs ("\t.IMPORT $global$,DATA\n"
5644 "\t.IMPORT $$dyncall,MILLICODE\n");
5645 pa_file_start_mcount ("CODE");
5646 pa_file_start_file (0);
5650 pa_linux_file_start (void)
5652 pa_file_start_file (1);
5653 pa_file_start_level ();
5654 pa_file_start_mcount ("CODE");
5658 pa_hpux64_gas_file_start (void)
5660 pa_file_start_level ();
5661 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5663 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, "_mcount", "function");
5665 pa_file_start_file (1);
5669 pa_hpux64_hpas_file_start (void)
5671 pa_file_start_level ();
5672 pa_file_start_space (1);
5673 pa_file_start_mcount ("CODE");
5674 pa_file_start_file (0);
5678 /* Search the deferred plabel list for SYMBOL and return its internal
5679 label. If an entry for SYMBOL is not found, a new entry is created. */
5682 pa_get_deferred_plabel (rtx symbol
)
5684 const char *fname
= XSTR (symbol
, 0);
5687 /* See if we have already put this function on the list of deferred
5688 plabels. This list is generally small, so a liner search is not
5689 too ugly. If it proves too slow replace it with something faster. */
5690 for (i
= 0; i
< n_deferred_plabels
; i
++)
5691 if (strcmp (fname
, XSTR (deferred_plabels
[i
].symbol
, 0)) == 0)
5694 /* If the deferred plabel list is empty, or this entry was not found
5695 on the list, create a new entry on the list. */
5696 if (deferred_plabels
== NULL
|| i
== n_deferred_plabels
)
5700 if (deferred_plabels
== 0)
5701 deferred_plabels
= ggc_alloc
<deferred_plabel
> ();
5703 deferred_plabels
= GGC_RESIZEVEC (struct deferred_plabel
,
5705 n_deferred_plabels
+ 1);
5707 i
= n_deferred_plabels
++;
5708 deferred_plabels
[i
].internal_label
= gen_label_rtx ();
5709 deferred_plabels
[i
].symbol
= symbol
;
5711 /* Gross. We have just implicitly taken the address of this
5712 function. Mark it in the same manner as assemble_name. */
5713 id
= maybe_get_identifier (targetm
.strip_name_encoding (fname
));
5715 mark_referenced (id
);
5718 return deferred_plabels
[i
].internal_label
;
5722 output_deferred_plabels (void)
5726 /* If we have some deferred plabels, then we need to switch into the
5727 data or readonly data section, and align it to a 4 byte boundary
5728 before outputting the deferred plabels. */
5729 if (n_deferred_plabels
)
5731 switch_to_section (flag_pic
? data_section
: readonly_data_section
);
5732 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
5735 /* Now output the deferred plabels. */
5736 for (i
= 0; i
< n_deferred_plabels
; i
++)
5738 targetm
.asm_out
.internal_label (asm_out_file
, "L",
5739 CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
5740 assemble_integer (deferred_plabels
[i
].symbol
,
5741 TARGET_64BIT
? 8 : 4, TARGET_64BIT
? 64 : 32, 1);
5745 /* Initialize optabs to point to emulation routines. */
5748 pa_init_libfuncs (void)
5750 if (HPUX_LONG_DOUBLE_LIBRARY
)
5752 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
5753 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
5754 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
5755 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
5756 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qmin");
5757 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
5758 set_optab_libfunc (sqrt_optab
, TFmode
, "_U_Qfsqrt");
5759 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
5760 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
5762 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
5763 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
5764 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
5765 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
5766 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
5767 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
5768 set_optab_libfunc (unord_optab
, TFmode
, "_U_Qfunord");
5770 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
5771 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
5772 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
5773 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
5775 set_conv_libfunc (sfix_optab
, SImode
, TFmode
,
5776 TARGET_64BIT
? "__U_Qfcnvfxt_quad_to_sgl"
5777 : "_U_Qfcnvfxt_quad_to_sgl");
5778 set_conv_libfunc (sfix_optab
, DImode
, TFmode
,
5779 "_U_Qfcnvfxt_quad_to_dbl");
5780 set_conv_libfunc (ufix_optab
, SImode
, TFmode
,
5781 "_U_Qfcnvfxt_quad_to_usgl");
5782 set_conv_libfunc (ufix_optab
, DImode
, TFmode
,
5783 "_U_Qfcnvfxt_quad_to_udbl");
5785 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
,
5786 "_U_Qfcnvxf_sgl_to_quad");
5787 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
,
5788 "_U_Qfcnvxf_dbl_to_quad");
5789 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
,
5790 "_U_Qfcnvxf_usgl_to_quad");
5791 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
,
5792 "_U_Qfcnvxf_udbl_to_quad");
5795 if (TARGET_SYNC_LIBCALL
)
5796 init_sync_libfuncs (8);
5799 /* HP's millicode routines mean something special to the assembler.
5800 Keep track of which ones we have used. */
5802 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, end1000
};
5803 static void import_milli (enum millicodes
);
5804 static char imported
[(int) end1000
];
5805 static const char * const milli_names
[] = {"remI", "remU", "divI", "divU", "mulI"};
5806 static const char import_string
[] = ".IMPORT $$....,MILLICODE";
5807 #define MILLI_START 10
5810 import_milli (enum millicodes code
)
5812 char str
[sizeof (import_string
)];
5814 if (!imported
[(int) code
])
5816 imported
[(int) code
] = 1;
5817 strcpy (str
, import_string
);
5818 strncpy (str
+ MILLI_START
, milli_names
[(int) code
], 4);
5819 output_asm_insn (str
, 0);
5823 /* The register constraints have put the operands and return value in
5824 the proper registers. */
5827 pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
5829 import_milli (mulI
);
5830 return pa_output_millicode_call (insn
, gen_rtx_SYMBOL_REF (Pmode
, "$$mulI"));
5833 /* Emit the rtl for doing a division by a constant. */
5835 /* Do magic division millicodes exist for this value? */
5836 const int pa_magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5838 /* We'll use an array to keep track of the magic millicodes and
5839 whether or not we've used them already. [n][0] is signed, [n][1] is
5842 static int div_milli
[16][2];
5845 pa_emit_hpdiv_const (rtx
*operands
, int unsignedp
)
5847 if (GET_CODE (operands
[2]) == CONST_INT
5848 && INTVAL (operands
[2]) > 0
5849 && INTVAL (operands
[2]) < 16
5850 && pa_magic_milli
[INTVAL (operands
[2])])
5852 rtx ret
= gen_rtx_REG (SImode
, TARGET_64BIT
? 2 : 31);
5854 emit_move_insn (gen_rtx_REG (SImode
, 26), operands
[1]);
5858 gen_rtvec (6, gen_rtx_SET (gen_rtx_REG (SImode
, 29),
5859 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
5861 gen_rtx_REG (SImode
, 26),
5863 gen_rtx_CLOBBER (VOIDmode
, operands
[4]),
5864 gen_rtx_CLOBBER (VOIDmode
, operands
[3]),
5865 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 26)),
5866 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 25)),
5867 gen_rtx_CLOBBER (VOIDmode
, ret
))));
5868 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 29));
5875 pa_output_div_insn (rtx
*operands
, int unsignedp
, rtx_insn
*insn
)
5879 /* If the divisor is a constant, try to use one of the special
5881 if (GET_CODE (operands
[0]) == CONST_INT
)
5883 static char buf
[100];
5884 divisor
= INTVAL (operands
[0]);
5885 if (!div_milli
[divisor
][unsignedp
])
5887 div_milli
[divisor
][unsignedp
] = 1;
5889 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
5891 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
5895 sprintf (buf
, "$$divU_" HOST_WIDE_INT_PRINT_DEC
,
5896 INTVAL (operands
[0]));
5897 return pa_output_millicode_call (insn
,
5898 gen_rtx_SYMBOL_REF (SImode
, buf
));
5902 sprintf (buf
, "$$divI_" HOST_WIDE_INT_PRINT_DEC
,
5903 INTVAL (operands
[0]));
5904 return pa_output_millicode_call (insn
,
5905 gen_rtx_SYMBOL_REF (SImode
, buf
));
5908 /* Divisor isn't a special constant. */
5913 import_milli (divU
);
5914 return pa_output_millicode_call (insn
,
5915 gen_rtx_SYMBOL_REF (SImode
, "$$divU"));
5919 import_milli (divI
);
5920 return pa_output_millicode_call (insn
,
5921 gen_rtx_SYMBOL_REF (SImode
, "$$divI"));
5926 /* Output a $$rem millicode to do mod. */
5929 pa_output_mod_insn (int unsignedp
, rtx_insn
*insn
)
5933 import_milli (remU
);
5934 return pa_output_millicode_call (insn
,
5935 gen_rtx_SYMBOL_REF (SImode
, "$$remU"));
5939 import_milli (remI
);
5940 return pa_output_millicode_call (insn
,
5941 gen_rtx_SYMBOL_REF (SImode
, "$$remI"));
5946 pa_output_arg_descriptor (rtx_insn
*call_insn
)
5948 const char *arg_regs
[4];
5949 machine_mode arg_mode
;
5951 int i
, output_flag
= 0;
5954 /* We neither need nor want argument location descriptors for the
5955 64bit runtime environment or the ELF32 environment. */
5956 if (TARGET_64BIT
|| TARGET_ELF32
)
5959 for (i
= 0; i
< 4; i
++)
5962 /* Specify explicitly that no argument relocations should take place
5963 if using the portable runtime calling conventions. */
5964 if (TARGET_PORTABLE_RUNTIME
)
5966 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5971 gcc_assert (CALL_P (call_insn
));
5972 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
);
5973 link
; link
= XEXP (link
, 1))
5975 rtx use
= XEXP (link
, 0);
5977 if (! (GET_CODE (use
) == USE
5978 && GET_CODE (XEXP (use
, 0)) == REG
5979 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
5982 arg_mode
= GET_MODE (XEXP (use
, 0));
5983 regno
= REGNO (XEXP (use
, 0));
5984 if (regno
>= 23 && regno
<= 26)
5986 arg_regs
[26 - regno
] = "GR";
5987 if (arg_mode
== DImode
)
5988 arg_regs
[25 - regno
] = "GR";
5990 else if (regno
>= 32 && regno
<= 39)
5992 if (arg_mode
== SFmode
)
5993 arg_regs
[(regno
- 32) / 2] = "FR";
5996 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5997 arg_regs
[(regno
- 34) / 2] = "FR";
5998 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
6000 arg_regs
[(regno
- 34) / 2] = "FU";
6001 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
6006 fputs ("\t.CALL ", asm_out_file
);
6007 for (i
= 0; i
< 4; i
++)
6012 fputc (',', asm_out_file
);
6013 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
6016 fputc ('\n', asm_out_file
);
6019 /* Inform reload about cases where moving X with a mode MODE to or from
6020 a register in RCLASS requires an extra scratch or immediate register.
6021 Return the class needed for the immediate register. */
6024 pa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
6025 machine_mode mode
, secondary_reload_info
*sri
)
6028 enum reg_class rclass
= (enum reg_class
) rclass_i
;
6030 /* Handle the easy stuff first. */
6031 if (rclass
== R1_REGS
)
6037 if (rclass
== BASE_REG_CLASS
&& regno
< FIRST_PSEUDO_REGISTER
)
6043 /* If we have something like (mem (mem (...)), we can safely assume the
6044 inner MEM will end up in a general register after reloading, so there's
6045 no need for a secondary reload. */
6046 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == MEM
)
6049 /* Trying to load a constant into a FP register during PIC code
6050 generation requires %r1 as a scratch register. For float modes,
6051 the only legitimate constant is CONST0_RTX. However, there are
6052 a few patterns that accept constant double operands. */
6054 && FP_REG_CLASS_P (rclass
)
6055 && (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
))
6060 sri
->icode
= CODE_FOR_reload_insi_r1
;
6064 sri
->icode
= CODE_FOR_reload_indi_r1
;
6068 sri
->icode
= CODE_FOR_reload_insf_r1
;
6072 sri
->icode
= CODE_FOR_reload_indf_r1
;
6081 /* Secondary reloads of symbolic expressions require %r1 as a scratch
6082 register when we're generating PIC code or when the operand isn't
6084 if (pa_symbolic_expression_p (x
))
6086 if (GET_CODE (x
) == HIGH
)
6089 if (flag_pic
|| !read_only_operand (x
, VOIDmode
))
6094 sri
->icode
= CODE_FOR_reload_insi_r1
;
6098 sri
->icode
= CODE_FOR_reload_indi_r1
;
6108 /* Profiling showed the PA port spends about 1.3% of its compilation
6109 time in true_regnum from calls inside pa_secondary_reload_class. */
6110 if (regno
>= FIRST_PSEUDO_REGISTER
|| GET_CODE (x
) == SUBREG
)
6111 regno
= true_regnum (x
);
6113 /* Handle reloads for floating point loads and stores. */
6114 if ((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
6115 && FP_REG_CLASS_P (rclass
))
6121 /* We don't need a secondary reload for indexed memory addresses.
6123 When INT14_OK_STRICT is true, it might appear that we could
6124 directly allow register indirect memory addresses. However,
6125 this doesn't work because we don't support SUBREGs in
6126 floating-point register copies and reload doesn't tell us
6127 when it's going to use a SUBREG. */
6128 if (IS_INDEX_ADDR_P (x
))
6132 /* Request a secondary reload with a general scratch register
6133 for everything else. ??? Could symbolic operands be handled
6134 directly when generating non-pic PA 2.0 code? */
6136 ? direct_optab_handler (reload_in_optab
, mode
)
6137 : direct_optab_handler (reload_out_optab
, mode
));
6141 /* A SAR<->FP register copy requires an intermediate general register
6142 and secondary memory. We need a secondary reload with a general
6143 scratch register for spills. */
6144 if (rclass
== SHIFT_REGS
)
6147 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
< 0)
6150 ? direct_optab_handler (reload_in_optab
, mode
)
6151 : direct_optab_handler (reload_out_optab
, mode
));
6155 /* Handle FP copy. */
6156 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno
)))
6157 return GENERAL_REGS
;
6160 if (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
6161 && REGNO_REG_CLASS (regno
) == SHIFT_REGS
6162 && FP_REG_CLASS_P (rclass
))
6163 return GENERAL_REGS
;
6168 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. */
6171 pa_secondary_memory_needed (machine_mode mode ATTRIBUTE_UNUSED
,
6172 reg_class_t class1 ATTRIBUTE_UNUSED
,
6173 reg_class_t class2 ATTRIBUTE_UNUSED
)
6175 #ifdef PA_SECONDARY_MEMORY_NEEDED
6176 return PA_SECONDARY_MEMORY_NEEDED (mode
, class1
, class2
);
6182 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
6183 is only marked as live on entry by df-scan when it is a fixed
6184 register. It isn't a fixed register in the 64-bit runtime,
6185 so we need to mark it here. */
6188 pa_extra_live_on_entry (bitmap regs
)
6191 bitmap_set_bit (regs
, ARG_POINTER_REGNUM
);
6194 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
6195 to prevent it from being deleted. */
6198 pa_eh_return_handler_rtx (void)
6202 tmp
= gen_rtx_PLUS (word_mode
, hard_frame_pointer_rtx
,
6203 TARGET_64BIT
? GEN_INT (-16) : GEN_INT (-20));
6204 tmp
= gen_rtx_MEM (word_mode
, tmp
);
6209 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6210 by invisible reference. As a GCC extension, we also pass anything
6211 with a zero or variable size by reference.
6213 The 64-bit runtime does not describe passing any types by invisible
6214 reference. The internals of GCC can't currently handle passing
6215 empty structures, and zero or variable length arrays when they are
6216 not passed entirely on the stack or by reference. Thus, as a GCC
6217 extension, we pass these types by reference. The HP compiler doesn't
6218 support these types, so hopefully there shouldn't be any compatibility
6219 issues. This may have to be revisited when HP releases a C99 compiler
6220 or updates the ABI. */
6223 pa_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
6225 HOST_WIDE_INT size
= arg
.type_size_in_bytes ();
6229 return size
<= 0 || size
> 8;
6232 /* Implement TARGET_FUNCTION_ARG_PADDING. */
6234 static pad_direction
6235 pa_function_arg_padding (machine_mode mode
, const_tree type
)
6240 && (AGGREGATE_TYPE_P (type
)
6241 || TREE_CODE (type
) == COMPLEX_TYPE
6242 || TREE_CODE (type
) == VECTOR_TYPE
)))
6244 /* Return PAD_NONE if justification is not required. */
6246 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
6247 && (int_size_in_bytes (type
) * BITS_PER_UNIT
) % PARM_BOUNDARY
== 0)
6250 /* The directions set here are ignored when a BLKmode argument larger
6251 than a word is placed in a register. Different code is used for
6252 the stack and registers. This makes it difficult to have a
6253 consistent data representation for both the stack and registers.
6254 For both runtimes, the justification and padding for arguments on
6255 the stack and in registers should be identical. */
6257 /* The 64-bit runtime specifies left justification for aggregates. */
6260 /* The 32-bit runtime architecture specifies right justification.
6261 When the argument is passed on the stack, the argument is padded
6262 with garbage on the left. The HP compiler pads with zeros. */
6263 return PAD_DOWNWARD
;
6266 if (GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
6267 return PAD_DOWNWARD
;
6273 /* Do what is necessary for `va_start'. We look at the current function
6274 to determine if stdargs or varargs is used and fill in an initial
6275 va_list. A pointer to this constructor is returned. */
6278 hppa_builtin_saveregs (void)
6281 tree fntype
= TREE_TYPE (current_function_decl
);
6282 int argadj
= ((!stdarg_p (fntype
))
6283 ? UNITS_PER_WORD
: 0);
6286 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
6288 offset
= crtl
->args
.arg_offset_rtx
;
6294 /* Adjust for varargs/stdarg differences. */
6296 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, -argadj
);
6298 offset
= crtl
->args
.arg_offset_rtx
;
6300 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6301 from the incoming arg pointer and growing to larger addresses. */
6302 for (i
= 26, off
= -64; i
>= 19; i
--, off
+= 8)
6303 emit_move_insn (gen_rtx_MEM (word_mode
,
6304 plus_constant (Pmode
,
6305 arg_pointer_rtx
, off
)),
6306 gen_rtx_REG (word_mode
, i
));
6308 /* The incoming args pointer points just beyond the flushback area;
6309 normally this is not a serious concern. However, when we are doing
6310 varargs/stdargs we want to make the arg pointer point to the start
6311 of the incoming argument area. */
6312 emit_move_insn (virtual_incoming_args_rtx
,
6313 plus_constant (Pmode
, arg_pointer_rtx
, -64));
6315 /* Now return a pointer to the first anonymous argument. */
6316 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6317 virtual_incoming_args_rtx
,
6318 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6321 /* Store general registers on the stack. */
6322 dest
= gen_rtx_MEM (BLKmode
,
6323 plus_constant (Pmode
, crtl
->args
.internal_arg_pointer
,
6325 set_mem_alias_set (dest
, get_varargs_alias_set ());
6326 set_mem_align (dest
, BITS_PER_WORD
);
6327 move_block_from_reg (23, dest
, 4);
6329 /* move_block_from_reg will emit code to store the argument registers
6330 individually as scalar stores.
6332 However, other insns may later load from the same addresses for
6333 a structure load (passing a struct to a varargs routine).
6335 The alias code assumes that such aliasing can never happen, so we
6336 have to keep memory referencing insns from moving up beyond the
6337 last argument register store. So we emit a blockage insn here. */
6338 emit_insn (gen_blockage ());
6340 return copy_to_reg (expand_binop (Pmode
, add_optab
,
6341 crtl
->args
.internal_arg_pointer
,
6342 offset
, 0, 0, OPTAB_LIB_WIDEN
));
6346 hppa_va_start (tree valist
, rtx nextarg
)
6348 nextarg
= expand_builtin_saveregs ();
6349 std_expand_builtin_va_start (valist
, nextarg
);
6353 hppa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6358 /* Args grow upward. We can use the generic routines. */
6359 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6361 else /* !TARGET_64BIT */
6363 tree ptr
= build_pointer_type (type
);
6366 unsigned int size
, ofs
;
6369 indirect
= pass_va_arg_by_reference (type
);
6373 ptr
= build_pointer_type (type
);
6375 size
= int_size_in_bytes (type
);
6376 valist_type
= TREE_TYPE (valist
);
6378 /* Args grow down. Not handled by generic routines. */
6380 u
= fold_convert (sizetype
, size_in_bytes (type
));
6381 u
= fold_build1 (NEGATE_EXPR
, sizetype
, u
);
6382 t
= fold_build_pointer_plus (valist
, u
);
6384 /* Align to 4 or 8 byte boundary depending on argument size. */
6386 u
= build_int_cst (TREE_TYPE (t
), (HOST_WIDE_INT
)(size
> 4 ? -8 : -4));
6387 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6388 t
= fold_convert (valist_type
, t
);
6390 t
= build2 (MODIFY_EXPR
, valist_type
, valist
, t
);
6392 ofs
= (8 - size
) % 4;
6394 t
= fold_build_pointer_plus_hwi (t
, ofs
);
6396 t
= fold_convert (ptr
, t
);
6397 t
= build_va_arg_indirect_ref (t
);
6400 t
= build_va_arg_indirect_ref (t
);
6406 /* True if MODE is valid for the target. By "valid", we mean able to
6407 be manipulated in non-trivial ways. In particular, this means all
6408 the arithmetic is supported.
6410 Currently, TImode is not valid as the HP 64-bit runtime documentation
6411 doesn't document the alignment and calling conventions for this type.
6412 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6413 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6416 pa_scalar_mode_supported_p (scalar_mode mode
)
6418 int precision
= GET_MODE_PRECISION (mode
);
6420 switch (GET_MODE_CLASS (mode
))
6422 case MODE_PARTIAL_INT
:
6424 if (precision
== CHAR_TYPE_SIZE
)
6426 if (precision
== SHORT_TYPE_SIZE
)
6428 if (precision
== INT_TYPE_SIZE
)
6430 if (precision
== LONG_TYPE_SIZE
)
6432 if (precision
== LONG_LONG_TYPE_SIZE
)
6437 if (precision
== FLOAT_TYPE_SIZE
)
6439 if (precision
== DOUBLE_TYPE_SIZE
)
6441 if (precision
== LONG_DOUBLE_TYPE_SIZE
)
6445 case MODE_DECIMAL_FLOAT
:
6453 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6454 it branches into the delay slot. Otherwise, return FALSE. */
6457 branch_to_delay_slot_p (rtx_insn
*insn
)
6459 rtx_insn
*jump_insn
;
6461 if (dbr_sequence_length ())
6464 jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6467 insn
= next_active_insn (insn
);
6468 if (jump_insn
== insn
)
6471 /* We can't rely on the length of asms. So, we return FALSE when
6472 the branch is followed by an asm. */
6474 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6475 || asm_noperands (PATTERN (insn
)) >= 0
6476 || get_attr_length (insn
) > 0)
6483 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6485 This occurs when INSN has an unfilled delay slot and is followed
6486 by an asm. Disaster can occur if the asm is empty and the jump
6487 branches into the delay slot. So, we add a nop in the delay slot
6488 when this occurs. */
6491 branch_needs_nop_p (rtx_insn
*insn
)
6493 rtx_insn
*jump_insn
;
6495 if (dbr_sequence_length ())
6498 jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6501 insn
= next_active_insn (insn
);
6502 if (!insn
|| jump_insn
== insn
)
6505 if (!(GET_CODE (PATTERN (insn
)) == ASM_INPUT
6506 || asm_noperands (PATTERN (insn
)) >= 0)
6507 && get_attr_length (insn
) > 0)
6514 /* Return TRUE if INSN, a forward jump insn, can use nullification
6515 to skip the following instruction. This avoids an extra cycle due
6516 to a mis-predicted branch when we fall through. */
6519 use_skip_p (rtx_insn
*insn
)
6521 rtx_insn
*jump_insn
= next_active_insn (JUMP_LABEL_AS_INSN (insn
));
6525 insn
= next_active_insn (insn
);
6527 /* We can't rely on the length of asms, so we can't skip asms. */
6529 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
6530 || asm_noperands (PATTERN (insn
)) >= 0)
6532 if (get_attr_length (insn
) == 4
6533 && jump_insn
== next_active_insn (insn
))
6535 if (get_attr_length (insn
) > 0)
6542 /* This routine handles all the normal conditional branch sequences we
6543 might need to generate. It handles compare immediate vs compare
6544 register, nullification of delay slots, varying length branches,
6545 negated branches, and all combinations of the above. It returns the
6546 output appropriate to emit the branch corresponding to all given
6550 pa_output_cbranch (rtx
*operands
, int negated
, rtx_insn
*insn
)
6552 static char buf
[100];
6554 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6555 int length
= get_attr_length (insn
);
6558 /* A conditional branch to the following instruction (e.g. the delay slot)
6559 is asking for a disaster. This can happen when not optimizing and
6560 when jump optimization fails.
6562 While it is usually safe to emit nothing, this can fail if the
6563 preceding instruction is a nullified branch with an empty delay
6564 slot and the same branch target as this branch. We could check
6565 for this but jump optimization should eliminate nop jumps. It
6566 is always safe to emit a nop. */
6567 if (branch_to_delay_slot_p (insn
))
6570 /* The doubleword form of the cmpib instruction doesn't have the LEU
6571 and GTU conditions while the cmpb instruction does. Since we accept
6572 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6573 if (GET_MODE (operands
[1]) == DImode
&& operands
[2] == const0_rtx
)
6574 operands
[2] = gen_rtx_REG (DImode
, 0);
6575 if (GET_MODE (operands
[2]) == DImode
&& operands
[1] == const0_rtx
)
6576 operands
[1] = gen_rtx_REG (DImode
, 0);
6578 /* If this is a long branch with its delay slot unfilled, set `nullify'
6579 as it can nullify the delay slot and save a nop. */
6580 if (length
== 8 && dbr_sequence_length () == 0)
6583 /* If this is a short forward conditional branch which did not get
6584 its delay slot filled, the delay slot can still be nullified. */
6585 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6586 nullify
= forward_branch_p (insn
);
6588 /* A forward branch over a single nullified insn can be done with a
6589 comclr instruction. This avoids a single cycle penalty due to
6590 mis-predicted branch if we fall through (branch not taken). */
6591 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6595 /* All short conditional branches except backwards with an unfilled
6599 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6601 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6602 if (GET_MODE (operands
[1]) == DImode
)
6605 strcat (buf
, "%B3");
6607 strcat (buf
, "%S3");
6609 strcat (buf
, " %2,%r1,%%r0");
6612 if (branch_needs_nop_p (insn
))
6613 strcat (buf
, ",n %2,%r1,%0%#");
6615 strcat (buf
, ",n %2,%r1,%0");
6618 strcat (buf
, " %2,%r1,%0");
6621 /* All long conditionals. Note a short backward branch with an
6622 unfilled delay slot is treated just like a long backward branch
6623 with an unfilled delay slot. */
6625 /* Handle weird backwards branch with a filled delay slot
6626 which is nullified. */
6627 if (dbr_sequence_length () != 0
6628 && ! forward_branch_p (insn
)
6631 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6632 if (GET_MODE (operands
[1]) == DImode
)
6635 strcat (buf
, "%S3");
6637 strcat (buf
, "%B3");
6638 strcat (buf
, ",n %2,%r1,.+12\n\tb %0");
6640 /* Handle short backwards branch with an unfilled delay slot.
6641 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6642 taken and untaken branches. */
6643 else if (dbr_sequence_length () == 0
6644 && ! forward_branch_p (insn
)
6645 && INSN_ADDRESSES_SET_P ()
6646 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
6647 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
6649 strcpy (buf
, "{com%I2b,|cmp%I2b,}");
6650 if (GET_MODE (operands
[1]) == DImode
)
6653 strcat (buf
, "%B3 %2,%r1,%0%#");
6655 strcat (buf
, "%S3 %2,%r1,%0%#");
6659 strcpy (buf
, "{com%I2clr,|cmp%I2clr,}");
6660 if (GET_MODE (operands
[1]) == DImode
)
6663 strcat (buf
, "%S3");
6665 strcat (buf
, "%B3");
6667 strcat (buf
, " %2,%r1,%%r0\n\tb,n %0");
6669 strcat (buf
, " %2,%r1,%%r0\n\tb %0");
6674 /* The reversed conditional branch must branch over one additional
6675 instruction if the delay slot is filled and needs to be extracted
6676 by pa_output_lbranch. If the delay slot is empty or this is a
6677 nullified forward branch, the instruction after the reversed
6678 condition branch must be nullified. */
6679 if (dbr_sequence_length () == 0
6680 || (nullify
&& forward_branch_p (insn
)))
6684 operands
[4] = GEN_INT (length
);
6689 operands
[4] = GEN_INT (length
+ 4);
6692 /* Create a reversed conditional branch which branches around
6693 the following insns. */
6694 if (GET_MODE (operands
[1]) != DImode
)
6700 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6703 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6709 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6712 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6721 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6724 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6730 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6733 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6737 output_asm_insn (buf
, operands
);
6738 return pa_output_lbranch (operands
[0], insn
, xdelay
);
6743 /* Output a PIC pc-relative instruction sequence to load the address of
6744 OPERANDS[0] to register OPERANDS[2]. OPERANDS[0] is a symbol ref
6745 or a code label. OPERANDS[1] specifies the register to use to load
6746 the program counter. OPERANDS[3] may be used for label generation
6747 The sequence is always three instructions in length. The program
6748 counter recorded for PA 1.X is eight bytes more than that for PA 2.0.
6749 Register %r1 is clobbered. */
6752 pa_output_pic_pcrel_sequence (rtx
*operands
)
6754 gcc_assert (SYMBOL_REF_P (operands
[0]) || LABEL_P (operands
[0]));
6757 /* We can use mfia to determine the current program counter. */
6758 if (TARGET_SOM
|| !TARGET_GAS
)
6760 operands
[3] = gen_label_rtx ();
6761 targetm
.asm_out
.internal_label (asm_out_file
, "L",
6762 CODE_LABEL_NUMBER (operands
[3]));
6763 output_asm_insn ("mfia %1", operands
);
6764 output_asm_insn ("addil L'%0-%l3,%1", operands
);
6765 output_asm_insn ("ldo R'%0-%l3(%%r1),%2", operands
);
6769 output_asm_insn ("mfia %1", operands
);
6770 output_asm_insn ("addil L'%0-$PIC_pcrel$0+12,%1", operands
);
6771 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+16(%%r1),%2", operands
);
6776 /* We need to use a branch to determine the current program counter. */
6777 output_asm_insn ("{bl|b,l} .+8,%1", operands
);
6778 if (TARGET_SOM
|| !TARGET_GAS
)
6780 operands
[3] = gen_label_rtx ();
6781 output_asm_insn ("addil L'%0-%l3,%1", operands
);
6782 targetm
.asm_out
.internal_label (asm_out_file
, "L",
6783 CODE_LABEL_NUMBER (operands
[3]));
6784 output_asm_insn ("ldo R'%0-%l3(%%r1),%2", operands
);
6788 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%1", operands
);
6789 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%2", operands
);
6794 /* This routine handles output of long unconditional branches that
6795 exceed the maximum range of a simple branch instruction. Since
6796 we don't have a register available for the branch, we save register
6797 %r1 in the frame marker, load the branch destination DEST into %r1,
6798 execute the branch, and restore %r1 in the delay slot of the branch.
6800 Since long branches may have an insn in the delay slot and the
6801 delay slot is used to restore %r1, we in general need to extract
6802 this insn and execute it before the branch. However, to facilitate
6803 use of this function by conditional branches, we also provide an
6804 option to not extract the delay insn so that it will be emitted
6805 after the long branch. So, if there is an insn in the delay slot,
6806 it is extracted if XDELAY is nonzero.
6808 The lengths of the various long-branch sequences are 20, 16 and 24
6809 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6812 pa_output_lbranch (rtx dest
, rtx_insn
*insn
, int xdelay
)
6816 xoperands
[0] = dest
;
6818 /* First, free up the delay slot. */
6819 if (xdelay
&& dbr_sequence_length () != 0)
6821 /* We can't handle a jump in the delay slot. */
6822 gcc_assert (! JUMP_P (NEXT_INSN (insn
)));
6824 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
6827 /* Now delete the delay insn. */
6828 SET_INSN_DELETED (NEXT_INSN (insn
));
6831 /* Output an insn to save %r1. The runtime documentation doesn't
6832 specify whether the "Clean Up" slot in the callers frame can
6833 be clobbered by the callee. It isn't copied by HP's builtin
6834 alloca, so this suggests that it can be clobbered if necessary.
6835 The "Static Link" location is copied by HP builtin alloca, so
6836 we avoid using it. Using the cleanup slot might be a problem
6837 if we have to interoperate with languages that pass cleanup
6838 information. However, it should be possible to handle these
6839 situations with GCC's asm feature.
6841 The "Current RP" slot is reserved for the called procedure, so
6842 we try to use it when we don't have a frame of our own. It's
6843 rather unlikely that we won't have a frame when we need to emit
6846 Really the way to go long term is a register scavenger; goto
6847 the target of the jump and find a register which we can use
6848 as a scratch to hold the value in %r1. Then, we wouldn't have
6849 to free up the delay slot or clobber a slot that may be needed
6850 for other purposes. */
6853 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6854 /* Use the return pointer slot in the frame marker. */
6855 output_asm_insn ("std %%r1,-16(%%r30)", xoperands
);
6857 /* Use the slot at -40 in the frame marker since HP builtin
6858 alloca doesn't copy it. */
6859 output_asm_insn ("std %%r1,-40(%%r30)", xoperands
);
6863 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6864 /* Use the return pointer slot in the frame marker. */
6865 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands
);
6867 /* Use the "Clean Up" slot in the frame marker. In GCC,
6868 the only other use of this location is for copying a
6869 floating point double argument from a floating-point
6870 register to two general registers. The copy is done
6871 as an "atomic" operation when outputting a call, so it
6872 won't interfere with our using the location here. */
6873 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands
);
6876 if (TARGET_PORTABLE_RUNTIME
)
6878 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
6879 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
6880 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6884 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
6885 xoperands
[2] = xoperands
[1];
6886 pa_output_pic_pcrel_sequence (xoperands
);
6887 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
6890 /* Now output a very long branch to the original target. */
6891 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands
);
6893 /* Now restore the value of %r1 in the delay slot. */
6896 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6897 return "ldd -16(%%r30),%%r1";
6899 return "ldd -40(%%r30),%%r1";
6903 if (actual_fsize
== 0 && !df_regs_ever_live_p (2))
6904 return "ldw -20(%%r30),%%r1";
6906 return "ldw -12(%%r30),%%r1";
6910 /* This routine handles all the branch-on-bit conditional branch sequences we
6911 might need to generate. It handles nullification of delay slots,
6912 varying length branches, negated branches and all combinations of the
6913 above. it returns the appropriate output template to emit the branch. */
6916 pa_output_bb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx_insn
*insn
, int which
)
6918 static char buf
[100];
6920 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
6921 int length
= get_attr_length (insn
);
6924 /* A conditional branch to the following instruction (e.g. the delay slot) is
6925 asking for a disaster. I do not think this can happen as this pattern
6926 is only used when optimizing; jump optimization should eliminate the
6927 jump. But be prepared just in case. */
6929 if (branch_to_delay_slot_p (insn
))
6932 /* If this is a long branch with its delay slot unfilled, set `nullify'
6933 as it can nullify the delay slot and save a nop. */
6934 if (length
== 8 && dbr_sequence_length () == 0)
6937 /* If this is a short forward conditional branch which did not get
6938 its delay slot filled, the delay slot can still be nullified. */
6939 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
6940 nullify
= forward_branch_p (insn
);
6942 /* A forward branch over a single nullified insn can be done with a
6943 extrs instruction. This avoids a single cycle penalty due to
6944 mis-predicted branch if we fall through (branch not taken). */
6945 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
6950 /* All short conditional branches except backwards with an unfilled
6954 strcpy (buf
, "{extrs,|extrw,s,}");
6956 strcpy (buf
, "bb,");
6957 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
6958 strcpy (buf
, "extrd,s,*");
6959 else if (GET_MODE (operands
[0]) == DImode
)
6960 strcpy (buf
, "bb,*");
6961 if ((which
== 0 && negated
)
6962 || (which
== 1 && ! negated
))
6967 strcat (buf
, " %0,%1,1,%%r0");
6968 else if (nullify
&& negated
)
6970 if (branch_needs_nop_p (insn
))
6971 strcat (buf
, ",n %0,%1,%3%#");
6973 strcat (buf
, ",n %0,%1,%3");
6975 else if (nullify
&& ! negated
)
6977 if (branch_needs_nop_p (insn
))
6978 strcat (buf
, ",n %0,%1,%2%#");
6980 strcat (buf
, ",n %0,%1,%2");
6982 else if (! nullify
&& negated
)
6983 strcat (buf
, " %0,%1,%3");
6984 else if (! nullify
&& ! negated
)
6985 strcat (buf
, " %0,%1,%2");
6988 /* All long conditionals. Note a short backward branch with an
6989 unfilled delay slot is treated just like a long backward branch
6990 with an unfilled delay slot. */
6992 /* Handle weird backwards branch with a filled delay slot
6993 which is nullified. */
6994 if (dbr_sequence_length () != 0
6995 && ! forward_branch_p (insn
)
6998 strcpy (buf
, "bb,");
6999 if (GET_MODE (operands
[0]) == DImode
)
7001 if ((which
== 0 && negated
)
7002 || (which
== 1 && ! negated
))
7007 strcat (buf
, ",n %0,%1,.+12\n\tb %3");
7009 strcat (buf
, ",n %0,%1,.+12\n\tb %2");
7011 /* Handle short backwards branch with an unfilled delay slot.
7012 Using a bb;nop rather than extrs;bl saves 1 cycle for both
7013 taken and untaken branches. */
7014 else if (dbr_sequence_length () == 0
7015 && ! forward_branch_p (insn
)
7016 && INSN_ADDRESSES_SET_P ()
7017 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7018 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7020 strcpy (buf
, "bb,");
7021 if (GET_MODE (operands
[0]) == DImode
)
7023 if ((which
== 0 && negated
)
7024 || (which
== 1 && ! negated
))
7029 strcat (buf
, " %0,%1,%3%#");
7031 strcat (buf
, " %0,%1,%2%#");
7035 if (GET_MODE (operands
[0]) == DImode
)
7036 strcpy (buf
, "extrd,s,*");
7038 strcpy (buf
, "{extrs,|extrw,s,}");
7039 if ((which
== 0 && negated
)
7040 || (which
== 1 && ! negated
))
7044 if (nullify
&& negated
)
7045 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %3");
7046 else if (nullify
&& ! negated
)
7047 strcat (buf
, " %0,%1,1,%%r0\n\tb,n %2");
7049 strcat (buf
, " %0,%1,1,%%r0\n\tb %3");
7051 strcat (buf
, " %0,%1,1,%%r0\n\tb %2");
7056 /* The reversed conditional branch must branch over one additional
7057 instruction if the delay slot is filled and needs to be extracted
7058 by pa_output_lbranch. If the delay slot is empty or this is a
7059 nullified forward branch, the instruction after the reversed
7060 condition branch must be nullified. */
7061 if (dbr_sequence_length () == 0
7062 || (nullify
&& forward_branch_p (insn
)))
7066 operands
[4] = GEN_INT (length
);
7071 operands
[4] = GEN_INT (length
+ 4);
7074 if (GET_MODE (operands
[0]) == DImode
)
7075 strcpy (buf
, "bb,*");
7077 strcpy (buf
, "bb,");
7078 if ((which
== 0 && negated
)
7079 || (which
== 1 && !negated
))
7084 strcat (buf
, ",n %0,%1,.+%4");
7086 strcat (buf
, " %0,%1,.+%4");
7087 output_asm_insn (buf
, operands
);
7088 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
7094 /* This routine handles all the branch-on-variable-bit conditional branch
7095 sequences we might need to generate. It handles nullification of delay
7096 slots, varying length branches, negated branches and all combinations
7097 of the above. it returns the appropriate output template to emit the
7101 pa_output_bvb (rtx
*operands ATTRIBUTE_UNUSED
, int negated
, rtx_insn
*insn
,
7104 static char buf
[100];
7106 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7107 int length
= get_attr_length (insn
);
7110 /* A conditional branch to the following instruction (e.g. the delay slot) is
7111 asking for a disaster. I do not think this can happen as this pattern
7112 is only used when optimizing; jump optimization should eliminate the
7113 jump. But be prepared just in case. */
7115 if (branch_to_delay_slot_p (insn
))
7118 /* If this is a long branch with its delay slot unfilled, set `nullify'
7119 as it can nullify the delay slot and save a nop. */
7120 if (length
== 8 && dbr_sequence_length () == 0)
7123 /* If this is a short forward conditional branch which did not get
7124 its delay slot filled, the delay slot can still be nullified. */
7125 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7126 nullify
= forward_branch_p (insn
);
7128 /* A forward branch over a single nullified insn can be done with a
7129 extrs instruction. This avoids a single cycle penalty due to
7130 mis-predicted branch if we fall through (branch not taken). */
7131 useskip
= (length
== 4 && nullify
) ? use_skip_p (insn
) : FALSE
;
7136 /* All short conditional branches except backwards with an unfilled
7140 strcpy (buf
, "{vextrs,|extrw,s,}");
7142 strcpy (buf
, "{bvb,|bb,}");
7143 if (useskip
&& GET_MODE (operands
[0]) == DImode
)
7144 strcpy (buf
, "extrd,s,*");
7145 else if (GET_MODE (operands
[0]) == DImode
)
7146 strcpy (buf
, "bb,*");
7147 if ((which
== 0 && negated
)
7148 || (which
== 1 && ! negated
))
7153 strcat (buf
, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
7154 else if (nullify
&& negated
)
7156 if (branch_needs_nop_p (insn
))
7157 strcat (buf
, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
7159 strcat (buf
, "{,n %0,%3|,n %0,%%sar,%3}");
7161 else if (nullify
&& ! negated
)
7163 if (branch_needs_nop_p (insn
))
7164 strcat (buf
, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
7166 strcat (buf
, "{,n %0,%2|,n %0,%%sar,%2}");
7168 else if (! nullify
&& negated
)
7169 strcat (buf
, "{ %0,%3| %0,%%sar,%3}");
7170 else if (! nullify
&& ! negated
)
7171 strcat (buf
, "{ %0,%2| %0,%%sar,%2}");
7174 /* All long conditionals. Note a short backward branch with an
7175 unfilled delay slot is treated just like a long backward branch
7176 with an unfilled delay slot. */
7178 /* Handle weird backwards branch with a filled delay slot
7179 which is nullified. */
7180 if (dbr_sequence_length () != 0
7181 && ! forward_branch_p (insn
)
7184 strcpy (buf
, "{bvb,|bb,}");
7185 if (GET_MODE (operands
[0]) == DImode
)
7187 if ((which
== 0 && negated
)
7188 || (which
== 1 && ! negated
))
7193 strcat (buf
, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
7195 strcat (buf
, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
7197 /* Handle short backwards branch with an unfilled delay slot.
7198 Using a bb;nop rather than extrs;bl saves 1 cycle for both
7199 taken and untaken branches. */
7200 else if (dbr_sequence_length () == 0
7201 && ! forward_branch_p (insn
)
7202 && INSN_ADDRESSES_SET_P ()
7203 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7204 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7206 strcpy (buf
, "{bvb,|bb,}");
7207 if (GET_MODE (operands
[0]) == DImode
)
7209 if ((which
== 0 && negated
)
7210 || (which
== 1 && ! negated
))
7215 strcat (buf
, "{ %0,%3%#| %0,%%sar,%3%#}");
7217 strcat (buf
, "{ %0,%2%#| %0,%%sar,%2%#}");
7221 strcpy (buf
, "{vextrs,|extrw,s,}");
7222 if (GET_MODE (operands
[0]) == DImode
)
7223 strcpy (buf
, "extrd,s,*");
7224 if ((which
== 0 && negated
)
7225 || (which
== 1 && ! negated
))
7229 if (nullify
&& negated
)
7230 strcat (buf
, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
7231 else if (nullify
&& ! negated
)
7232 strcat (buf
, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
7234 strcat (buf
, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
7236 strcat (buf
, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
7241 /* The reversed conditional branch must branch over one additional
7242 instruction if the delay slot is filled and needs to be extracted
7243 by pa_output_lbranch. If the delay slot is empty or this is a
7244 nullified forward branch, the instruction after the reversed
7245 condition branch must be nullified. */
7246 if (dbr_sequence_length () == 0
7247 || (nullify
&& forward_branch_p (insn
)))
7251 operands
[4] = GEN_INT (length
);
7256 operands
[4] = GEN_INT (length
+ 4);
7259 if (GET_MODE (operands
[0]) == DImode
)
7260 strcpy (buf
, "bb,*");
7262 strcpy (buf
, "{bvb,|bb,}");
7263 if ((which
== 0 && negated
)
7264 || (which
== 1 && !negated
))
7269 strcat (buf
, ",n {%0,.+%4|%0,%%sar,.+%4}");
7271 strcat (buf
, " {%0,.+%4|%0,%%sar,.+%4}");
7272 output_asm_insn (buf
, operands
);
7273 return pa_output_lbranch (negated
? operands
[3] : operands
[2],
7279 /* Return the output template for emitting a dbra type insn.
7281 Note it may perform some output operations on its own before
7282 returning the final output string. */
7284 pa_output_dbra (rtx
*operands
, rtx_insn
*insn
, int which_alternative
)
7286 int length
= get_attr_length (insn
);
7288 /* A conditional branch to the following instruction (e.g. the delay slot) is
7289 asking for a disaster. Be prepared! */
7291 if (branch_to_delay_slot_p (insn
))
7293 if (which_alternative
== 0)
7294 return "ldo %1(%0),%0";
7295 else if (which_alternative
== 1)
7297 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands
);
7298 output_asm_insn ("ldw -16(%%r30),%4", operands
);
7299 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7300 return "{fldws|fldw} -16(%%r30),%0";
7304 output_asm_insn ("ldw %0,%4", operands
);
7305 return "ldo %1(%4),%4\n\tstw %4,%0";
7309 if (which_alternative
== 0)
7311 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7314 /* If this is a long branch with its delay slot unfilled, set `nullify'
7315 as it can nullify the delay slot and save a nop. */
7316 if (length
== 8 && dbr_sequence_length () == 0)
7319 /* If this is a short forward conditional branch which did not get
7320 its delay slot filled, the delay slot can still be nullified. */
7321 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7322 nullify
= forward_branch_p (insn
);
7329 if (branch_needs_nop_p (insn
))
7330 return "addib,%C2,n %1,%0,%3%#";
7332 return "addib,%C2,n %1,%0,%3";
7335 return "addib,%C2 %1,%0,%3";
7338 /* Handle weird backwards branch with a fulled delay slot
7339 which is nullified. */
7340 if (dbr_sequence_length () != 0
7341 && ! forward_branch_p (insn
)
7343 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7344 /* Handle short backwards branch with an unfilled delay slot.
7345 Using a addb;nop rather than addi;bl saves 1 cycle for both
7346 taken and untaken branches. */
7347 else if (dbr_sequence_length () == 0
7348 && ! forward_branch_p (insn
)
7349 && INSN_ADDRESSES_SET_P ()
7350 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7351 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7352 return "addib,%C2 %1,%0,%3%#";
7354 /* Handle normal cases. */
7356 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7358 return "addi,%N2 %1,%0,%0\n\tb %3";
7361 /* The reversed conditional branch must branch over one additional
7362 instruction if the delay slot is filled and needs to be extracted
7363 by pa_output_lbranch. If the delay slot is empty or this is a
7364 nullified forward branch, the instruction after the reversed
7365 condition branch must be nullified. */
7366 if (dbr_sequence_length () == 0
7367 || (nullify
&& forward_branch_p (insn
)))
7371 operands
[4] = GEN_INT (length
);
7376 operands
[4] = GEN_INT (length
+ 4);
7380 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands
);
7382 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands
);
7384 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7388 /* Deal with gross reload from FP register case. */
7389 else if (which_alternative
== 1)
7391 /* Move loop counter from FP register to MEM then into a GR,
7392 increment the GR, store the GR into MEM, and finally reload
7393 the FP register from MEM from within the branch's delay slot. */
7394 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7396 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands
);
7398 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7399 else if (length
== 28)
7400 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7403 operands
[5] = GEN_INT (length
- 16);
7404 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands
);
7405 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7406 return pa_output_lbranch (operands
[3], insn
, 0);
7409 /* Deal with gross reload from memory case. */
7412 /* Reload loop counter from memory, the store back to memory
7413 happens in the branch's delay slot. */
7414 output_asm_insn ("ldw %0,%4", operands
);
7416 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7417 else if (length
== 16)
7418 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7421 operands
[5] = GEN_INT (length
- 4);
7422 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands
);
7423 return pa_output_lbranch (operands
[3], insn
, 0);
7428 /* Return the output template for emitting a movb type insn.
7430 Note it may perform some output operations on its own before
7431 returning the final output string. */
7433 pa_output_movb (rtx
*operands
, rtx_insn
*insn
, int which_alternative
,
7434 int reverse_comparison
)
7436 int length
= get_attr_length (insn
);
7438 /* A conditional branch to the following instruction (e.g. the delay slot) is
7439 asking for a disaster. Be prepared! */
7441 if (branch_to_delay_slot_p (insn
))
7443 if (which_alternative
== 0)
7444 return "copy %1,%0";
7445 else if (which_alternative
== 1)
7447 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7448 return "{fldws|fldw} -16(%%r30),%0";
7450 else if (which_alternative
== 2)
7456 /* Support the second variant. */
7457 if (reverse_comparison
)
7458 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
7460 if (which_alternative
== 0)
7462 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
7465 /* If this is a long branch with its delay slot unfilled, set `nullify'
7466 as it can nullify the delay slot and save a nop. */
7467 if (length
== 8 && dbr_sequence_length () == 0)
7470 /* If this is a short forward conditional branch which did not get
7471 its delay slot filled, the delay slot can still be nullified. */
7472 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
7473 nullify
= forward_branch_p (insn
);
7480 if (branch_needs_nop_p (insn
))
7481 return "movb,%C2,n %1,%0,%3%#";
7483 return "movb,%C2,n %1,%0,%3";
7486 return "movb,%C2 %1,%0,%3";
7489 /* Handle weird backwards branch with a filled delay slot
7490 which is nullified. */
7491 if (dbr_sequence_length () != 0
7492 && ! forward_branch_p (insn
)
7494 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7496 /* Handle short backwards branch with an unfilled delay slot.
7497 Using a movb;nop rather than or;bl saves 1 cycle for both
7498 taken and untaken branches. */
7499 else if (dbr_sequence_length () == 0
7500 && ! forward_branch_p (insn
)
7501 && INSN_ADDRESSES_SET_P ()
7502 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn
)))
7503 - INSN_ADDRESSES (INSN_UID (insn
)) - 8))
7504 return "movb,%C2 %1,%0,%3%#";
7505 /* Handle normal cases. */
7507 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7509 return "or,%N2 %1,%%r0,%0\n\tb %3";
7512 /* The reversed conditional branch must branch over one additional
7513 instruction if the delay slot is filled and needs to be extracted
7514 by pa_output_lbranch. If the delay slot is empty or this is a
7515 nullified forward branch, the instruction after the reversed
7516 condition branch must be nullified. */
7517 if (dbr_sequence_length () == 0
7518 || (nullify
&& forward_branch_p (insn
)))
7522 operands
[4] = GEN_INT (length
);
7527 operands
[4] = GEN_INT (length
+ 4);
7531 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands
);
7533 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands
);
7535 return pa_output_lbranch (operands
[3], insn
, xdelay
);
7538 /* Deal with gross reload for FP destination register case. */
7539 else if (which_alternative
== 1)
7541 /* Move source register to MEM, perform the branch test, then
7542 finally load the FP register from MEM from within the branch's
7544 output_asm_insn ("stw %1,-16(%%r30)", operands
);
7546 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7547 else if (length
== 16)
7548 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7551 operands
[4] = GEN_INT (length
- 4);
7552 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands
);
7553 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands
);
7554 return pa_output_lbranch (operands
[3], insn
, 0);
7557 /* Deal with gross reload from memory case. */
7558 else if (which_alternative
== 2)
7560 /* Reload loop counter from memory, the store back to memory
7561 happens in the branch's delay slot. */
7563 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7564 else if (length
== 12)
7565 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7568 operands
[4] = GEN_INT (length
);
7569 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7571 return pa_output_lbranch (operands
[3], insn
, 0);
7574 /* Handle SAR as a destination. */
7578 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7579 else if (length
== 12)
7580 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7583 operands
[4] = GEN_INT (length
);
7584 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7586 return pa_output_lbranch (operands
[3], insn
, 0);
7591 /* Copy any FP arguments in INSN into integer registers. */
7593 copy_fp_args (rtx_insn
*insn
)
7598 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7600 int arg_mode
, regno
;
7601 rtx use
= XEXP (link
, 0);
7603 if (! (GET_CODE (use
) == USE
7604 && GET_CODE (XEXP (use
, 0)) == REG
7605 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7608 arg_mode
= GET_MODE (XEXP (use
, 0));
7609 regno
= REGNO (XEXP (use
, 0));
7611 /* Is it a floating point register? */
7612 if (regno
>= 32 && regno
<= 39)
7614 /* Copy the FP register into an integer register via memory. */
7615 if (arg_mode
== SFmode
)
7617 xoperands
[0] = XEXP (use
, 0);
7618 xoperands
[1] = gen_rtx_REG (SImode
, 26 - (regno
- 32) / 2);
7619 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands
);
7620 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7624 xoperands
[0] = XEXP (use
, 0);
7625 xoperands
[1] = gen_rtx_REG (DImode
, 25 - (regno
- 34) / 2);
7626 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands
);
7627 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
7628 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
7634 /* Compute length of the FP argument copy sequence for INSN. */
7636 length_fp_args (rtx_insn
*insn
)
7641 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
7643 int arg_mode
, regno
;
7644 rtx use
= XEXP (link
, 0);
7646 if (! (GET_CODE (use
) == USE
7647 && GET_CODE (XEXP (use
, 0)) == REG
7648 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
7651 arg_mode
= GET_MODE (XEXP (use
, 0));
7652 regno
= REGNO (XEXP (use
, 0));
7654 /* Is it a floating point register? */
7655 if (regno
>= 32 && regno
<= 39)
7657 if (arg_mode
== SFmode
)
7667 /* Return the attribute length for the millicode call instruction INSN.
7668 The length must match the code generated by pa_output_millicode_call.
7669 We include the delay slot in the returned length as it is better to
7670 over estimate the length than to under estimate it. */
7673 pa_attr_length_millicode_call (rtx_insn
*insn
)
7675 unsigned long distance
= -1;
7676 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7678 if (INSN_ADDRESSES_SET_P ())
7680 distance
= (total
+ insn_current_reference_address (insn
));
7681 if (distance
< total
)
7687 if (!TARGET_LONG_CALLS
&& distance
< 7600000)
7692 else if (TARGET_PORTABLE_RUNTIME
)
7696 if (!TARGET_LONG_CALLS
&& distance
< MAX_PCREL17F_OFFSET
)
7706 /* INSN is a function call.
7708 CALL_DEST is the routine we are calling. */
7711 pa_output_millicode_call (rtx_insn
*insn
, rtx call_dest
)
7713 int attr_length
= get_attr_length (insn
);
7714 int seq_length
= dbr_sequence_length ();
7717 xoperands
[0] = call_dest
;
7719 /* Handle the common case where we are sure that the branch will
7720 reach the beginning of the $CODE$ subspace. The within reach
7721 form of the $$sh_func_adrs call has a length of 28. Because it
7722 has an attribute type of sh_func_adrs, it never has a nonzero
7723 sequence length (i.e., the delay slot is never filled). */
7724 if (!TARGET_LONG_CALLS
7725 && (attr_length
== 8
7726 || (attr_length
== 28
7727 && get_attr_type (insn
) == TYPE_SH_FUNC_ADRS
)))
7729 xoperands
[1] = gen_rtx_REG (Pmode
, TARGET_64BIT
? 2 : 31);
7730 output_asm_insn ("{bl|b,l} %0,%1", xoperands
);
7736 /* It might seem that one insn could be saved by accessing
7737 the millicode function using the linkage table. However,
7738 this doesn't work in shared libraries and other dynamically
7739 loaded objects. Using a pc-relative sequence also avoids
7740 problems related to the implicit use of the gp register. */
7741 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
7742 xoperands
[2] = xoperands
[1];
7743 pa_output_pic_pcrel_sequence (xoperands
);
7744 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
7746 else if (TARGET_PORTABLE_RUNTIME
)
7748 /* Pure portable runtime doesn't allow be/ble; we also don't
7749 have PIC support in the assembler/linker, so this sequence
7752 /* Get the address of our target into %r1. */
7753 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7754 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands
);
7756 /* Get our return address into %r31. */
7757 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands
);
7758 output_asm_insn ("addi 8,%%r31,%%r31", xoperands
);
7760 /* Jump to our target address in %r1. */
7761 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7765 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7767 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands
);
7769 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
7773 xoperands
[1] = gen_rtx_REG (Pmode
, 31);
7774 xoperands
[2] = gen_rtx_REG (Pmode
, 1);
7775 pa_output_pic_pcrel_sequence (xoperands
);
7777 /* Adjust return address. */
7778 output_asm_insn ("ldo {16|24}(%%r31),%%r31", xoperands
);
7780 /* Jump to our target address in %r1. */
7781 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
7785 if (seq_length
== 0)
7786 output_asm_insn ("nop", xoperands
);
7791 /* Return the attribute length of the call instruction INSN. The SIBCALL
7792 flag indicates whether INSN is a regular call or a sibling call. The
7793 length returned must be longer than the code actually generated by
7794 pa_output_call. Since branch shortening is done before delay branch
7795 sequencing, there is no way to determine whether or not the delay
7796 slot will be filled during branch shortening. Even when the delay
7797 slot is filled, we may have to add a nop if the delay slot contains
7798 a branch that can't reach its target. Thus, we always have to include
7799 the delay slot in the length estimate. This used to be done in
7800 pa_adjust_insn_length but we do it here now as some sequences always
7801 fill the delay slot and we can save four bytes in the estimate for
7805 pa_attr_length_call (rtx_insn
*insn
, int sibcall
)
7808 rtx call
, call_dest
;
7811 rtx pat
= PATTERN (insn
);
7812 unsigned long distance
= -1;
7814 gcc_assert (CALL_P (insn
));
7816 if (INSN_ADDRESSES_SET_P ())
7818 unsigned long total
;
7820 total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
7821 distance
= (total
+ insn_current_reference_address (insn
));
7822 if (distance
< total
)
7826 gcc_assert (GET_CODE (pat
) == PARALLEL
);
7828 /* Get the call rtx. */
7829 call
= XVECEXP (pat
, 0, 0);
7830 if (GET_CODE (call
) == SET
)
7831 call
= SET_SRC (call
);
7833 gcc_assert (GET_CODE (call
) == CALL
);
7835 /* Determine if this is a local call. */
7836 call_dest
= XEXP (XEXP (call
, 0), 0);
7837 call_decl
= SYMBOL_REF_DECL (call_dest
);
7838 local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7840 /* pc-relative branch. */
7841 if (!TARGET_LONG_CALLS
7842 && ((TARGET_PA_20
&& !sibcall
&& distance
< 7600000)
7843 || distance
< MAX_PCREL17F_OFFSET
))
7846 /* 64-bit plabel sequence. */
7847 else if (TARGET_64BIT
&& !local_call
)
7850 /* non-pic long absolute branch sequence. */
7851 else if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7854 /* long pc-relative branch sequence. */
7855 else if (TARGET_LONG_PIC_SDIFF_CALL
7856 || (TARGET_GAS
&& !TARGET_SOM
&& local_call
))
7860 if (!TARGET_PA_20
&& !TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7864 /* 32-bit plabel sequence. */
7870 length
+= length_fp_args (insn
);
7880 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
7888 /* INSN is a function call.
7890 CALL_DEST is the routine we are calling. */
7893 pa_output_call (rtx_insn
*insn
, rtx call_dest
, int sibcall
)
7895 int seq_length
= dbr_sequence_length ();
7896 tree call_decl
= SYMBOL_REF_DECL (call_dest
);
7897 int local_call
= call_decl
&& targetm
.binds_local_p (call_decl
);
7900 xoperands
[0] = call_dest
;
7902 /* Handle the common case where we're sure that the branch will reach
7903 the beginning of the "$CODE$" subspace. This is the beginning of
7904 the current function if we are in a named section. */
7905 if (!TARGET_LONG_CALLS
&& pa_attr_length_call (insn
, sibcall
) == 8)
7907 xoperands
[1] = gen_rtx_REG (word_mode
, sibcall
? 0 : 2);
7908 output_asm_insn ("{bl|b,l} %0,%1", xoperands
);
7912 if (TARGET_64BIT
&& !local_call
)
7914 /* ??? As far as I can tell, the HP linker doesn't support the
7915 long pc-relative sequence described in the 64-bit runtime
7916 architecture. So, we use a slightly longer indirect call. */
7917 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
7918 xoperands
[1] = gen_label_rtx ();
7920 /* Put the load of %r27 into the delay slot. We don't need to
7921 do anything when generating fast indirect calls. */
7922 if (seq_length
!= 0)
7924 final_scan_insn (NEXT_INSN (insn
), asm_out_file
,
7927 /* Now delete the delay insn. */
7928 SET_INSN_DELETED (NEXT_INSN (insn
));
7931 output_asm_insn ("addil LT'%0,%%r27", xoperands
);
7932 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands
);
7933 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands
);
7934 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands
);
7935 output_asm_insn ("bve,l (%%r2),%%r2", xoperands
);
7936 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands
);
7941 int indirect_call
= 0;
7943 /* Emit a long call. There are several different sequences
7944 of increasing length and complexity. In most cases,
7945 they don't allow an instruction in the delay slot. */
7946 if (!((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7947 && !TARGET_LONG_PIC_SDIFF_CALL
7948 && !(TARGET_GAS
&& !TARGET_SOM
&& local_call
)
7956 || ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)))
7958 /* A non-jump insn in the delay slot. By definition we can
7959 emit this insn before the call (and in fact before argument
7961 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0,
7964 /* Now delete the delay insn. */
7965 SET_INSN_DELETED (NEXT_INSN (insn
));
7969 if ((TARGET_LONG_ABS_CALL
|| local_call
) && !flag_pic
)
7971 /* This is the best sequence for making long calls in
7972 non-pic code. Unfortunately, GNU ld doesn't provide
7973 the stub needed for external calls, and GAS's support
7974 for this with the SOM linker is buggy. It is safe
7975 to use this for local calls. */
7976 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
7978 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands
);
7982 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7985 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands
);
7987 output_asm_insn ("copy %%r31,%%r2", xoperands
);
7993 /* The HP assembler and linker can handle relocations for
7994 the difference of two symbols. The HP assembler
7995 recognizes the sequence as a pc-relative call and
7996 the linker provides stubs when needed. */
7998 /* GAS currently can't generate the relocations that
7999 are needed for the SOM linker under HP-UX using this
8000 sequence. The GNU linker doesn't generate the stubs
8001 that are needed for external calls on TARGET_ELF32
8002 with this sequence. For now, we have to use a longer
8003 plabel sequence when using GAS for non local calls. */
8004 if (TARGET_LONG_PIC_SDIFF_CALL
8005 || (TARGET_GAS
&& !TARGET_SOM
&& local_call
))
8007 xoperands
[1] = gen_rtx_REG (Pmode
, 1);
8008 xoperands
[2] = xoperands
[1];
8009 pa_output_pic_pcrel_sequence (xoperands
);
8013 /* Emit a long plabel-based call sequence. This is
8014 essentially an inline implementation of $$dyncall.
8015 We don't actually try to call $$dyncall as this is
8016 as difficult as calling the function itself. */
8017 xoperands
[0] = pa_get_deferred_plabel (call_dest
);
8018 xoperands
[1] = gen_label_rtx ();
8020 /* Since the call is indirect, FP arguments in registers
8021 need to be copied to the general registers. Then, the
8022 argument relocation stub will copy them back. */
8024 copy_fp_args (insn
);
8028 output_asm_insn ("addil LT'%0,%%r19", xoperands
);
8029 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands
);
8030 output_asm_insn ("ldw 0(%%r1),%%r22", xoperands
);
8034 output_asm_insn ("addil LR'%0-$global$,%%r27",
8036 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r22",
8040 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands
);
8041 output_asm_insn ("depi 0,31,2,%%r22", xoperands
);
8042 /* Should this be an ordered load to ensure the target
8043 address is loaded before the global pointer? */
8044 output_asm_insn ("ldw 0(%%r22),%%r1", xoperands
);
8045 output_asm_insn ("ldw 4(%%r22),%%r19", xoperands
);
8047 if (!sibcall
&& !TARGET_PA_20
)
8049 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands
);
8050 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8051 output_asm_insn ("addi 8,%%r2,%%r2", xoperands
);
8053 output_asm_insn ("addi 16,%%r2,%%r2", xoperands
);
8060 output_asm_insn ("bve (%%r1)", xoperands
);
8065 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8066 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands
);
8070 output_asm_insn ("bve,l (%%r1),%%r2", xoperands
);
8075 if (!TARGET_NO_SPACE_REGS
&& (!local_call
|| flag_pic
))
8076 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
8081 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8082 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands
);
8084 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands
);
8088 if (TARGET_NO_SPACE_REGS
|| (local_call
&& !flag_pic
))
8089 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands
);
8091 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands
);
8094 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands
);
8096 output_asm_insn ("copy %%r31,%%r2", xoperands
);
8104 if (seq_length
== 0)
8105 output_asm_insn ("nop", xoperands
);
8110 /* Return the attribute length of the indirect call instruction INSN.
8111 The length must match the code generated by output_indirect call.
8112 The returned length includes the delay slot. Currently, the delay
8113 slot of an indirect call sequence is not exposed and it is used by
8114 the sequence itself. */
8117 pa_attr_length_indirect_call (rtx_insn
*insn
)
8119 unsigned long distance
= -1;
8120 unsigned long total
= IN_NAMED_SECTION_P (cfun
->decl
) ? 0 : total_code_bytes
;
8122 if (INSN_ADDRESSES_SET_P ())
8124 distance
= (total
+ insn_current_reference_address (insn
));
8125 if (distance
< total
)
8132 if (TARGET_FAST_INDIRECT_CALLS
)
8135 if (TARGET_PORTABLE_RUNTIME
)
8138 if (!TARGET_LONG_CALLS
8139 && ((TARGET_PA_20
&& !TARGET_SOM
&& distance
< 7600000)
8140 || distance
< MAX_PCREL17F_OFFSET
))
8143 /* Out of reach, can use ble. */
8147 /* Inline versions of $$dyncall. */
8150 if (TARGET_NO_SPACE_REGS
)
8157 /* Long PIC pc-relative call. */
8162 pa_output_indirect_call (rtx_insn
*insn
, rtx call_dest
)
8169 xoperands
[0] = call_dest
;
8170 output_asm_insn ("ldd 16(%0),%%r2\n\t"
8171 "bve,l (%%r2),%%r2\n\t"
8172 "ldd 24(%0),%%r27", xoperands
);
8176 /* First the special case for kernels, level 0 systems, etc. */
8177 if (TARGET_FAST_INDIRECT_CALLS
)
8179 pa_output_arg_descriptor (insn
);
8181 return "bve,l,n (%%r22),%%r2\n\tnop";
8182 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8185 if (TARGET_PORTABLE_RUNTIME
)
8187 output_asm_insn ("ldil L'$$dyncall,%%r31\n\t"
8188 "ldo R'$$dyncall(%%r31),%%r31", xoperands
);
8189 pa_output_arg_descriptor (insn
);
8190 return "blr %%r0,%%r2\n\tbv,n %%r0(%%r31)";
8193 /* Now the normal case -- we can reach $$dyncall directly or
8194 we're sure that we can get there via a long-branch stub.
8196 No need to check target flags as the length uniquely identifies
8197 the remaining cases. */
8198 length
= pa_attr_length_indirect_call (insn
);
8201 pa_output_arg_descriptor (insn
);
8203 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8204 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8205 variant of the B,L instruction can't be used on the SOM target. */
8206 if (TARGET_PA_20
&& !TARGET_SOM
)
8207 return "b,l,n $$dyncall,%%r2\n\tnop";
8209 return "bl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8212 /* Long millicode call, but we are not generating PIC or portable runtime
8216 output_asm_insn ("ldil L'$$dyncall,%%r2", xoperands
);
8217 pa_output_arg_descriptor (insn
);
8218 return "ble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8221 /* The long PIC pc-relative call sequence is five instructions. So,
8222 let's use an inline version of $$dyncall when the calling sequence
8223 has a roughly similar number of instructions and we are not optimizing
8224 for size. We need two instructions to load the return pointer plus
8225 the $$dyncall implementation. */
8228 if (TARGET_NO_SPACE_REGS
)
8230 pa_output_arg_descriptor (insn
);
8231 output_asm_insn ("bl .+8,%%r2\n\t"
8232 "ldo 20(%%r2),%%r2\n\t"
8233 "extru,<> %%r22,30,1,%%r0\n\t"
8234 "bv,n %%r0(%%r22)\n\t"
8235 "ldw -2(%%r22),%%r21\n\t"
8236 "bv %%r0(%%r21)\n\t"
8237 "ldw 2(%%r22),%%r19", xoperands
);
8242 pa_output_arg_descriptor (insn
);
8243 output_asm_insn ("bl .+8,%%r2\n\t"
8244 "ldo 24(%%r2),%%r2\n\t"
8245 "stw %%r2,-24(%%sp)\n\t"
8246 "extru,<> %r22,30,1,%%r0\n\t"
8248 "ldw -2(%%r22),%%r21\n\t"
8250 "ldw 2(%%r22),%%r19", xoperands
);
8255 /* We need a long PIC call to $$dyncall. */
8256 xoperands
[0] = gen_rtx_SYMBOL_REF (Pmode
, "$$dyncall");
8257 xoperands
[1] = gen_rtx_REG (Pmode
, 2);
8258 xoperands
[2] = gen_rtx_REG (Pmode
, 1);
8259 pa_output_pic_pcrel_sequence (xoperands
);
8260 pa_output_arg_descriptor (insn
);
8261 return "bv %%r0(%%r1)\n\tldo {12|20}(%%r2),%%r2";
8264 /* In HPUX 8.0's shared library scheme, special relocations are needed
8265 for function labels if they might be passed to a function
8266 in a shared library (because shared libraries don't live in code
8267 space), and special magic is needed to construct their address. */
8270 pa_encode_label (rtx sym
)
8272 const char *str
= XSTR (sym
, 0);
8273 int len
= strlen (str
) + 1;
8276 p
= newstr
= XALLOCAVEC (char, len
+ 1);
8280 XSTR (sym
, 0) = ggc_alloc_string (newstr
, len
);
8284 pa_encode_section_info (tree decl
, rtx rtl
, int first
)
8286 int old_referenced
= 0;
8288 if (!first
&& MEM_P (rtl
) && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
)
8290 = SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) & SYMBOL_FLAG_REFERENCED
;
8292 default_encode_section_info (decl
, rtl
, first
);
8294 if (first
&& TEXT_SPACE_P (decl
))
8296 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
8297 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8298 pa_encode_label (XEXP (rtl
, 0));
8300 else if (old_referenced
)
8301 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= old_referenced
;
8304 /* This is sort of inverse to pa_encode_section_info. */
8307 pa_strip_name_encoding (const char *str
)
8309 str
+= (*str
== '@');
8310 str
+= (*str
== '*');
8314 /* Returns 1 if OP is a function label involved in a simple addition
8315 with a constant. Used to keep certain patterns from matching
8316 during instruction combination. */
8318 pa_is_function_label_plus_const (rtx op
)
8320 /* Strip off any CONST. */
8321 if (GET_CODE (op
) == CONST
)
8324 return (GET_CODE (op
) == PLUS
8325 && function_label_operand (XEXP (op
, 0), VOIDmode
)
8326 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
8329 /* Output assembly code for a thunk to FUNCTION. */
8332 pa_asm_output_mi_thunk (FILE *file
, tree thunk_fndecl
, HOST_WIDE_INT delta
,
8333 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
8336 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
8337 static unsigned int current_thunk_number
;
8338 int val_14
= VAL_14_BITS_P (delta
);
8339 unsigned int old_last_address
= last_address
, nbytes
= 0;
8343 xoperands
[0] = XEXP (DECL_RTL (function
), 0);
8344 xoperands
[1] = XEXP (DECL_RTL (thunk_fndecl
), 0);
8345 xoperands
[2] = GEN_INT (delta
);
8347 assemble_start_function (thunk_fndecl
, fnname
);
8348 final_start_function (emit_barrier (), file
, 1);
8350 /* Output the thunk. We know that the function is in the same
8351 translation unit (i.e., the same space) as the thunk, and that
8352 thunks are output after their method. Thus, we don't need an
8353 external branch to reach the function. With SOM and GAS,
8354 functions and thunks are effectively in different sections.
8355 Thus, we can always use a IA-relative branch and the linker
8356 will add a long branch stub if necessary.
8358 However, we have to be careful when generating PIC code on the
8359 SOM port to ensure that the sequence does not transfer to an
8360 import stub for the target function as this could clobber the
8361 return value saved at SP-24. This would also apply to the
8362 32-bit linux port if the multi-space model is implemented. */
8363 if ((!TARGET_LONG_CALLS
&& TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8364 && !(flag_pic
&& TREE_PUBLIC (function
))
8365 && (TARGET_GAS
|| last_address
< 262132))
8366 || (!TARGET_LONG_CALLS
&& !TARGET_SOM
&& !TARGET_PORTABLE_RUNTIME
8367 && ((targetm_common
.have_named_sections
8368 && DECL_SECTION_NAME (thunk_fndecl
) != NULL
8369 /* The GNU 64-bit linker has rather poor stub management.
8370 So, we use a long branch from thunks that aren't in
8371 the same section as the target function. */
8373 && (DECL_SECTION_NAME (thunk_fndecl
)
8374 != DECL_SECTION_NAME (function
)))
8375 || ((DECL_SECTION_NAME (thunk_fndecl
)
8376 == DECL_SECTION_NAME (function
))
8377 && last_address
< 262132)))
8378 /* In this case, we need to be able to reach the start of
8379 the stub table even though the function is likely closer
8380 and can be jumped to directly. */
8381 || (targetm_common
.have_named_sections
8382 && DECL_SECTION_NAME (thunk_fndecl
) == NULL
8383 && DECL_SECTION_NAME (function
) == NULL
8384 && total_code_bytes
< MAX_PCREL17F_OFFSET
)
8386 || (!targetm_common
.have_named_sections
8387 && total_code_bytes
< MAX_PCREL17F_OFFSET
))))
8390 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8392 output_asm_insn ("b %0", xoperands
);
8396 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8401 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8405 else if (TARGET_64BIT
)
8409 /* We only have one call-clobbered scratch register, so we can't
8410 make use of the delay slot if delta doesn't fit in 14 bits. */
8413 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8414 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8417 /* Load function address into %r1. */
8418 xop
[0] = xoperands
[0];
8419 xop
[1] = gen_rtx_REG (Pmode
, 1);
8421 pa_output_pic_pcrel_sequence (xop
);
8425 output_asm_insn ("bv %%r0(%%r1)", xoperands
);
8426 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8431 output_asm_insn ("bv,n %%r0(%%r1)", xoperands
);
8435 else if (TARGET_PORTABLE_RUNTIME
)
8437 output_asm_insn ("ldil L'%0,%%r1", xoperands
);
8438 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands
);
8441 output_asm_insn ("ldil L'%2,%%r26", xoperands
);
8443 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8447 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8452 output_asm_insn ("ldo R'%2(%%r26),%%r26", xoperands
);
8456 else if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8458 /* The function is accessible from outside this module. The only
8459 way to avoid an import stub between the thunk and function is to
8460 call the function directly with an indirect sequence similar to
8461 that used by $$dyncall. This is possible because $$dyncall acts
8462 as the import stub in an indirect call. */
8463 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHN", current_thunk_number
);
8464 xoperands
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8465 output_asm_insn ("addil LT'%3,%%r19", xoperands
);
8466 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands
);
8467 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8468 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands
);
8469 output_asm_insn ("depi 0,31,2,%%r22", xoperands
);
8470 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands
);
8471 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands
);
8475 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8481 output_asm_insn ("bve (%%r22)", xoperands
);
8484 else if (TARGET_NO_SPACE_REGS
)
8486 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands
);
8491 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands
);
8492 output_asm_insn ("mtsp %%r21,%%sr0", xoperands
);
8493 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands
);
8498 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8500 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8506 /* Load function address into %r22. */
8507 xop
[0] = xoperands
[0];
8508 xop
[1] = gen_rtx_REG (Pmode
, 1);
8509 xop
[2] = gen_rtx_REG (Pmode
, 22);
8510 pa_output_pic_pcrel_sequence (xop
);
8513 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8515 output_asm_insn ("bv %%r0(%%r22)", xoperands
);
8519 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8524 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8531 output_asm_insn ("addil L'%2,%%r26", xoperands
);
8533 output_asm_insn ("ldil L'%0,%%r22", xoperands
);
8534 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands
);
8538 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands
);
8543 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands
);
8548 final_end_function ();
8550 if (TARGET_SOM
&& flag_pic
&& TREE_PUBLIC (function
))
8552 switch_to_section (data_section
);
8553 output_asm_insn (".align 4", xoperands
);
8554 ASM_OUTPUT_LABEL (file
, label
);
8555 output_asm_insn (".word P'%0", xoperands
);
8558 current_thunk_number
++;
8559 nbytes
= ((nbytes
+ FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1)
8560 & ~(FUNCTION_BOUNDARY
/ BITS_PER_UNIT
- 1));
8561 last_address
+= nbytes
;
8562 if (old_last_address
> last_address
)
8563 last_address
= UINT_MAX
;
8564 update_total_code_bytes (nbytes
);
8565 assemble_end_function (thunk_fndecl
, fnname
);
8568 /* Only direct calls to static functions are allowed to be sibling (tail)
8571 This restriction is necessary because some linker generated stubs will
8572 store return pointers into rp' in some cases which might clobber a
8573 live value already in rp'.
8575 In a sibcall the current function and the target function share stack
8576 space. Thus if the path to the current function and the path to the
8577 target function save a value in rp', they save the value into the
8578 same stack slot, which has undesirable consequences.
8580 Because of the deferred binding nature of shared libraries any function
8581 with external scope could be in a different load module and thus require
8582 rp' to be saved when calling that function. So sibcall optimizations
8583 can only be safe for static function.
8585 Note that GCC never needs return value relocations, so we don't have to
8586 worry about static calls with return value relocations (which require
8589 It is safe to perform a sibcall optimization when the target function
8590 will never return. */
8592 pa_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
8594 /* Sibcalls are not ok because the arg pointer register is not a fixed
8595 register. This prevents the sibcall optimization from occurring. In
8596 addition, there are problems with stub placement using GNU ld. This
8597 is because a normal sibcall branch uses a 17-bit relocation while
8598 a regular call branch uses a 22-bit relocation. As a result, more
8599 care needs to be taken in the placement of long-branch stubs. */
8603 if (TARGET_PORTABLE_RUNTIME
)
8606 /* Sibcalls are only ok within a translation unit. */
8607 return decl
&& targetm
.binds_local_p (decl
);
8610 /* ??? Addition is not commutative on the PA due to the weird implicit
8611 space register selection rules for memory addresses. Therefore, we
8612 don't consider a + b == b + a, as this might be inside a MEM. */
8614 pa_commutative_p (const_rtx x
, int outer_code
)
8616 return (COMMUTATIVE_P (x
)
8617 && (TARGET_NO_SPACE_REGS
8618 || (outer_code
!= UNKNOWN
&& outer_code
!= MEM
)
8619 || GET_CODE (x
) != PLUS
));
8622 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8623 use in fmpyadd instructions. */
8625 pa_fmpyaddoperands (rtx
*operands
)
8627 machine_mode mode
= GET_MODE (operands
[0]);
8629 /* Must be a floating point mode. */
8630 if (mode
!= SFmode
&& mode
!= DFmode
)
8633 /* All modes must be the same. */
8634 if (! (mode
== GET_MODE (operands
[1])
8635 && mode
== GET_MODE (operands
[2])
8636 && mode
== GET_MODE (operands
[3])
8637 && mode
== GET_MODE (operands
[4])
8638 && mode
== GET_MODE (operands
[5])))
8641 /* All operands must be registers. */
8642 if (! (GET_CODE (operands
[1]) == REG
8643 && GET_CODE (operands
[2]) == REG
8644 && GET_CODE (operands
[3]) == REG
8645 && GET_CODE (operands
[4]) == REG
8646 && GET_CODE (operands
[5]) == REG
))
8649 /* Only 2 real operands to the addition. One of the input operands must
8650 be the same as the output operand. */
8651 if (! rtx_equal_p (operands
[3], operands
[4])
8652 && ! rtx_equal_p (operands
[3], operands
[5]))
8655 /* Inout operand of add cannot conflict with any operands from multiply. */
8656 if (rtx_equal_p (operands
[3], operands
[0])
8657 || rtx_equal_p (operands
[3], operands
[1])
8658 || rtx_equal_p (operands
[3], operands
[2]))
8661 /* multiply cannot feed into addition operands. */
8662 if (rtx_equal_p (operands
[4], operands
[0])
8663 || rtx_equal_p (operands
[5], operands
[0]))
8666 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8668 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8669 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8670 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8671 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8672 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8673 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8676 /* Passed. Operands are suitable for fmpyadd. */
8680 #if !defined(USE_COLLECT2)
8682 pa_asm_out_constructor (rtx symbol
, int priority
)
8684 if (!function_label_operand (symbol
, VOIDmode
))
8685 pa_encode_label (symbol
);
8687 #ifdef CTORS_SECTION_ASM_OP
8688 default_ctor_section_asm_out_constructor (symbol
, priority
);
8690 # ifdef TARGET_ASM_NAMED_SECTION
8691 default_named_section_asm_out_constructor (symbol
, priority
);
8693 default_stabs_asm_out_constructor (symbol
, priority
);
8699 pa_asm_out_destructor (rtx symbol
, int priority
)
8701 if (!function_label_operand (symbol
, VOIDmode
))
8702 pa_encode_label (symbol
);
8704 #ifdef DTORS_SECTION_ASM_OP
8705 default_dtor_section_asm_out_destructor (symbol
, priority
);
8707 # ifdef TARGET_ASM_NAMED_SECTION
8708 default_named_section_asm_out_destructor (symbol
, priority
);
8710 default_stabs_asm_out_destructor (symbol
, priority
);
8716 /* This function places uninitialized global data in the bss section.
8717 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8718 function on the SOM port to prevent uninitialized global data from
8719 being placed in the data section. */
8722 pa_asm_output_aligned_bss (FILE *stream
,
8724 unsigned HOST_WIDE_INT size
,
8727 switch_to_section (bss_section
);
8728 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8730 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8731 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8734 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8735 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8738 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8739 ASM_OUTPUT_LABEL (stream
, name
);
8740 fprintf (stream
, "\t.block " HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8743 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8744 that doesn't allow the alignment of global common storage to be directly
8745 specified. The SOM linker aligns common storage based on the rounded
8746 value of the NUM_BYTES parameter in the .comm directive. It's not
8747 possible to use the .align directive as it doesn't affect the alignment
8748 of the label associated with a .comm directive. */
8751 pa_asm_output_aligned_common (FILE *stream
,
8753 unsigned HOST_WIDE_INT size
,
8756 unsigned int max_common_align
;
8758 max_common_align
= TARGET_64BIT
? 128 : (size
>= 4096 ? 256 : 64);
8759 if (align
> max_common_align
)
8761 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8762 "for global common data. Using %u",
8763 align
/ BITS_PER_UNIT
, name
, max_common_align
/ BITS_PER_UNIT
);
8764 align
= max_common_align
;
8767 switch_to_section (bss_section
);
8769 assemble_name (stream
, name
);
8770 fprintf (stream
, "\t.comm " HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8771 MAX (size
, align
/ BITS_PER_UNIT
));
8774 /* We can't use .comm for local common storage as the SOM linker effectively
8775 treats the symbol as universal and uses the same storage for local symbols
8776 with the same name in different object files. The .block directive
8777 reserves an uninitialized block of storage. However, it's not common
8778 storage. Fortunately, GCC never requests common storage with the same
8779 name in any given translation unit. */
8782 pa_asm_output_aligned_local (FILE *stream
,
8784 unsigned HOST_WIDE_INT size
,
8787 switch_to_section (bss_section
);
8788 fprintf (stream
, "\t.align %u\n", align
/ BITS_PER_UNIT
);
8791 fprintf (stream
, "%s", LOCAL_ASM_OP
);
8792 assemble_name (stream
, name
);
8793 fprintf (stream
, "\n");
8796 ASM_OUTPUT_LABEL (stream
, name
);
8797 fprintf (stream
, "\t.block " HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8800 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8801 use in fmpysub instructions. */
8803 pa_fmpysuboperands (rtx
*operands
)
8805 machine_mode mode
= GET_MODE (operands
[0]);
8807 /* Must be a floating point mode. */
8808 if (mode
!= SFmode
&& mode
!= DFmode
)
8811 /* All modes must be the same. */
8812 if (! (mode
== GET_MODE (operands
[1])
8813 && mode
== GET_MODE (operands
[2])
8814 && mode
== GET_MODE (operands
[3])
8815 && mode
== GET_MODE (operands
[4])
8816 && mode
== GET_MODE (operands
[5])))
8819 /* All operands must be registers. */
8820 if (! (GET_CODE (operands
[1]) == REG
8821 && GET_CODE (operands
[2]) == REG
8822 && GET_CODE (operands
[3]) == REG
8823 && GET_CODE (operands
[4]) == REG
8824 && GET_CODE (operands
[5]) == REG
))
8827 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8828 operation, so operands[4] must be the same as operand[3]. */
8829 if (! rtx_equal_p (operands
[3], operands
[4]))
8832 /* multiply cannot feed into subtraction. */
8833 if (rtx_equal_p (operands
[5], operands
[0]))
8836 /* Inout operand of sub cannot conflict with any operands from multiply. */
8837 if (rtx_equal_p (operands
[3], operands
[0])
8838 || rtx_equal_p (operands
[3], operands
[1])
8839 || rtx_equal_p (operands
[3], operands
[2]))
8842 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8844 && (REGNO_REG_CLASS (REGNO (operands
[0])) != FPUPPER_REGS
8845 || REGNO_REG_CLASS (REGNO (operands
[1])) != FPUPPER_REGS
8846 || REGNO_REG_CLASS (REGNO (operands
[2])) != FPUPPER_REGS
8847 || REGNO_REG_CLASS (REGNO (operands
[3])) != FPUPPER_REGS
8848 || REGNO_REG_CLASS (REGNO (operands
[4])) != FPUPPER_REGS
8849 || REGNO_REG_CLASS (REGNO (operands
[5])) != FPUPPER_REGS
))
8852 /* Passed. Operands are suitable for fmpysub. */
8856 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8857 constants for a MULT embedded inside a memory address. */
8859 pa_mem_shadd_constant_p (int val
)
8861 if (val
== 2 || val
== 4 || val
== 8)
8867 /* Return 1 if the given constant is 1, 2, or 3. These are the valid
8868 constants for shadd instructions. */
8870 pa_shadd_constant_p (int val
)
8872 if (val
== 1 || val
== 2 || val
== 3)
8878 /* Return TRUE if INSN branches forward. */
8881 forward_branch_p (rtx_insn
*insn
)
8883 rtx lab
= JUMP_LABEL (insn
);
8885 /* The INSN must have a jump label. */
8886 gcc_assert (lab
!= NULL_RTX
);
8888 if (INSN_ADDRESSES_SET_P ())
8889 return INSN_ADDRESSES (INSN_UID (lab
)) > INSN_ADDRESSES (INSN_UID (insn
));
8896 insn
= NEXT_INSN (insn
);
8902 /* Output an unconditional move and branch insn. */
8905 pa_output_parallel_movb (rtx
*operands
, rtx_insn
*insn
)
8907 int length
= get_attr_length (insn
);
8909 /* These are the cases in which we win. */
8911 return "mov%I1b,tr %1,%0,%2";
8913 /* None of the following cases win, but they don't lose either. */
8916 if (dbr_sequence_length () == 0)
8918 /* Nothing in the delay slot, fake it by putting the combined
8919 insn (the copy or add) in the delay slot of a bl. */
8920 if (GET_CODE (operands
[1]) == CONST_INT
)
8921 return "b %2\n\tldi %1,%0";
8923 return "b %2\n\tcopy %1,%0";
8927 /* Something in the delay slot, but we've got a long branch. */
8928 if (GET_CODE (operands
[1]) == CONST_INT
)
8929 return "ldi %1,%0\n\tb %2";
8931 return "copy %1,%0\n\tb %2";
8935 if (GET_CODE (operands
[1]) == CONST_INT
)
8936 output_asm_insn ("ldi %1,%0", operands
);
8938 output_asm_insn ("copy %1,%0", operands
);
8939 return pa_output_lbranch (operands
[2], insn
, 1);
8942 /* Output an unconditional add and branch insn. */
8945 pa_output_parallel_addb (rtx
*operands
, rtx_insn
*insn
)
8947 int length
= get_attr_length (insn
);
8949 /* To make life easy we want operand0 to be the shared input/output
8950 operand and operand1 to be the readonly operand. */
8951 if (operands
[0] == operands
[1])
8952 operands
[1] = operands
[2];
8954 /* These are the cases in which we win. */
8956 return "add%I1b,tr %1,%0,%3";
8958 /* None of the following cases win, but they don't lose either. */
8961 if (dbr_sequence_length () == 0)
8962 /* Nothing in the delay slot, fake it by putting the combined
8963 insn (the copy or add) in the delay slot of a bl. */
8964 return "b %3\n\tadd%I1 %1,%0,%0";
8966 /* Something in the delay slot, but we've got a long branch. */
8967 return "add%I1 %1,%0,%0\n\tb %3";
8970 output_asm_insn ("add%I1 %1,%0,%0", operands
);
8971 return pa_output_lbranch (operands
[3], insn
, 1);
8974 /* We use this hook to perform a PA specific optimization which is difficult
8975 to do in earlier passes. */
8980 remove_useless_addtr_insns (1);
8982 if (pa_cpu
< PROCESSOR_8000
)
8983 pa_combine_instructions ();
8986 /* The PA has a number of odd instructions which can perform multiple
8987 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8988 it may be profitable to combine two instructions into one instruction
8989 with two outputs. It's not profitable PA2.0 machines because the
8990 two outputs would take two slots in the reorder buffers.
8992 This routine finds instructions which can be combined and combines
8993 them. We only support some of the potential combinations, and we
8994 only try common ways to find suitable instructions.
8996 * addb can add two registers or a register and a small integer
8997 and jump to a nearby (+-8k) location. Normally the jump to the
8998 nearby location is conditional on the result of the add, but by
8999 using the "true" condition we can make the jump unconditional.
9000 Thus addb can perform two independent operations in one insn.
9002 * movb is similar to addb in that it can perform a reg->reg
9003 or small immediate->reg copy and jump to a nearby (+-8k location).
9005 * fmpyadd and fmpysub can perform a FP multiply and either an
9006 FP add or FP sub if the operands of the multiply and add/sub are
9007 independent (there are other minor restrictions). Note both
9008 the fmpy and fadd/fsub can in theory move to better spots according
9009 to data dependencies, but for now we require the fmpy stay at a
9012 * Many of the memory operations can perform pre & post updates
9013 of index registers. GCC's pre/post increment/decrement addressing
9014 is far too simple to take advantage of all the possibilities. This
9015 pass may not be suitable since those insns may not be independent.
9017 * comclr can compare two ints or an int and a register, nullify
9018 the following instruction and zero some other register. This
9019 is more difficult to use as it's harder to find an insn which
9020 will generate a comclr than finding something like an unconditional
9021 branch. (conditional moves & long branches create comclr insns).
9023 * Most arithmetic operations can conditionally skip the next
9024 instruction. They can be viewed as "perform this operation
9025 and conditionally jump to this nearby location" (where nearby
9026 is an insns away). These are difficult to use due to the
9027 branch length restrictions. */
9030 pa_combine_instructions (void)
9034 /* This can get expensive since the basic algorithm is on the
9035 order of O(n^2) (or worse). Only do it for -O2 or higher
9036 levels of optimization. */
9040 /* Walk down the list of insns looking for "anchor" insns which
9041 may be combined with "floating" insns. As the name implies,
9042 "anchor" instructions don't move, while "floating" insns may
9044 rtx par
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, NULL_RTX
, NULL_RTX
));
9045 rtx_insn
*new_rtx
= make_insn_raw (par
);
9047 for (anchor
= get_insns (); anchor
; anchor
= NEXT_INSN (anchor
))
9049 enum attr_pa_combine_type anchor_attr
;
9050 enum attr_pa_combine_type floater_attr
;
9052 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9053 Also ignore any special USE insns. */
9054 if ((! NONJUMP_INSN_P (anchor
) && ! JUMP_P (anchor
) && ! CALL_P (anchor
))
9055 || GET_CODE (PATTERN (anchor
)) == USE
9056 || GET_CODE (PATTERN (anchor
)) == CLOBBER
)
9059 anchor_attr
= get_attr_pa_combine_type (anchor
);
9060 /* See if anchor is an insn suitable for combination. */
9061 if (anchor_attr
== PA_COMBINE_TYPE_FMPY
9062 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9063 || (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9064 && ! forward_branch_p (anchor
)))
9068 for (floater
= PREV_INSN (anchor
);
9070 floater
= PREV_INSN (floater
))
9072 if (NOTE_P (floater
)
9073 || (NONJUMP_INSN_P (floater
)
9074 && (GET_CODE (PATTERN (floater
)) == USE
9075 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9078 /* Anything except a regular INSN will stop our search. */
9079 if (! NONJUMP_INSN_P (floater
))
9085 /* See if FLOATER is suitable for combination with the
9087 floater_attr
= get_attr_pa_combine_type (floater
);
9088 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9089 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9090 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9091 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9093 /* If ANCHOR and FLOATER can be combined, then we're
9094 done with this pass. */
9095 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9096 SET_DEST (PATTERN (floater
)),
9097 XEXP (SET_SRC (PATTERN (floater
)), 0),
9098 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9102 else if (anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
9103 && floater_attr
== PA_COMBINE_TYPE_ADDMOVE
)
9105 if (GET_CODE (SET_SRC (PATTERN (floater
))) == PLUS
)
9107 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9108 SET_DEST (PATTERN (floater
)),
9109 XEXP (SET_SRC (PATTERN (floater
)), 0),
9110 XEXP (SET_SRC (PATTERN (floater
)), 1)))
9115 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 0,
9116 SET_DEST (PATTERN (floater
)),
9117 SET_SRC (PATTERN (floater
)),
9118 SET_SRC (PATTERN (floater
))))
9124 /* If we didn't find anything on the backwards scan try forwards. */
9126 && (anchor_attr
== PA_COMBINE_TYPE_FMPY
9127 || anchor_attr
== PA_COMBINE_TYPE_FADDSUB
))
9129 for (floater
= anchor
; floater
; floater
= NEXT_INSN (floater
))
9131 if (NOTE_P (floater
)
9132 || (NONJUMP_INSN_P (floater
)
9133 && (GET_CODE (PATTERN (floater
)) == USE
9134 || GET_CODE (PATTERN (floater
)) == CLOBBER
)))
9138 /* Anything except a regular INSN will stop our search. */
9139 if (! NONJUMP_INSN_P (floater
))
9145 /* See if FLOATER is suitable for combination with the
9147 floater_attr
= get_attr_pa_combine_type (floater
);
9148 if ((anchor_attr
== PA_COMBINE_TYPE_FMPY
9149 && floater_attr
== PA_COMBINE_TYPE_FADDSUB
)
9150 || (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9151 && floater_attr
== PA_COMBINE_TYPE_FMPY
))
9153 /* If ANCHOR and FLOATER can be combined, then we're
9154 done with this pass. */
9155 if (pa_can_combine_p (new_rtx
, anchor
, floater
, 1,
9156 SET_DEST (PATTERN (floater
)),
9157 XEXP (SET_SRC (PATTERN (floater
)),
9159 XEXP (SET_SRC (PATTERN (floater
)),
9166 /* FLOATER will be nonzero if we found a suitable floating
9167 insn for combination with ANCHOR. */
9169 && (anchor_attr
== PA_COMBINE_TYPE_FADDSUB
9170 || anchor_attr
== PA_COMBINE_TYPE_FMPY
))
9172 /* Emit the new instruction and delete the old anchor. */
9173 rtvec vtemp
= gen_rtvec (2, copy_rtx (PATTERN (anchor
)),
9174 copy_rtx (PATTERN (floater
)));
9175 rtx temp
= gen_rtx_PARALLEL (VOIDmode
, vtemp
);
9176 emit_insn_before (temp
, anchor
);
9178 SET_INSN_DELETED (anchor
);
9180 /* Emit a special USE insn for FLOATER, then delete
9181 the floating insn. */
9182 temp
= copy_rtx (PATTERN (floater
));
9183 emit_insn_before (gen_rtx_USE (VOIDmode
, temp
), floater
);
9184 delete_insn (floater
);
9189 && anchor_attr
== PA_COMBINE_TYPE_UNCOND_BRANCH
)
9191 /* Emit the new_jump instruction and delete the old anchor. */
9192 rtvec vtemp
= gen_rtvec (2, copy_rtx (PATTERN (anchor
)),
9193 copy_rtx (PATTERN (floater
)));
9194 rtx temp
= gen_rtx_PARALLEL (VOIDmode
, vtemp
);
9195 temp
= emit_jump_insn_before (temp
, anchor
);
9197 JUMP_LABEL (temp
) = JUMP_LABEL (anchor
);
9198 SET_INSN_DELETED (anchor
);
9200 /* Emit a special USE insn for FLOATER, then delete
9201 the floating insn. */
9202 temp
= copy_rtx (PATTERN (floater
));
9203 emit_insn_before (gen_rtx_USE (VOIDmode
, temp
), floater
);
9204 delete_insn (floater
);
9212 pa_can_combine_p (rtx_insn
*new_rtx
, rtx_insn
*anchor
, rtx_insn
*floater
,
9213 int reversed
, rtx dest
,
9216 int insn_code_number
;
9217 rtx_insn
*start
, *end
;
9219 /* Create a PARALLEL with the patterns of ANCHOR and
9220 FLOATER, try to recognize it, then test constraints
9221 for the resulting pattern.
9223 If the pattern doesn't match or the constraints
9224 aren't met keep searching for a suitable floater
9226 XVECEXP (PATTERN (new_rtx
), 0, 0) = PATTERN (anchor
);
9227 XVECEXP (PATTERN (new_rtx
), 0, 1) = PATTERN (floater
);
9228 INSN_CODE (new_rtx
) = -1;
9229 insn_code_number
= recog_memoized (new_rtx
);
9230 basic_block bb
= BLOCK_FOR_INSN (anchor
);
9231 if (insn_code_number
< 0
9232 || (extract_insn (new_rtx
),
9233 !constrain_operands (1, get_preferred_alternatives (new_rtx
, bb
))))
9247 /* There's up to three operands to consider. One
9248 output and two inputs.
9250 The output must not be used between FLOATER & ANCHOR
9251 exclusive. The inputs must not be set between
9252 FLOATER and ANCHOR exclusive. */
9254 if (reg_used_between_p (dest
, start
, end
))
9257 if (reg_set_between_p (src1
, start
, end
))
9260 if (reg_set_between_p (src2
, start
, end
))
9263 /* If we get here, then everything is good. */
9267 /* Return nonzero if references for INSN are delayed.
9269 Millicode insns are actually function calls with some special
9270 constraints on arguments and register usage.
9272 Millicode calls always expect their arguments in the integer argument
9273 registers, and always return their result in %r29 (ret1). They
9274 are expected to clobber their arguments, %r1, %r29, and the return
9275 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9277 This function tells reorg that the references to arguments and
9278 millicode calls do not appear to happen until after the millicode call.
9279 This allows reorg to put insns which set the argument registers into the
9280 delay slot of the millicode call -- thus they act more like traditional
9283 Note we cannot consider side effects of the insn to be delayed because
9284 the branch and link insn will clobber the return pointer. If we happened
9285 to use the return pointer in the delay slot of the call, then we lose.
9287 get_attr_type will try to recognize the given insn, so make sure to
9288 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9291 pa_insn_refs_are_delayed (rtx_insn
*insn
)
9293 return ((NONJUMP_INSN_P (insn
)
9294 && GET_CODE (PATTERN (insn
)) != SEQUENCE
9295 && GET_CODE (PATTERN (insn
)) != USE
9296 && GET_CODE (PATTERN (insn
)) != CLOBBER
9297 && get_attr_type (insn
) == TYPE_MILLI
));
9300 /* Promote the return value, but not the arguments. */
9303 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9305 int *punsignedp ATTRIBUTE_UNUSED
,
9306 const_tree fntype ATTRIBUTE_UNUSED
,
9309 if (for_return
== 0)
9311 return promote_mode (type
, mode
, punsignedp
);
9314 /* On the HP-PA the value is found in register(s) 28(-29), unless
9315 the mode is SF or DF. Then the value is returned in fr4 (32).
9317 This must perform the same promotions as PROMOTE_MODE, else promoting
9318 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9320 Small structures must be returned in a PARALLEL on PA64 in order
9321 to match the HP Compiler ABI. */
9324 pa_function_value (const_tree valtype
,
9325 const_tree func ATTRIBUTE_UNUSED
,
9326 bool outgoing ATTRIBUTE_UNUSED
)
9328 machine_mode valmode
;
9330 if (AGGREGATE_TYPE_P (valtype
)
9331 || TREE_CODE (valtype
) == COMPLEX_TYPE
9332 || TREE_CODE (valtype
) == VECTOR_TYPE
)
9334 HOST_WIDE_INT valsize
= int_size_in_bytes (valtype
);
9336 /* Handle aggregates that fit exactly in a word or double word. */
9337 if ((valsize
& (UNITS_PER_WORD
- 1)) == 0)
9338 return gen_rtx_REG (TYPE_MODE (valtype
), 28);
9342 /* Aggregates with a size less than or equal to 128 bits are
9343 returned in GR 28(-29). They are left justified. The pad
9344 bits are undefined. Larger aggregates are returned in
9348 int ub
= valsize
<= UNITS_PER_WORD
? 1 : 2;
9350 for (i
= 0; i
< ub
; i
++)
9352 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9353 gen_rtx_REG (DImode
, 28 + i
),
9358 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (ub
, loc
));
9360 else if (valsize
> UNITS_PER_WORD
)
9362 /* Aggregates 5 to 8 bytes in size are returned in general
9363 registers r28-r29 in the same manner as other non
9364 floating-point objects. The data is right-justified and
9365 zero-extended to 64 bits. This is opposite to the normal
9366 justification used on big endian targets and requires
9367 special treatment. */
9368 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9369 gen_rtx_REG (DImode
, 28), const0_rtx
);
9370 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9374 if ((INTEGRAL_TYPE_P (valtype
)
9375 && GET_MODE_BITSIZE (TYPE_MODE (valtype
)) < BITS_PER_WORD
)
9376 || POINTER_TYPE_P (valtype
))
9377 valmode
= word_mode
;
9379 valmode
= TYPE_MODE (valtype
);
9381 if (TREE_CODE (valtype
) == REAL_TYPE
9382 && !AGGREGATE_TYPE_P (valtype
)
9383 && TYPE_MODE (valtype
) != TFmode
9384 && !TARGET_SOFT_FLOAT
)
9385 return gen_rtx_REG (valmode
, 32);
9387 return gen_rtx_REG (valmode
, 28);
9390 /* Implement the TARGET_LIBCALL_VALUE hook. */
9393 pa_libcall_value (machine_mode mode
,
9394 const_rtx fun ATTRIBUTE_UNUSED
)
9396 if (! TARGET_SOFT_FLOAT
9397 && (mode
== SFmode
|| mode
== DFmode
))
9398 return gen_rtx_REG (mode
, 32);
9400 return gen_rtx_REG (mode
, 28);
9403 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9406 pa_function_value_regno_p (const unsigned int regno
)
9409 || (! TARGET_SOFT_FLOAT
&& regno
== 32))
9415 /* Update the data in CUM to advance over argument ARG. */
9418 pa_function_arg_advance (cumulative_args_t cum_v
,
9419 const function_arg_info
&arg
)
9421 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9422 int arg_size
= pa_function_arg_size (arg
.mode
, arg
.type
);
9424 cum
->nargs_prototype
--;
9425 cum
->words
+= (arg_size
9426 + ((cum
->words
& 01)
9427 && arg
.type
!= NULL_TREE
9431 /* Return the location of a parameter that is passed in a register or NULL
9432 if the parameter has any component that is passed in memory.
9434 This is new code and will be pushed to into the net sources after
9437 ??? We might want to restructure this so that it looks more like other
9440 pa_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
9442 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9443 tree type
= arg
.type
;
9444 machine_mode mode
= arg
.mode
;
9445 int max_arg_words
= (TARGET_64BIT
? 8 : 4);
9452 if (arg
.end_marker_p ())
9455 arg_size
= pa_function_arg_size (mode
, type
);
9457 /* If this arg would be passed partially or totally on the stack, then
9458 this routine should return zero. pa_arg_partial_bytes will
9459 handle arguments which are split between regs and stack slots if
9460 the ABI mandates split arguments. */
9463 /* The 32-bit ABI does not split arguments. */
9464 if (cum
->words
+ arg_size
> max_arg_words
)
9470 alignment
= cum
->words
& 1;
9471 if (cum
->words
+ alignment
>= max_arg_words
)
9475 /* The 32bit ABIs and the 64bit ABIs are rather different,
9476 particularly in their handling of FP registers. We might
9477 be able to cleverly share code between them, but I'm not
9478 going to bother in the hope that splitting them up results
9479 in code that is more easily understood. */
9483 /* Advance the base registers to their current locations.
9485 Remember, gprs grow towards smaller register numbers while
9486 fprs grow to higher register numbers. Also remember that
9487 although FP regs are 32-bit addressable, we pretend that
9488 the registers are 64-bits wide. */
9489 gpr_reg_base
= 26 - cum
->words
;
9490 fpr_reg_base
= 32 + cum
->words
;
9492 /* Arguments wider than one word and small aggregates need special
9496 || (type
&& (AGGREGATE_TYPE_P (type
)
9497 || TREE_CODE (type
) == COMPLEX_TYPE
9498 || TREE_CODE (type
) == VECTOR_TYPE
)))
9500 /* Double-extended precision (80-bit), quad-precision (128-bit)
9501 and aggregates including complex numbers are aligned on
9502 128-bit boundaries. The first eight 64-bit argument slots
9503 are associated one-to-one, with general registers r26
9504 through r19, and also with floating-point registers fr4
9505 through fr11. Arguments larger than one word are always
9506 passed in general registers.
9508 Using a PARALLEL with a word mode register results in left
9509 justified data on a big-endian target. */
9512 int i
, offset
= 0, ub
= arg_size
;
9514 /* Align the base register. */
9515 gpr_reg_base
-= alignment
;
9517 ub
= MIN (ub
, max_arg_words
- cum
->words
- alignment
);
9518 for (i
= 0; i
< ub
; i
++)
9520 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
9521 gen_rtx_REG (DImode
, gpr_reg_base
),
9527 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (ub
, loc
));
9532 /* If the argument is larger than a word, then we know precisely
9533 which registers we must use. */
9547 /* Structures 5 to 8 bytes in size are passed in the general
9548 registers in the same manner as other non floating-point
9549 objects. The data is right-justified and zero-extended
9550 to 64 bits. This is opposite to the normal justification
9551 used on big endian targets and requires special treatment.
9552 We now define BLOCK_REG_PADDING to pad these objects.
9553 Aggregates, complex and vector types are passed in the same
9554 manner as structures. */
9556 || (type
&& (AGGREGATE_TYPE_P (type
)
9557 || TREE_CODE (type
) == COMPLEX_TYPE
9558 || TREE_CODE (type
) == VECTOR_TYPE
)))
9560 rtx loc
= gen_rtx_EXPR_LIST (VOIDmode
,
9561 gen_rtx_REG (DImode
, gpr_reg_base
),
9563 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec (1, loc
));
9568 /* We have a single word (32 bits). A simple computation
9569 will get us the register #s we need. */
9570 gpr_reg_base
= 26 - cum
->words
;
9571 fpr_reg_base
= 32 + 2 * cum
->words
;
9575 /* Determine if the argument needs to be passed in both general and
9576 floating point registers. */
9577 if (((TARGET_PORTABLE_RUNTIME
|| TARGET_64BIT
|| TARGET_ELF32
)
9578 /* If we are doing soft-float with portable runtime, then there
9579 is no need to worry about FP regs. */
9580 && !TARGET_SOFT_FLOAT
9581 /* The parameter must be some kind of scalar float, else we just
9582 pass it in integer registers. */
9583 && GET_MODE_CLASS (mode
) == MODE_FLOAT
9584 /* The target function must not have a prototype. */
9585 && cum
->nargs_prototype
<= 0
9586 /* libcalls do not need to pass items in both FP and general
9588 && type
!= NULL_TREE
9589 /* All this hair applies to "outgoing" args only. This includes
9590 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9592 /* Also pass outgoing floating arguments in both registers in indirect
9593 calls with the 32 bit ABI and the HP assembler since there is no
9594 way to the specify argument locations in static functions. */
9599 && GET_MODE_CLASS (mode
) == MODE_FLOAT
))
9605 gen_rtx_EXPR_LIST (VOIDmode
,
9606 gen_rtx_REG (mode
, fpr_reg_base
),
9608 gen_rtx_EXPR_LIST (VOIDmode
,
9609 gen_rtx_REG (mode
, gpr_reg_base
),
9614 /* See if we should pass this parameter in a general register. */
9615 if (TARGET_SOFT_FLOAT
9616 /* Indirect calls in the normal 32bit ABI require all arguments
9617 to be passed in general registers. */
9618 || (!TARGET_PORTABLE_RUNTIME
9622 /* If the parameter is not a scalar floating-point parameter,
9623 then it belongs in GPRs. */
9624 || GET_MODE_CLASS (mode
) != MODE_FLOAT
9625 /* Structure with single SFmode field belongs in GPR. */
9626 || (type
&& AGGREGATE_TYPE_P (type
)))
9627 retval
= gen_rtx_REG (mode
, gpr_reg_base
);
9629 retval
= gen_rtx_REG (mode
, fpr_reg_base
);
9634 /* Arguments larger than one word are double word aligned. */
9637 pa_function_arg_boundary (machine_mode mode
, const_tree type
)
9639 bool singleword
= (type
9640 ? (integer_zerop (TYPE_SIZE (type
))
9641 || !TREE_CONSTANT (TYPE_SIZE (type
))
9642 || int_size_in_bytes (type
) <= UNITS_PER_WORD
)
9643 : GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
);
9645 return singleword
? PARM_BOUNDARY
: MAX_PARM_BOUNDARY
;
9648 /* If this arg would be passed totally in registers or totally on the stack,
9649 then this routine should return zero. */
9652 pa_arg_partial_bytes (cumulative_args_t cum_v
, const function_arg_info
&arg
)
9654 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9655 unsigned int max_arg_words
= 8;
9656 unsigned int offset
= 0;
9661 if (pa_function_arg_size (arg
.mode
, arg
.type
) > 1 && (cum
->words
& 1))
9664 if (cum
->words
+ offset
+ pa_function_arg_size (arg
.mode
, arg
.type
)
9666 /* Arg fits fully into registers. */
9668 else if (cum
->words
+ offset
>= max_arg_words
)
9669 /* Arg fully on the stack. */
9673 return (max_arg_words
- cum
->words
- offset
) * UNITS_PER_WORD
;
9677 /* A get_unnamed_section callback for switching to the text section.
9679 This function is only used with SOM. Because we don't support
9680 named subspaces, we can only create a new subspace or switch back
9681 to the default text subspace. */
9684 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
9686 gcc_assert (TARGET_SOM
);
9689 if (cfun
&& cfun
->machine
&& !cfun
->machine
->in_nsubspa
)
9691 /* We only want to emit a .nsubspa directive once at the
9692 start of the function. */
9693 cfun
->machine
->in_nsubspa
= 1;
9695 /* Create a new subspace for the text. This provides
9696 better stub placement and one-only functions. */
9698 && DECL_ONE_ONLY (cfun
->decl
)
9699 && !DECL_WEAK (cfun
->decl
))
9701 output_section_asm_op ("\t.SPACE $TEXT$\n"
9702 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9703 "ACCESS=44,SORT=24,COMDAT");
9709 /* There isn't a current function or the body of the current
9710 function has been completed. So, we are changing to the
9711 text section to output debugging information. Thus, we
9712 need to forget that we are in the text section so that
9713 varasm.c will call us when text_section is selected again. */
9714 gcc_assert (!cfun
|| !cfun
->machine
9715 || cfun
->machine
->in_nsubspa
== 2);
9718 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9721 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9724 /* A get_unnamed_section callback for switching to comdat data
9725 sections. This function is only used with SOM. */
9728 som_output_comdat_data_section_asm_op (const void *data
)
9731 output_section_asm_op (data
);
9734 /* Implement TARGET_ASM_INIT_SECTIONS. */
9737 pa_som_asm_init_sections (void)
9740 = get_unnamed_section (0, som_output_text_section_asm_op
, NULL
);
9742 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9743 is not being generated. */
9744 som_readonly_data_section
9745 = get_unnamed_section (0, output_section_asm_op
,
9746 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9748 /* When secondary definitions are not supported, SOM makes readonly
9749 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9751 som_one_only_readonly_data_section
9752 = get_unnamed_section (0, som_output_comdat_data_section_asm_op
,
9754 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9755 "ACCESS=0x2c,SORT=16,COMDAT");
9758 /* When secondary definitions are not supported, SOM makes data one-only
9759 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9760 som_one_only_data_section
9761 = get_unnamed_section (SECTION_WRITE
,
9762 som_output_comdat_data_section_asm_op
,
9763 "\t.SPACE $PRIVATE$\n"
9764 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9765 "ACCESS=31,SORT=24,COMDAT");
9768 som_tm_clone_table_section
9769 = get_unnamed_section (0, output_section_asm_op
,
9770 "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$");
9772 /* HPUX ld generates incorrect GOT entries for "T" fixups which
9773 reference data within the $TEXT$ space (for example constant
9774 strings in the $LIT$ subspace).
9776 The assemblers (GAS and HP as) both have problems with handling
9777 the difference of two symbols. This is the other correct way to
9778 reference constant data during PIC code generation.
9780 Thus, we can't put constant data needing relocation in the $TEXT$
9781 space during PIC generation.
9783 Previously, we placed all constant data into the $DATA$ subspace
9784 when generating PIC code. This reduces sharing, but it works
9785 correctly. Now we rely on pa_reloc_rw_mask() for section selection.
9786 This puts constant data not needing relocation into the $TEXT$ space. */
9787 readonly_data_section
= som_readonly_data_section
;
9789 /* We must not have a reference to an external symbol defined in a
9790 shared library in a readonly section, else the SOM linker will
9793 So, we force exception information into the data section. */
9794 exception_section
= data_section
;
9797 /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */
9800 pa_som_tm_clone_table_section (void)
9802 return som_tm_clone_table_section
;
9805 /* On hpux10, the linker will give an error if we have a reference
9806 in the read-only data section to a symbol defined in a shared
9807 library. Therefore, expressions that might require a reloc
9808 cannot be placed in the read-only data section. */
9811 pa_select_section (tree exp
, int reloc
,
9812 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
9814 if (TREE_CODE (exp
) == VAR_DECL
9815 && TREE_READONLY (exp
)
9816 && !TREE_THIS_VOLATILE (exp
)
9817 && DECL_INITIAL (exp
)
9818 && (DECL_INITIAL (exp
) == error_mark_node
9819 || TREE_CONSTANT (DECL_INITIAL (exp
)))
9820 && !(reloc
& pa_reloc_rw_mask ()))
9823 && DECL_ONE_ONLY (exp
)
9824 && !DECL_WEAK (exp
))
9825 return som_one_only_readonly_data_section
;
9827 return readonly_data_section
;
9829 else if (CONSTANT_CLASS_P (exp
)
9830 && !(reloc
& pa_reloc_rw_mask ()))
9831 return readonly_data_section
;
9833 && TREE_CODE (exp
) == VAR_DECL
9834 && DECL_ONE_ONLY (exp
)
9835 && !DECL_WEAK (exp
))
9836 return som_one_only_data_section
;
9838 return data_section
;
9841 /* Implement pa_reloc_rw_mask. */
9844 pa_reloc_rw_mask (void)
9846 if (flag_pic
|| (TARGET_SOM
&& !TARGET_HPUX_11
))
9849 /* HP linker does not support global relocs in readonly memory. */
9850 return TARGET_SOM
? 2 : 0;
9854 pa_globalize_label (FILE *stream
, const char *name
)
9856 /* We only handle DATA objects here, functions are globalized in
9857 ASM_DECLARE_FUNCTION_NAME. */
9858 if (! FUNCTION_NAME_P (name
))
9860 fputs ("\t.EXPORT ", stream
);
9861 assemble_name (stream
, name
);
9862 fputs (",DATA\n", stream
);
9866 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9869 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9870 int incoming ATTRIBUTE_UNUSED
)
9872 return gen_rtx_REG (Pmode
, PA_STRUCT_VALUE_REGNUM
);
9875 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9878 pa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9880 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9881 PA64 ABI says that objects larger than 128 bits are returned in memory.
9882 Note, int_size_in_bytes can return -1 if the size of the object is
9883 variable or larger than the maximum value that can be expressed as
9884 a HOST_WIDE_INT. It can also return zero for an empty type. The
9885 simplest way to handle variable and empty types is to pass them in
9886 memory. This avoids problems in defining the boundaries of argument
9887 slots, allocating registers, etc. */
9888 return (int_size_in_bytes (type
) > (TARGET_64BIT
? 16 : 8)
9889 || int_size_in_bytes (type
) <= 0);
9892 /* Structure to hold declaration and name of external symbols that are
9893 emitted by GCC. We generate a vector of these symbols and output them
9894 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9895 This avoids putting out names that are never really used. */
9897 typedef struct GTY(()) extern_symbol
9903 /* Define gc'd vector type for extern_symbol. */
9905 /* Vector of extern_symbol pointers. */
9906 static GTY(()) vec
<extern_symbol
, va_gc
> *extern_symbols
;
9908 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9909 /* Mark DECL (name NAME) as an external reference (assembler output
9910 file FILE). This saves the names to output at the end of the file
9911 if actually referenced. */
9914 pa_hpux_asm_output_external (FILE *file
, tree decl
, const char *name
)
9916 gcc_assert (file
== asm_out_file
);
9917 extern_symbol p
= {decl
, name
};
9918 vec_safe_push (extern_symbols
, p
);
9922 /* Output text required at the end of an assembler file.
9923 This includes deferred plabels and .import directives for
9924 all external symbols that were actually referenced. */
9929 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9933 if (!NO_DEFERRED_PROFILE_COUNTERS
)
9934 output_deferred_profile_counters ();
9937 output_deferred_plabels ();
9939 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9940 for (i
= 0; vec_safe_iterate (extern_symbols
, i
, &p
); i
++)
9942 tree decl
= p
->decl
;
9944 if (!TREE_ASM_WRITTEN (decl
)
9945 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl
), 0)))
9946 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file
, decl
, p
->name
);
9949 vec_free (extern_symbols
);
9952 if (NEED_INDICATE_EXEC_STACK
)
9953 file_end_indicate_exec_stack ();
9956 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
9959 pa_can_change_mode_class (machine_mode from
, machine_mode to
,
9965 if (GET_MODE_SIZE (from
) == GET_MODE_SIZE (to
))
9968 /* Reject changes to/from modes with zero size. */
9969 if (!GET_MODE_SIZE (from
) || !GET_MODE_SIZE (to
))
9972 /* Reject changes to/from complex and vector modes. */
9973 if (COMPLEX_MODE_P (from
) || VECTOR_MODE_P (from
)
9974 || COMPLEX_MODE_P (to
) || VECTOR_MODE_P (to
))
9977 /* There is no way to load QImode or HImode values directly from memory
9978 to a FP register. SImode loads to the FP registers are not zero
9979 extended. On the 64-bit target, this conflicts with the definition
9980 of LOAD_EXTEND_OP. Thus, we reject all mode changes in the FP registers
9981 except for DImode to SImode on the 64-bit target. It is handled by
9982 register renaming in pa_print_operand. */
9983 if (MAYBE_FP_REG_CLASS_P (rclass
))
9984 return TARGET_64BIT
&& from
== DImode
&& to
== SImode
;
9986 /* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word
9987 in specific sets of registers. Thus, we cannot allow changing
9988 to a larger mode when it's larger than a word. */
9989 if (GET_MODE_SIZE (to
) > UNITS_PER_WORD
9990 && GET_MODE_SIZE (to
) > GET_MODE_SIZE (from
))
9996 /* Implement TARGET_MODES_TIEABLE_P.
9998 We should return FALSE for QImode and HImode because these modes
9999 are not ok in the floating-point registers. However, this prevents
10000 tieing these modes to SImode and DImode in the general registers.
10001 So, this isn't a good idea. We rely on TARGET_HARD_REGNO_MODE_OK and
10002 TARGET_CAN_CHANGE_MODE_CLASS to prevent these modes from being used
10003 in the floating-point registers. */
10006 pa_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
10008 /* Don't tie modes in different classes. */
10009 if (GET_MODE_CLASS (mode1
) != GET_MODE_CLASS (mode2
))
10016 /* Length in units of the trampoline instruction code. */
10018 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 36 : 48))
10021 /* Output assembler code for a block containing the constant parts
10022 of a trampoline, leaving space for the variable parts.\
10024 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10025 and then branches to the specified routine.
10027 This code template is copied from text segment to stack location
10028 and then patched with pa_trampoline_init to contain valid values,
10029 and then entered as a subroutine.
10031 It is best to keep this as small as possible to avoid having to
10032 flush multiple lines in the cache. */
10035 pa_asm_trampoline_template (FILE *f
)
10041 fputs ("\tmfia %r20\n", f
);
10042 fputs ("\tldw 48(%r20),%r22\n", f
);
10043 fputs ("\tcopy %r22,%r21\n", f
);
10044 fputs ("\tbb,>=,n %r22,30,.+16\n", f
);
10045 fputs ("\tdepwi 0,31,2,%r22\n", f
);
10046 fputs ("\tldw 0(%r22),%r21\n", f
);
10047 fputs ("\tldw 4(%r22),%r19\n", f
);
10048 fputs ("\tbve (%r21)\n", f
);
10049 fputs ("\tldw 52(%r1),%r29\n", f
);
10050 fputs ("\t.word 0\n", f
);
10051 fputs ("\t.word 0\n", f
);
10052 fputs ("\t.word 0\n", f
);
10056 if (ASSEMBLER_DIALECT
== 0)
10058 fputs ("\tbl .+8,%r20\n", f
);
10059 fputs ("\tdepi 0,31,2,%r20\n", f
);
10063 fputs ("\tb,l .+8,%r20\n", f
);
10064 fputs ("\tdepwi 0,31,2,%r20\n", f
);
10066 fputs ("\tldw 40(%r20),%r22\n", f
);
10067 fputs ("\tcopy %r22,%r21\n", f
);
10068 fputs ("\tbb,>=,n %r22,30,.+16\n", f
);
10069 if (ASSEMBLER_DIALECT
== 0)
10070 fputs ("\tdepi 0,31,2,%r22\n", f
);
10072 fputs ("\tdepwi 0,31,2,%r22\n", f
);
10073 fputs ("\tldw 0(%r22),%r21\n", f
);
10074 fputs ("\tldw 4(%r22),%r19\n", f
);
10075 fputs ("\tldsid (%r21),%r1\n", f
);
10076 fputs ("\tmtsp %r1,%sr0\n", f
);
10077 fputs ("\tbe 0(%sr0,%r21)\n", f
);
10078 fputs ("\tldw 44(%r20),%r29\n", f
);
10080 fputs ("\t.word 0\n", f
);
10081 fputs ("\t.word 0\n", f
);
10082 fputs ("\t.word 0\n", f
);
10083 fputs ("\t.word 0\n", f
);
10087 fputs ("\t.dword 0\n", f
);
10088 fputs ("\t.dword 0\n", f
);
10089 fputs ("\t.dword 0\n", f
);
10090 fputs ("\t.dword 0\n", f
);
10091 fputs ("\tmfia %r31\n", f
);
10092 fputs ("\tldd 24(%r31),%r27\n", f
);
10093 fputs ("\tldd 32(%r31),%r31\n", f
);
10094 fputs ("\tldd 16(%r27),%r1\n", f
);
10095 fputs ("\tbve (%r1)\n", f
);
10096 fputs ("\tldd 24(%r27),%r27\n", f
);
10097 fputs ("\t.dword 0 ; fptr\n", f
);
10098 fputs ("\t.dword 0 ; static link\n", f
);
10102 /* Emit RTL insns to initialize the variable parts of a trampoline.
10103 FNADDR is an RTX for the address of the function's pure code.
10104 CXT is an RTX for the static chain value for the function.
10106 Move the function address to the trampoline template at offset 48.
10107 Move the static chain value to trampoline template at offset 52.
10108 Move the trampoline address to trampoline template at offset 56.
10109 Move r19 to trampoline template at offset 60. The latter two
10110 words create a plabel for the indirect call to the trampoline.
10112 A similar sequence is used for the 64-bit port but the plabel is
10113 at the beginning of the trampoline.
10115 Finally, the cache entries for the trampoline code are flushed.
10116 This is necessary to ensure that the trampoline instruction sequence
10117 is written to memory prior to any attempts at prefetching the code
10121 pa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
10123 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
10124 rtx start_addr
= gen_reg_rtx (Pmode
);
10125 rtx end_addr
= gen_reg_rtx (Pmode
);
10126 rtx line_length
= gen_reg_rtx (Pmode
);
10129 emit_block_move (m_tramp
, assemble_trampoline_template (),
10130 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
10131 r_tramp
= force_reg (Pmode
, XEXP (m_tramp
, 0));
10135 tmp
= adjust_address (m_tramp
, Pmode
, 48);
10136 emit_move_insn (tmp
, fnaddr
);
10137 tmp
= adjust_address (m_tramp
, Pmode
, 52);
10138 emit_move_insn (tmp
, chain_value
);
10140 /* Create a fat pointer for the trampoline. */
10141 tmp
= adjust_address (m_tramp
, Pmode
, 56);
10142 emit_move_insn (tmp
, r_tramp
);
10143 tmp
= adjust_address (m_tramp
, Pmode
, 60);
10144 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 19));
10146 /* fdc and fic only use registers for the address to flush,
10147 they do not accept integer displacements. We align the
10148 start and end addresses to the beginning of their respective
10149 cache lines to minimize the number of lines flushed. */
10150 emit_insn (gen_andsi3 (start_addr
, r_tramp
,
10151 GEN_INT (-MIN_CACHELINE_SIZE
)));
10152 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
,
10153 TRAMPOLINE_CODE_SIZE
-1));
10154 emit_insn (gen_andsi3 (end_addr
, tmp
,
10155 GEN_INT (-MIN_CACHELINE_SIZE
)));
10156 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10157 emit_insn (gen_dcacheflushsi (start_addr
, end_addr
, line_length
));
10158 emit_insn (gen_icacheflushsi (start_addr
, end_addr
, line_length
,
10159 gen_reg_rtx (Pmode
),
10160 gen_reg_rtx (Pmode
)));
10164 tmp
= adjust_address (m_tramp
, Pmode
, 56);
10165 emit_move_insn (tmp
, fnaddr
);
10166 tmp
= adjust_address (m_tramp
, Pmode
, 64);
10167 emit_move_insn (tmp
, chain_value
);
10169 /* Create a fat pointer for the trampoline. */
10170 tmp
= adjust_address (m_tramp
, Pmode
, 16);
10171 emit_move_insn (tmp
, force_reg (Pmode
, plus_constant (Pmode
,
10173 tmp
= adjust_address (m_tramp
, Pmode
, 24);
10174 emit_move_insn (tmp
, gen_rtx_REG (Pmode
, 27));
10176 /* fdc and fic only use registers for the address to flush,
10177 they do not accept integer displacements. We align the
10178 start and end addresses to the beginning of their respective
10179 cache lines to minimize the number of lines flushed. */
10180 tmp
= force_reg (Pmode
, plus_constant (Pmode
, r_tramp
, 32));
10181 emit_insn (gen_anddi3 (start_addr
, tmp
,
10182 GEN_INT (-MIN_CACHELINE_SIZE
)));
10183 tmp
= force_reg (Pmode
, plus_constant (Pmode
, tmp
,
10184 TRAMPOLINE_CODE_SIZE
- 1));
10185 emit_insn (gen_anddi3 (end_addr
, tmp
,
10186 GEN_INT (-MIN_CACHELINE_SIZE
)));
10187 emit_move_insn (line_length
, GEN_INT (MIN_CACHELINE_SIZE
));
10188 emit_insn (gen_dcacheflushdi (start_addr
, end_addr
, line_length
));
10189 emit_insn (gen_icacheflushdi (start_addr
, end_addr
, line_length
,
10190 gen_reg_rtx (Pmode
),
10191 gen_reg_rtx (Pmode
)));
10194 #ifdef HAVE_ENABLE_EXECUTE_STACK
10195 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10196 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10200 /* Perform any machine-specific adjustment in the address of the trampoline.
10201 ADDR contains the address that was passed to pa_trampoline_init.
10202 Adjust the trampoline address to point to the plabel at offset 56. */
10205 pa_trampoline_adjust_address (rtx addr
)
10208 addr
= memory_address (Pmode
, plus_constant (Pmode
, addr
, 58));
10213 pa_delegitimize_address (rtx orig_x
)
10215 rtx x
= delegitimize_mem_from_attrs (orig_x
);
10217 if (GET_CODE (x
) == LO_SUM
10218 && GET_CODE (XEXP (x
, 1)) == UNSPEC
10219 && XINT (XEXP (x
, 1), 1) == UNSPEC_DLTIND14R
)
10220 return gen_const_mem (Pmode
, XVECEXP (XEXP (x
, 1), 0, 0));
10225 pa_internal_arg_pointer (void)
10227 /* The argument pointer and the hard frame pointer are the same in
10228 the 32-bit runtime, so we don't need a copy. */
10230 return copy_to_reg (virtual_incoming_args_rtx
);
10232 return virtual_incoming_args_rtx
;
10235 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10236 Frame pointer elimination is automatically handled. */
10239 pa_can_eliminate (const int from
, const int to
)
10241 /* The argument cannot be eliminated in the 64-bit runtime. */
10242 if (TARGET_64BIT
&& from
== ARG_POINTER_REGNUM
)
10245 return (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
10246 ? ! frame_pointer_needed
10250 /* Define the offset between two registers, FROM to be eliminated and its
10251 replacement TO, at the start of a routine. */
10253 pa_initial_elimination_offset (int from
, int to
)
10255 HOST_WIDE_INT offset
;
10257 if ((from
== HARD_FRAME_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
)
10258 && to
== STACK_POINTER_REGNUM
)
10259 offset
= -pa_compute_frame_size (get_frame_size (), 0);
10260 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
10263 gcc_unreachable ();
10269 pa_conditional_register_usage (void)
10273 if (!TARGET_64BIT
&& !TARGET_PA_11
)
10275 for (i
= 56; i
<= FP_REG_LAST
; i
++)
10276 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10277 for (i
= 33; i
< 56; i
+= 2)
10278 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10280 if (TARGET_DISABLE_FPREGS
|| TARGET_SOFT_FLOAT
)
10282 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
10283 fixed_regs
[i
] = call_used_regs
[i
] = 1;
10286 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10289 /* Target hook for c_mode_for_suffix. */
10291 static machine_mode
10292 pa_c_mode_for_suffix (char suffix
)
10294 if (HPUX_LONG_DOUBLE_LIBRARY
)
10303 /* Target hook for function_section. */
10306 pa_function_section (tree decl
, enum node_frequency freq
,
10307 bool startup
, bool exit
)
10309 /* Put functions in text section if target doesn't have named sections. */
10310 if (!targetm_common
.have_named_sections
)
10311 return text_section
;
10313 /* Force nested functions into the same section as the containing
10316 && DECL_SECTION_NAME (decl
) == NULL
10317 && DECL_CONTEXT (decl
) != NULL_TREE
10318 && TREE_CODE (DECL_CONTEXT (decl
)) == FUNCTION_DECL
10319 && DECL_SECTION_NAME (DECL_CONTEXT (decl
)) == NULL
)
10320 return function_section (DECL_CONTEXT (decl
));
10322 /* Otherwise, use the default function section. */
10323 return default_function_section (decl
, freq
, startup
, exit
);
10326 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
10328 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
10329 that need more than three instructions to load prior to reload. This
10330 limit is somewhat arbitrary. It takes three instructions to load a
10331 CONST_INT from memory but two are memory accesses. It may be better
10332 to increase the allowed range for CONST_INTS. We may also be able
10333 to handle CONST_DOUBLES. */
10336 pa_legitimate_constant_p (machine_mode mode
, rtx x
)
10338 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& x
!= CONST0_RTX (mode
))
10341 if (!NEW_HP_ASSEMBLER
&& !TARGET_GAS
&& GET_CODE (x
) == LABEL_REF
)
10344 /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
10345 legitimate constants. The other variants can't be handled by
10346 the move patterns after reload starts. */
10347 if (tls_referenced_p (x
))
10350 if (TARGET_64BIT
&& GET_CODE (x
) == CONST_DOUBLE
)
10354 && HOST_BITS_PER_WIDE_INT
> 32
10355 && GET_CODE (x
) == CONST_INT
10356 && !reload_in_progress
10357 && !reload_completed
10358 && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x
))
10359 && !pa_cint_ok_for_move (UINTVAL (x
)))
10362 if (function_label_operand (x
, mode
))
10368 /* Implement TARGET_SECTION_TYPE_FLAGS. */
10370 static unsigned int
10371 pa_section_type_flags (tree decl
, const char *name
, int reloc
)
10373 unsigned int flags
;
10375 flags
= default_section_type_flags (decl
, name
, reloc
);
10377 /* Function labels are placed in the constant pool. This can
10378 cause a section conflict if decls are put in ".data.rel.ro"
10379 or ".data.rel.ro.local" using the __attribute__ construct. */
10380 if (strcmp (name
, ".data.rel.ro") == 0
10381 || strcmp (name
, ".data.rel.ro.local") == 0)
10382 flags
|= SECTION_WRITE
| SECTION_RELRO
;
10387 /* pa_legitimate_address_p recognizes an RTL expression that is a
10388 valid memory address for an instruction. The MODE argument is the
10389 machine mode for the MEM expression that wants to use this address.
10391 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
10392 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
10393 available with floating point loads and stores, and integer loads.
10394 We get better code by allowing indexed addresses in the initial
10397 The acceptance of indexed addresses as legitimate implies that we
10398 must provide patterns for doing indexed integer stores, or the move
10399 expanders must force the address of an indexed store to a register.
10400 We have adopted the latter approach.
10402 Another function of pa_legitimate_address_p is to ensure that
10403 the base register is a valid pointer for indexed instructions.
10404 On targets that have non-equivalent space registers, we have to
10405 know at the time of assembler output which register in a REG+REG
10406 pair is the base register. The REG_POINTER flag is sometimes lost
10407 in reload and the following passes, so it can't be relied on during
10408 code generation. Thus, we either have to canonicalize the order
10409 of the registers in REG+REG indexed addresses, or treat REG+REG
10410 addresses separately and provide patterns for both permutations.
10412 The latter approach requires several hundred additional lines of
10413 code in pa.md. The downside to canonicalizing is that a PLUS
10414 in the wrong order can't combine to form to make a scaled indexed
10415 memory operand. As we won't need to canonicalize the operands if
10416 the REG_POINTER lossage can be fixed, it seems better canonicalize.
10418 We initially break out scaled indexed addresses in canonical order
10419 in pa_emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
10420 scaled indexed addresses during RTL generation. However, fold_rtx
10421 has its own opinion on how the operands of a PLUS should be ordered.
10422 If one of the operands is equivalent to a constant, it will make
10423 that operand the second operand. As the base register is likely to
10424 be equivalent to a SYMBOL_REF, we have made it the second operand.
10426 pa_legitimate_address_p accepts REG+REG as legitimate when the
10427 operands are in the order INDEX+BASE on targets with non-equivalent
10428 space registers, and in any order on targets with equivalent space
10429 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
10431 We treat a SYMBOL_REF as legitimate if it is part of the current
10432 function's constant-pool, because such addresses can actually be
10433 output as REG+SMALLINT. */
10436 pa_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
10439 && (strict
? STRICT_REG_OK_FOR_BASE_P (x
)
10440 : REG_OK_FOR_BASE_P (x
)))
10441 || ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
10442 || GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
)
10443 && REG_P (XEXP (x
, 0))
10444 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10445 : REG_OK_FOR_BASE_P (XEXP (x
, 0)))))
10448 if (GET_CODE (x
) == PLUS
)
10452 /* For REG+REG, the base register should be in XEXP (x, 1),
10453 so check it first. */
10454 if (REG_P (XEXP (x
, 1))
10455 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 1))
10456 : REG_OK_FOR_BASE_P (XEXP (x
, 1))))
10457 base
= XEXP (x
, 1), index
= XEXP (x
, 0);
10458 else if (REG_P (XEXP (x
, 0))
10459 && (strict
? STRICT_REG_OK_FOR_BASE_P (XEXP (x
, 0))
10460 : REG_OK_FOR_BASE_P (XEXP (x
, 0))))
10461 base
= XEXP (x
, 0), index
= XEXP (x
, 1);
10465 if (GET_CODE (index
) == CONST_INT
)
10467 if (INT_5_BITS (index
))
10470 /* When INT14_OK_STRICT is false, a secondary reload is needed
10471 to adjust the displacement of SImode and DImode floating point
10472 instructions but this may fail when the register also needs
10473 reloading. So, we return false when STRICT is true. We
10474 also reject long displacements for float mode addresses since
10475 the majority of accesses will use floating point instructions
10476 that don't support 14-bit offsets. */
10477 if (!INT14_OK_STRICT
10478 && (strict
|| !(reload_in_progress
|| reload_completed
))
10483 return base14_operand (index
, mode
);
10486 if (!TARGET_DISABLE_INDEXING
10487 /* Only accept the "canonical" INDEX+BASE operand order
10488 on targets with non-equivalent space registers. */
10489 && (TARGET_NO_SPACE_REGS
10491 : (base
== XEXP (x
, 1) && REG_P (index
)
10492 && (reload_completed
10493 || (reload_in_progress
&& HARD_REGISTER_P (base
))
10494 || REG_POINTER (base
))
10495 && (reload_completed
10496 || (reload_in_progress
&& HARD_REGISTER_P (index
))
10497 || !REG_POINTER (index
))))
10498 && MODE_OK_FOR_UNSCALED_INDEXING_P (mode
)
10499 && (strict
? STRICT_REG_OK_FOR_INDEX_P (index
)
10500 : REG_OK_FOR_INDEX_P (index
))
10501 && borx_reg_operand (base
, Pmode
)
10502 && borx_reg_operand (index
, Pmode
))
10505 if (!TARGET_DISABLE_INDEXING
10506 && GET_CODE (index
) == MULT
10507 /* Only accept base operands with the REG_POINTER flag prior to
10508 reload on targets with non-equivalent space registers. */
10509 && (TARGET_NO_SPACE_REGS
10510 || (base
== XEXP (x
, 1)
10511 && (reload_completed
10512 || (reload_in_progress
&& HARD_REGISTER_P (base
))
10513 || REG_POINTER (base
))))
10514 && REG_P (XEXP (index
, 0))
10515 && GET_MODE (XEXP (index
, 0)) == Pmode
10516 && MODE_OK_FOR_SCALED_INDEXING_P (mode
)
10517 && (strict
? STRICT_REG_OK_FOR_INDEX_P (XEXP (index
, 0))
10518 : REG_OK_FOR_INDEX_P (XEXP (index
, 0)))
10519 && GET_CODE (XEXP (index
, 1)) == CONST_INT
10520 && INTVAL (XEXP (index
, 1))
10521 == (HOST_WIDE_INT
) GET_MODE_SIZE (mode
)
10522 && borx_reg_operand (base
, Pmode
))
10528 if (GET_CODE (x
) == LO_SUM
)
10530 rtx y
= XEXP (x
, 0);
10532 if (GET_CODE (y
) == SUBREG
)
10533 y
= SUBREG_REG (y
);
10536 && (strict
? STRICT_REG_OK_FOR_BASE_P (y
)
10537 : REG_OK_FOR_BASE_P (y
)))
10539 /* Needed for -fPIC */
10541 && GET_CODE (XEXP (x
, 1)) == UNSPEC
)
10544 if (!INT14_OK_STRICT
10545 && (strict
|| !(reload_in_progress
|| reload_completed
))
10550 if (CONSTANT_P (XEXP (x
, 1)))
10556 if (GET_CODE (x
) == CONST_INT
&& INT_5_BITS (x
))
10562 /* Look for machine dependent ways to make the invalid address AD a
10565 For the PA, transform:
10567 memory(X + <large int>)
10571 if (<large int> & mask) >= 16
10572 Y = (<large int> & ~mask) + mask + 1 Round up.
10574 Y = (<large int> & ~mask) Round down.
10576 memory (Z + (<large int> - Y));
10578 This makes reload inheritance and reload_cse work better since Z
10581 There may be more opportunities to improve code with this hook. */
10584 pa_legitimize_reload_address (rtx ad
, machine_mode mode
,
10585 int opnum
, int type
,
10586 int ind_levels ATTRIBUTE_UNUSED
)
10588 long offset
, newoffset
, mask
;
10589 rtx new_rtx
, temp
= NULL_RTX
;
10591 mask
= (GET_MODE_CLASS (mode
) == MODE_FLOAT
10592 && !INT14_OK_STRICT
? 0x1f : 0x3fff);
10594 if (optimize
&& GET_CODE (ad
) == PLUS
)
10595 temp
= simplify_binary_operation (PLUS
, Pmode
,
10596 XEXP (ad
, 0), XEXP (ad
, 1));
10598 new_rtx
= temp
? temp
: ad
;
10601 && GET_CODE (new_rtx
) == PLUS
10602 && GET_CODE (XEXP (new_rtx
, 0)) == REG
10603 && GET_CODE (XEXP (new_rtx
, 1)) == CONST_INT
)
10605 offset
= INTVAL (XEXP ((new_rtx
), 1));
10607 /* Choose rounding direction. Round up if we are >= halfway. */
10608 if ((offset
& mask
) >= ((mask
+ 1) / 2))
10609 newoffset
= (offset
& ~mask
) + mask
+ 1;
10611 newoffset
= offset
& ~mask
;
10613 /* Ensure that long displacements are aligned. */
10615 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
10616 || (TARGET_64BIT
&& (mode
) == DImode
)))
10617 newoffset
&= ~(GET_MODE_SIZE (mode
) - 1);
10619 if (newoffset
!= 0 && VAL_14_BITS_P (newoffset
))
10621 temp
= gen_rtx_PLUS (Pmode
, XEXP (new_rtx
, 0),
10622 GEN_INT (newoffset
));
10623 ad
= gen_rtx_PLUS (Pmode
, temp
, GEN_INT (offset
- newoffset
));
10624 push_reload (XEXP (ad
, 0), 0, &XEXP (ad
, 0), 0,
10625 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
10626 opnum
, (enum reload_type
) type
);
10634 /* Output address vector. */
10637 pa_output_addr_vec (rtx lab
, rtx body
)
10639 int idx
, vlen
= XVECLEN (body
, 0);
10642 fputs ("\t.align 4\n", asm_out_file
);
10643 targetm
.asm_out
.internal_label (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10645 fputs ("\t.begin_brtab\n", asm_out_file
);
10646 for (idx
= 0; idx
< vlen
; idx
++)
10648 ASM_OUTPUT_ADDR_VEC_ELT
10649 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10652 fputs ("\t.end_brtab\n", asm_out_file
);
10655 /* Output address difference vector. */
10658 pa_output_addr_diff_vec (rtx lab
, rtx body
)
10660 rtx base
= XEXP (XEXP (body
, 0), 0);
10661 int idx
, vlen
= XVECLEN (body
, 1);
10663 targetm
.asm_out
.internal_label (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10665 fputs ("\t.begin_brtab\n", asm_out_file
);
10666 for (idx
= 0; idx
< vlen
; idx
++)
10668 ASM_OUTPUT_ADDR_DIFF_ELT
10671 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10672 CODE_LABEL_NUMBER (base
));
10675 fputs ("\t.end_brtab\n", asm_out_file
);
10678 /* This is a helper function for the other atomic operations. This function
10679 emits a loop that contains SEQ that iterates until a compare-and-swap
10680 operation at the end succeeds. MEM is the memory to be modified. SEQ is
10681 a set of instructions that takes a value from OLD_REG as an input and
10682 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
10683 set to the current contents of MEM. After SEQ, a compare-and-swap will
10684 attempt to update MEM with NEW_REG. The function returns true when the
10685 loop was generated successfully. */
10688 pa_expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
10690 machine_mode mode
= GET_MODE (mem
);
10691 rtx_code_label
*label
;
10692 rtx cmp_reg
, success
, oldval
;
10694 /* The loop we want to generate looks like
10700 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
10704 Note that we only do the plain load from memory once. Subsequent
10705 iterations use the value loaded by the compare-and-swap pattern. */
10707 label
= gen_label_rtx ();
10708 cmp_reg
= gen_reg_rtx (mode
);
10710 emit_move_insn (cmp_reg
, mem
);
10711 emit_label (label
);
10712 emit_move_insn (old_reg
, cmp_reg
);
10716 success
= NULL_RTX
;
10718 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
10719 new_reg
, false, MEMMODEL_SYNC_SEQ_CST
,
10723 if (oldval
!= cmp_reg
)
10724 emit_move_insn (cmp_reg
, oldval
);
10726 /* Mark this jump predicted not taken. */
10727 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
10728 GET_MODE (success
), 1, label
,
10729 profile_probability::guessed_never ());
10733 /* This function tries to implement an atomic exchange operation using a
10734 compare_and_swap loop. VAL is written to *MEM. The previous contents of
10735 *MEM are returned, using TARGET if possible. No memory model is required
10736 since a compare_and_swap loop is seq-cst. */
10739 pa_maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
10741 machine_mode mode
= GET_MODE (mem
);
10743 if (can_compare_and_swap_p (mode
, true))
10745 if (!target
|| !register_operand (target
, mode
))
10746 target
= gen_reg_rtx (mode
);
10747 if (pa_expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
10754 /* Implement TARGET_CALLEE_COPIES. The callee is responsible for copying
10755 arguments passed by hidden reference in the 32-bit HP runtime. Users
10756 can override this behavior for better compatibility with openmp at the
10757 risk of library incompatibilities. Arguments are always passed by value
10758 in the 64-bit HP runtime. */
10761 pa_callee_copies (cumulative_args_t
, const function_arg_info
&)
10763 return !TARGET_CALLER_COPIES
;
10766 /* Implement TARGET_HARD_REGNO_NREGS. */
10768 static unsigned int
10769 pa_hard_regno_nregs (unsigned int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
10771 return PA_HARD_REGNO_NREGS (regno
, mode
);
10774 /* Implement TARGET_HARD_REGNO_MODE_OK. */
10777 pa_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
10779 return PA_HARD_REGNO_MODE_OK (regno
, mode
);
10782 /* Implement TARGET_STARTING_FRAME_OFFSET.
10784 On the 32-bit ports, we reserve one slot for the previous frame
10785 pointer and one fill slot. The fill slot is for compatibility
10786 with HP compiled programs. On the 64-bit ports, we reserve one
10787 slot for the previous frame pointer. */
10789 static HOST_WIDE_INT
10790 pa_starting_frame_offset (void)
10795 /* Figure out the size in words of the function argument. The size
10796 returned by this function should always be greater than zero because
10797 we pass variable and zero sized objects by reference. */
10800 pa_function_arg_size (machine_mode mode
, const_tree type
)
10802 HOST_WIDE_INT size
;
10804 size
= mode
!= BLKmode
? GET_MODE_SIZE (mode
) : int_size_in_bytes (type
);
10805 return CEIL (size
, UNITS_PER_WORD
);