gcc/config/rs6000/constraints.md

   1 ;; Constraint definitions for RS6000
   2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Available constraint letters: e k q t u A B C D S T
  21
  22 ;; Register constraints
  23
  24 (define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]"
  25   "@internal")
  26
  27 (define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]"
  28   "@internal")
  29
  30 (define_register_constraint "b" "BASE_REGS"
  31   "@internal")
  32
  33 (define_register_constraint "h" "SPECIAL_REGS"
  34   "@internal")
  35
  36 (define_register_constraint "c" "CTR_REGS"
  37   "@internal")
  38
  39 (define_register_constraint "l" "LINK_REGS"
  40   "@internal")
  41
  42 (define_register_constraint "v" "ALTIVEC_REGS"
  43   "@internal")
  44
  45 (define_register_constraint "x" "CR0_REGS"
  46   "@internal")
  47
  48 (define_register_constraint "y" "CR_REGS"
  49   "@internal")
  50
  51 (define_register_constraint "z" "CA_REGS"
  52   "@internal")
  53
  54 ;; Use w as a prefix to add VSX modes
  55 ;; any VSX register
  56 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
  57   "Any VSX register if the -mvsx option was used or NO_REGS.")
  58
  59 ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
  60 ;; It is currently used for that purpose in LLVM.
  61
  62 (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
  63   "VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
  64
  65 ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
  66 ;; direct move directly, and movsf can't to move between the register sets.
  67 ;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
  68 (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
  69
  70 (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
  71   "General purpose register if 64-bit instructions are enabled or NO_REGS.")
  72
  73 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
  74   "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
  75
  76 (define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
  77   "BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
  78
  79 ;; wB needs ISA 2.07 VUPKHSW
  80 (define_constraint "wB"
  81   "Signed 5-bit constant integer that can be loaded into an altivec register."
  82   (and (match_code "const_int")
  83        (and (match_test "TARGET_P8_VECTOR")
  84             (match_operand 0 "s5bit_cint_operand"))))
  85
  86 (define_constraint "wD"
  87   "Int constant that is the element number of the 64-bit scalar in a vector."
  88   (and (match_code "const_int")
  89        (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)")))
  90
  91 (define_constraint "wE"
  92   "Vector constant that can be loaded with the XXSPLTIB instruction."
  93   (match_test "xxspltib_constant_nosplit (op, mode)"))
  94
  95 ;; Extended fusion store
  96 (define_memory_constraint "wF"
  97   "Memory operand suitable for power8 GPR load fusion"
  98   (match_operand 0 "fusion_addis_mem_combo_load"))
  99
 100 (define_constraint "wL"
 101   "Int constant that is the element number mfvsrld accesses in a vector."
 102   (and (match_code "const_int")
 103        (and (match_test "TARGET_DIRECT_MOVE_128")
 104             (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
 105
 106 ;; Generate the XXORC instruction to set a register to all 1's
 107 (define_constraint "wM"
 108   "Match vector constant with all 1's if the XXLORC instruction is available"
 109   (and (match_test "TARGET_P8_VECTOR")
 110        (match_operand 0 "all_ones_constant")))
 111
 112 ;; ISA 3.0 vector d-form addresses
 113 (define_memory_constraint "wO"
 114   "Memory operand suitable for the ISA 3.0 vector d-form instructions."
 115   (match_operand 0 "vsx_quad_dform_memory_operand"))
 116
 117 ;; Lq/stq validates the address for load/store quad
 118 (define_memory_constraint "wQ"
 119   "Memory operand suitable for the load/store quad instructions"
 120   (match_operand 0 "quad_memory_operand"))
 121
 122 (define_constraint "wS"
 123   "Vector constant that can be loaded with XXSPLTIB & sign extension."
 124   (match_test "xxspltib_constant_split (op, mode)"))
 125
 126 ;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form.
 127 ;; Used by LXSD/STXSD/LXSSP/STXSSP.  In contrast to "Y", the multiple-of-four
 128 ;; offset is enforced for 32-bit too.
 129 (define_memory_constraint "wY"
 130   "Offsettable memory operand, with bottom 2 bits 0"
 131   (and (match_code "mem")
 132        (not (match_test "update_address_mem (op, mode)"))
 133        (match_test "mem_operand_ds_form (op, mode)")))
 134
 135 ;; Altivec style load/store that ignores the bottom bits of the address
 136 (define_memory_constraint "wZ"
 137   "Indexed or indirect memory operand, ignoring the bottom 4 bits"
 138   (match_operand 0 "altivec_indexed_or_indirect_operand"))
 139
 140 ;; Integer constraints
 141
 142 (define_constraint "I"
 143   "A signed 16-bit constant"
 144   (and (match_code "const_int")
 145        (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000")))
 146
 147 (define_constraint "J"
 148   "high-order 16 bits nonzero"
 149   (and (match_code "const_int")
 150        (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
 151
 152 (define_constraint "K"
 153   "low-order 16 bits nonzero"
 154   (and (match_code "const_int")
 155        (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
 156
 157 (define_constraint "L"
 158   "signed 16-bit constant shifted left 16 bits"
 159   (and (match_code "const_int")
 160        (match_test "((ival & 0xffff) == 0
 161                       && (ival >> 31 == -1 || ival >> 31 == 0))")))
 162
 163 (define_constraint "M"
 164   "constant greater than 31"
 165   (and (match_code "const_int")
 166        (match_test "ival > 31")))
 167
 168 (define_constraint "N"
 169   "positive constant that is an exact power of two"
 170   (and (match_code "const_int")
 171        (match_test "ival > 0 && exact_log2 (ival) >= 0")))
 172
 173 (define_constraint "O"
 174   "constant zero"
 175   (and (match_code "const_int")
 176        (match_test "ival == 0")))
 177
 178 (define_constraint "P"
 179   "constant whose negation is signed 16-bit constant"
 180   (and (match_code "const_int")
 181        (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
 182
 183 ;; 34-bit signed integer constant
 184 (define_constraint "eI"
 185   "34-bit constant integer that can be loaded with PADDI"
 186   (match_operand 0 "cint34_operand"))
 187
 188 ;; Floating-point constraints.  These two are defined so that insn
 189 ;; length attributes can be calculated exactly.
 190
 191 (define_constraint "G"
 192   "Constant that can be copied into GPR with two insns for DF/DD
 193    and one for SF/SD."
 194   (and (match_code "const_double")
 195        (match_test "num_insns_constant (op, mode)
 196                     == (mode == SFmode || mode == SDmode ? 1 : 2)")))
 197
 198 (define_constraint "H"
 199   "DF/DD constant that takes three insns."
 200   (and (match_code "const_double")
 201        (match_test "num_insns_constant (op, mode) == 3")))
 202
 203 ;; Memory constraints
 204
 205 (define_memory_constraint "es"
 206   "A ``stable'' memory operand; that is, one which does not include any
 207 automodification of the base register.  Unlike @samp{m}, this constraint
 208 can be used in @code{asm} statements that might access the operand
 209 several times, or that might not access it at all."
 210   (and (match_code "mem")
 211        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 212
 213 (define_memory_constraint "Q"
 214   "Memory operand that is an offset from a register (it is usually better
 215 to use @samp{m} or @samp{es} in @code{asm} statements)"
 216   (and (match_code "mem")
 217        (match_test "REG_P (XEXP (op, 0))")))
 218
 219 (define_memory_constraint "Y"
 220   "memory operand for 8 byte and 16 byte gpr load/store"
 221   (and (match_code "mem")
 222        (match_test "mem_operand_gpr (op, mode)")))
 223
 224 (define_memory_constraint "Z"
 225   "Memory operand that is an indexed or indirect from a register (it is
 226 usually better to use @samp{m} or @samp{es} in @code{asm} statements)"
 227   (match_operand 0 "indexed_or_indirect_operand"))
 228
 229 ;; Address constraints
 230
 231 (define_address_constraint "a"
 232   "Indexed or indirect address operand"
 233   (match_operand 0 "indexed_or_indirect_address"))
 234
 235 (define_constraint "R"
 236   "AIX TOC entry"
 237   (match_test "legitimate_constant_pool_address_p (op, QImode, false)"))
 238
 239 ;; General constraints
 240
 241 (define_constraint "U"
 242   "V.4 small data reference"
 243   (and (match_test "DEFAULT_ABI == ABI_V4")
 244        (match_test "small_data_operand (op, mode)")))
 245
 246 (define_constraint "W"
 247   "vector constant that does not require memory"
 248   (match_operand 0 "easy_vector_constant"))
 249
 250 (define_constraint "j"
 251   "Zero vector constant"
 252   (match_test "op == const0_rtx || op == CONST0_RTX (mode)"))