1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
29 #include "insn-config.h"
32 #include "stringpool.h"
33 #include "stor-layout.h"
38 #include "insn-codes.h"
45 #include "hard-reg-set.h"
50 #include "insn-attr.h"
51 #include "diagnostic-core.h"
56 #include "target-def.h"
57 #include "langhooks.h"
59 #include "dominance.h"
65 #include "cfgcleanup.h"
66 #include "basic-block.h"
69 #include "sched-int.h"
72 #include "hash-table.h"
73 #include "tree-ssa-alias.h"
74 #include "internal-fn.h"
75 #include "gimple-fold.h"
77 #include "gimple-expr.h"
82 #include "alloc-pool.h"
83 #include "tm-constrs.h"
85 #include "tree-pass.h"
86 #include "pass_manager.h"
91 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
93 /* These are some macros to abstract register modes. */
94 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
95 && ((HOST_WIDE_INT)(VALUE)) <= 511)
97 #define CONST_OK_FOR_ADD(size) \
98 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
99 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
100 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
101 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
103 /* Used to simplify the logic below. Find the attributes wherever
105 #define SH_ATTRIBUTES(decl) \
106 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
107 : DECL_ATTRIBUTES (decl) \
108 ? (DECL_ATTRIBUTES (decl)) \
109 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
111 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
112 int current_function_interrupt
;
114 tree sh_deferred_function_attributes
;
115 tree
*sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
117 /* Global variables for machine-dependent things. */
119 /* Which cpu are we scheduling for. */
120 enum processor_type sh_cpu
;
122 /* Definitions used in ready queue reordering for first scheduling pass. */
124 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
125 static short *regmode_weight
[2];
127 /* Total SFmode and SImode weights of scheduled insns. */
128 static int curr_regmode_pressure
[2];
130 /* Number of r0 life regions. */
131 static int r0_life_regions
;
133 /* If true, skip cycles for Q -> R movement. */
134 static int skip_cycles
= 0;
136 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
137 and returned from sh_reorder2. */
138 static short cached_can_issue_more
;
140 /* Unique number for UNSPEC_BBR pattern. */
141 static unsigned int unspec_bbr_uid
= 1;
143 /* Provides the class number of the smallest class containing
145 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
147 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
148 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
149 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
150 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
151 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
152 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
153 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
154 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
155 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
156 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
157 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
158 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
159 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
160 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
161 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
162 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
163 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
164 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
165 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
166 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
167 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
168 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
169 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
170 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
171 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
172 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
173 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
174 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
175 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
176 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
177 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
178 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
179 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
180 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
181 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
182 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
183 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
184 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
185 GENERAL_REGS
, GENERAL_REGS
,
188 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
189 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
191 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
192 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
193 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
195 int assembler_dialect
;
197 static bool shmedia_space_reserved_for_target_registers
;
199 static void split_branches (rtx_insn
*);
200 static int branch_dest (rtx
);
201 static void print_slot (rtx_sequence
*);
202 static rtx_code_label
*add_constant (rtx
, machine_mode
, rtx
);
203 static void dump_table (rtx_insn
*, rtx_insn
*);
204 static bool broken_move (rtx_insn
*);
205 static bool mova_p (rtx_insn
*);
206 static rtx_insn
*find_barrier (int, rtx_insn
*, rtx_insn
*);
207 static bool noncall_uses_reg (rtx
, rtx_insn
*, rtx
*);
208 static rtx_insn
*gen_block_redirect (rtx_insn
*, int, int);
209 static void sh_reorg (void);
210 static void sh_option_override (void);
211 static void output_stack_adjust (int, rtx
, int, HARD_REG_SET
*, bool);
212 static rtx_insn
*frame_insn (rtx
);
213 static rtx
push (int);
214 static void pop (int);
215 static void push_regs (HARD_REG_SET
*, int);
216 static int calc_live_regs (HARD_REG_SET
*);
217 static HOST_WIDE_INT
rounded_frame_size (int);
218 static bool sh_frame_pointer_required (void);
219 static void sh_emit_mode_set (int, int, int, HARD_REG_SET
);
220 static int sh_mode_needed (int, rtx_insn
*);
221 static int sh_mode_after (int, int, rtx_insn
*);
222 static int sh_mode_entry (int);
223 static int sh_mode_exit (int);
224 static int sh_mode_priority (int entity
, int n
);
226 static rtx
mark_constant_pool_use (rtx
);
227 static tree
sh_handle_interrupt_handler_attribute (tree
*, tree
, tree
,
229 static tree
sh_handle_resbank_handler_attribute (tree
*, tree
,
231 static tree
sh2a_handle_function_vector_handler_attribute (tree
*, tree
,
233 static tree
sh_handle_sp_switch_attribute (tree
*, tree
, tree
, int, bool *);
234 static tree
sh_handle_trap_exit_attribute (tree
*, tree
, tree
, int, bool *);
235 static tree
sh_handle_renesas_attribute (tree
*, tree
, tree
, int, bool *);
236 static void sh_print_operand (FILE *, rtx
, int);
237 static void sh_print_operand_address (FILE *, rtx
);
238 static bool sh_print_operand_punct_valid_p (unsigned char code
);
239 static bool sh_asm_output_addr_const_extra (FILE *file
, rtx x
);
240 static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT
);
241 static void sh_insert_attributes (tree
, tree
*);
242 static const char *sh_check_pch_target_flags (int);
243 static int sh_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
244 static int sh_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
245 static int sh_issue_rate (void);
246 static int sh_dfa_new_cycle (FILE *, int, rtx_insn
*, int, int, int *sort_p
);
247 static short find_set_regmode_weight (rtx
, machine_mode
);
248 static short find_insn_regmode_weight (rtx
, machine_mode
);
249 static void find_regmode_weight (basic_block
, machine_mode
);
250 static int find_r0_life_regions (basic_block
);
251 static void sh_md_init_global (FILE *, int, int);
252 static void sh_md_finish_global (FILE *, int);
253 static int rank_for_reorder (const void *, const void *);
254 static void swap_reorder (rtx_insn
**, int);
255 static void ready_reorder (rtx_insn
**, int);
256 static bool high_pressure (machine_mode
);
257 static int sh_reorder (FILE *, int, rtx_insn
**, int *, int);
258 static int sh_reorder2 (FILE *, int, rtx_insn
**, int *, int);
259 static void sh_md_init (FILE *, int, int);
260 static int sh_variable_issue (FILE *, int, rtx_insn
*, int);
262 static bool sh_function_ok_for_sibcall (tree
, tree
);
264 static bool sh_cannot_modify_jumps_p (void);
265 static reg_class_t
sh_target_reg_class (void);
266 static bool sh_optimize_target_register_callee_saved (bool);
267 static bool sh_ms_bitfield_layout_p (const_tree
);
269 static void sh_init_builtins (void);
270 static tree
sh_builtin_decl (unsigned, bool);
271 static rtx
sh_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
272 static void sh_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
273 HOST_WIDE_INT
, tree
);
274 static void sh_file_start (void);
275 static bool flow_dependent_p (rtx
, rtx
);
276 static void flow_dependent_p_1 (rtx
, const_rtx
, void *);
277 static int shiftcosts (rtx
);
278 static int and_xor_ior_costs (rtx
, int);
279 static int addsubcosts (rtx
);
280 static int multcosts (rtx
);
281 static bool unspec_caller_rtx_p (rtx
);
282 static bool sh_cannot_copy_insn_p (rtx_insn
*);
283 static bool sh_rtx_costs (rtx
, int, int, int, int *, bool);
284 static int sh_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
285 static int sh_pr_n_sets (void);
286 static rtx
sh_allocate_initial_value (rtx
);
287 static reg_class_t
sh_preferred_reload_class (rtx
, reg_class_t
);
288 static reg_class_t
sh_secondary_reload (bool, rtx
, reg_class_t
,
290 struct secondary_reload_info
*);
291 static bool sh_legitimate_address_p (machine_mode
, rtx
, bool);
292 static rtx
sh_legitimize_address (rtx
, rtx
, machine_mode
);
293 static rtx
sh_delegitimize_address (rtx
);
294 static int shmedia_target_regs_stack_space (HARD_REG_SET
*);
295 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET
*);
296 static int shmedia_target_regs_stack_adjust (HARD_REG_SET
*);
297 static int scavenge_reg (HARD_REG_SET
*s
);
298 struct save_schedule_s
;
299 static struct save_entry_s
*sh5_schedule_saves (HARD_REG_SET
*,
300 struct save_schedule_s
*, int);
302 static rtx
sh_struct_value_rtx (tree
, int);
303 static rtx
sh_function_value (const_tree
, const_tree
, bool);
304 static bool sh_function_value_regno_p (const unsigned int);
305 static rtx
sh_libcall_value (machine_mode
, const_rtx
);
306 static bool sh_return_in_memory (const_tree
, const_tree
);
307 static rtx
sh_builtin_saveregs (void);
308 static void sh_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
310 static bool sh_strict_argument_naming (cumulative_args_t
);
311 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t
);
312 static tree
sh_build_builtin_va_list (void);
313 static void sh_va_start (tree
, rtx
);
314 static tree
sh_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
315 static bool sh_promote_prototypes (const_tree
);
316 static machine_mode
sh_promote_function_mode (const_tree type
,
321 static bool sh_pass_by_reference (cumulative_args_t
, machine_mode
,
323 static bool sh_callee_copies (cumulative_args_t
, machine_mode
,
325 static int sh_arg_partial_bytes (cumulative_args_t
, machine_mode
,
327 static void sh_function_arg_advance (cumulative_args_t
, machine_mode
,
329 static rtx
sh_function_arg (cumulative_args_t
, machine_mode
,
331 static bool sh_scalar_mode_supported_p (machine_mode
);
332 static int sh_dwarf_calling_convention (const_tree
);
333 static void sh_encode_section_info (tree
, rtx
, int);
334 static bool sh2a_function_vector_p (tree
);
335 static void sh_trampoline_init (rtx
, tree
, rtx
);
336 static rtx
sh_trampoline_adjust_address (rtx
);
337 static void sh_conditional_register_usage (void);
338 static bool sh_legitimate_constant_p (machine_mode
, rtx
);
339 static int mov_insn_size (machine_mode
, bool);
340 static int mov_insn_alignment_mask (machine_mode
, bool);
341 static bool sh_use_by_pieces_infrastructure_p (unsigned int,
343 enum by_pieces_operation
,
345 static bool sequence_insn_p (rtx_insn
*);
346 static void sh_canonicalize_comparison (int *, rtx
*, rtx
*, bool);
347 static void sh_canonicalize_comparison (enum rtx_code
&, rtx
&, rtx
&,
349 static bool sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
);
351 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
353 static const struct attribute_spec sh_attribute_table
[] =
355 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
356 affects_type_identity } */
357 { "interrupt_handler", 0, 0, true, false, false,
358 sh_handle_interrupt_handler_attribute
, false },
359 { "sp_switch", 1, 1, true, false, false,
360 sh_handle_sp_switch_attribute
, false },
361 { "trap_exit", 1, 1, true, false, false,
362 sh_handle_trap_exit_attribute
, false },
363 { "renesas", 0, 0, false, true, false,
364 sh_handle_renesas_attribute
, false },
365 { "trapa_handler", 0, 0, true, false, false,
366 sh_handle_interrupt_handler_attribute
, false },
367 { "nosave_low_regs", 0, 0, true, false, false,
368 sh_handle_interrupt_handler_attribute
, false },
369 { "resbank", 0, 0, true, false, false,
370 sh_handle_resbank_handler_attribute
, false },
371 { "function_vector", 1, 1, true, false, false,
372 sh2a_handle_function_vector_handler_attribute
, false },
373 { NULL
, 0, 0, false, false, false, NULL
, false }
376 /* Initialize the GCC target structure. */
377 #undef TARGET_ATTRIBUTE_TABLE
378 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
380 /* The next two are used for debug info when compiling with -gdwarf. */
381 #undef TARGET_ASM_UNALIGNED_HI_OP
382 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
383 #undef TARGET_ASM_UNALIGNED_SI_OP
384 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
386 /* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE. */
387 #undef TARGET_ASM_UNALIGNED_DI_OP
388 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
389 #undef TARGET_ASM_ALIGNED_DI_OP
390 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
392 #undef TARGET_OPTION_OVERRIDE
393 #define TARGET_OPTION_OVERRIDE sh_option_override
395 #undef TARGET_PRINT_OPERAND
396 #define TARGET_PRINT_OPERAND sh_print_operand
397 #undef TARGET_PRINT_OPERAND_ADDRESS
398 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
399 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
400 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
401 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
402 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
404 #undef TARGET_ASM_FUNCTION_EPILOGUE
405 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
407 #undef TARGET_ASM_OUTPUT_MI_THUNK
408 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
410 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
411 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
412 hook_bool_const_tree_hwi_hwi_const_tree_true
414 #undef TARGET_ASM_FILE_START
415 #define TARGET_ASM_FILE_START sh_file_start
416 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
417 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
419 #undef TARGET_REGISTER_MOVE_COST
420 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
422 #undef TARGET_INSERT_ATTRIBUTES
423 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
425 #undef TARGET_SCHED_ADJUST_COST
426 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
428 #undef TARGET_SCHED_ISSUE_RATE
429 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
431 /* The next 5 hooks have been implemented for reenabling sched1. With the
432 help of these macros we are limiting the movement of insns in sched1 to
433 reduce the register pressure. The overall idea is to keep count of SImode
434 and SFmode regs required by already scheduled insns. When these counts
435 cross some threshold values; give priority to insns that free registers.
436 The insn that frees registers is most likely to be the insn with lowest
437 LUID (original insn order); but such an insn might be there in the stalled
438 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
439 up to a max of 8 cycles so that such insns may move from Q -> R.
441 The description of the hooks are as below:
443 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
444 scheduler; it is called inside the sched_init function just after
445 find_insn_reg_weights function call. It is used to calculate the SImode
446 and SFmode weights of insns of basic blocks; much similar to what
447 find_insn_reg_weights does.
448 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
450 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
451 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
454 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
455 high; reorder the ready queue so that the insn with lowest LUID will be
458 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
459 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
461 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
462 can be returned from TARGET_SCHED_REORDER2.
464 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
466 #undef TARGET_SCHED_DFA_NEW_CYCLE
467 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
469 #undef TARGET_SCHED_INIT_GLOBAL
470 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
472 #undef TARGET_SCHED_FINISH_GLOBAL
473 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
475 #undef TARGET_SCHED_VARIABLE_ISSUE
476 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
478 #undef TARGET_SCHED_REORDER
479 #define TARGET_SCHED_REORDER sh_reorder
481 #undef TARGET_SCHED_REORDER2
482 #define TARGET_SCHED_REORDER2 sh_reorder2
484 #undef TARGET_SCHED_INIT
485 #define TARGET_SCHED_INIT sh_md_init
487 #undef TARGET_DELEGITIMIZE_ADDRESS
488 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
490 #undef TARGET_LEGITIMIZE_ADDRESS
491 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
493 #undef TARGET_CANNOT_MODIFY_JUMPS_P
494 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
495 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
496 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
497 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
498 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
499 sh_optimize_target_register_callee_saved
501 #undef TARGET_MS_BITFIELD_LAYOUT_P
502 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
504 #undef TARGET_INIT_BUILTINS
505 #define TARGET_INIT_BUILTINS sh_init_builtins
506 #undef TARGET_BUILTIN_DECL
507 #define TARGET_BUILTIN_DECL sh_builtin_decl
508 #undef TARGET_EXPAND_BUILTIN
509 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
511 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
512 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
514 #undef TARGET_CANNOT_COPY_INSN_P
515 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
516 #undef TARGET_RTX_COSTS
517 #define TARGET_RTX_COSTS sh_rtx_costs
518 #undef TARGET_ADDRESS_COST
519 #define TARGET_ADDRESS_COST sh_address_cost
520 #undef TARGET_ALLOCATE_INITIAL_VALUE
521 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
523 #undef TARGET_MACHINE_DEPENDENT_REORG
524 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
526 #undef TARGET_DWARF_REGISTER_SPAN
527 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
530 #undef TARGET_HAVE_TLS
531 #define TARGET_HAVE_TLS true
534 #undef TARGET_PROMOTE_PROTOTYPES
535 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
536 #undef TARGET_PROMOTE_FUNCTION_MODE
537 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
539 #undef TARGET_FUNCTION_VALUE
540 #define TARGET_FUNCTION_VALUE sh_function_value
541 #undef TARGET_FUNCTION_VALUE_REGNO_P
542 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
543 #undef TARGET_LIBCALL_VALUE
544 #define TARGET_LIBCALL_VALUE sh_libcall_value
545 #undef TARGET_STRUCT_VALUE_RTX
546 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
547 #undef TARGET_RETURN_IN_MEMORY
548 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
550 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
551 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
552 #undef TARGET_SETUP_INCOMING_VARARGS
553 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
554 #undef TARGET_STRICT_ARGUMENT_NAMING
555 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
556 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
557 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
558 #undef TARGET_MUST_PASS_IN_STACK
559 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
560 #undef TARGET_PASS_BY_REFERENCE
561 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
562 #undef TARGET_CALLEE_COPIES
563 #define TARGET_CALLEE_COPIES sh_callee_copies
564 #undef TARGET_ARG_PARTIAL_BYTES
565 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
566 #undef TARGET_FUNCTION_ARG
567 #define TARGET_FUNCTION_ARG sh_function_arg
568 #undef TARGET_FUNCTION_ARG_ADVANCE
569 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
571 #undef TARGET_BUILD_BUILTIN_VA_LIST
572 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
573 #undef TARGET_EXPAND_BUILTIN_VA_START
574 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
575 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
576 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
578 #undef TARGET_SCALAR_MODE_SUPPORTED_P
579 #define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p
580 #undef TARGET_VECTOR_MODE_SUPPORTED_P
581 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
583 #undef TARGET_CHECK_PCH_TARGET_FLAGS
584 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
586 #undef TARGET_DWARF_CALLING_CONVENTION
587 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
589 #undef TARGET_FRAME_POINTER_REQUIRED
590 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
592 #undef TARGET_MODE_EMIT
593 #define TARGET_MODE_EMIT sh_emit_mode_set
595 #undef TARGET_MODE_NEEDED
596 #define TARGET_MODE_NEEDED sh_mode_needed
598 #undef TARGET_MODE_AFTER
599 #define TARGET_MODE_AFTER sh_mode_after
601 #undef TARGET_MODE_ENTRY
602 #define TARGET_MODE_ENTRY sh_mode_entry
604 #undef TARGET_MODE_EXIT
605 #define TARGET_MODE_EXIT sh_mode_exit
607 #undef TARGET_MODE_PRIORITY
608 #define TARGET_MODE_PRIORITY sh_mode_priority
610 /* Return regmode weight for insn. */
611 #define INSN_REGMODE_WEIGHT(INSN, MODE)\
612 regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
614 /* Return current register pressure for regmode. */
615 #define CURR_REGMODE_PRESSURE(MODE)\
616 curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
618 #undef TARGET_ENCODE_SECTION_INFO
619 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
621 #undef TARGET_SECONDARY_RELOAD
622 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
624 #undef TARGET_PREFERRED_RELOAD_CLASS
625 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
627 #undef TARGET_CONDITIONAL_REGISTER_USAGE
628 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
630 #undef TARGET_LEGITIMATE_ADDRESS_P
631 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
633 #undef TARGET_TRAMPOLINE_INIT
634 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
635 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
636 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
638 #undef TARGET_LEGITIMATE_CONSTANT_P
639 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
641 #undef TARGET_CANONICALIZE_COMPARISON
642 #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
644 #undef TARGET_FIXED_CONDITION_CODE_REGS
645 #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
647 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
648 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
649 sh_use_by_pieces_infrastructure_p
651 /* Machine-specific symbol_ref flags. */
652 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
654 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
655 is used by optabs.c atomic op expansion code as well as in sync.md. */
656 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
657 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
659 struct gcc_target targetm
= TARGET_INITIALIZER
;
662 /* Information on the currently selected atomic model.
663 This is initialized in sh_option_override. */
664 static sh_atomic_model selected_atomic_model_
;
666 const sh_atomic_model
&
667 selected_atomic_model (void)
669 return selected_atomic_model_
;
672 static sh_atomic_model
673 parse_validate_atomic_model_option (const char* str
)
675 const char* model_names
[sh_atomic_model::num_models
];
676 model_names
[sh_atomic_model::none
] = "none";
677 model_names
[sh_atomic_model::soft_gusa
] = "soft-gusa";
678 model_names
[sh_atomic_model::hard_llcs
] = "hard-llcs";
679 model_names
[sh_atomic_model::soft_tcb
] = "soft-tcb";
680 model_names
[sh_atomic_model::soft_imask
] = "soft-imask";
682 const char* model_cdef_names
[sh_atomic_model::num_models
];
683 model_cdef_names
[sh_atomic_model::none
] = "NONE";
684 model_cdef_names
[sh_atomic_model::soft_gusa
] = "SOFT_GUSA";
685 model_cdef_names
[sh_atomic_model::hard_llcs
] = "HARD_LLCS";
686 model_cdef_names
[sh_atomic_model::soft_tcb
] = "SOFT_TCB";
687 model_cdef_names
[sh_atomic_model::soft_imask
] = "SOFT_IMASK";
690 ret
.type
= sh_atomic_model::none
;
691 ret
.name
= model_names
[sh_atomic_model::none
];
692 ret
.cdef_name
= model_cdef_names
[sh_atomic_model::none
];
694 ret
.tcb_gbr_offset
= -1;
696 /* Handle empty string as 'none'. */
697 if (str
== NULL
|| *str
== '\0')
700 #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0)
702 std::vector
<std::string
> tokens
;
703 for (std::stringstream
ss (str
); ss
.good (); )
705 tokens
.push_back (std::string ());
706 std::getline (ss
, tokens
.back (), ',');
710 err_ret ("invalid atomic model option");
712 /* The first token must be the atomic model name. */
714 for (size_t i
= 0; i
< sh_atomic_model::num_models
; ++i
)
715 if (tokens
.front () == model_names
[i
])
717 ret
.type
= (sh_atomic_model::enum_type
)i
;
718 ret
.name
= model_names
[i
];
719 ret
.cdef_name
= model_cdef_names
[i
];
723 err_ret ("invalid atomic model name \"%s\"", tokens
.front ().c_str ());
727 /* Go through the remaining tokens. */
728 for (size_t i
= 1; i
< tokens
.size (); ++i
)
730 if (tokens
[i
] == "strict")
732 else if (tokens
[i
].find ("gbr-offset=") == 0)
734 std::string offset_str
= tokens
[i
].substr (strlen ("gbr-offset="));
735 ret
.tcb_gbr_offset
= integral_argument (offset_str
.c_str ());
736 if (offset_str
.empty () || ret
.tcb_gbr_offset
== -1)
737 err_ret ("could not parse gbr-offset value \"%s\" in atomic model "
738 "option", offset_str
.c_str ());
741 err_ret ("unknown parameter \"%s\" in atomic model option",
745 /* Check that the selection makes sense. */
746 if (TARGET_SHMEDIA
&& ret
.type
!= sh_atomic_model::none
)
747 err_ret ("atomic operations are not supported on SHmedia");
749 if (ret
.type
== sh_atomic_model::soft_gusa
&& !TARGET_SH3
)
750 err_ret ("atomic model %s is only available on SH3 and SH4 targets",
753 if (ret
.type
== sh_atomic_model::hard_llcs
&& !TARGET_SH4A
)
754 err_ret ("atomic model %s is only available on SH4A targets", ret
.name
);
756 if (ret
.type
== sh_atomic_model::soft_tcb
&& ret
.tcb_gbr_offset
== -1)
757 err_ret ("atomic model %s requires gbr-offset parameter", ret
.name
);
759 if (ret
.type
== sh_atomic_model::soft_tcb
760 && (ret
.tcb_gbr_offset
< 0 || ret
.tcb_gbr_offset
> 1020
761 || (ret
.tcb_gbr_offset
& 3) != 0))
762 err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be "
763 "a multiple of 4 in the range 0-1020", ret
.tcb_gbr_offset
,
766 if (ret
.type
== sh_atomic_model::soft_imask
&& TARGET_USERMODE
)
767 err_ret ("cannot use atomic model %s in user mode", ret
.name
);
774 /* Register SH specific RTL passes. */
775 extern opt_pass
* make_pass_sh_treg_combine (gcc::context
* ctx
, bool split_insns
,
777 extern opt_pass
* make_pass_sh_optimize_sett_clrt (gcc::context
* ctx
,
780 register_sh_passes (void)
785 /* Running the sh_treg_combine pass after ce1 generates better code when
786 comparisons are combined and reg-reg moves are introduced, because
787 reg-reg moves will be eliminated afterwards. However, there are quite
788 some cases where combine will be unable to fold comparison related insns,
789 thus for now don't do it.
790 register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
791 PASS_POS_INSERT_AFTER, "ce1", 1);
794 /* Run sh_treg_combine pass after combine but before register allocation. */
795 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine2"),
796 PASS_POS_INSERT_AFTER
, "split1", 1);
798 /* Run sh_treg_combine pass after register allocation and basic block
799 reordering as this sometimes creates new opportunities. */
800 register_pass (make_pass_sh_treg_combine (g
, true, "sh_treg_combine3"),
801 PASS_POS_INSERT_AFTER
, "split4", 1);
803 /* Optimize sett and clrt insns, by e.g. removing them if the T bit value
804 is known after a conditional branch.
805 This must be done after basic blocks and branch conditions have
806 stabilized and won't be changed by further passes. */
807 register_pass (make_pass_sh_optimize_sett_clrt (g
, "sh_optimize_sett_clrt"),
808 PASS_POS_INSERT_BEFORE
, "sched2", 1);
811 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
812 various options, and do some machine dependent initialization. */
814 sh_option_override (void)
818 SUBTARGET_OVERRIDE_OPTIONS
;
819 if (optimize
> 1 && !optimize_size
)
820 target_flags
|= MASK_SAVE_ALL_TARGET_REGS
;
822 /* Set default values of TARGET_CBRANCHDI4 and TARGET_CMPEQDI_T. */
823 TARGET_CBRANCHDI4
= 1;
824 TARGET_CMPEQDI_T
= 0;
826 sh_cpu
= PROCESSOR_SH1
;
827 assembler_dialect
= 0;
829 sh_cpu
= PROCESSOR_SH2
;
831 sh_cpu
= PROCESSOR_SH2E
;
833 sh_cpu
= PROCESSOR_SH2A
;
835 sh_cpu
= PROCESSOR_SH3
;
837 sh_cpu
= PROCESSOR_SH3E
;
840 assembler_dialect
= 1;
841 sh_cpu
= PROCESSOR_SH4
;
845 assembler_dialect
= 1;
846 sh_cpu
= PROCESSOR_SH4A
;
850 sh_cpu
= PROCESSOR_SH5
;
851 target_flags
|= MASK_ALIGN_DOUBLE
;
852 if (TARGET_SHMEDIA_FPU
)
853 target_flags
|= MASK_FMOVD
;
856 /* There are no delay slots on SHmedia. */
857 flag_delayed_branch
= 0;
858 /* Relaxation isn't yet supported for SHmedia */
859 target_flags
&= ~MASK_RELAX
;
860 /* After reload, if conversion does little good but can cause
862 - find_if_block doesn't do anything for SH because we don't
863 have conditional execution patterns. (We use conditional
864 move patterns, which are handled differently, and only
866 - find_cond_trap doesn't do anything for the SH because we
867 don't have conditional traps.
868 - find_if_case_1 uses redirect_edge_and_branch_force in
869 the only path that does an optimization, and this causes
870 an ICE when branch targets are in registers.
871 - find_if_case_2 doesn't do anything for the SHmedia after
872 reload except when it can redirect a tablejump - and
873 that's rather rare. */
874 flag_if_conversion2
= 0;
875 if (! strcmp (sh_div_str
, "call"))
876 sh_div_strategy
= SH_DIV_CALL
;
877 else if (! strcmp (sh_div_str
, "call2"))
878 sh_div_strategy
= SH_DIV_CALL2
;
879 if (! strcmp (sh_div_str
, "fp") && TARGET_FPU_ANY
)
880 sh_div_strategy
= SH_DIV_FP
;
881 else if (! strcmp (sh_div_str
, "inv"))
882 sh_div_strategy
= SH_DIV_INV
;
883 else if (! strcmp (sh_div_str
, "inv:minlat"))
884 sh_div_strategy
= SH_DIV_INV_MINLAT
;
885 else if (! strcmp (sh_div_str
, "inv20u"))
886 sh_div_strategy
= SH_DIV_INV20U
;
887 else if (! strcmp (sh_div_str
, "inv20l"))
888 sh_div_strategy
= SH_DIV_INV20L
;
889 else if (! strcmp (sh_div_str
, "inv:call2"))
890 sh_div_strategy
= SH_DIV_INV_CALL2
;
891 else if (! strcmp (sh_div_str
, "inv:call"))
892 sh_div_strategy
= SH_DIV_INV_CALL
;
893 else if (! strcmp (sh_div_str
, "inv:fp"))
896 sh_div_strategy
= SH_DIV_INV_FP
;
898 sh_div_strategy
= SH_DIV_INV
;
900 TARGET_CBRANCHDI4
= 0;
901 /* Assembler CFI isn't yet fully supported for SHmedia. */
902 flag_dwarf2_cfi_asm
= 0;
907 /* Only the sh64-elf assembler fully supports .quad properly. */
908 targetm
.asm_out
.aligned_op
.di
= NULL
;
909 targetm
.asm_out
.unaligned_op
.di
= NULL
;
912 /* User/priviledged mode is supported only on SH3*, SH4* and SH5*.
913 Disable it for everything else. */
914 if (! (TARGET_SH3
|| TARGET_SH5
) && TARGET_USERMODE
)
915 TARGET_USERMODE
= false;
919 if (! strcmp (sh_div_str
, "call-div1"))
920 sh_div_strategy
= SH_DIV_CALL_DIV1
;
921 else if (! strcmp (sh_div_str
, "call-fp")
922 && (TARGET_FPU_DOUBLE
|| TARGET_FPU_SINGLE_ONLY
923 || (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)))
924 sh_div_strategy
= SH_DIV_CALL_FP
;
925 else if (! strcmp (sh_div_str
, "call-table") && TARGET_DYNSHIFT
)
926 sh_div_strategy
= SH_DIV_CALL_TABLE
;
928 /* Pick one that makes most sense for the target in general.
929 It is not much good to use different functions depending
930 on -Os, since then we'll end up with two different functions
931 when some of the code is compiled for size, and some for
934 /* SH4 tends to emphasize speed. */
936 sh_div_strategy
= SH_DIV_CALL_TABLE
;
937 /* These have their own way of doing things. */
938 else if (TARGET_SH2A
)
939 sh_div_strategy
= SH_DIV_INTRINSIC
;
940 /* ??? Should we use the integer SHmedia function instead? */
941 else if (TARGET_SHCOMPACT
&& TARGET_FPU_ANY
)
942 sh_div_strategy
= SH_DIV_CALL_FP
;
943 /* SH1 .. SH3 cores often go into small-footprint systems, so
944 default to the smallest implementation available. */
946 sh_div_strategy
= SH_DIV_CALL_DIV1
;
949 TARGET_PRETEND_CMOVE
= 0;
950 if (sh_divsi3_libfunc
[0])
951 ; /* User supplied - leave it alone. */
952 else if (TARGET_DIVIDE_CALL_FP
)
953 sh_divsi3_libfunc
= "__sdivsi3_i4";
954 else if (TARGET_DIVIDE_CALL_TABLE
)
955 sh_divsi3_libfunc
= "__sdivsi3_i4i";
957 sh_divsi3_libfunc
= "__sdivsi3_1";
959 sh_divsi3_libfunc
= "__sdivsi3";
961 if (sh_branch_cost
== -1)
963 /* The SH1 does not have delay slots, hence we get a pipeline stall
964 at every branch. The SH4 is superscalar, so the single delay slot
965 is not sufficient to keep both pipelines filled.
966 In any case, set the default branch cost to '2', as it results in
967 slightly overall smaller code and also enables some if conversions
968 that are required for matching special T bit related insns. */
972 /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
973 if (! global_options_set
.x_TARGET_ZDCBRANCH
&& TARGET_HARD_SH4
)
974 TARGET_ZDCBRANCH
= 1;
976 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
977 if (! VALID_REGISTER_P (regno
))
978 sh_register_names
[regno
][0] = '\0';
980 for (regno
= 0; regno
< ADDREGNAMES_SIZE
; regno
++)
981 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno
)))
982 sh_additional_register_names
[regno
][0] = '\0';
984 if ((flag_pic
&& ! TARGET_PREFERGOT
)
985 || (TARGET_SHMEDIA
&& !TARGET_PT_FIXED
))
986 flag_no_function_cse
= 1;
988 if (targetm
.small_register_classes_for_mode_p (VOIDmode
))
990 /* Never run scheduling before reload, since that can
991 break global alloc, and generates slower code anyway due
992 to the pressure on R0. */
993 /* Enable sched1 for SH4 if the user explicitly requests.
994 When sched1 is enabled, the ready queue will be reordered by
995 the target hooks if pressure is high. We can not do this for
996 PIC, SH3 and lower as they give spill failures for R0. */
997 if (!TARGET_HARD_SH4
|| flag_pic
)
998 flag_schedule_insns
= 0;
999 /* ??? Current exception handling places basic block boundaries
1000 after call_insns. It causes the high pressure on R0 and gives
1001 spill failures for R0 in reload. See PR 22553 and the thread
1003 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
1004 else if (flag_exceptions
)
1006 if (flag_schedule_insns
&& global_options_set
.x_flag_schedule_insns
)
1007 warning (0, "ignoring -fschedule-insns because of exception "
1009 flag_schedule_insns
= 0;
1011 else if (flag_schedule_insns
1012 && !global_options_set
.x_flag_schedule_insns
)
1013 flag_schedule_insns
= 0;
1016 /* Unwind info is not correct around the CFG unless either a frame
1017 pointer is present or M_A_O_A is set. Fixing this requires rewriting
1018 unwind info generation to be aware of the CFG and propagating states
1020 if ((flag_unwind_tables
|| flag_asynchronous_unwind_tables
1021 || flag_exceptions
|| flag_non_call_exceptions
)
1022 && flag_omit_frame_pointer
&& !TARGET_ACCUMULATE_OUTGOING_ARGS
)
1024 warning (0, "unwind tables currently require either a frame pointer "
1025 "or -maccumulate-outgoing-args for correctness");
1026 TARGET_ACCUMULATE_OUTGOING_ARGS
= 1;
1029 /* Unwinding with -freorder-blocks-and-partition does not work on this
1030 architecture, because it requires far jumps to label crossing between
1031 hot/cold sections which are rejected on this architecture. */
1032 if (flag_reorder_blocks_and_partition
)
1034 if (flag_exceptions
)
1036 inform (input_location
,
1037 "-freorder-blocks-and-partition does not work with "
1038 "exceptions on this architecture");
1039 flag_reorder_blocks_and_partition
= 0;
1040 flag_reorder_blocks
= 1;
1042 else if (flag_unwind_tables
)
1044 inform (input_location
,
1045 "-freorder-blocks-and-partition does not support unwind "
1046 "info on this architecture");
1047 flag_reorder_blocks_and_partition
= 0;
1048 flag_reorder_blocks
= 1;
1052 /* Adjust loop, jump and function alignment values (in bytes), if those
1053 were not specified by the user using -falign-loops, -falign-jumps
1054 and -falign-functions options.
1055 32 bit alignment is better for speed, because instructions can be
1056 fetched as a pair from a longword boundary. For size use 16 bit
1057 alignment to get more compact code.
1058 Aligning all jumps increases the code size, even if it might
1059 result in slightly faster code. Thus, it is set to the smallest
1060 alignment possible if not specified by the user. */
1061 if (align_loops
== 0)
1066 align_loops
= optimize_size
? 2 : 4;
1069 if (align_jumps
== 0)
1072 align_jumps
= 1 << CACHE_LOG
;
1076 else if (align_jumps
< (TARGET_SHMEDIA
? 4 : 2))
1077 align_jumps
= TARGET_SHMEDIA
? 4 : 2;
1079 if (align_functions
== 0)
1082 align_functions
= optimize_size
1083 ? FUNCTION_BOUNDARY
/8 : (1 << CACHE_LOG
);
1085 align_functions
= optimize_size
? 2 : 4;
1088 /* The linker relaxation code breaks when a function contains
1089 alignments that are larger than that at the start of a
1090 compilation unit. */
1093 int min_align
= align_loops
> align_jumps
? align_loops
: align_jumps
;
1095 /* Also take possible .long constants / mova tables into account. */
1098 if (align_functions
< min_align
)
1099 align_functions
= min_align
;
1102 if (flag_unsafe_math_optimizations
)
1104 /* Enable fsca insn for SH4A if not otherwise specified by the user. */
1105 if (global_options_set
.x_TARGET_FSCA
== 0 && TARGET_SH4A_FP
)
1108 /* Enable fsrra insn for SH4A if not otherwise specified by the user. */
1109 if (global_options_set
.x_TARGET_FSRRA
== 0 && TARGET_SH4A_FP
)
1113 /* Allow fsrra insn only if -funsafe-math-optimizations and
1114 -ffinite-math-only is enabled. */
1115 TARGET_FSRRA
= TARGET_FSRRA
1116 && flag_unsafe_math_optimizations
1117 && flag_finite_math_only
;
1119 /* If the -mieee option was not explicitly set by the user, turn it on
1120 unless -ffinite-math-only was specified. See also PR 33135. */
1121 if (! global_options_set
.x_TARGET_IEEE
)
1122 TARGET_IEEE
= ! flag_finite_math_only
;
1124 if (sh_fixed_range_str
)
1125 sh_fix_range (sh_fixed_range_str
);
1127 /* This target defaults to strict volatile bitfields. */
1128 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
1129 flag_strict_volatile_bitfields
= 1;
1131 /* Parse atomic model option and make sure it is valid for the current
1133 selected_atomic_model_
1134 = parse_validate_atomic_model_option (sh_atomic_model_str
);
1136 register_sh_passes ();
1139 /* Print the operand address in x to the stream. */
1141 sh_print_operand_address (FILE *stream
, rtx x
)
1143 switch (GET_CODE (x
))
1147 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
1152 rtx base
= XEXP (x
, 0);
1153 rtx index
= XEXP (x
, 1);
1155 switch (GET_CODE (index
))
1158 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
1159 reg_names
[true_regnum (base
)]);
1165 int base_num
= true_regnum (base
);
1166 int index_num
= true_regnum (index
);
1168 fprintf (stream
, "@(r0,%s)",
1169 reg_names
[MAX (base_num
, index_num
)]);
1180 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
1184 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
1188 x
= mark_constant_pool_use (x
);
1189 output_addr_const (stream
, x
);
1194 /* Print operand x (an rtx) in assembler syntax to file stream
1195 according to modifier code.
1197 '.' print a .s if insn needs delay slot
1198 ',' print LOCAL_LABEL_PREFIX
1199 '@' print trap, rte or rts depending upon pragma interruptness
1200 '#' output a nop if there is nothing to put in the delay slot
1201 ''' print likelihood suffix (/u for unlikely).
1202 '>' print branch target if -fverbose-asm
1203 'O' print a constant without the #
1204 'R' print the LSW of a dp value - changes if in little endian
1205 'S' print the MSW of a dp value - changes if in little endian
1206 'T' print the next word of a dp value - same as 'R' in big endian mode.
1207 'M' SHMEDIA: print an `x' if `m' will print `base,index'.
1208 otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM.
1209 'N' print 'r63' if the operand is (const_int 0).
1210 'd' print a V2SF reg as dN instead of fpN.
1211 'm' print a pair `base,offset' or `base,index', for LD and ST.
1212 'U' Likewise for {LD,ST}{HI,LO}.
1213 'V' print the position of a single bit set.
1214 'W' print the position of a single bit cleared.
1215 't' print a memory address which is a register.
1216 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1217 'o' output an operator. */
1219 sh_print_operand (FILE *stream
, rtx x
, int code
)
1230 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
1231 && get_attr_length (final_sequence
->insn (1)))
1232 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
1235 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
1238 trapa_attr
= lookup_attribute ("trap_exit",
1239 DECL_ATTRIBUTES (current_function_decl
));
1241 fprintf (stream
, "trapa #%ld",
1242 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr
))));
1243 else if (sh_cfun_interrupt_handler_p ())
1245 if (sh_cfun_resbank_handler_p ())
1246 fprintf (stream
, "resbank\n");
1247 fprintf (stream
, "rte");
1250 fprintf (stream
, "rts");
1253 /* Output a nop if there's nothing in the delay slot. */
1254 if (dbr_sequence_length () == 0)
1255 fprintf (stream
, "\n\tnop");
1259 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1261 if (note
&& XINT (note
, 0) * 2 < REG_BR_PROB_BASE
)
1262 fputs ("/u", stream
);
1266 if (flag_verbose_asm
&& JUMP_LABEL (current_output_insn
))
1268 fputs ("\t! target: ", stream
);
1269 output_addr_const (stream
, JUMP_LABEL (current_output_insn
));
1273 x
= mark_constant_pool_use (x
);
1274 output_addr_const (stream
, x
);
1276 /* N.B.: %R / %S / %T adjust memory addresses by four.
1277 For SHMEDIA, that means they can be used to access the first and
1278 second 32 bit part of a 64 bit (or larger) value that
1279 might be held in floating point registers or memory.
1280 While they can be used to access 64 bit parts of a larger value
1281 held in general purpose registers, that won't work with memory -
1282 neither for fp registers, since the frxx names are used. */
1284 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1286 regno
= true_regnum (x
);
1287 regno
+= FP_REGISTER_P (regno
) ? 1 : SH_REG_LSW_OFFSET
;
1288 fputs (reg_names
[regno
], (stream
));
1292 x
= adjust_address (x
, SImode
, 4 * SH_REG_LSW_OFFSET
);
1293 sh_print_operand_address (stream
, XEXP (x
, 0));
1299 mode
= GET_MODE (x
);
1300 if (mode
== VOIDmode
)
1302 if (GET_MODE_SIZE (mode
) >= 8)
1303 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_LSW_OFFSET
);
1305 sh_print_operand (stream
, sub
, 0);
1307 output_operand_lossage ("invalid operand to %%R");
1311 if (REG_P (x
) || GET_CODE (x
) == SUBREG
)
1313 regno
= true_regnum (x
);
1314 regno
+= FP_REGISTER_P (regno
) ? 0 : SH_REG_MSW_OFFSET
;
1315 fputs (reg_names
[regno
], (stream
));
1319 x
= adjust_address (x
, SImode
, 4 * SH_REG_MSW_OFFSET
);
1320 sh_print_operand_address (stream
, XEXP (x
, 0));
1326 mode
= GET_MODE (x
);
1327 if (mode
== VOIDmode
)
1329 if (GET_MODE_SIZE (mode
) >= 8)
1330 sub
= simplify_subreg (SImode
, x
, mode
, 4 * SH_REG_MSW_OFFSET
);
1332 sh_print_operand (stream
, sub
, 0);
1334 output_operand_lossage ("invalid operand to %%S");
1338 /* Next word of a double. */
1339 switch (GET_CODE (x
))
1342 fputs (reg_names
[REGNO (x
) + 1], (stream
));
1345 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
1346 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
1347 x
= adjust_address (x
, SImode
, 4);
1348 sh_print_operand_address (stream
, XEXP (x
, 0));
1356 gcc_assert (MEM_P (x
));
1358 switch (GET_CODE (x
))
1362 sh_print_operand (stream
, x
, 0);
1370 switch (GET_CODE (x
))
1372 case PLUS
: fputs ("add", stream
); break;
1373 case MINUS
: fputs ("sub", stream
); break;
1374 case MULT
: fputs ("mul", stream
); break;
1375 case DIV
: fputs ("div", stream
); break;
1376 case EQ
: fputs ("eq", stream
); break;
1377 case NE
: fputs ("ne", stream
); break;
1378 case GT
: case LT
: fputs ("gt", stream
); break;
1379 case GE
: case LE
: fputs ("ge", stream
); break;
1380 case GTU
: case LTU
: fputs ("gtu", stream
); break;
1381 case GEU
: case LEU
: fputs ("geu", stream
); break;
1390 && GET_CODE (XEXP (x
, 0)) == PLUS
1391 && (REG_P (XEXP (XEXP (x
, 0), 1))
1392 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
1393 fputc ('x', stream
);
1399 switch (GET_MODE (x
))
1401 case QImode
: fputs (".b", stream
); break;
1402 case HImode
: fputs (".w", stream
); break;
1403 case SImode
: fputs (".l", stream
); break;
1404 case SFmode
: fputs (".s", stream
); break;
1405 case DFmode
: fputs (".d", stream
); break;
1406 default: gcc_unreachable ();
1413 gcc_assert (MEM_P (x
));
1417 switch (GET_CODE (x
))
1421 sh_print_operand (stream
, x
, 0);
1422 fputs (", 0", stream
);
1426 sh_print_operand (stream
, XEXP (x
, 0), 0);
1427 fputs (", ", stream
);
1428 sh_print_operand (stream
, XEXP (x
, 1), 0);
1438 int num
= exact_log2 (INTVAL (x
));
1439 gcc_assert (num
>= 0);
1440 fprintf (stream
, "#%d", num
);
1446 int num
= exact_log2 (~INTVAL (x
));
1447 gcc_assert (num
>= 0);
1448 fprintf (stream
, "#%d", num
);
1453 gcc_assert (REG_P (x
) && GET_MODE (x
) == V2SFmode
);
1455 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
1459 if (x
== CONST0_RTX (GET_MODE (x
)))
1461 fprintf ((stream
), "r63");
1464 goto default_output
;
1466 if (CONST_INT_P (x
))
1468 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
1476 mode
= GET_MODE (x
);
1478 switch (GET_CODE (x
))
1482 rtx inner
= XEXP (x
, 0);
1484 machine_mode inner_mode
;
1486 /* We might see SUBREGs with vector mode registers inside. */
1487 if (GET_CODE (inner
) == SUBREG
1488 && (GET_MODE_SIZE (GET_MODE (inner
))
1489 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1490 && subreg_lowpart_p (inner
))
1491 inner
= SUBREG_REG (inner
);
1492 if (CONST_INT_P (inner
))
1494 x
= GEN_INT (trunc_int_for_mode (INTVAL (inner
), GET_MODE (x
)));
1495 goto default_output
;
1497 inner_mode
= GET_MODE (inner
);
1498 if (GET_CODE (inner
) == SUBREG
1499 && (GET_MODE_SIZE (GET_MODE (inner
))
1500 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1501 && REG_P (SUBREG_REG (inner
)))
1503 offset
= subreg_regno_offset (REGNO (SUBREG_REG (inner
)),
1504 GET_MODE (SUBREG_REG (inner
)),
1505 SUBREG_BYTE (inner
),
1507 inner
= SUBREG_REG (inner
);
1509 if (!REG_P (inner
) || GET_MODE_SIZE (inner_mode
) > 8)
1511 /* Floating point register pairs are always big endian;
1512 general purpose registers are 64 bit wide. */
1513 regno
= REGNO (inner
);
1514 regno
= (HARD_REGNO_NREGS (regno
, inner_mode
)
1515 - HARD_REGNO_NREGS (regno
, mode
))
1523 /* FIXME: We need this on SHmedia32 because reload generates
1524 some sign-extended HI or QI loads into DImode registers
1525 but, because Pmode is SImode, the address ends up with a
1526 subreg:SI of the DImode register. Maybe reload should be
1527 fixed so as to apply alter_subreg to such loads? */
1529 gcc_assert (trapping_target_operand (x
, VOIDmode
));
1530 x
= XEXP (XEXP (x
, 2), 0);
1531 goto default_output
;
1533 gcc_assert (SUBREG_BYTE (x
) == 0
1534 && REG_P (SUBREG_REG (x
)));
1542 if (FP_REGISTER_P (regno
)
1543 && mode
== V16SFmode
)
1544 fprintf ((stream
), "mtrx%s", reg_names
[regno
] + 2);
1545 else if (FP_REGISTER_P (REGNO (x
))
1546 && mode
== V4SFmode
)
1547 fprintf ((stream
), "fv%s", reg_names
[regno
] + 2);
1549 && mode
== V2SFmode
)
1550 fprintf ((stream
), "fp%s", reg_names
[regno
] + 2);
1551 else if (FP_REGISTER_P (REGNO (x
))
1552 && GET_MODE_SIZE (mode
) > 4)
1553 fprintf ((stream
), "d%s", reg_names
[regno
] + 1);
1555 fputs (reg_names
[regno
], (stream
));
1559 output_address (XEXP (x
, 0));
1564 fputc ('#', stream
);
1565 output_addr_const (stream
, x
);
1573 sh_print_operand_punct_valid_p (unsigned char code
)
1575 return (code
== '.' || code
== '#' || code
== '@' || code
== ','
1576 || code
== '$' || code
== '\'' || code
== '>');
1579 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1581 sh_asm_output_addr_const_extra (FILE *file
, rtx x
)
1583 if (GET_CODE (x
) == UNSPEC
)
1585 switch (XINT (x
, 1))
1587 case UNSPEC_DATALABEL
:
1588 fputs ("datalabel ", file
);
1589 output_addr_const (file
, XVECEXP (x
, 0, 0));
1592 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1593 output_addr_const (file
, XVECEXP (x
, 0, 0));
1596 output_addr_const (file
, XVECEXP (x
, 0, 0));
1597 fputs ("@GOT", file
);
1600 output_addr_const (file
, XVECEXP (x
, 0, 0));
1601 fputs ("@GOTOFF", file
);
1604 output_addr_const (file
, XVECEXP (x
, 0, 0));
1605 fputs ("@PLT", file
);
1608 output_addr_const (file
, XVECEXP (x
, 0, 0));
1609 fputs ("@GOTPLT", file
);
1612 output_addr_const (file
, XVECEXP (x
, 0, 0));
1613 fputs ("@DTPOFF", file
);
1615 case UNSPEC_GOTTPOFF
:
1616 output_addr_const (file
, XVECEXP (x
, 0, 0));
1617 fputs ("@GOTTPOFF", file
);
1620 output_addr_const (file
, XVECEXP (x
, 0, 0));
1621 fputs ("@TPOFF", file
);
1626 /* LPCS stands for Label for PIC Call Site. */
1627 targetm
.asm_out
.generate_internal_label (name
, "LPCS",
1628 INTVAL (XVECEXP (x
, 0, 0)));
1629 assemble_name (file
, name
);
1632 case UNSPEC_EXTRACT_S16
:
1633 case UNSPEC_EXTRACT_U16
:
1637 val
= XVECEXP (x
, 0, 0);
1638 shift
= XVECEXP (x
, 0, 1);
1640 if (shift
!= const0_rtx
)
1642 if (GET_CODE (val
) == CONST
1643 || GET_RTX_CLASS (GET_CODE (val
)) != RTX_OBJ
)
1646 output_addr_const (file
, val
);
1650 output_addr_const (file
, val
);
1651 if (shift
!= const0_rtx
)
1653 fputs (" >> ", file
);
1654 output_addr_const (file
, shift
);
1657 fputs (" & 65535)", file
);
1661 output_addr_const (file
, XVECEXP (x
, 0, 0));
1663 if (GET_CODE (XVECEXP (x
, 0, 1)) == CONST
)
1666 output_addr_const (file
, XVECEXP (x
, 0, 1));
1670 output_addr_const (file
, XVECEXP (x
, 0, 1));
1672 case UNSPEC_PCREL_SYMOFF
:
1673 output_addr_const (file
, XVECEXP (x
, 0, 0));
1675 output_addr_const (file
, XVECEXP (x
, 0, 1));
1676 fputs ("-.)", file
);
1687 /* Encode symbol attributes of a SYMBOL_REF into its
1688 SYMBOL_REF_FLAGS. */
1690 sh_encode_section_info (tree decl
, rtx rtl
, int first
)
1692 default_encode_section_info (decl
, rtl
, first
);
1694 if (TREE_CODE (decl
) == FUNCTION_DECL
1695 && sh2a_function_vector_p (decl
) && TARGET_SH2A
)
1696 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
1699 /* Prepare operands for a move define_expand; specifically, one of the
1700 operands must be in a register. */
1702 prepare_move_operands (rtx operands
[], machine_mode mode
)
1704 if ((mode
== SImode
|| mode
== DImode
)
1706 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
1707 && tls_symbolic_operand (operands
[1], Pmode
) != TLS_MODEL_NONE
))
1710 if (SYMBOLIC_CONST_P (operands
[1]))
1712 if (MEM_P (operands
[0]))
1713 operands
[1] = force_reg (Pmode
, operands
[1]);
1714 else if (TARGET_SHMEDIA
1715 && GET_CODE (operands
[1]) == LABEL_REF
1716 && target_reg_operand (operands
[0], mode
))
1720 temp
= (!can_create_pseudo_p ()
1722 : gen_reg_rtx (Pmode
));
1723 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
1726 else if (GET_CODE (operands
[1]) == CONST
1727 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1728 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
1730 temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
1731 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
1733 operands
[1] = expand_binop (mode
, add_optab
, temp
,
1734 XEXP (XEXP (operands
[1], 0), 1),
1735 (!can_create_pseudo_p ()
1737 : gen_reg_rtx (Pmode
)),
1738 0, OPTAB_LIB_WIDEN
);
1742 if (! reload_in_progress
&& ! reload_completed
)
1744 /* Copy the source to a register if both operands aren't registers. */
1745 if (! register_operand (operands
[0], mode
)
1746 && ! sh_register_operand (operands
[1], mode
))
1747 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1749 if (MEM_P (operands
[0]) && ! memory_operand (operands
[0], mode
))
1751 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1752 except that we can't use that function because it is static. */
1753 rtx new_rtx
= change_address (operands
[0], mode
, 0);
1754 MEM_COPY_ATTRIBUTES (new_rtx
, operands
[0]);
1755 operands
[0] = new_rtx
;
1758 /* This case can happen while generating code to move the result
1759 of a library call to the target. Reject `st r0,@(rX,rY)' because
1760 reload will fail to find a spill register for rX, since r0 is already
1761 being used for the source. */
1763 && refers_to_regno_p (R0_REG
, R0_REG
+ 1, operands
[1], (rtx
*)0)
1764 && MEM_P (operands
[0])
1765 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
1766 && REG_P (XEXP (XEXP (operands
[0], 0), 1)))
1767 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
1770 if (mode
== Pmode
|| mode
== ptr_mode
)
1773 enum tls_model tls_kind
;
1777 if (GET_CODE (op1
) == CONST
1778 && GET_CODE (XEXP (op1
, 0)) == PLUS
1779 && (tls_symbolic_operand (XEXP (XEXP (op1
, 0), 0), Pmode
)
1782 opc
= XEXP (XEXP (op1
, 0), 1);
1783 op1
= XEXP (XEXP (op1
, 0), 0);
1788 if (! reload_in_progress
&& ! reload_completed
1789 && (tls_kind
= tls_symbolic_operand (op1
, Pmode
)) != TLS_MODEL_NONE
)
1791 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
1794 && (tls_kind
== TLS_MODEL_GLOBAL_DYNAMIC
1795 || tls_kind
== TLS_MODEL_LOCAL_DYNAMIC
1796 || tls_kind
== TLS_MODEL_INITIAL_EXEC
))
1798 /* Don't schedule insns for getting GOT address when
1799 the first scheduling is enabled, to avoid spill
1801 if (flag_schedule_insns
)
1802 emit_insn (gen_blockage ());
1803 emit_insn (gen_GOTaddr2picreg ());
1804 emit_use (gen_rtx_REG (SImode
, PIC_REG
));
1805 if (flag_schedule_insns
)
1806 emit_insn (gen_blockage ());
1811 case TLS_MODEL_GLOBAL_DYNAMIC
:
1812 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1813 emit_call_insn (gen_tls_global_dynamic (tga_ret
, op1
));
1814 tmp
= gen_reg_rtx (Pmode
);
1815 emit_move_insn (tmp
, tga_ret
);
1819 case TLS_MODEL_LOCAL_DYNAMIC
:
1820 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
1821 emit_call_insn (gen_tls_local_dynamic (tga_ret
, op1
));
1823 tmp
= gen_reg_rtx (Pmode
);
1824 emit_move_insn (tmp
, tga_ret
);
1826 if (register_operand (op0
, Pmode
))
1829 tmp2
= gen_reg_rtx (Pmode
);
1831 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
1835 case TLS_MODEL_INITIAL_EXEC
:
1836 tga_op1
= !can_create_pseudo_p () ? op0
: gen_reg_rtx (Pmode
);
1837 tmp
= gen_sym2GOTTPOFF (op1
);
1838 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
1842 case TLS_MODEL_LOCAL_EXEC
:
1843 tmp2
= gen_reg_rtx (Pmode
);
1844 emit_insn (gen_store_gbr (tmp2
));
1845 tmp
= gen_reg_rtx (Pmode
);
1846 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
1848 if (register_operand (op0
, Pmode
))
1851 op1
= gen_reg_rtx (Pmode
);
1853 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
1860 emit_insn (gen_addsi3 (op1
, op1
, force_reg (SImode
, opc
)));
1866 /* Implement the canonicalize_comparison target hook for the combine
1867 pass. For the target hook this function is invoked via
1868 sh_canonicalize_comparison. This function is also re-used to
1869 canonicalize comparisons in cbranch pattern expanders. */
1871 sh_canonicalize_comparison (enum rtx_code
& cmp
, rtx
& op0
, rtx
& op1
,
1873 bool op0_preserve_value
)
1875 /* When invoked from within the combine pass the mode is not specified,
1876 so try to get it from one of the operands. */
1877 if (mode
== VOIDmode
)
1878 mode
= GET_MODE (op0
);
1879 if (mode
== VOIDmode
)
1880 mode
= GET_MODE (op1
);
1882 // We need to have a mode to do something useful here.
1883 if (mode
== VOIDmode
)
1886 // Currently, we don't deal with floats here.
1887 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1890 // Make sure that the constant operand is the second operand.
1891 if (CONST_INT_P (op0
) && !CONST_INT_P (op1
))
1893 if (op0_preserve_value
)
1896 std::swap (op0
, op1
);
1897 cmp
= swap_condition (cmp
);
1900 if (CONST_INT_P (op1
))
1902 /* Try to adjust the constant operand in such a way that available
1903 comparison insns can be utilized better and the constant can be
1904 loaded with a 'mov #imm,Rm' insn. This avoids a load from the
1906 const HOST_WIDE_INT val
= INTVAL (op1
);
1908 /* x > -1 --> x >= 0
1909 x > 0xFFFFFF7F --> x >= 0xFFFFFF80
1911 x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */
1912 if ((val
== -1 || val
== -0x81) && (cmp
== GT
|| cmp
== LE
))
1914 cmp
= cmp
== GT
? GE
: LT
;
1915 op1
= gen_int_mode (val
+ 1, mode
);
1919 x >= 0x80 --> x > 0x7F
1921 x < 0x80 --> x <= 0x7F */
1922 else if ((val
== 1 || val
== 0x80) && (cmp
== GE
|| cmp
== LT
))
1924 cmp
= cmp
== GE
? GT
: LE
;
1925 op1
= gen_int_mode (val
- 1, mode
);
1928 /* unsigned x >= 1 --> x != 0
1929 unsigned x < 1 --> x == 0 */
1930 else if (val
== 1 && (cmp
== GEU
|| cmp
== LTU
))
1932 cmp
= cmp
== GEU
? NE
: EQ
;
1933 op1
= CONST0_RTX (mode
);
1936 /* unsigned x >= 0x80 --> unsigned x > 0x7F
1937 unsigned x < 0x80 --> unsigned x < 0x7F */
1938 else if (val
== 0x80 && (cmp
== GEU
|| cmp
== LTU
))
1940 cmp
= cmp
== GEU
? GTU
: LEU
;
1941 op1
= gen_int_mode (val
- 1, mode
);
1944 /* unsigned x > 0 --> x != 0
1945 unsigned x <= 0 --> x == 0 */
1946 else if (val
== 0 && (cmp
== GTU
|| cmp
== LEU
))
1947 cmp
= cmp
== GTU
? NE
: EQ
;
1949 /* unsigned x > 0x7FFFFFFF --> signed x < 0
1950 unsigned x <= 0x7FFFFFFF --> signed x >= 0 */
1951 else if (mode
== SImode
&& (cmp
== GTU
|| cmp
== LEU
)
1952 && val
== 0x7FFFFFFF)
1954 cmp
= cmp
== GTU
? LT
: GE
;
1958 /* unsigned x >= 0x80000000 --> signed x < 0
1959 unsigned x < 0x80000000 --> signed x >= 0 */
1960 else if (mode
== SImode
&& (cmp
== GEU
|| cmp
== LTU
)
1961 && (unsigned HOST_WIDE_INT
)val
1962 == ((unsigned HOST_WIDE_INT
)0x7FFFFFFF + 1))
1964 cmp
= cmp
== GEU
? LT
: GE
;
1970 /* This function implements the canonicalize_comparison target hook.
1971 This wrapper around the internally used sh_canonicalize_comparison
1972 function is needed to do the enum rtx_code <-> int conversion.
1973 Target hooks cannot use enum rtx_code in its definition. */
1975 sh_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1976 bool op0_preserve_value
)
1978 enum rtx_code tmp_code
= (enum rtx_code
)*code
;
1979 sh_canonicalize_comparison (tmp_code
, *op0
, *op1
,
1980 VOIDmode
, op0_preserve_value
);
1981 *code
= (int)tmp_code
;
1985 sh_fixed_condition_code_regs (unsigned int* p1
, unsigned int* p2
)
1988 *p2
= INVALID_REGNUM
;
1993 prepare_cbranch_operands (rtx
*operands
, machine_mode mode
,
1994 enum rtx_code comparison
)
1996 /* The scratch reg is only available when this is invoked from within
1997 the cbranchdi4_i splitter, through expand_cbranchdi4. */
1998 rtx scratch
= NULL_RTX
;
2000 if (comparison
== LAST_AND_UNUSED_RTX_CODE
)
2001 comparison
= GET_CODE (operands
[0]);
2003 scratch
= operands
[4];
2005 sh_canonicalize_comparison (comparison
, operands
[1], operands
[2],
2008 /* Notice that this function is also invoked after reload by
2009 the cbranchdi4_i pattern, through expand_cbranchdi4. */
2010 rtx op1
= operands
[1];
2012 if (can_create_pseudo_p ())
2013 operands
[1] = force_reg (mode
, op1
);
2014 /* When we are handling DImode comparisons, we want to keep constants so
2015 that we can optimize the component comparisons; however, memory loads
2016 are better issued as a whole so that they can be scheduled well.
2017 SImode equality comparisons allow I08 constants, but only when they
2018 compare r0. Hence, if operands[1] has to be loaded from somewhere else
2019 into a register, that register might as well be r0, and we allow the
2020 constant. If it is already in a register, this is likely to be
2021 allocated to a different hard register, thus we load the constant into
2022 a register unless it is zero. */
2023 if (!REG_P (operands
[2])
2024 && (!CONST_INT_P (operands
[2])
2025 || (mode
== SImode
&& operands
[2] != CONST0_RTX (SImode
)
2026 && ((comparison
!= EQ
&& comparison
!= NE
)
2027 || (REG_P (op1
) && REGNO (op1
) != R0_REG
)
2028 || !satisfies_constraint_I08 (operands
[2])))))
2030 if (scratch
&& GET_MODE (scratch
) == mode
)
2032 emit_move_insn (scratch
, operands
[2]);
2033 operands
[2] = scratch
;
2035 else if (can_create_pseudo_p ())
2036 operands
[2] = force_reg (mode
, operands
[2]);
2042 expand_cbranchsi4 (rtx
*operands
, enum rtx_code comparison
, int probability
)
2044 rtx (*branch_expander
) (rtx
) = gen_branch_true
;
2045 comparison
= prepare_cbranch_operands (operands
, SImode
, comparison
);
2048 case NE
: case LT
: case LE
: case LTU
: case LEU
:
2049 comparison
= reverse_condition (comparison
);
2050 branch_expander
= gen_branch_false
;
2053 emit_insn (gen_rtx_SET (VOIDmode
, get_t_reg_rtx (),
2054 gen_rtx_fmt_ee (comparison
, SImode
,
2055 operands
[1], operands
[2])));
2056 rtx_insn
*jump
= emit_jump_insn (branch_expander (operands
[3]));
2057 if (probability
>= 0)
2058 add_int_reg_note (jump
, REG_BR_PROB
, probability
);
2061 /* ??? How should we distribute probabilities when more than one branch
2062 is generated. So far we only have some ad-hoc observations:
2063 - If the operands are random, they are likely to differ in both parts.
2064 - If comparing items in a hash chain, the operands are random or equal;
2065 operation should be EQ or NE.
2066 - If items are searched in an ordered tree from the root, we can expect
2067 the highpart to be unequal about half of the time; operation should be
2068 an inequality comparison, operands non-constant, and overall probability
2069 about 50%. Likewise for quicksort.
2070 - Range checks will be often made against constants. Even if we assume for
2071 simplicity an even distribution of the non-constant operand over a
2072 sub-range here, the same probability could be generated with differently
2073 wide sub-ranges - as long as the ratio of the part of the subrange that
2074 is before the threshold to the part that comes after the threshold stays
2075 the same. Thus, we can't really tell anything here;
2076 assuming random distribution is at least simple.
2079 expand_cbranchdi4 (rtx
*operands
, enum rtx_code comparison
)
2081 enum rtx_code msw_taken
, msw_skip
, lsw_taken
;
2082 rtx_code_label
*skip_label
= NULL
;
2083 rtx op1h
, op1l
, op2h
, op2l
;
2086 int msw_taken_prob
= -1, msw_skip_prob
= -1, lsw_taken_prob
= -1;
2087 rtx scratch
= operands
[4];
2089 comparison
= prepare_cbranch_operands (operands
, DImode
, comparison
);
2090 op1h
= gen_highpart_mode (SImode
, DImode
, operands
[1]);
2091 op2h
= gen_highpart_mode (SImode
, DImode
, operands
[2]);
2092 op1l
= gen_lowpart (SImode
, operands
[1]);
2093 op2l
= gen_lowpart (SImode
, operands
[2]);
2094 msw_taken
= msw_skip
= lsw_taken
= LAST_AND_UNUSED_RTX_CODE
;
2095 prob
= split_branch_probability
;
2096 rev_prob
= REG_BR_PROB_BASE
- prob
;
2099 /* ??? Should we use the cmpeqdi_t pattern for equality comparisons?
2100 That costs 1 cycle more when the first branch can be predicted taken,
2101 but saves us mispredicts because only one branch needs prediction.
2102 It also enables generating the cmpeqdi_t-1 pattern. */
2104 if (TARGET_CMPEQDI_T
)
2106 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
2107 emit_jump_insn (gen_branch_true (operands
[3]));
2114 // If we had more precision, we'd use rev_prob - (rev_prob >> 32) .
2115 msw_skip_prob
= rev_prob
;
2116 if (REG_BR_PROB_BASE
<= 65535)
2117 lsw_taken_prob
= prob
? REG_BR_PROB_BASE
: 0;
2123 - ((gcov_type
) REG_BR_PROB_BASE
* rev_prob
2124 / ((gcov_type
) prob
<< 32)))
2130 if (TARGET_CMPEQDI_T
)
2132 emit_insn (gen_cmpeqdi_t (operands
[1], operands
[2]));
2133 emit_jump_insn (gen_branch_false (operands
[3]));
2137 msw_taken_prob
= prob
;
2142 msw_taken
= comparison
;
2143 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2145 if (comparison
!= GTU
|| op2h
!= CONST0_RTX (SImode
))
2146 msw_skip
= swap_condition (msw_taken
);
2150 if (op2l
== CONST0_RTX (SImode
))
2151 msw_taken
= comparison
;
2154 msw_taken
= comparison
== GE
? GT
: GTU
;
2155 msw_skip
= swap_condition (msw_taken
);
2160 msw_taken
= comparison
;
2161 if (op2l
== CONST0_RTX (SImode
))
2163 msw_skip
= swap_condition (msw_taken
);
2167 if (CONST_INT_P (op2l
) && INTVAL (op2l
) == -1)
2168 msw_taken
= comparison
;
2172 if (comparison
== LE
)
2174 else if (op2h
!= CONST0_RTX (SImode
))
2178 msw_skip
= swap_condition (LTU
);
2181 msw_skip
= swap_condition (msw_taken
);
2184 default: return false;
2186 num_branches
= ((msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2187 + (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2188 + (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
));
2189 if (comparison
!= EQ
&& comparison
!= NE
&& num_branches
> 1)
2191 if (!CONSTANT_P (operands
[2])
2192 && prob
>= (int) (REG_BR_PROB_BASE
* 3 / 8U)
2193 && prob
<= (int) (REG_BR_PROB_BASE
* 5 / 8U))
2195 msw_taken_prob
= prob
/ 2U;
2197 = REG_BR_PROB_BASE
* rev_prob
/ (REG_BR_PROB_BASE
+ rev_prob
);
2198 lsw_taken_prob
= prob
;
2202 msw_taken_prob
= prob
;
2203 msw_skip_prob
= REG_BR_PROB_BASE
;
2204 /* ??? If we have a constant op2h, should we use that when
2205 calculating lsw_taken_prob? */
2206 lsw_taken_prob
= prob
;
2211 operands
[4] = NULL_RTX
;
2212 if (reload_completed
2213 && ! arith_reg_or_0_operand (op2h
, SImode
)
2214 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
))
2215 && (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
2216 || msw_skip
!= LAST_AND_UNUSED_RTX_CODE
))
2218 emit_move_insn (scratch
, operands
[2]);
2219 operands
[2] = scratch
;
2221 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2222 expand_cbranchsi4 (operands
, msw_taken
, msw_taken_prob
);
2223 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2225 rtx taken_label
= operands
[3];
2227 /* Operands were possibly modified, but msw_skip doesn't expect this.
2228 Always use the original ones. */
2229 if (msw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2233 if (reload_completed
2234 && ! arith_reg_or_0_operand (op2h
, SImode
)
2235 && (true_regnum (op1h
) || (comparison
!= EQ
&& comparison
!= NE
)))
2237 emit_move_insn (scratch
, operands
[2]);
2238 operands
[2] = scratch
;
2242 operands
[3] = skip_label
= gen_label_rtx ();
2243 expand_cbranchsi4 (operands
, msw_skip
, msw_skip_prob
);
2244 operands
[3] = taken_label
;
2248 if (lsw_taken
!= LAST_AND_UNUSED_RTX_CODE
)
2250 if (reload_completed
2251 && ! arith_reg_or_0_operand (op2l
, SImode
)
2252 && (true_regnum (op1l
) || (lsw_taken
!= EQ
&& lsw_taken
!= NE
)))
2254 emit_move_insn (scratch
, operands
[2]);
2255 operands
[2] = scratch
;
2257 expand_cbranchsi4 (operands
, lsw_taken
, lsw_taken_prob
);
2259 if (msw_skip
!= LAST_AND_UNUSED_RTX_CODE
)
2260 emit_label (skip_label
);
2264 /* Given an operand, return 1 if the evaluated operand plugged into an
2265 if_then_else will result in a branch_true, 0 if branch_false, or
2266 -1 if neither nor applies. The truth table goes like this:
2268 op | cmpval | code | result
2269 ---------+--------+---------+--------------------
2270 T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
2271 T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
2272 T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
2273 T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
2274 !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
2275 !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
2276 !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
2277 !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
2279 sh_eval_treg_value (rtx op
)
2281 if (t_reg_operand (op
, GET_MODE (op
)))
2283 if (negt_reg_operand (op
, GET_MODE (op
)))
2286 rtx_code code
= GET_CODE (op
);
2287 if ((code
!= EQ
&& code
!= NE
) || !CONST_INT_P (XEXP (op
, 1)))
2290 int cmpop
= code
== EQ
? 1 : 0;
2291 int cmpval
= INTVAL (XEXP (op
, 1));
2292 if (cmpval
!= 0 && cmpval
!= 1)
2296 if (t_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2298 else if (negt_reg_operand (XEXP (op
, 0), GET_MODE (XEXP (op
, 0))))
2303 return t
^ (cmpval
== cmpop
);
2306 /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case
2307 of floating-point comparisons. */
2309 sh_emit_set_t_insn (rtx insn
, machine_mode mode
)
2311 if (TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
2312 && GET_CODE (insn
) != PARALLEL
)
2314 insn
= gen_rtx_PARALLEL (VOIDmode
,
2316 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_STAT_REG
)),
2317 gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, FPSCR_MODES_REG
))));
2322 /* Prepare the operands for an scc instruction; make sure that the
2323 compare has been done and the result is in T_REG. */
2325 sh_emit_scc_to_t (enum rtx_code code
, rtx op0
, rtx op1
)
2327 rtx t_reg
= get_t_reg_rtx ();
2328 enum rtx_code oldcode
= code
;
2331 /* First need a compare insn. */
2335 /* It isn't possible to handle this case. */
2352 if (code
!= oldcode
)
2353 std::swap (op0
, op1
);
2355 mode
= GET_MODE (op0
);
2356 if (mode
== VOIDmode
)
2357 mode
= GET_MODE (op1
);
2359 op0
= force_reg (mode
, op0
);
2360 if ((code
!= EQ
&& code
!= NE
2361 && (op1
!= const0_rtx
2362 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2363 || (mode
== DImode
&& op1
!= const0_rtx
)
2364 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2365 op1
= force_reg (mode
, op1
);
2367 sh_emit_set_t_insn (gen_rtx_SET (VOIDmode
, t_reg
,
2368 gen_rtx_fmt_ee (code
, SImode
, op0
, op1
)),
2373 sh_emit_cheap_store_flag (machine_mode mode
, enum rtx_code code
,
2376 rtx target
= gen_reg_rtx (SImode
);
2379 gcc_assert (TARGET_SHMEDIA
);
2388 tmp
= gen_rtx_fmt_ee (code
, SImode
, op0
, op1
);
2389 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2399 tmp
= gen_rtx_fmt_ee (reverse_condition (code
), mode
, op0
, op1
);
2400 emit_insn (gen_cstore4_media (target
, tmp
, op0
, op1
));
2418 rtx t2
= gen_reg_rtx (DImode
);
2419 emit_insn (gen_extendsidi2 (t2
, target
));
2423 return gen_rtx_fmt_ee (code
, VOIDmode
, target
, const0_rtx
);
2426 /* Called from the md file, set up the operands of a compare instruction. */
2428 sh_emit_compare_and_branch (rtx
*operands
, machine_mode mode
)
2430 enum rtx_code code
= GET_CODE (operands
[0]);
2431 enum rtx_code branch_code
;
2432 rtx op0
= operands
[1];
2433 rtx op1
= operands
[2];
2435 bool need_ccmpeq
= false;
2437 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2439 op0
= force_reg (mode
, op0
);
2440 op1
= force_reg (mode
, op1
);
2444 if (code
!= EQ
|| mode
== DImode
)
2446 /* Force args into regs, since we can't use constants here. */
2447 op0
= force_reg (mode
, op0
);
2448 if (op1
!= const0_rtx
|| code
== GTU
|| code
== GEU
)
2449 op1
= force_reg (mode
, op1
);
2453 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2456 || (code
== LE
&& TARGET_IEEE
&& TARGET_SH2E
)
2457 || (code
== GE
&& !(TARGET_IEEE
&& TARGET_SH2E
)))
2459 std::swap (op0
, op1
);
2460 code
= swap_condition (code
);
2463 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2466 gcc_assert (TARGET_IEEE
&& TARGET_SH2E
);
2471 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2472 to EQ/GT respectively. */
2473 gcc_assert (code
== EQ
|| code
== GT
|| code
== NE
|| code
== LE
);
2490 branch_code
= reverse_condition (code
);
2496 insn
= gen_rtx_SET (VOIDmode
,
2498 gen_rtx_fmt_ee (branch_code
, SImode
, op0
, op1
));
2500 sh_emit_set_t_insn (insn
, mode
);
2502 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0
, op1
), mode
);
2504 if (branch_code
== code
)
2505 emit_jump_insn (gen_branch_true (operands
[3]));
2507 emit_jump_insn (gen_branch_false (operands
[3]));
2511 sh_emit_compare_and_set (rtx
*operands
, machine_mode mode
)
2513 enum rtx_code code
= GET_CODE (operands
[1]);
2514 rtx op0
= operands
[2];
2515 rtx op1
= operands
[3];
2516 rtx_code_label
*lab
= NULL
;
2517 bool invert
= false;
2519 op0
= force_reg (mode
, op0
);
2520 if ((code
!= EQ
&& code
!= NE
2521 && (op1
!= const0_rtx
2522 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
2523 || (mode
== DImode
&& op1
!= const0_rtx
)
2524 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2525 op1
= force_reg (mode
, op1
);
2527 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2529 if (code
== LT
|| code
== LE
)
2531 std::swap (op0
, op1
);
2532 code
= swap_condition (code
);
2538 lab
= gen_label_rtx ();
2539 sh_emit_scc_to_t (EQ
, op0
, op1
);
2540 emit_jump_insn (gen_branch_true (lab
));
2557 sh_emit_scc_to_t (code
, op0
, op1
);
2561 emit_insn (gen_movnegt (operands
[0], get_t_reg_rtx ()));
2563 emit_move_insn (operands
[0], get_t_reg_rtx ());
2566 /* Functions to output assembly code. */
2568 /* Return a sequence of instructions to perform DI or DF move.
2570 Since the SH cannot move a DI or DF in one instruction, we have
2571 to take care when we see overlapping source and dest registers. */
2573 output_movedouble (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
2576 rtx dst
= operands
[0];
2577 rtx src
= operands
[1];
2580 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
2581 return "mov.l %T1,%0" "\n"
2584 if (register_operand (dst
, mode
)
2585 && register_operand (src
, mode
))
2587 if (REGNO (src
) == MACH_REG
)
2588 return "sts mach,%S0" "\n"
2591 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2592 when mov.d r1,r0 do r1->r0 then r2->r1. */
2593 if (REGNO (src
) + 1 == REGNO (dst
))
2594 return "mov %T1,%T0" "\n"
2597 return "mov %1,%0" "\n"
2600 else if (CONST_INT_P (src
))
2602 if (INTVAL (src
) < 0)
2603 output_asm_insn ("mov #-1,%S0", operands
);
2605 output_asm_insn ("mov #0,%S0", operands
);
2607 return "mov %1,%R0";
2609 else if (MEM_P (src
))
2612 int dreg
= REGNO (dst
);
2613 rtx inside
= XEXP (src
, 0);
2615 switch (GET_CODE (inside
))
2618 ptrreg
= REGNO (inside
);
2622 ptrreg
= subreg_regno (inside
);
2626 ptrreg
= REGNO (XEXP (inside
, 0));
2627 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2628 an offsettable address. Unfortunately, offsettable addresses use
2629 QImode to check the offset, and a QImode offsettable address
2630 requires r0 for the other operand, which is not currently
2631 supported, so we can't use the 'o' constraint.
2632 Thus we must check for and handle r0+REG addresses here.
2633 We punt for now, since this is likely very rare. */
2634 gcc_assert (!REG_P (XEXP (inside
, 1)));
2638 return "mov.l %1,%0" "\n"
2641 return "mov.l %1,%0" "\n"
2647 /* Work out the safe way to copy. Copy into the second half first. */
2649 return "mov.l %T1,%T0" "\n"
2653 return "mov.l %1,%0" "\n"
2657 /* Print an instruction which would have gone into a delay slot after
2658 another instruction, but couldn't because the other instruction expanded
2659 into a sequence where putting the slot insn at the end wouldn't work. */
2661 print_slot (rtx_sequence
*seq
)
2663 final_scan_insn (seq
->insn (1), asm_out_file
, optimize
, 1, NULL
);
2665 seq
->insn (1)->set_deleted ();
2669 output_far_jump (rtx_insn
*insn
, rtx op
)
2671 struct { rtx lab
, reg
, op
; } this_jmp
;
2672 rtx_code_label
*braf_base_lab
= NULL
;
2675 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2678 this_jmp
.lab
= gen_label_rtx ();
2682 && offset
- get_attr_length (insn
) <= 32766)
2685 jump
= "mov.w %O0,%1" "\n"
2694 jump
= "mov.l %O0,%1" "\n"
2697 jump
= "mov.l r0,@-r15" "\n"
2699 " mov.l @r0,%1" "\n"
2701 " mov.l @r15+,r0" "\n"
2705 jump
= "mov.l %O0,%1" "\n"
2708 /* If we have a scratch register available, use it. */
2709 if (NONJUMP_INSN_P ((prev
= prev_nonnote_insn (insn
)))
2710 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2712 this_jmp
.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
2713 if (REGNO (this_jmp
.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
2714 jump
= "mov.l r1,@-r15" "\n"
2716 " mov.l @r0,r1" "\n"
2718 " mov.l @r15+,r1" "\n"
2720 output_asm_insn (jump
, &this_jmp
.lab
);
2721 if (dbr_sequence_length ())
2722 print_slot (final_sequence
);
2724 output_asm_insn ("nop", 0);
2728 /* Output the delay slot insn first if any. */
2729 if (dbr_sequence_length ())
2730 print_slot (final_sequence
);
2732 this_jmp
.reg
= gen_rtx_REG (SImode
, 13);
2733 /* We must keep the stack aligned to 8-byte boundaries on SH5.
2734 Fortunately, MACL is fixed and call-clobbered, and we never
2735 need its value across jumps, so save r13 in it instead of in
2738 output_asm_insn ("lds r13,macl", 0);
2740 output_asm_insn ("mov.l r13,@-r15", 0);
2741 output_asm_insn (jump
, &this_jmp
.lab
);
2743 output_asm_insn ("sts macl,r13", 0);
2745 output_asm_insn ("mov.l @r15+,r13", 0);
2747 if (far
&& flag_pic
&& TARGET_SH2
)
2749 braf_base_lab
= gen_label_rtx ();
2750 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
2751 CODE_LABEL_NUMBER (braf_base_lab
));
2754 output_asm_insn (".align 2", 0);
2755 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this_jmp
.lab
));
2757 if (far
&& flag_pic
)
2760 this_jmp
.lab
= braf_base_lab
;
2761 output_asm_insn (".long %O2-%O0", &this_jmp
.lab
);
2764 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this_jmp
.lab
);
2768 /* Local label counter, used for constants in the pool and inside
2769 pattern branches. */
2770 static int lf
= 100;
2772 /* Output code for ordinary branches. */
2774 output_branch (int logic
, rtx_insn
*insn
, rtx
*operands
)
2776 switch (get_attr_length (insn
))
2779 /* This can happen if filling the delay slot has caused a forward
2780 branch to exceed its range (we could reverse it, but only
2781 when we know we won't overextend other branches; this should
2782 best be handled by relaxation).
2783 It can also happen when other condbranches hoist delay slot insn
2784 from their destination, thus leading to code size increase.
2785 But the branch will still be in the range -4092..+4098 bytes. */
2789 /* The call to print_slot will clobber the operands. */
2790 rtx op0
= operands
[0];
2792 /* If the instruction in the delay slot is annulled (true), then
2793 there is no delay slot where we can put it now. The only safe
2794 place for it is after the label. final will do that by default. */
2797 && ! INSN_ANNULLED_BRANCH_P (final_sequence
->insn (0))
2798 && get_attr_length (final_sequence
->insn (1)))
2800 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
2801 ASSEMBLER_DIALECT
? "/" : ".", label
);
2802 print_slot (final_sequence
);
2805 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
2807 output_asm_insn ("bra\t%l0", &op0
);
2808 fprintf (asm_out_file
, "\tnop\n");
2809 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2813 /* When relaxing, handle this like a short branch. The linker
2814 will fix it up if it still doesn't fit after relaxation. */
2816 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
2818 /* These are for SH2e, in which we have to account for the
2819 extra nop because of the hardware bug in annulled branches. */
2825 gcc_assert (!final_sequence
2826 || !(INSN_ANNULLED_BRANCH_P
2827 (XVECEXP (final_sequence
, 0, 0))));
2828 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
2830 ASSEMBLER_DIALECT
? "/" : ".", label
);
2831 fprintf (asm_out_file
, "\tnop\n");
2832 output_asm_insn ("bra\t%l0", operands
);
2833 fprintf (asm_out_file
, "\tnop\n");
2834 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
2838 /* When relaxing, fall through. */
2843 sprintf (buffer
, "b%s%ss\t%%l0",
2845 ASSEMBLER_DIALECT
? "/" : ".");
2846 output_asm_insn (buffer
, &operands
[0]);
2851 /* There should be no longer branches now - that would
2852 indicate that something has destroyed the branches set
2853 up in machine_dependent_reorg. */
2858 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2859 fill in operands 9 as a label to the successor insn.
2860 We try to use jump threading where possible.
2861 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2862 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2863 follow jmp and bt, if the address is in range. */
2865 output_branchy_insn (enum rtx_code code
, const char *templ
,
2866 rtx_insn
*insn
, rtx
*operands
)
2868 rtx_insn
*next_insn
= NEXT_INSN (insn
);
2870 if (next_insn
&& JUMP_P (next_insn
) && condjump_p (next_insn
))
2872 rtx src
= SET_SRC (PATTERN (next_insn
));
2873 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
2875 /* Following branch not taken */
2876 rtx_code_label
*lab
= gen_label_rtx ();
2877 emit_label_after (lab
, next_insn
);
2878 INSN_ADDRESSES_NEW (lab
,
2879 INSN_ADDRESSES (INSN_UID (next_insn
))
2880 + get_attr_length (next_insn
));
2886 int offset
= (branch_dest (next_insn
)
2887 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
2888 if (offset
>= -252 && offset
<= 258)
2890 if (GET_CODE (src
) == IF_THEN_ELSE
)
2892 src
= XEXP (src
, 1);
2898 rtx_code_label
*lab
= gen_label_rtx ();
2899 emit_label_after (lab
, insn
);
2900 INSN_ADDRESSES_NEW (lab
,
2901 INSN_ADDRESSES (INSN_UID (insn
))
2902 + get_attr_length (insn
));
2908 output_ieee_ccmpeq (rtx_insn
*insn
, rtx
*operands
)
2910 return output_branchy_insn (NE
, "bt %l9" "\n"
2915 /* Output the start of the assembler file. */
2917 sh_file_start (void)
2919 default_file_start ();
2922 /* We need to show the text section with the proper
2923 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2924 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2925 will complain. We can teach GAS specifically about the
2926 default attributes for our choice of text section, but
2927 then we would have to change GAS again if/when we change
2928 the text section name. */
2929 fprintf (asm_out_file
, "%s\n", TEXT_SECTION_ASM_OP
);
2931 /* Switch to the data section so that the coffsem symbol
2932 isn't in the text section. */
2933 switch_to_section (data_section
);
2935 if (TARGET_LITTLE_ENDIAN
)
2936 fputs ("\t.little\n", asm_out_file
);
2940 if (TARGET_SHCOMPACT
)
2941 fputs ("\t.mode\tSHcompact\n", asm_out_file
);
2942 else if (TARGET_SHMEDIA
)
2943 fprintf (asm_out_file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
2944 TARGET_SHMEDIA64
? 64 : 32);
2948 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2950 unspec_caller_rtx_p (rtx pat
)
2955 split_const (pat
, &base
, &offset
);
2956 if (GET_CODE (base
) == UNSPEC
)
2958 if (XINT (base
, 1) == UNSPEC_CALLER
)
2960 for (i
= 0; i
< XVECLEN (base
, 0); i
++)
2961 if (unspec_caller_rtx_p (XVECEXP (base
, 0, i
)))
2967 /* Indicate that INSN cannot be duplicated. This is true for insn
2968 that generates a unique label. */
2970 sh_cannot_copy_insn_p (rtx_insn
*insn
)
2974 if (!reload_completed
|| !flag_pic
)
2977 if (!NONJUMP_INSN_P (insn
))
2979 if (asm_noperands (insn
) >= 0)
2982 pat
= PATTERN (insn
);
2983 if (GET_CODE (pat
) != SET
)
2985 pat
= SET_SRC (pat
);
2987 if (unspec_caller_rtx_p (pat
))
2993 /* Number of instructions used to make an arithmetic right shift by N. */
2994 static const char ashiftrt_insns
[] =
2995 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2997 /* Description of a logical left or right shift, when expanded to a sequence
2999 Notice that one bit right shifts clobber the T bit. One bit left shifts
3000 are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */
3003 ASHL_CLOBBERS_T
= 1 << 0,
3004 LSHR_CLOBBERS_T
= 1 << 1
3007 struct ashl_lshr_sequence
3014 static const struct ashl_lshr_sequence ashl_lshr_seq
[32] =
3016 { 0, { 0 }, 0 }, // 0
3017 { 1, { 1 }, LSHR_CLOBBERS_T
},
3019 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
3020 { 2, { 2, 2 }, 0 }, // 4
3021 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
3022 { 3, { 2, 2, 2 }, 0 },
3023 { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3024 { 1, { 8 }, 0 }, // 8
3025 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
3027 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
3028 { 3, { 8, 2, 2 }, 0 }, // 12
3029 { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3030 { 3, { 8, -2, 8 }, 0 },
3031 { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T
},
3032 { 1, { 16 }, 0 }, // 16
3033 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
3034 { 2, { 16, 2 }, 0 },
3035 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
3036 { 3, { 16, 2, 2 }, 0 }, // 20
3037 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3038 { 3, { 16, -2, 8 }, 0 },
3039 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
3040 { 2, { 16, 8 }, 0 }, // 24
3041 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
3042 { 3, { 16, 8, 2 }, 0 },
3043 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
3044 { 4, { 16, 8, 2, 2 }, 0 }, // 28
3045 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
3046 { 3, { 16, -2, 16 }, 0 },
3048 /* For a right shift by 31 a 2 insn shll-movt sequence can be used.
3049 For a left shift by 31 a 2 insn and-rotl sequences can be used.
3050 However, the shift-and combiner code needs this entry here to be in
3051 terms of real shift insns. */
3052 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
3055 /* Individual shift amounts for shift amounts < 16, up to three highmost
3056 bits might be clobbered. This is typically used when combined with some
3057 kind of sign or zero extension. */
3058 static const struct ashl_lshr_sequence ext_ashl_lshr_seq
[32] =
3060 { 0, { 0 }, 0 }, // 0
3061 { 1, { 1 }, LSHR_CLOBBERS_T
},
3063 { 2, { 2, 1 }, LSHR_CLOBBERS_T
},
3064 { 2, { 2, 2 }, 0 }, // 4
3065 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T
},
3066 { 2, { 8, -2 }, 0 },
3067 { 2, { 8, -1 }, ASHL_CLOBBERS_T
},
3068 { 1, { 8 }, 0 }, // 8
3069 { 2, { 8, 1 }, LSHR_CLOBBERS_T
},
3071 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T
},
3072 { 3, { 8, 2, 2 }, 0 }, // 12
3073 { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T
},
3074 { 2, { 16, -2 }, 0 },
3075 { 2, { 16, -1 }, ASHL_CLOBBERS_T
},
3076 { 1, { 16 }, 0 }, // 16
3077 { 2, { 16, 1 }, LSHR_CLOBBERS_T
},
3078 { 2, { 16, 2 }, 0 },
3079 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T
},
3080 { 3, { 16, 2, 2 }, 0 }, // 20
3081 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T
},
3082 { 3, { 16, -2, 8 }, 0 },
3083 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T
},
3084 { 2, { 16, 8 }, 0 }, // 24
3085 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T
},
3086 { 3, { 16, 8, 2 }, 0 },
3087 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T
},
3088 { 4, { 16, 8, 2, 2 }, 0 }, // 28
3089 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T
},
3090 { 3, { 16, -2, 16 }, 0 },
3091 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T
}
3094 /* Return true if a shift left consisting of 1/2/8/16 shift instructions
3095 will clobber the T bit. */
3097 sh_ashlsi_clobbers_t_reg_p (rtx shift_amount
)
3099 gcc_assert (CONST_INT_P (shift_amount
));
3101 const int shift_amount_i
= INTVAL (shift_amount
) & 31;
3103 /* Special case for shift count of 31: use and-rotl sequence. */
3104 if (shift_amount_i
== 31)
3107 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3108 & ASHL_CLOBBERS_T
) != 0;
3111 /* Return true if a logical right shift consisting of 1/2/8/16 shift
3112 instructions will clobber the T bit. */
3114 sh_lshrsi_clobbers_t_reg_p (rtx shift_amount
)
3116 gcc_assert (CONST_INT_P (shift_amount
));
3118 const int shift_amount_i
= INTVAL (shift_amount
) & 31;
3120 /* Special case for shift count of 31: use shll-movt sequence. */
3121 if (shift_amount_i
== 31)
3124 return (ashl_lshr_seq
[shift_amount_i
].clobbers_t
3125 & LSHR_CLOBBERS_T
) != 0;
3128 /* Return true if it is potentially beneficial to use a dynamic shift
3129 instruction (shad / shar) instead of a combination of 1/2/8/16
3130 shift instructions for the specified shift count.
3131 If dynamic shifts are not available, always return false. */
3133 sh_dynamicalize_shift_p (rtx count
)
3135 gcc_assert (CONST_INT_P (count
));
3137 const int shift_amount_i
= INTVAL (count
) & 31;
3140 /* For left and right shifts, there are shorter 2 insn sequences for
3141 shift amounts of 31. */
3142 if (shift_amount_i
== 31)
3145 insn_count
= ashl_lshr_seq
[shift_amount_i
].insn_count
;
3147 return TARGET_DYNSHIFT
&& (insn_count
> 1 + SH_DYNAMIC_SHIFT_COST
);
3150 /* Assuming we have a value that has been sign-extended by at least one bit,
3151 can we use the ext_shift_amounts with the last shift turned to an
3152 arithmetic shift to shift it by N without data loss, and quicker than by
3154 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
3156 /* Return the cost of a shift. */
3165 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
3167 if (GET_MODE (x
) == DImode
3168 && CONST_INT_P (XEXP (x
, 1))
3169 && INTVAL (XEXP (x
, 1)) == 1)
3172 /* Everything else is invalid, because there is no pattern for it. */
3175 /* If shift by a non constant, then this will be expensive. */
3176 if (!CONST_INT_P (XEXP (x
, 1)))
3177 return SH_DYNAMIC_SHIFT_COST
;
3179 /* Otherwise, return the true cost in instructions. Cope with out of range
3180 shift counts more or less arbitrarily. */
3181 value
= INTVAL (XEXP (x
, 1)) & 31;
3183 if (GET_CODE (x
) == ASHIFTRT
)
3185 int cost
= ashiftrt_insns
[value
];
3186 /* If dynamic shifts are available and profitable in this case, then we
3187 put the constant in a reg and use shad. */
3188 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
3189 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
3193 return ashl_lshr_seq
[value
].insn_count
;
3196 /* Return the cost of an AND/XOR/IOR operation. */
3198 and_xor_ior_costs (rtx x
, int code
)
3200 /* On SH1-4 we have only max. SImode operations.
3201 Double the cost for modes > SImode. */
3202 const int cost_scale
= !TARGET_SHMEDIA
3203 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
3206 /* A logical operation with two registers is a single cycle
3208 if (!CONST_INT_P (XEXP (x
, 1)))
3209 return 1 * cost_scale
;
3211 int i
= INTVAL (XEXP (x
, 1));
3215 if (satisfies_constraint_I10 (XEXP (x
, 1))
3216 || satisfies_constraint_J16 (XEXP (x
, 1)))
3219 return 1 + rtx_cost (XEXP (x
, 1), AND
, 1, !optimize_size
);
3222 /* These constants are single cycle extu.[bw] instructions. */
3223 if ((i
== 0xff || i
== 0xffff) && code
== AND
)
3224 return 1 * cost_scale
;
3225 /* Constants that can be used in an instruction as an immediate are
3226 a single cycle, but this requires r0, so make it a little more
3228 if (CONST_OK_FOR_K08 (i
))
3229 return 2 * cost_scale
;
3230 /* Constants that can be loaded with a mov immediate need one more cycle.
3231 This case is probably unnecessary. */
3232 if (CONST_OK_FOR_I08 (i
))
3233 return 2 * cost_scale
;
3234 /* Any other constant requires an additional 2 cycle pc-relative load.
3235 This case is probably unnecessary. */
3236 return 3 * cost_scale
;
3239 /* Return the cost of an addition or a subtraction. */
3243 if (GET_MODE (x
) == SImode
)
3245 /* The addc or subc patterns will eventually become one or two
3246 instructions. Below are some costs for some of the patterns
3247 which combine would reject because the costs of the individual
3248 insns in the patterns are lower.
3250 FIXME: It would be much easier if we had something like insn cost
3251 attributes and the cost calculation machinery used those attributes
3252 in the first place. This would eliminate redundant recog-like C
3253 code to calculate costs of complex patterns. */
3254 rtx op0
= XEXP (x
, 0);
3255 rtx op1
= XEXP (x
, 1);
3257 if (GET_CODE (x
) == PLUS
)
3259 if (GET_CODE (op0
) == AND
3260 && XEXP (op0
, 1) == const1_rtx
3261 && (GET_CODE (op1
) == PLUS
3262 || (GET_CODE (op1
) == MULT
&& XEXP (op1
, 1) == const2_rtx
)))
3265 if (GET_CODE (op0
) == MULT
&& XEXP (op0
, 1) == const2_rtx
3266 && GET_CODE (op1
) == LSHIFTRT
3267 && CONST_INT_P (XEXP (op1
, 1)) && INTVAL (XEXP (op1
, 1)) == 31)
3272 /* On SH1-4 we have only max. SImode operations.
3273 Double the cost for modes > SImode. */
3274 const int cost_scale
= !TARGET_SHMEDIA
3275 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
3278 /* Adding a register is a single cycle insn. */
3279 if (REG_P (XEXP (x
, 1))
3280 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
3281 return 1 * cost_scale
;
3283 /* Likewise for small constants. */
3284 if (CONST_INT_P (XEXP (x
, 1))
3285 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
3286 return 1 * cost_scale
;
3289 switch (GET_CODE (XEXP (x
, 1)))
3294 return TARGET_SHMEDIA64
? 5 : 3;
3297 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1))))
3299 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1)) >> 16))
3301 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
3309 /* Any other constant requires a 2 cycle pc-relative load plus an
3311 return 3 * cost_scale
;
3314 /* Return the cost of a multiply. */
3316 multcosts (rtx x ATTRIBUTE_UNUSED
)
3318 if (sh_multcost
>= 0)
3321 /* ??? We have a mul insn, but it has a latency of three, and doesn't
3322 accept constants. Ideally, we would use a cost of one or two and
3323 add the cost of the operand, but disregard the latter when inside loops
3324 and loop invariant code motion is still to follow.
3325 Using a multiply first and splitting it later if it's a loss
3326 doesn't work because of different sign / zero extension semantics
3327 of multiplies vs. shifts. */
3328 return optimize_size
? 2 : 3;
3332 /* We have a mul insn, so we can never take more than the mul and the
3333 read of the mac reg, but count more because of the latency and extra
3340 /* If we're aiming at small code, then just count the number of
3341 insns in a multiply call sequence. */
3345 /* Otherwise count all the insns in the routine we'd be calling too. */
3349 /* Compute a (partial) cost for rtx X. Return true if the complete
3350 cost has been computed, and false if subexpressions should be
3351 scanned. In either case, *TOTAL contains the cost result. */
3353 sh_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3354 int *total
, bool speed ATTRIBUTE_UNUSED
)
3358 /* The lower-subreg pass decides whether to split multi-word regs
3359 into individual regs by looking at the cost for a SET of certain
3360 modes with the following patterns:
3362 (set (reg) (const_int 0))
3363 On machines that support vector-move operations a multi-word move
3364 is the same cost as individual reg move. On SH there is no
3365 vector-move, so we have to provide the correct cost in the number
3366 of move insns to load/store the reg of the mode in question. */
3368 if (register_operand (SET_DEST (x
), VOIDmode
)
3369 && (register_operand (SET_SRC (x
), VOIDmode
)
3370 || satisfies_constraint_Z (SET_SRC (x
))))
3372 const machine_mode mode
= GET_MODE (SET_DEST (x
));
3373 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
)
3374 / mov_insn_size (mode
, TARGET_SH2A
));
3379 /* The cost of a mem access is mainly the cost of the address mode. */
3381 *total
= sh_address_cost (XEXP (x
, 0), GET_MODE (x
), MEM_ADDR_SPACE (x
),
3385 /* The cost of a sign or zero extend depends on whether the source is a
3386 reg or a mem. In case of a mem take the address into acount. */
3388 if (REG_P (XEXP (x
, 0)))
3390 *total
= COSTS_N_INSNS (1);
3393 if (MEM_P (XEXP (x
, 0)))
3395 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3396 GET_MODE (XEXP (x
, 0)),
3397 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3403 if (REG_P (XEXP (x
, 0)))
3405 *total
= COSTS_N_INSNS (1);
3408 else if (TARGET_SH2A
&& MEM_P (XEXP (x
, 0))
3409 && (GET_MODE (XEXP (x
, 0)) == QImode
3410 || GET_MODE (XEXP (x
, 0)) == HImode
))
3412 /* Handle SH2A's movu.b and movu.w insn. */
3413 *total
= sh_address_cost (XEXP (XEXP (x
, 0), 0),
3414 GET_MODE (XEXP (x
, 0)),
3415 MEM_ADDR_SPACE (XEXP (x
, 0)), true);
3420 /* mems for SFmode and DFmode can be inside a parallel due to
3421 the way the fpscr is handled. */
3423 for (int i
= 0; i
< XVECLEN (x
, 0); i
++)
3425 rtx xx
= XVECEXP (x
, 0, i
);
3426 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 0)))
3428 *total
= sh_address_cost (XEXP (XEXP (xx
, 0), 0),
3429 GET_MODE (XEXP (xx
, 0)),
3430 MEM_ADDR_SPACE (XEXP (xx
, 0)), true);
3433 if (GET_CODE (xx
) == SET
&& MEM_P (XEXP (xx
, 1)))
3435 *total
= sh_address_cost (XEXP (XEXP (xx
, 1), 0),
3436 GET_MODE (XEXP (xx
, 1)),
3437 MEM_ADDR_SPACE (XEXP (xx
, 1)), true);
3442 if (sh_1el_vec (x
, VOIDmode
))
3443 *total
= outer_code
!= SET
;
3444 else if (sh_rep_vec (x
, VOIDmode
))
3445 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3446 + (outer_code
!= SET
));
3448 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3454 if (INTVAL (x
) == 0)
3456 else if (outer_code
== AND
&& and_operand ((x
), DImode
))
3458 else if ((outer_code
== IOR
|| outer_code
== XOR
3459 || outer_code
== PLUS
)
3460 && CONST_OK_FOR_I10 (INTVAL (x
)))
3462 else if (CONST_OK_FOR_I16 (INTVAL (x
)))
3463 *total
= COSTS_N_INSNS (outer_code
!= SET
);
3464 else if (CONST_OK_FOR_I16 (INTVAL (x
) >> 16))
3465 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 1);
3466 else if (CONST_OK_FOR_I16 ((INTVAL (x
) >> 16) >> 16))
3467 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 2);
3469 *total
= COSTS_N_INSNS ((outer_code
!= SET
) + 3);
3472 if (CONST_OK_FOR_I08 (INTVAL (x
)))
3474 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
3475 && CONST_OK_FOR_K08 (INTVAL (x
)))
3477 /* prepare_cmp_insn will force costly constants int registers before
3478 the cbranch[sd]i4 patterns can see them, so preserve potentially
3479 interesting ones not covered by I08 above. */
3480 else if (outer_code
== COMPARE
3481 && ((unsigned HOST_WIDE_INT
) INTVAL (x
)
3482 == (unsigned HOST_WIDE_INT
) 0x7fffffff + 1
3483 || INTVAL (x
) == 0x7fffffff
3484 || INTVAL (x
) == 0x80 || INTVAL (x
) == -0x81))
3491 /* An and with a constant compared against zero is
3492 most likely going to be a TST #imm, R0 instruction.
3493 Notice that this does not catch the zero_extract variants from
3495 if (GET_CODE (XEXP (x
, 0)) == AND
3496 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 0)
3506 /* This is most likely a clips.b or clips.w insn that is being made up
3509 && (GET_CODE (XEXP (x
, 0)) == SMAX
|| GET_CODE (XEXP (x
, 0)) == SMIN
)
3510 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3511 && REG_P (XEXP (XEXP (x
, 0), 0))
3512 && CONST_INT_P (XEXP (x
, 1)))
3514 *total
= COSTS_N_INSNS (1);
3523 if (TARGET_SHMEDIA64
)
3524 *total
= COSTS_N_INSNS (4);
3525 else if (TARGET_SHMEDIA32
)
3526 *total
= COSTS_N_INSNS (2);
3533 *total
= COSTS_N_INSNS (4);
3534 /* prepare_cmp_insn will force costly constants int registers before
3535 the cbranchdi4 pattern can see them, so preserve potentially
3536 interesting ones. */
3537 else if (outer_code
== COMPARE
&& GET_MODE (x
) == DImode
)
3544 /* FIXME: This looks broken. Only the last statement has any effect.
3545 Probably this could be folded with the PARALLEL case? */
3546 if (x
== CONST0_RTX (GET_MODE (x
)))
3548 else if (sh_1el_vec (x
, VOIDmode
))
3549 *total
= outer_code
!= SET
;
3550 if (sh_rep_vec (x
, VOIDmode
))
3551 *total
= ((GET_MODE_UNIT_SIZE (GET_MODE (x
)) + 3) / 4
3552 + (outer_code
!= SET
));
3553 *total
= COSTS_N_INSNS (3) + (outer_code
!= SET
);
3558 *total
= COSTS_N_INSNS (addsubcosts (x
));
3564 *total
= COSTS_N_INSNS (and_xor_ior_costs (x
, code
));
3568 *total
= COSTS_N_INSNS (multcosts (x
));
3573 /* div0s sign comparison. */
3574 if (GET_CODE (XEXP (x
, 0)) == XOR
3575 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3576 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3577 && satisfies_constraint_Z (XEXP (x
, 1)))
3579 *total
= COSTS_N_INSNS (1);
3586 /* div0s sign comparison. */
3587 if (GET_CODE (XEXP (x
, 0)) == XOR
3588 && REG_P ((XEXP (XEXP (x
, 0), 0)))
3589 && REG_P ((XEXP (XEXP (x
, 0), 1)))
3590 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 31)
3592 *total
= COSTS_N_INSNS (1);
3595 /* Fall through to shiftcosts. */
3599 int cost
= shiftcosts (x
);
3602 *total
= COSTS_N_INSNS (cost
);
3610 *total
= COSTS_N_INSNS (20);
3623 /* Determine the size of the fundamental move insn that will be used
3624 for the specified mode. */
3626 mov_insn_size (machine_mode mode
, bool consider_sh2a
)
3628 const int mode_sz
= GET_MODE_SIZE (mode
);
3630 if ((consider_sh2a
&& TARGET_SH2A_DOUBLE
&& mode
== DFmode
)
3631 || (TARGET_FMOVD
&& mode
== DFmode
))
3635 /* The max. available mode for actual move insns is SImode.
3636 Larger accesses will be split into multiple loads/stores. */
3637 const int max_mov_sz
= GET_MODE_SIZE (SImode
);
3638 return mode_sz
>= max_mov_sz
? max_mov_sz
: mode_sz
;
3642 /* Determine the maximum possible displacement for a move insn for the
3645 sh_max_mov_insn_displacement (machine_mode mode
, bool consider_sh2a
)
3647 /* The 4 byte displacement move insns are the same as the 2 byte
3648 versions but take a 12 bit displacement. All we need to do is to
3649 scale the max. displacement value accordingly. */
3650 const int disp_scale
= consider_sh2a
? (4095 / 15) : 1;
3652 /* SH2A supports FPU move insns with 12 bit displacements.
3653 Other variants to do not support any kind of displacements for
3655 if (! consider_sh2a
&& TARGET_FPU_ANY
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3659 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3660 const int mode_sz
= GET_MODE_SIZE (mode
);
3661 int r
= 15 * mov_insn_sz
* disp_scale
;
3663 /* If the mov insn will be split into multiple loads/stores, the
3664 maximum possible displacement is a bit smaller. */
3665 if (mode_sz
> mov_insn_sz
)
3666 r
-= mode_sz
- mov_insn_sz
;
3671 /* Determine the alignment mask for a move insn of the
3674 mov_insn_alignment_mask (machine_mode mode
, bool consider_sh2a
)
3676 const int mov_insn_sz
= mov_insn_size (mode
, consider_sh2a
);
3677 return mov_insn_sz
> 0 ? (mov_insn_sz
- 1) : 0;
3680 /* Return the displacement value of a displacement address. */
3682 sh_disp_addr_displacement (rtx x
)
3684 gcc_assert (satisfies_constraint_Sdd (x
));
3685 return INTVAL (XEXP (XEXP (x
, 0), 1));
3688 /* Compute the cost of an address. */
3690 sh_address_cost (rtx x
, machine_mode mode
,
3691 addr_space_t as ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
3693 /* 'GBR + 0'. Account one more because of R0 restriction. */
3694 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
3697 /* Simple reg, post-inc, pre-dec addressing. */
3698 if (REG_P (x
) || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
3701 /* 'reg + disp' addressing. */
3702 if (GET_CODE (x
) == PLUS
3703 && REG_P (XEXP (x
, 0)) && CONST_INT_P (XEXP (x
, 1)))
3705 /* 'GBR + disp'. Account one more because of R0 restriction. */
3706 if (REGNO (XEXP (x
, 0)) == GBR_REG
3707 && gbr_displacement (XEXP (x
, 1), mode
))
3710 const HOST_WIDE_INT offset
= INTVAL (XEXP (x
, 1));
3715 /* The displacement would fit into a 2 byte move insn.
3716 HImode and QImode loads/stores with displacement put pressure on
3717 R0 which will most likely require another reg copy. Thus account
3718 a higher cost for that. */
3719 if (offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, false))
3720 return (mode
== HImode
|| mode
== QImode
) ? 2 : 1;
3722 /* The displacement would fit into a 4 byte move insn (SH2A). */
3724 && offset
> 0 && offset
<= sh_max_mov_insn_displacement (mode
, true))
3727 /* The displacement is probably out of range and will require extra
3732 /* 'reg + reg' addressing. Account a slightly higher cost because of
3733 increased pressure on R0. */
3734 if (GET_CODE (x
) == PLUS
&& ! CONSTANT_P (XEXP (x
, 1))
3735 && ! TARGET_SHMEDIA
)
3738 /* Not sure what it is - probably expensive. */
3742 /* Code to expand a shift. */
3744 gen_ashift (int type
, int n
, rtx reg
)
3748 /* Negative values here come from the shift_amounts array. */
3758 n_rtx
= GEN_INT (n
);
3759 gcc_assert (satisfies_constraint_P27 (n_rtx
));
3764 emit_insn (gen_ashrsi3_k (reg
, reg
, n_rtx
));
3768 emit_insn (gen_shlr (reg
, reg
));
3770 emit_insn (gen_lshrsi3_k (reg
, reg
, n_rtx
));
3773 emit_insn (gen_ashlsi3_k (reg
, reg
, n_rtx
));
3780 /* Code to expand a HImode shift. */
3782 gen_ashift_hi (int type
, int n
, rtx reg
)
3784 /* Negative values here come from the shift_amounts array. */
3798 /* We don't have HImode right shift operations because using the
3799 ordinary 32 bit shift instructions for that doesn't generate proper
3800 zero/sign extension.
3801 gen_ashift_hi is only called in contexts where we know that the
3802 sign extension works out correctly. */
3805 if (GET_CODE (reg
) == SUBREG
)
3807 offset
= SUBREG_BYTE (reg
);
3808 reg
= SUBREG_REG (reg
);
3810 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
3814 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
3819 /* Output RTL to split a constant shift into its component SH constant
3820 shift instructions. */
3822 gen_shifty_op (int code
, rtx
*operands
)
3824 int value
= INTVAL (operands
[2]);
3827 /* Truncate the shift count in case it is out of bounds. */
3832 if (code
== LSHIFTRT
)
3834 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
3835 emit_insn (gen_movt (operands
[0], get_t_reg_rtx ()));
3838 else if (code
== ASHIFT
)
3840 /* There is a two instruction sequence for 31 bit left shifts,
3841 but it requires r0. */
3842 if (REG_P (operands
[0]) && REGNO (operands
[0]) == 0)
3844 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
3845 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
3850 else if (value
== 0)
3852 /* This can happen even when optimizing, if there were subregs before
3853 reload. Don't output a nop here, as this is never optimized away;
3854 use a no-op move instead. */
3855 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[0]));
3859 max
= ashl_lshr_seq
[value
].insn_count
;
3860 for (i
= 0; i
< max
; i
++)
3861 gen_ashift (code
, ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3864 /* Same as gen_shifty_op, but optimized for values where the topmost bits
3867 gen_shifty_hi_op (int code
, rtx
*operands
)
3869 int value
= INTVAL (operands
[2]);
3871 void (*gen_fun
) (int, int, rtx
);
3873 /* This operation is used by and_shl for SImode values with a few
3874 high bits known to be cleared. */
3878 emit_insn (gen_nop ());
3882 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
3885 max
= ext_ashl_lshr_seq
[value
].insn_count
;
3886 for (i
= 0; i
< max
; i
++)
3887 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3890 /* When shifting right, emit the shifts in reverse order, so that
3891 solitary negative values come first. */
3892 for (i
= ext_ashl_lshr_seq
[value
].insn_count
- 1; i
>= 0; i
--)
3893 gen_fun (code
, ext_ashl_lshr_seq
[value
].amount
[i
], operands
[0]);
3896 /* Output RTL for an arithmetic right shift.
3897 ??? Rewrite to use super-optimizer sequences. */
3899 expand_ashiftrt (rtx
*operands
)
3905 if (TARGET_DYNSHIFT
)
3907 if (!CONST_INT_P (operands
[2]))
3909 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
3910 emit_insn (gen_negsi2 (count
, count
));
3911 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3914 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
3915 > 1 + SH_DYNAMIC_SHIFT_COST
)
3918 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
3919 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
3923 if (!CONST_INT_P (operands
[2]))
3926 value
= INTVAL (operands
[2]) & 31;
3930 /* If we are called from abs expansion, arrange things so that we
3931 we can use a single MT instruction that doesn't clobber the source,
3932 if LICM can hoist out the load of the constant zero. */
3933 if (currently_expanding_to_rtl
)
3935 emit_insn (gen_cmpgtsi_t (force_reg (SImode
, CONST0_RTX (SImode
)),
3937 emit_insn (gen_mov_neg_si_t (operands
[0], get_t_reg_rtx ()));
3940 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
3943 else if (value
>= 16 && value
<= 19)
3945 wrk
= gen_reg_rtx (SImode
);
3946 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
3949 gen_ashift (ASHIFTRT
, 1, wrk
);
3950 emit_move_insn (operands
[0], wrk
);
3953 /* Expand a short sequence inline, longer call a magic routine. */
3954 else if (value
<= 5)
3956 wrk
= gen_reg_rtx (SImode
);
3957 emit_move_insn (wrk
, operands
[1]);
3959 gen_ashift (ASHIFTRT
, 1, wrk
);
3960 emit_move_insn (operands
[0], wrk
);
3964 wrk
= gen_reg_rtx (Pmode
);
3966 /* Load the value into an arg reg and call a helper. */
3967 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
3968 sprintf (func
, "__ashiftrt_r4_%d", value
);
3969 function_symbol (wrk
, func
, SFUNC_STATIC
);
3970 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
3971 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
3975 /* Try to find a good way to implement the combiner pattern
3976 [(set (match_operand:SI 0 "register_operand" "r")
3977 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3978 (match_operand:SI 2 "const_int_operand" "n"))
3979 (match_operand:SI 3 "const_int_operand" "n"))) .
3980 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3981 return 0 for simple right / left or left/right shift combination.
3982 return 1 for a combination of shifts with zero_extend.
3983 return 2 for a combination of shifts with an AND that needs r0.
3984 return 3 for a combination of shifts with an AND that needs an extra
3985 scratch register, when the three highmost bits of the AND mask are clear.
3986 return 4 for a combination of shifts with an AND that needs an extra
3987 scratch register, when any of the three highmost bits of the AND mask
3989 If ATTRP is set, store an initial right shift width in ATTRP[0],
3990 and the instruction length in ATTRP[1] . These values are not valid
3992 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3993 shift_amounts for the last shift value that is to be used before the
3996 shl_and_kind (rtx left_rtx
, rtx mask_rtx
, int *attrp
)
3998 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
3999 int left
= INTVAL (left_rtx
), right
;
4001 int cost
, best_cost
= 10000;
4002 int best_right
= 0, best_len
= 0;
4006 if (left
< 0 || left
> 31)
4008 if (CONST_INT_P (mask_rtx
))
4009 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
4011 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
4012 /* Can this be expressed as a right shift / left shift pair? */
4013 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
4014 right
= exact_log2 (lsb
);
4015 mask2
= ~(mask
+ lsb
- 1);
4016 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
4017 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
4019 best_cost
= ashl_lshr_seq
[right
].insn_count
4020 + ashl_lshr_seq
[right
+ left
].insn_count
;
4021 /* mask has no trailing zeroes <==> ! right */
4022 else if (! right
&& mask2
== ~(lsb2
- 1))
4024 int late_right
= exact_log2 (lsb2
);
4025 best_cost
= ashl_lshr_seq
[left
+ late_right
].insn_count
4026 + ashl_lshr_seq
[late_right
].insn_count
;
4028 /* Try to use zero extend. */
4029 if (mask2
== ~(lsb2
- 1))
4033 for (width
= 8; width
<= 16; width
+= 8)
4035 /* Can we zero-extend right away? */
4036 if (lsb2
== (unsigned HOST_WIDE_INT
) 1 << width
)
4038 cost
= 1 + ext_ashl_lshr_seq
[right
].insn_count
4039 + ext_ashl_lshr_seq
[left
+ right
].insn_count
;
4040 if (cost
< best_cost
)
4051 /* ??? Could try to put zero extend into initial right shift,
4052 or even shift a bit left before the right shift. */
4053 /* Determine value of first part of left shift, to get to the
4054 zero extend cut-off point. */
4055 first
= width
- exact_log2 (lsb2
) + right
;
4056 if (first
>= 0 && right
+ left
- first
>= 0)
4058 cost
= ext_ashl_lshr_seq
[right
].insn_count
4059 + ext_ashl_lshr_seq
[first
].insn_count
+ 1
4060 + ext_ashl_lshr_seq
[right
+ left
- first
].insn_count
;
4062 if (cost
< best_cost
)
4074 /* Try to use r0 AND pattern */
4075 for (i
= 0; i
<= 2; i
++)
4079 if (! CONST_OK_FOR_K08 (mask
>> i
))
4081 cost
= (i
!= 0) + 2 + ext_ashl_lshr_seq
[left
+ i
].insn_count
;
4082 if (cost
< best_cost
)
4087 best_len
= cost
- 1;
4090 /* Try to use a scratch register to hold the AND operand. */
4091 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
) 3 << 30)) == 0;
4092 for (i
= 0; i
<= 2; i
++)
4096 cost
= (i
!= 0) + (CONST_OK_FOR_I08 (mask
>> i
) ? 2 : 3)
4099 : ashl_lshr_seq
)[left
+ i
].insn_count
;
4100 if (cost
< best_cost
)
4105 best_len
= cost
- 1 - ! CONST_OK_FOR_I08 (mask
>> i
);
4111 attrp
[0] = best_right
;
4112 attrp
[1] = best_len
;
4117 /* This is used in length attributes of the unnamed instructions
4118 corresponding to shl_and_kind return values of 1 and 2. */
4120 shl_and_length (rtx insn
)
4122 rtx set_src
, left_rtx
, mask_rtx
;
4125 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4126 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4127 mask_rtx
= XEXP (set_src
, 1);
4128 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4129 return attributes
[1];
4132 /* This is used in length attribute of the and_shl_scratch instruction. */
4134 shl_and_scr_length (rtx insn
)
4136 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4137 int len
= ashl_lshr_seq
[INTVAL (XEXP (set_src
, 1)) & 31].insn_count
;
4138 rtx op
= XEXP (set_src
, 0);
4139 len
+= ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
+ 1;
4140 op
= XEXP (XEXP (op
, 0), 0);
4141 return len
+ ashl_lshr_seq
[INTVAL (XEXP (op
, 1)) & 31].insn_count
;
4144 /* Generate rtl for instructions for which shl_and_kind advised a particular
4145 method of generating them, i.e. returned zero. */
4147 gen_shl_and (rtx dest
, rtx left_rtx
, rtx mask_rtx
, rtx source
)
4150 unsigned HOST_WIDE_INT mask
;
4151 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
4152 int right
, total_shift
;
4153 void (*shift_gen_fun
) (int, rtx
*) = gen_shifty_hi_op
;
4155 right
= attributes
[0];
4156 total_shift
= INTVAL (left_rtx
) + right
;
4157 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
4164 int first
= attributes
[2];
4169 emit_insn ((mask
<< right
) <= 0xff
4170 ? gen_zero_extendqisi2 (dest
,
4171 gen_lowpart (QImode
, source
))
4172 : gen_zero_extendhisi2 (dest
,
4173 gen_lowpart (HImode
, source
)));
4177 emit_insn (gen_movsi (dest
, source
));
4181 operands
[2] = GEN_INT (right
);
4182 gen_shifty_hi_op (LSHIFTRT
, operands
);
4186 operands
[2] = GEN_INT (first
);
4187 gen_shifty_hi_op (ASHIFT
, operands
);
4188 total_shift
-= first
;
4192 emit_insn (mask
<= 0xff
4193 ? gen_zero_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4194 : gen_zero_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4195 if (total_shift
> 0)
4197 operands
[2] = GEN_INT (total_shift
);
4198 gen_shifty_hi_op (ASHIFT
, operands
);
4203 shift_gen_fun
= gen_shifty_op
;
4205 /* If the topmost bit that matters is set, set the topmost bits
4206 that don't matter. This way, we might be able to get a shorter
4208 if (mask
& ((HOST_WIDE_INT
) 1 << (31 - total_shift
)))
4209 mask
|= (HOST_WIDE_INT
) ~0 << (31 - total_shift
);
4211 /* Don't expand fine-grained when combining, because that will
4212 make the pattern fail. */
4213 if (currently_expanding_to_rtl
4214 || reload_in_progress
|| reload_completed
)
4218 /* Cases 3 and 4 should be handled by this split
4219 only while combining */
4220 gcc_assert (kind
<= 2);
4223 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
4226 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
4231 operands
[2] = GEN_INT (total_shift
);
4232 shift_gen_fun (ASHIFT
, operands
);
4239 if (kind
!= 4 && total_shift
< 16)
4241 neg
= -ext_ashl_lshr_seq
[total_shift
].amount
[1];
4243 neg
-= ext_ashl_lshr_seq
[total_shift
].amount
[2];
4247 emit_insn (gen_and_shl_scratch (dest
, source
,
4250 GEN_INT (total_shift
+ neg
),
4252 emit_insn (gen_movsi (dest
, dest
));
4259 /* Try to find a good way to implement the combiner pattern
4260 [(set (match_operand:SI 0 "register_operand" "=r")
4261 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4262 (match_operand:SI 2 "const_int_operand" "n")
4263 (match_operand:SI 3 "const_int_operand" "n")
4265 (clobber (reg:SI T_REG))]
4266 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
4267 return 0 for simple left / right shift combination.
4268 return 1 for left shift / 8 bit sign extend / left shift.
4269 return 2 for left shift / 16 bit sign extend / left shift.
4270 return 3 for left shift / 8 bit sign extend / shift / sign extend.
4271 return 4 for left shift / 16 bit sign extend / shift / sign extend.
4272 return 5 for left shift / 16 bit sign extend / right shift
4273 return 6 for < 8 bit sign extend / left shift.
4274 return 7 for < 8 bit sign extend / left shift / single right shift.
4275 If COSTP is nonzero, assign the calculated cost to *COSTP. */
4277 shl_sext_kind (rtx left_rtx
, rtx size_rtx
, int *costp
)
4279 int left
, size
, insize
, ext
;
4280 int cost
= 0, best_cost
;
4283 left
= INTVAL (left_rtx
);
4284 size
= INTVAL (size_rtx
);
4285 insize
= size
- left
;
4286 gcc_assert (insize
> 0);
4287 /* Default to left / right shift. */
4289 best_cost
= ashl_lshr_seq
[32 - insize
].insn_count
4290 + ashl_lshr_seq
[32 - size
].insn_count
;
4293 /* 16 bit shift / sign extend / 16 bit shift */
4294 cost
= ashl_lshr_seq
[16 - insize
].insn_count
+ 1
4295 + ashl_lshr_seq
[16 - size
].insn_count
;
4296 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
4297 below, by alternative 3 or something even better. */
4298 if (cost
< best_cost
)
4304 /* Try a plain sign extend between two shifts. */
4305 for (ext
= 16; ext
>= insize
; ext
-= 8)
4309 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4310 + ashl_lshr_seq
[size
- ext
].insn_count
;
4311 if (cost
< best_cost
)
4313 kind
= ext
/ (unsigned) 8;
4317 /* Check if we can do a sloppy shift with a final signed shift
4318 restoring the sign. */
4319 if (EXT_SHIFT_SIGNED (size
- ext
))
4320 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
4321 + ext_ashl_lshr_seq
[size
- ext
].insn_count
+ 1;
4322 /* If not, maybe it's still cheaper to do the second shift sloppy,
4323 and do a final sign extend? */
4324 else if (size
<= 16)
4325 cost
= ext_ashl_lshr_seq
[ext
- insize
].insn_count
+ 1
4326 + ext_ashl_lshr_seq
[size
> ext
? size
- ext
: ext
- size
].insn_count
4330 if (cost
< best_cost
)
4332 kind
= ext
/ (unsigned) 8 + 2;
4336 /* Check if we can sign extend in r0 */
4339 cost
= 3 + ashl_lshr_seq
[left
].insn_count
;
4340 if (cost
< best_cost
)
4345 /* Try the same with a final signed shift. */
4348 cost
= 3 + ext_ashl_lshr_seq
[left
+ 1].insn_count
+ 1;
4349 if (cost
< best_cost
)
4356 if (TARGET_DYNSHIFT
)
4358 /* Try to use a dynamic shift. */
4359 cost
= ashl_lshr_seq
[32 - insize
].insn_count
+ 1 + SH_DYNAMIC_SHIFT_COST
;
4360 if (cost
< best_cost
)
4371 /* Function to be used in the length attribute of the instructions
4372 implementing this pattern. */
4374 shl_sext_length (rtx insn
)
4376 rtx set_src
, left_rtx
, size_rtx
;
4379 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
4380 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
4381 size_rtx
= XEXP (set_src
, 1);
4382 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4386 /* Generate rtl for this pattern */
4388 gen_shl_sext (rtx dest
, rtx left_rtx
, rtx size_rtx
, rtx source
)
4391 int left
, size
, insize
, cost
;
4394 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
4395 left
= INTVAL (left_rtx
);
4396 size
= INTVAL (size_rtx
);
4397 insize
= size
- left
;
4405 int ext
= kind
& 1 ? 8 : 16;
4406 int shift2
= size
- ext
;
4408 /* Don't expand fine-grained when combining, because that will
4409 make the pattern fail. */
4410 if (! currently_expanding_to_rtl
4411 && ! reload_in_progress
&& ! reload_completed
)
4413 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4414 emit_insn (gen_movsi (dest
, source
));
4418 emit_insn (gen_movsi (dest
, source
));
4422 operands
[2] = GEN_INT (ext
- insize
);
4423 gen_shifty_hi_op (ASHIFT
, operands
);
4426 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4427 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4432 operands
[2] = GEN_INT (shift2
);
4433 gen_shifty_op (ASHIFT
, operands
);
4440 if (EXT_SHIFT_SIGNED (shift2
))
4442 operands
[2] = GEN_INT (shift2
+ 1);
4443 gen_shifty_op (ASHIFT
, operands
);
4444 operands
[2] = const1_rtx
;
4445 gen_shifty_op (ASHIFTRT
, operands
);
4448 operands
[2] = GEN_INT (shift2
);
4449 gen_shifty_hi_op (ASHIFT
, operands
);
4453 operands
[2] = GEN_INT (-shift2
);
4454 gen_shifty_hi_op (LSHIFTRT
, operands
);
4456 emit_insn (size
<= 8
4457 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
4458 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4465 if (! currently_expanding_to_rtl
4466 && ! reload_in_progress
&& ! reload_completed
)
4467 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4471 operands
[2] = GEN_INT (16 - insize
);
4472 gen_shifty_hi_op (ASHIFT
, operands
);
4473 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
4475 /* Don't use gen_ashrsi3 because it generates new pseudos. */
4477 gen_ashift (ASHIFTRT
, 1, dest
);
4482 /* Don't expand fine-grained when combining, because that will
4483 make the pattern fail. */
4484 if (! currently_expanding_to_rtl
4485 && ! reload_in_progress
&& ! reload_completed
)
4487 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
4488 emit_insn (gen_movsi (dest
, source
));
4491 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
4492 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
4493 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
4495 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
4496 gen_shifty_op (ASHIFT
, operands
);
4498 emit_insn (gen_ashrsi3_k (dest
, dest
, const1_rtx
));
4506 /* Prefix a symbol_ref name with "datalabel". */
4508 gen_datalabel_ref (rtx sym
)
4512 if (GET_CODE (sym
) == LABEL_REF
)
4513 return gen_rtx_CONST (GET_MODE (sym
),
4514 gen_rtx_UNSPEC (GET_MODE (sym
),
4518 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
);
4520 str
= XSTR (sym
, 0);
4521 /* Share all SYMBOL_REF strings with the same value - that is important
4523 str
= IDENTIFIER_POINTER (get_identifier (str
));
4524 XSTR (sym
, 0) = str
;
4530 static alloc_pool label_ref_list_pool
;
4532 typedef struct label_ref_list_d
4534 rtx_code_label
*label
;
4535 struct label_ref_list_d
*next
;
4536 } *label_ref_list_t
;
4538 /* The SH cannot load a large constant into a register, constants have to
4539 come from a pc relative load. The reference of a pc relative load
4540 instruction must be less than 1k in front of the instruction. This
4541 means that we often have to dump a constant inside a function, and
4542 generate code to branch around it.
4544 It is important to minimize this, since the branches will slow things
4545 down and make things bigger.
4547 Worst case code looks like:
4565 We fix this by performing a scan before scheduling, which notices which
4566 instructions need to have their operands fetched from the constant table
4567 and builds the table.
4571 scan, find an instruction which needs a pcrel move. Look forward, find the
4572 last barrier which is within MAX_COUNT bytes of the requirement.
4573 If there isn't one, make one. Process all the instructions between
4574 the find and the barrier.
4576 In the above example, we can tell that L3 is within 1k of L1, so
4577 the first move can be shrunk from the 3 insn+constant sequence into
4578 just 1 insn, and the constant moved to L3 to make:
4589 Then the second move becomes the target for the shortening process. */
4593 rtx value
; /* Value in table. */
4594 rtx_code_label
*label
; /* Label of value. */
4595 label_ref_list_t wend
; /* End of window. */
4596 machine_mode mode
; /* Mode of value. */
4598 /* True if this constant is accessed as part of a post-increment
4599 sequence. Note that HImode constants are never accessed in this way. */
4600 bool part_of_sequence_p
;
4603 /* The maximum number of constants that can fit into one pool, since
4604 constants in the range 0..510 are at least 2 bytes long, and in the
4605 range from there to 1018 at least 4 bytes. */
4607 #define MAX_POOL_SIZE 372
4608 static pool_node pool_vector
[MAX_POOL_SIZE
];
4609 static int pool_size
;
4610 static rtx_code_label
*pool_window_label
;
4611 static int pool_window_last
;
4613 static int max_labelno_before_reorg
;
4615 /* ??? If we need a constant in HImode which is the truncated value of a
4616 constant we need in SImode, we could combine the two entries thus saving
4617 two bytes. Is this common enough to be worth the effort of implementing
4620 /* ??? This stuff should be done at the same time that we shorten branches.
4621 As it is now, we must assume that all branches are the maximum size, and
4622 this causes us to almost always output constant pools sooner than
4625 /* Add a constant to the pool and return its label. */
4626 static rtx_code_label
*
4627 add_constant (rtx x
, machine_mode mode
, rtx last_value
)
4630 rtx_code_label
*lab
, *new_rtx
;
4631 label_ref_list_t ref
, newref
;
4633 /* First see if we've already got it. */
4634 for (i
= 0; i
< pool_size
; i
++)
4636 if (x
->code
== pool_vector
[i
].value
->code
4637 && mode
== pool_vector
[i
].mode
)
4639 if (x
->code
== CODE_LABEL
)
4641 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
4644 if (rtx_equal_p (x
, pool_vector
[i
].value
))
4649 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
4651 new_rtx
= gen_label_rtx ();
4652 LABEL_REFS (new_rtx
) = pool_vector
[i
].label
;
4653 pool_vector
[i
].label
= lab
= new_rtx
;
4655 if (lab
&& pool_window_label
)
4657 newref
= (label_ref_list_t
) pool_alloc (label_ref_list_pool
);
4658 newref
->label
= pool_window_label
;
4659 ref
= pool_vector
[pool_window_last
].wend
;
4661 pool_vector
[pool_window_last
].wend
= newref
;
4664 pool_window_label
= new_rtx
;
4665 pool_window_last
= i
;
4671 /* Need a new one. */
4672 pool_vector
[pool_size
].value
= x
;
4673 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
4676 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
4679 lab
= gen_label_rtx ();
4680 pool_vector
[pool_size
].mode
= mode
;
4681 pool_vector
[pool_size
].label
= lab
;
4682 pool_vector
[pool_size
].wend
= NULL
;
4683 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
4684 if (lab
&& pool_window_label
)
4686 newref
= (label_ref_list_t
) pool_alloc (label_ref_list_pool
);
4687 newref
->label
= pool_window_label
;
4688 ref
= pool_vector
[pool_window_last
].wend
;
4690 pool_vector
[pool_window_last
].wend
= newref
;
4693 pool_window_label
= lab
;
4694 pool_window_last
= pool_size
;
4699 /* Output the literal table. START, if nonzero, is the first instruction
4700 this table is needed for, and also indicates that there is at least one
4701 casesi_worker_2 instruction; We have to emit the operand3 labels from
4702 these insns at a 4-byte aligned position. BARRIER is the barrier
4703 after which we are to place the table. */
4705 dump_table (rtx_insn
*start
, rtx_insn
*barrier
)
4707 rtx_insn
*scan
= barrier
;
4709 bool need_align
= true;
4711 label_ref_list_t ref
;
4712 bool have_df
= false;
4714 /* Do two passes, first time dump out the HI sized constants. */
4716 for (i
= 0; i
< pool_size
; i
++)
4718 pool_node
*p
= &pool_vector
[i
];
4720 if (p
->mode
== HImode
)
4724 scan
= emit_insn_after (gen_align_2 (), scan
);
4727 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4728 scan
= emit_label_after (lab
, scan
);
4729 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
4731 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4734 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4737 else if (p
->mode
== DFmode
)
4745 scan
= emit_insn_after (gen_align_4 (), scan
);
4747 for (; start
!= barrier
; start
= NEXT_INSN (start
))
4748 if (NONJUMP_INSN_P (start
)
4749 && recog_memoized (start
) == CODE_FOR_casesi_worker_2
)
4751 rtx src
= SET_SRC (XVECEXP (PATTERN (start
), 0, 0));
4752 rtx lab
= XEXP (XVECEXP (src
, 0, 3), 0);
4754 scan
= emit_label_after (lab
, scan
);
4757 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
4759 rtx_insn
*align_insn
= NULL
;
4761 scan
= emit_label_after (gen_label_rtx (), scan
);
4762 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4765 for (i
= 0; i
< pool_size
; i
++)
4767 pool_node
*p
= &pool_vector
[i
];
4775 if (align_insn
&& !p
->part_of_sequence_p
)
4777 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4778 emit_label_before (lab
, align_insn
);
4779 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
4781 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4784 emit_insn_before (gen_consttable_window_end (lab
),
4787 delete_insn (align_insn
);
4793 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4794 scan
= emit_label_after (lab
, scan
);
4795 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
4797 need_align
= ! need_align
;
4803 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
4808 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4809 scan
= emit_label_after (lab
, scan
);
4810 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4817 if (p
->mode
!= HImode
)
4819 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4822 scan
= emit_insn_after (gen_consttable_window_end (lab
),
4831 for (i
= 0; i
< pool_size
; i
++)
4833 pool_node
*p
= &pool_vector
[i
];
4844 scan
= emit_label_after (gen_label_rtx (), scan
);
4845 scan
= emit_insn_after (gen_align_4 (), scan
);
4847 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4848 scan
= emit_label_after (lab
, scan
);
4849 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
4857 scan
= emit_label_after (gen_label_rtx (), scan
);
4858 scan
= emit_insn_after (gen_align_4 (), scan
);
4860 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
4861 scan
= emit_label_after (lab
, scan
);
4862 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
4869 if (p
->mode
!= HImode
)
4871 for (ref
= p
->wend
; ref
; ref
= ref
->next
)
4874 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
4879 scan
= emit_insn_after (gen_consttable_end (), scan
);
4880 scan
= emit_barrier_after (scan
);
4882 pool_window_label
= NULL
;
4883 pool_window_last
= 0;
4886 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4888 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4890 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4891 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4892 need to fix it if the input value is CONST_OK_FOR_I08. */
4894 broken_move (rtx_insn
*insn
)
4896 if (NONJUMP_INSN_P (insn
))
4898 rtx pat
= PATTERN (insn
);
4899 if (GET_CODE (pat
) == PARALLEL
)
4900 pat
= XVECEXP (pat
, 0, 0);
4901 if (GET_CODE (pat
) == SET
4902 /* We can load any 8-bit value if we don't care what the high
4903 order bits end up as. */
4904 && GET_MODE (SET_DEST (pat
)) != QImode
4905 && (CONSTANT_P (SET_SRC (pat
))
4906 || (GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
4907 && XINT (SET_SRC (pat
), 1) == UNSPECV_SP_SWITCH_B
)
4908 /* Match mova_const. */
4909 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
4910 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
4911 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
4913 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
4914 && (fp_zero_operand (SET_SRC (pat
))
4915 || fp_one_operand (SET_SRC (pat
)))
4916 /* In general we don't know the current setting of fpscr, so
4918 There is an exception if this was a register-register move
4919 before reload - and hence it was ascertained that we have
4920 single precision setting - and in a post-reload optimization
4921 we changed this to do a constant load. In that case
4922 we don't have an r0 clobber, hence we must use fldi. */
4924 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
4926 && REG_P (SET_DEST (pat
))
4927 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
4929 && GET_MODE (SET_DEST (pat
)) == SImode
4930 && (satisfies_constraint_I20 (SET_SRC (pat
))
4931 || satisfies_constraint_I28 (SET_SRC (pat
))))
4932 && ! satisfies_constraint_I08 (SET_SRC (pat
)))
4939 /* Return true if the specified insn is a mova insn. */
4941 mova_p (rtx_insn
*insn
)
4943 return (NONJUMP_INSN_P (insn
)
4944 && GET_CODE (PATTERN (insn
)) == SET
4945 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
4946 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
4947 /* Don't match mova_const. */
4948 && GET_CODE (MOVA_LABELREF (insn
)) == LABEL_REF
);
4951 /* Fix up a mova from a switch that went out of range. */
4953 fixup_mova (rtx_insn
*mova
)
4955 PUT_MODE (XEXP (MOVA_LABELREF (mova
), 0), QImode
);
4958 SET_SRC (PATTERN (mova
)) = MOVA_LABELREF (mova
);
4959 INSN_CODE (mova
) = -1;
4963 rtx_insn
*worker
= mova
;
4964 rtx_code_label
*lab
= gen_label_rtx ();
4965 rtx wpat
, wpat0
, wpat1
, wsrc
, target
, base
, diff
;
4969 worker
= NEXT_INSN (worker
);
4971 && !LABEL_P (worker
)
4972 && !JUMP_P (worker
));
4973 } while (NOTE_P (worker
)
4974 || recog_memoized (worker
) != CODE_FOR_casesi_worker_1
);
4975 wpat
= PATTERN (worker
);
4976 wpat0
= XVECEXP (wpat
, 0, 0);
4977 wpat1
= XVECEXP (wpat
, 0, 1);
4978 wsrc
= SET_SRC (wpat0
);
4979 PATTERN (worker
) = (gen_casesi_worker_2
4980 (SET_DEST (wpat0
), XVECEXP (wsrc
, 0, 1),
4981 XEXP (XVECEXP (wsrc
, 0, 2), 0), lab
,
4983 INSN_CODE (worker
) = -1;
4984 target
= XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
4985 base
= gen_rtx_LABEL_REF (Pmode
, lab
);
4986 diff
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, target
, base
), UNSPEC_SYMOFF
);
4987 SET_SRC (PATTERN (mova
)) = gen_rtx_CONST (Pmode
, diff
);
4988 INSN_CODE (mova
) = -1;
4992 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4993 *num_mova, and check if the new mova is not nested within the first one.
4994 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4995 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4997 untangle_mova (int *num_mova
, rtx_insn
**first_mova
, rtx_insn
*new_mova
)
4999 int n_addr
= 0; /* Initialization to shut up spurious warning. */
5000 int f_target
, n_target
= 0; /* Likewise. */
5004 /* If NEW_MOVA has no address yet, it will be handled later. */
5005 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova
))
5008 n_addr
= INSN_ADDRESSES (INSN_UID (new_mova
));
5009 n_target
= INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova
), 0)));
5010 if (n_addr
> n_target
|| n_addr
+ 1022 < n_target
)
5012 /* Change the mova into a load.
5013 broken_move will then return true for it. */
5014 fixup_mova (new_mova
);
5020 *first_mova
= new_mova
;
5025 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova
), 0))))
5030 if (f_target
- INSN_ADDRESSES (INSN_UID (*first_mova
))
5031 > n_target
- n_addr
)
5033 fixup_mova (*first_mova
);
5038 fixup_mova (new_mova
);
5043 /* Find the last barrier from insn FROM which is close enough to hold the
5044 constant pool. If we can't find one, then create one near the end of
5047 find_barrier (int num_mova
, rtx_insn
*mova
, rtx_insn
*from
)
5056 int leading_mova
= num_mova
;
5057 rtx_insn
*barrier_before_mova
= NULL
;
5058 rtx_insn
*found_barrier
= NULL
;
5059 rtx_insn
*good_barrier
= NULL
;
5062 rtx_insn
*orig
= from
;
5063 rtx_insn
*last_got
= NULL
;
5064 rtx_insn
*last_symoff
= NULL
;
5066 /* For HImode: range is 510, add 4 because pc counts from address of
5067 second instruction after this one, subtract 2 for the jump instruction
5068 that we may need to emit before the table, subtract 2 for the instruction
5069 that fills the jump delay slot (in very rare cases, reorg will take an
5070 instruction from after the constant pool or will leave the delay slot
5071 empty). This gives 510.
5072 For SImode: range is 1020, add 4 because pc counts from address of
5073 second instruction after this one, subtract 2 in case pc is 2 byte
5074 aligned, subtract 2 for the jump instruction that we may need to emit
5075 before the table, subtract 2 for the instruction that fills the jump
5076 delay slot. This gives 1018. */
5078 /* The branch will always be shortened now that the reference address for
5079 forward branches is the successor address, thus we need no longer make
5080 adjustments to the [sh]i_limit for -O0. */
5085 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
5087 int inc
= get_attr_length (from
);
5090 /* If this is a label that existed at the time of the compute_alignments
5091 call, determine the alignment. N.B. When find_barrier recurses for
5092 an out-of-reach mova, we might see labels at the start of previously
5093 inserted constant tables. */
5095 && CODE_LABEL_NUMBER (from
) <= max_labelno_before_reorg
)
5098 new_align
= 1 << label_to_alignment (from
);
5099 else if (BARRIER_P (prev_nonnote_insn (from
)))
5100 new_align
= 1 << barrier_align (from
);
5105 /* In case we are scanning a constant table because of recursion, check
5106 for explicit alignments. If the table is long, we might be forced
5107 to emit the new table in front of it; the length of the alignment
5108 might be the last straw. */
5109 else if (NONJUMP_INSN_P (from
)
5110 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5111 && XINT (PATTERN (from
), 1) == UNSPECV_ALIGN
)
5112 new_align
= INTVAL (XVECEXP (PATTERN (from
), 0, 0));
5113 /* When we find the end of a constant table, paste the new constant
5114 at the end. That is better than putting it in front because
5115 this way, we don't need extra alignment for adding a 4-byte-aligned
5116 mov(a) label to a 2/4 or 8/4 byte aligned table. */
5117 else if (NONJUMP_INSN_P (from
)
5118 && GET_CODE (PATTERN (from
)) == UNSPEC_VOLATILE
5119 && XINT (PATTERN (from
), 1) == UNSPECV_CONST_END
)
5122 if (BARRIER_P (from
))
5126 found_barrier
= from
;
5128 /* If we are at the end of the function, or in front of an alignment
5129 instruction, we need not insert an extra alignment. We prefer
5130 this kind of barrier. */
5131 if (barrier_align (from
) > 2)
5132 good_barrier
= from
;
5134 /* If we are at the end of a hot/cold block, dump the constants
5136 next
= NEXT_INSN (from
);
5139 && NOTE_KIND (next
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
5143 if (broken_move (from
))
5148 pat
= PATTERN (from
);
5149 if (GET_CODE (pat
) == PARALLEL
)
5150 pat
= XVECEXP (pat
, 0, 0);
5151 src
= SET_SRC (pat
);
5152 dst
= SET_DEST (pat
);
5153 mode
= GET_MODE (dst
);
5155 /* GOT pcrelat setting comes in pair of
5158 instructions. (plus add r0,r12).
5159 Remember if we see one without the other. */
5160 if (GET_CODE (src
) == UNSPEC
&& PIC_ADDR_P (XVECEXP (src
, 0, 0)))
5161 last_got
= last_got
? NULL
: from
;
5162 else if (PIC_ADDR_P (src
))
5163 last_got
= last_got
? NULL
: from
;
5165 /* We must explicitly check the mode, because sometimes the
5166 front end will generate code to load unsigned constants into
5167 HImode targets without properly sign extending them. */
5169 || (mode
== SImode
&& satisfies_constraint_I16 (src
)
5170 && REGNO (dst
) != FPUL_REG
))
5173 /* We put the short constants before the long constants, so
5174 we must count the length of short constants in the range
5175 for the long constants. */
5176 /* ??? This isn't optimal, but is easy to do. */
5181 /* We dump DF/DI constants before SF/SI ones, because
5182 the limit is the same, but the alignment requirements
5183 are higher. We may waste up to 4 additional bytes
5184 for alignment, and the DF/DI constant may have
5185 another SF/SI constant placed before it. */
5186 if (TARGET_SHCOMPACT
5188 && (mode
== DFmode
|| mode
== DImode
))
5193 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
5195 if (found_si
> count_si
)
5196 count_si
= found_si
;
5197 found_si
+= GET_MODE_SIZE (mode
);
5199 si_limit
-= GET_MODE_SIZE (mode
);
5205 switch (untangle_mova (&num_mova
, &mova
, from
))
5210 rtx src
= SET_SRC (PATTERN (from
));
5211 if (GET_CODE (src
) == CONST
5212 && GET_CODE (XEXP (src
, 0)) == UNSPEC
5213 && XINT (XEXP (src
, 0), 1) == UNSPEC_SYMOFF
)
5217 case 0: return find_barrier (0, 0, mova
);
5222 = good_barrier
? good_barrier
: found_barrier
;
5226 if (found_si
> count_si
)
5227 count_si
= found_si
;
5229 else if (JUMP_TABLE_DATA_P (from
)
5230 && GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
)
5232 if ((num_mova
> 1 && GET_MODE (prev_nonnote_insn (from
)) == VOIDmode
)
5234 && (prev_nonnote_insn (from
)
5235 == XEXP (MOVA_LABELREF (mova
), 0))))
5237 if (barrier_align (next_real_insn (from
)) == align_jumps_log
)
5239 /* We have just passed the barrier in front of the
5240 ADDR_DIFF_VEC, which is stored in found_barrier. Since
5241 the ADDR_DIFF_VEC is accessed as data, just like our pool
5242 constants, this is a good opportunity to accommodate what
5243 we have gathered so far.
5244 If we waited any longer, we could end up at a barrier in
5245 front of code, which gives worse cache usage for separated
5246 instruction / data caches. */
5247 good_barrier
= found_barrier
;
5252 rtx body
= PATTERN (from
);
5253 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
5256 /* For the SH1, we generate alignments even after jumps-around-jumps. */
5257 else if (JUMP_P (from
)
5262 /* There is a possibility that a bf is transformed into a bf/s by the
5263 delay slot scheduler. */
5265 && get_attr_type (from
) == TYPE_CBRANCH
5266 && ! sequence_insn_p (from
))
5272 if (new_align
> si_align
)
5274 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
5275 si_align
= new_align
;
5277 count_si
= (count_si
+ new_align
- 1) & -new_align
;
5282 if (new_align
> hi_align
)
5284 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
5285 hi_align
= new_align
;
5287 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
5289 from
= NEXT_INSN (from
);
5296 /* Try as we might, the leading mova is out of range. Change
5297 it into a load (which will become a pcload) and retry. */
5299 return find_barrier (0, 0, mova
);
5303 /* Insert the constant pool table before the mova instruction,
5304 to prevent the mova label reference from going out of range. */
5306 good_barrier
= found_barrier
= barrier_before_mova
;
5312 if (good_barrier
&& next_real_insn (found_barrier
))
5313 found_barrier
= good_barrier
;
5317 /* We didn't find a barrier in time to dump our stuff,
5318 so we'll make one. */
5319 rtx_code_label
*label
= gen_label_rtx ();
5321 /* Don't emit a constant table in the middle of insns for
5322 casesi_worker_2. This is a bit overkill but is enough
5323 because casesi_worker_2 wouldn't appear so frequently. */
5327 /* If we exceeded the range, then we must back up over the last
5328 instruction we looked at. Otherwise, we just need to undo the
5329 NEXT_INSN at the end of the loop. */
5330 if (PREV_INSN (from
) != orig
5331 && (count_hi
> hi_limit
|| count_si
> si_limit
))
5332 from
= PREV_INSN (PREV_INSN (from
));
5334 from
= PREV_INSN (from
);
5336 /* Don't emit a constant table int the middle of global pointer setting,
5337 since that that would move the addressing base GOT into another table.
5338 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
5339 in the pool anyway, so just move up the whole constant pool.
5341 However, avoid doing so when the last single GOT mov is the starting
5342 insn itself. Going past above the start insn would create a negative
5343 offset, causing errors. */
5344 if (last_got
&& last_got
!= orig
)
5345 from
= PREV_INSN (last_got
);
5347 /* Don't insert the constant pool table at the position which
5348 may be the landing pad. */
5351 && find_reg_note (from
, REG_EH_REGION
, NULL_RTX
))
5352 from
= PREV_INSN (from
);
5354 /* Walk back to be just before any jump or label.
5355 Putting it before a label reduces the number of times the branch
5356 around the constant pool table will be hit. Putting it before
5357 a jump makes it more likely that the bra delay slot will be
5359 while (NOTE_P (from
) || JUMP_P (from
)
5361 from
= PREV_INSN (from
);
5363 /* Make sure we do not split between a call and its corresponding
5364 CALL_ARG_LOCATION note. */
5367 rtx_insn
*next
= NEXT_INSN (from
);
5368 if (next
&& NOTE_P (next
)
5369 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
5373 from
= emit_jump_insn_after (gen_jump (label
), from
);
5374 JUMP_LABEL (from
) = label
;
5375 LABEL_NUSES (label
) = 1;
5376 found_barrier
= emit_barrier_after (from
);
5377 emit_label_after (label
, found_barrier
);
5380 return found_barrier
;
5383 /* If the instruction INSN is implemented by a special function, and we can
5384 positively find the register that is used to call the sfunc, and this
5385 register is not used anywhere else in this instruction - except as the
5386 destination of a set, return this register; else, return 0. */
5388 sfunc_uses_reg (rtx_insn
*insn
)
5391 rtx pattern
, part
, reg_part
, reg
;
5393 if (!NONJUMP_INSN_P (insn
))
5395 pattern
= PATTERN (insn
);
5396 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
5399 for (reg_part
= NULL_RTX
, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5401 part
= XVECEXP (pattern
, 0, i
);
5402 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
5407 reg
= XEXP (reg_part
, 0);
5408 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
5410 part
= XVECEXP (pattern
, 0, i
);
5411 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
5413 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
5414 && REG_P (SET_DEST (part
)))
5415 ? SET_SRC (part
) : part
)))
5421 /* See if the only way in which INSN uses REG is by calling it, or by
5422 setting it while calling it. Set *SET to a SET rtx if the register
5425 noncall_uses_reg (rtx reg
, rtx_insn
*insn
, rtx
*set
)
5431 reg2
= sfunc_uses_reg (insn
);
5432 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
5434 pattern
= single_set (insn
);
5436 && REG_P (SET_DEST (pattern
))
5437 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5443 /* We don't use rtx_equal_p because we don't care if the mode is
5445 pattern
= single_set (insn
);
5447 && REG_P (SET_DEST (pattern
))
5448 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
5454 par
= PATTERN (insn
);
5455 if (GET_CODE (par
) == PARALLEL
)
5456 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
5458 part
= XVECEXP (par
, 0, i
);
5459 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
5462 return reg_mentioned_p (reg
, SET_SRC (pattern
));
5468 pattern
= PATTERN (insn
);
5470 if (GET_CODE (pattern
) == PARALLEL
)
5474 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
5475 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
5477 pattern
= XVECEXP (pattern
, 0, 0);
5480 if (GET_CODE (pattern
) == SET
)
5482 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
5484 /* We don't use rtx_equal_p, because we don't care if the
5485 mode is different. */
5486 if (!REG_P (SET_DEST (pattern
))
5487 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
5493 pattern
= SET_SRC (pattern
);
5496 if (GET_CODE (pattern
) != CALL
5497 || !MEM_P (XEXP (pattern
, 0))
5498 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
5504 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5505 general registers. Bits 0..15 mean that the respective registers
5506 are used as inputs in the instruction. Bits 16..31 mean that the
5507 registers 0..15, respectively, are used as outputs, or are clobbered.
5508 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5510 regs_used (rtx x
, int is_dest
)
5518 code
= GET_CODE (x
);
5523 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5524 << (REGNO (x
) + is_dest
));
5528 rtx y
= SUBREG_REG (x
);
5533 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
5535 subreg_regno_offset (REGNO (y
),
5538 GET_MODE (x
)) + is_dest
));
5542 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
5544 /* If there was a return value, it must have been indicated with USE. */
5559 fmt
= GET_RTX_FORMAT (code
);
5561 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5566 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5567 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
5569 else if (fmt
[i
] == 'e')
5570 used
|= regs_used (XEXP (x
, i
), is_dest
);
5575 /* Create an instruction that prevents redirection of a conditional branch
5576 to the destination of the JUMP with address ADDR.
5577 If the branch needs to be implemented as an indirect jump, try to find
5578 a scratch register for it.
5579 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5580 If any preceding insn that doesn't fit into a delay slot is good enough,
5581 pass 1. Pass 2 if a definite blocking insn is needed.
5582 -1 is used internally to avoid deep recursion.
5583 If a blocking instruction is made or recognized, return it. */
5585 gen_block_redirect (rtx_insn
*jump
, int addr
, int need_block
)
5588 rtx_insn
*prev
= prev_nonnote_insn (jump
);
5591 /* First, check if we already have an instruction that satisfies our need. */
5592 if (prev
&& NONJUMP_INSN_P (prev
) && ! prev
->deleted ())
5594 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
5596 if (GET_CODE (PATTERN (prev
)) == USE
5597 || GET_CODE (PATTERN (prev
)) == CLOBBER
5598 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5600 else if ((need_block
&= ~1) < 0)
5602 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
5605 if (GET_CODE (PATTERN (jump
)) == RETURN
)
5609 /* Reorg even does nasty things with return insns that cause branches
5610 to go out of range - see find_end_label and callers. */
5611 return emit_insn_before (gen_block_branch_redirect (const0_rtx
) , jump
);
5613 /* We can't use JUMP_LABEL here because it might be undefined
5614 when not optimizing. */
5615 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
5616 /* If the branch is out of range, try to find a scratch register for it. */
5618 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5622 /* Don't look for the stack pointer as a scratch register,
5623 it would cause trouble if an interrupt occurred. */
5624 unsigned attempt
= 0x7fff, used
;
5625 int jump_left
= flag_expensive_optimizations
+ 1;
5627 /* It is likely that the most recent eligible instruction is wanted for
5628 the delay slot. Therefore, find out which registers it uses, and
5629 try to avoid using them. */
5631 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
5635 if (scan
->deleted ())
5637 code
= GET_CODE (scan
);
5638 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
5641 && GET_CODE (PATTERN (scan
)) != USE
5642 && GET_CODE (PATTERN (scan
)) != CLOBBER
5643 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
5645 attempt
&= ~regs_used (PATTERN (scan
), 0);
5649 for (used
= dead
= 0, scan
= JUMP_LABEL_AS_INSN (jump
);
5650 (scan
= NEXT_INSN (scan
)); )
5654 if (scan
->deleted ())
5656 code
= GET_CODE (scan
);
5659 used
|= regs_used (PATTERN (scan
), 0);
5660 if (code
== CALL_INSN
)
5661 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
5662 dead
|= (used
>> 16) & ~used
;
5668 if (code
== JUMP_INSN
)
5670 if (jump_left
-- && simplejump_p (scan
))
5671 scan
= JUMP_LABEL_AS_INSN (scan
);
5677 /* Mask out the stack pointer again, in case it was
5678 the only 'free' register we have found. */
5681 /* If the immediate destination is still in range, check for possible
5682 threading with a jump beyond the delay slot insn.
5683 Don't check if we are called recursively; the jump has been or will be
5684 checked in a different invocation then. */
5686 else if (optimize
&& need_block
>= 0)
5688 rtx_insn
*next
= next_active_insn (next_active_insn (dest
));
5689 if (next
&& JUMP_P (next
)
5690 && GET_CODE (PATTERN (next
)) == SET
5691 && recog_memoized (next
) == CODE_FOR_jump_compact
)
5693 dest
= JUMP_LABEL (next
);
5695 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
5697 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
5703 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
5705 /* It would be nice if we could convert the jump into an indirect
5706 jump / far branch right now, and thus exposing all constituent
5707 instructions to further optimization. However, reorg uses
5708 simplejump_p to determine if there is an unconditional jump where
5709 it should try to schedule instructions from the target of the
5710 branch; simplejump_p fails for indirect jumps even if they have
5712 rtx_insn
*insn
= emit_insn_before (gen_indirect_jump_scratch
5713 (reg
, GEN_INT (unspec_bbr_uid
++)),
5715 /* ??? We would like this to have the scope of the jump, but that
5716 scope will change when a delay slot insn of an inner scope is added.
5717 Hence, after delay slot scheduling, we'll have to expect
5718 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5721 INSN_LOCATION (insn
) = INSN_LOCATION (jump
);
5722 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
5725 else if (need_block
)
5726 /* We can't use JUMP_LABEL here because it might be undefined
5727 when not optimizing. */
5728 return emit_insn_before (gen_block_branch_redirect
5729 (GEN_INT (unspec_bbr_uid
++)),
5734 #define CONDJUMP_MIN -252
5735 #define CONDJUMP_MAX 262
5738 /* A label (to be placed) in front of the jump
5739 that jumps to our ultimate destination. */
5740 rtx_insn
*near_label
;
5741 /* Where we are going to insert it if we cannot move the jump any farther,
5742 or the jump itself if we have picked up an existing jump. */
5743 rtx_insn
*insert_place
;
5744 /* The ultimate destination. */
5745 rtx_insn
*far_label
;
5746 struct far_branch
*prev
;
5747 /* If the branch has already been created, its address;
5748 else the address of its first prospective user. */
5752 static void gen_far_branch (struct far_branch
*);
5753 enum mdep_reorg_phase_e mdep_reorg_phase
;
5755 gen_far_branch (struct far_branch
*bp
)
5757 rtx_insn
*insn
= bp
->insert_place
;
5759 rtx_code_label
*label
= gen_label_rtx ();
5762 emit_label_after (label
, insn
);
5765 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
5766 LABEL_NUSES (bp
->far_label
)++;
5769 jump
= emit_jump_insn_after (gen_return (), insn
);
5771 /* Emit a barrier so that reorg knows that any following instructions
5772 are not reachable via a fall-through path.
5773 But don't do this when not optimizing, since we wouldn't suppress the
5774 alignment for the barrier then, and could end up with out-of-range
5775 pc-relative loads. */
5777 emit_barrier_after (jump
);
5778 emit_label_after (bp
->near_label
, insn
);
5781 JUMP_LABEL (jump
) = bp
->far_label
;
5784 rtx pat
= PATTERN (jump
);
5785 gcc_assert (ANY_RETURN_P (pat
));
5786 JUMP_LABEL (jump
) = pat
;
5789 ok
= invert_jump (insn
, label
, 1);
5792 /* If we are branching around a jump (rather than a return), prevent
5793 reorg from using an insn from the jump target as the delay slot insn -
5794 when reorg did this, it pessimized code (we rather hide the delay slot)
5795 and it could cause branches to go out of range. */
5798 (gen_stuff_delay_slot
5799 (GEN_INT (unspec_bbr_uid
++),
5800 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
5802 /* Prevent reorg from undoing our splits. */
5803 gen_block_redirect (jump
, bp
->address
+= 2, 2);
5806 /* Fix up ADDR_DIFF_VECs. */
5808 fixup_addr_diff_vecs (rtx_insn
*first
)
5812 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
5814 rtx vec_lab
, pat
, prevpat
, x
, braf_label
;
5817 if (! JUMP_TABLE_DATA_P (insn
)
5818 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
5820 pat
= PATTERN (insn
);
5821 vec_lab
= XEXP (XEXP (pat
, 0), 0);
5823 /* Search the matching casesi_jump_2. */
5824 for (prev
= as_a
<rtx_insn
*> (vec_lab
); ; prev
= PREV_INSN (prev
))
5828 prevpat
= PATTERN (prev
);
5829 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
5831 x
= XVECEXP (prevpat
, 0, 1);
5832 if (GET_CODE (x
) != USE
)
5835 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
5838 /* FIXME: This is a bug in the optimizer, but it seems harmless
5839 to just avoid panicing. */
5843 /* Emit the reference label of the braf where it belongs, right after
5844 the casesi_jump_2 (i.e. braf). */
5845 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
5846 emit_label_after (braf_label
, prev
);
5848 /* Fix up the ADDR_DIF_VEC to be relative
5849 to the reference address of the braf. */
5850 XEXP (XEXP (pat
, 0), 0) = braf_label
;
5854 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5855 a barrier. Return the base 2 logarithm of the desired alignment. */
5857 barrier_align (rtx_insn
*barrier_or_label
)
5861 if (! barrier_or_label
)
5864 if (LABEL_P (barrier_or_label
)
5865 && NEXT_INSN (barrier_or_label
)
5866 && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label
)))
5869 if (BARRIER_P (barrier_or_label
)
5870 && PREV_INSN (barrier_or_label
)
5871 && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label
)))
5873 pat
= PATTERN (PREV_INSN (barrier_or_label
));
5874 /* If this is a very small table, we want to keep the alignment after
5875 the table to the minimum for proper code alignment. */
5876 return ((optimize_size
5877 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
5878 <= (unsigned) 1 << (CACHE_LOG
- 2)))
5879 ? 1 << TARGET_SHMEDIA
: align_jumps_log
);
5882 next
= next_active_insn (barrier_or_label
);
5887 pat
= PATTERN (next
);
5889 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
5890 /* This is a barrier in front of a constant table. */
5896 if (! TARGET_SH2
|| ! optimize
)
5897 return align_jumps_log
;
5899 /* When fixing up pcloads, a constant table might be inserted just before
5900 the basic block that ends with the barrier. Thus, we can't trust the
5901 instruction lengths before that. */
5902 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
5904 /* Check if there is an immediately preceding branch to the insn beyond
5905 the barrier. We must weight the cost of discarding useful information
5906 from the current cache line when executing this branch and there is
5907 an alignment, against that of fetching unneeded insn in front of the
5908 branch target when there is no alignment. */
5910 /* There are two delay_slot cases to consider. One is the simple case
5911 where the preceding branch is to the insn beyond the barrier (simple
5912 delay slot filling), and the other is where the preceding branch has
5913 a delay slot that is a duplicate of the insn after the barrier
5914 (fill_eager_delay_slots) and the branch is to the insn after the insn
5915 after the barrier. */
5918 bool jump_to_next
= false;
5920 /* Skip to the insn before the JUMP_INSN before the barrier under
5922 rtx_insn
*prev
= prev_real_insn (prev_active_insn (barrier_or_label
));
5924 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
5925 credit
>= 0 && prev
&& NONJUMP_INSN_P (prev
);
5926 prev
= prev_real_insn (prev
))
5928 jump_to_next
= false;
5929 if (GET_CODE (PATTERN (prev
)) == USE
5930 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
5932 if (rtx_sequence
*prev_seq
= dyn_cast
<rtx_sequence
*> (PATTERN (prev
)))
5934 prev
= prev_seq
->insn (1);
5935 if (INSN_UID (prev
) == INSN_UID (next
))
5937 /* Delay slot was filled with insn at jump target. */
5938 jump_to_next
= true;
5944 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
5946 credit
-= get_attr_length (prev
);
5948 if (prev
&& jump_to_label_p (prev
))
5952 || next_real_insn (JUMP_LABEL (prev
)) == next
5953 /* If relax_delay_slots() decides NEXT was redundant
5954 with some previous instruction, it will have
5955 redirected PREV's jump to the following insn. */
5956 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
5957 /* There is no upper bound on redundant instructions
5958 that might have been skipped, but we must not put an
5959 alignment where none had been before. */
5960 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
5962 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
5963 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
5964 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
5966 rtx pat
= PATTERN (prev
);
5967 if (GET_CODE (pat
) == PARALLEL
)
5968 pat
= XVECEXP (pat
, 0, 0);
5969 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
5975 return align_jumps_log
;
5978 /* If we are inside a phony loop, almost any kind of label can turn up as the
5979 first one in the loop. Aligning a braf label causes incorrect switch
5980 destination addresses; we can detect braf labels because they are
5981 followed by a BARRIER.
5982 Applying loop alignment to small constant or switch tables is a waste
5983 of space, so we suppress this too. */
5985 sh_loop_align (rtx_insn
*label
)
5987 rtx_insn
*next
= label
;
5989 if (! optimize
|| optimize_size
)
5993 next
= next_nonnote_insn (next
);
5994 while (next
&& LABEL_P (next
));
5998 || recog_memoized (next
) == CODE_FOR_consttable_2
)
6001 return align_loops_log
;
6004 /* Do a final pass over the function, just before delayed branch
6009 rtx_insn
*first
, *insn
, *mova
= NULL
;
6011 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
6012 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
6014 first
= get_insns ();
6015 max_labelno_before_reorg
= max_label_num ();
6017 /* We must split call insns before introducing `mova's. If we're
6018 optimizing, they'll have already been split. Otherwise, make
6019 sure we don't split them too late. */
6021 split_all_insns_noflow ();
6026 /* If relaxing, generate pseudo-ops to associate function calls with
6027 the symbols they call. It does no harm to not generate these
6028 pseudo-ops. However, when we can generate them, it enables the
6029 linker to potentially relax the jsr to a bsr, and eliminate the
6030 register load and, possibly, the constant pool entry. */
6032 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
6035 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
6036 own purposes. This works because none of the remaining passes
6037 need to look at them.
6039 ??? But it may break in the future. We should use a machine
6040 dependent REG_NOTE, or some other approach entirely. */
6041 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6047 while ((note
= find_reg_note (insn
, REG_LABEL_OPERAND
,
6049 remove_note (insn
, note
);
6053 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6055 rtx pattern
, reg
, set
, dies
;
6056 rtx_code_label
*label
;
6057 rtx_insn
*link
, *scan
;
6058 int rescan
= 0, foundinsn
= 0;
6062 pattern
= PATTERN (insn
);
6064 if (GET_CODE (pattern
) == PARALLEL
)
6065 pattern
= XVECEXP (pattern
, 0, 0);
6066 if (GET_CODE (pattern
) == SET
)
6067 pattern
= SET_SRC (pattern
);
6069 if (GET_CODE (pattern
) != CALL
6070 || !MEM_P (XEXP (pattern
, 0)))
6073 reg
= XEXP (XEXP (pattern
, 0), 0);
6077 reg
= sfunc_uses_reg (insn
);
6085 /* Try scanning backward to find where the register is set. */
6087 for (scan
= PREV_INSN (insn
);
6088 scan
&& !LABEL_P (scan
);
6089 scan
= PREV_INSN (scan
))
6091 if (! INSN_P (scan
))
6094 if (! reg_mentioned_p (reg
, scan
))
6097 if (noncall_uses_reg (reg
, scan
, &set
))
6110 /* The register is set at LINK. */
6112 /* We can only optimize the function call if the register is
6113 being set to a symbol. In theory, we could sometimes
6114 optimize calls to a constant location, but the assembler
6115 and linker do not support that at present. */
6116 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
6117 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
6120 /* Scan forward from LINK to the place where REG dies, and
6121 make sure that the only insns which use REG are
6122 themselves function calls. */
6124 /* ??? This doesn't work for call targets that were allocated
6125 by reload, since there may not be a REG_DEAD note for the
6129 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
6133 /* Don't try to trace forward past a CODE_LABEL if we haven't
6134 seen INSN yet. Ordinarily, we will only find the setting insn
6135 if it is in the same basic block. However,
6136 cross-jumping can insert code labels in between the load and
6137 the call, and can result in situations where a single call
6138 insn may have two targets depending on where we came from. */
6140 if (LABEL_P (scan
) && ! foundinsn
)
6143 if (! INSN_P (scan
))
6146 /* Don't try to trace forward past a JUMP. To optimize
6147 safely, we would have to check that all the
6148 instructions at the jump destination did not use REG. */
6153 if (! reg_mentioned_p (reg
, scan
))
6156 if (noncall_uses_reg (reg
, scan
, &scanset
))
6163 && (CALL_P (scan
) || sfunc_uses_reg (scan
)))
6165 /* There is a function call to this register other
6166 than the one we are checking. If we optimize
6167 this call, we need to rescan again below. */
6171 /* ??? We shouldn't have to worry about SCANSET here.
6172 We should just be able to check for a REG_DEAD note
6173 on a function call. However, the REG_DEAD notes are
6174 apparently not dependable around libcalls; c-torture
6175 execute/920501-2 is a test case. If SCANSET is set,
6176 then this insn sets the register, so it must have
6177 died earlier. Unfortunately, this will only handle
6178 the cases in which the register is, in fact, set in a
6181 /* ??? We shouldn't have to use FOUNDINSN here.
6182 This dates back to when we used LOG_LINKS to find
6183 the most recent insn which sets the register. */
6187 || find_reg_note (scan
, REG_DEAD
, reg
)))
6196 /* Either there was a branch, or some insn used REG
6197 other than as a function call address. */
6201 /* Create a code label, and put it in a REG_LABEL_OPERAND note
6202 on the insn which sets the register, and on each call insn
6203 which uses the register. In final_prescan_insn we look for
6204 the REG_LABEL_OPERAND notes, and output the appropriate label
6207 label
= gen_label_rtx ();
6208 add_reg_note (link
, REG_LABEL_OPERAND
, label
);
6209 add_reg_note (insn
, REG_LABEL_OPERAND
, label
);
6217 scan
= NEXT_INSN (scan
);
6220 && reg_mentioned_p (reg
, scan
))
6221 || ((reg2
= sfunc_uses_reg (scan
))
6222 && REGNO (reg2
) == REGNO (reg
))))
6223 add_reg_note (scan
, REG_LABEL_OPERAND
, label
);
6225 while (scan
!= dies
);
6231 fixup_addr_diff_vecs (first
);
6235 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
6236 shorten_branches (first
);
6239 /* Scan the function looking for move instructions which have to be
6240 changed to pc-relative loads and insert the literal tables. */
6241 label_ref_list_pool
= create_alloc_pool ("label references list",
6242 sizeof (struct label_ref_list_d
),
6244 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
6245 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
6249 /* ??? basic block reordering can move a switch table dispatch
6250 below the switch table. Check if that has happened.
6251 We only have the addresses available when optimizing; but then,
6252 this check shouldn't be needed when not optimizing. */
6253 if (!untangle_mova (&num_mova
, &mova
, insn
))
6259 else if (JUMP_TABLE_DATA_P (insn
)
6260 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
6262 /* ??? loop invariant motion can also move a mova out of a
6263 loop. Since loop does this code motion anyway, maybe we
6264 should wrap UNSPEC_MOVA into a CONST, so that reload can
6267 && GET_MODE (prev_nonnote_insn (insn
)) == VOIDmode
)
6268 || (prev_nonnote_insn (insn
)
6269 == XEXP (MOVA_LABELREF (mova
), 0))))
6276 /* Some code might have been inserted between the mova and
6277 its ADDR_DIFF_VEC. Check if the mova is still in range. */
6278 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
6279 total
+= get_attr_length (scan
);
6281 /* range of mova is 1020, add 4 because pc counts from address of
6282 second instruction after this one, subtract 2 in case pc is 2
6283 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
6284 cancels out with alignment effects of the mova itself. */
6287 /* Change the mova into a load, and restart scanning
6288 there. broken_move will then return true for mova. */
6293 if (broken_move (insn
)
6294 || (NONJUMP_INSN_P (insn
)
6295 && recog_memoized (insn
) == CODE_FOR_casesi_worker_2
))
6298 /* Scan ahead looking for a barrier to stick the constant table
6300 rtx_insn
*barrier
= find_barrier (num_mova
, mova
, insn
);
6301 rtx_insn
*last_float_move
= NULL
;
6302 rtx last_float
= 0, *last_float_addr
= NULL
;
6303 int need_aligned_label
= 0;
6305 if (num_mova
&& ! mova_p (mova
))
6307 /* find_barrier had to change the first mova into a
6308 pcload; thus, we have to start with this new pcload. */
6312 /* Now find all the moves between the points and modify them. */
6313 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
6317 if (NONJUMP_INSN_P (scan
)
6318 && recog_memoized (scan
) == CODE_FOR_casesi_worker_2
)
6319 need_aligned_label
= 1;
6320 if (broken_move (scan
))
6322 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
6328 if (GET_CODE (pat
) == PARALLEL
)
6329 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
6330 src
= SET_SRC (pat
);
6331 dst
= SET_DEST (pat
);
6332 mode
= GET_MODE (dst
);
6334 if (mode
== SImode
&& satisfies_constraint_I16 (src
)
6335 && REGNO (dst
) != FPUL_REG
)
6340 while (GET_CODE (dst
) == SUBREG
)
6342 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
6343 GET_MODE (SUBREG_REG (dst
)),
6346 dst
= SUBREG_REG (dst
);
6348 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
6350 if (REG_P (dst
) && FP_ANY_REGISTER_P (REGNO (dst
)))
6352 /* This must be an insn that clobbers r0. */
6353 rtx
*clobberp
= &XVECEXP (PATTERN (scan
), 0,
6354 XVECLEN (PATTERN (scan
), 0)
6356 rtx clobber
= *clobberp
;
6358 gcc_assert (GET_CODE (clobber
) == CLOBBER
6359 && rtx_equal_p (XEXP (clobber
, 0), r0_rtx
));
6362 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
6366 && GET_MODE_SIZE (mode
) != 4
6367 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
6369 lab
= add_constant (src
, mode
, last_float
);
6371 emit_insn_before (gen_mova (lab
), scan
);
6374 /* There will be a REG_UNUSED note for r0 on
6375 LAST_FLOAT_MOVE; we have to change it to REG_INC,
6376 lest reorg:mark_target_live_regs will not
6377 consider r0 to be used, and we end up with delay
6378 slot insn in front of SCAN that clobbers r0. */
6380 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
6382 /* If we are not optimizing, then there may not be
6385 PUT_REG_NOTE_KIND (note
, REG_INC
);
6387 *last_float_addr
= r0_inc_rtx
;
6389 last_float_move
= scan
;
6391 newsrc
= gen_const_mem (mode
,
6392 (((TARGET_SH4
&& ! TARGET_FMOVD
)
6393 || REGNO (dst
) == FPUL_REG
)
6396 last_float_addr
= &XEXP (newsrc
, 0);
6398 /* Remove the clobber of r0. */
6399 *clobberp
= gen_rtx_CLOBBER (GET_MODE (clobber
),
6400 gen_rtx_SCRATCH (Pmode
));
6402 /* This is a mova needing a label. Create it. */
6403 else if (GET_CODE (src
) == UNSPEC
6404 && XINT (src
, 1) == UNSPEC_MOVA
6405 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
6407 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
6408 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6409 newsrc
= gen_rtx_UNSPEC (SImode
,
6410 gen_rtvec (1, newsrc
),
6413 else if (GET_CODE (src
) == UNSPEC_VOLATILE
6414 && XINT (src
, 1) == UNSPECV_SP_SWITCH_B
)
6416 newsrc
= XVECEXP (src
, 0, 0);
6417 XVECEXP (src
, 0, 0) = gen_const_mem (mode
, newsrc
);
6418 INSN_CODE (scan
) = -1;
6423 lab
= add_constant (src
, mode
, 0);
6424 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
6425 newsrc
= gen_const_mem (mode
, newsrc
);
6427 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
6428 INSN_CODE (scan
) = -1;
6431 dump_table (need_aligned_label
? insn
: 0, barrier
);
6435 free_alloc_pool (label_ref_list_pool
);
6436 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6437 PUT_MODE (insn
, VOIDmode
);
6439 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
6440 INSN_ADDRESSES_FREE ();
6441 split_branches (first
);
6443 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
6444 also has an effect on the register that holds the address of the sfunc.
6445 Insert an extra dummy insn in front of each sfunc that pretends to
6446 use this register. */
6447 if (flag_delayed_branch
)
6449 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6451 rtx reg
= sfunc_uses_reg (insn
);
6455 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
6458 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
6461 /* Return the UID of the insn that follows the specified label. */
6463 get_dest_uid (rtx label
, int max_uid
)
6465 rtx_insn
*dest
= next_real_insn (label
);
6468 /* This can happen for an undefined label. */
6470 dest_uid
= INSN_UID (dest
);
6471 /* If this is a newly created branch redirection blocking instruction,
6472 we cannot index the branch_uid or insn_addresses arrays with its
6473 uid. But then, we won't need to, because the actual destination is
6474 the following branch. */
6475 while (dest_uid
>= max_uid
)
6477 dest
= NEXT_INSN (dest
);
6478 dest_uid
= INSN_UID (dest
);
6480 if (JUMP_P (dest
) && GET_CODE (PATTERN (dest
)) == RETURN
)
6485 /* Split condbranches that are out of range. Also add clobbers for
6486 scratch registers that are needed in far jumps.
6487 We do this before delay slot scheduling, so that it can take our
6488 newly created instructions into account. It also allows us to
6489 find branches with common targets more easily. */
6491 split_branches (rtx_insn
*first
)
6494 struct far_branch
**uid_branch
, *far_branch_list
= 0;
6495 int max_uid
= get_max_uid ();
6498 /* Find out which branches are out of range. */
6499 shorten_branches (first
);
6501 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
6502 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
6504 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
6505 if (! INSN_P (insn
))
6507 else if (insn
->deleted ())
6509 /* Shorten_branches would split this instruction again,
6510 so transform it into a note. */
6511 SET_INSN_DELETED (insn
);
6513 else if (JUMP_P (insn
))
6515 enum attr_type type
= get_attr_type (insn
);
6516 if (type
== TYPE_CBRANCH
)
6518 rtx_insn
*next
, *beyond
;
6520 if (get_attr_length (insn
) > 4)
6522 rtx src
= SET_SRC (PATTERN (insn
));
6523 rtx olabel
= XEXP (XEXP (src
, 1), 0);
6524 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6525 rtx_insn
*label
= 0;
6526 int dest_uid
= get_dest_uid (olabel
, max_uid
);
6527 struct far_branch
*bp
= uid_branch
[dest_uid
];
6529 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6530 the label if the LABEL_NUSES count drops to zero. There is
6531 always a jump_optimize pass that sets these values, but it
6532 proceeds to delete unreferenced code, and then if not
6533 optimizing, to un-delete the deleted instructions, thus
6534 leaving labels with too low uses counts. */
6537 JUMP_LABEL (insn
) = olabel
;
6538 LABEL_NUSES (olabel
)++;
6542 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6543 uid_branch
[dest_uid
] = bp
;
6544 bp
->prev
= far_branch_list
;
6545 far_branch_list
= bp
;
6546 bp
->far_label
= as_a
<rtx_insn
*> (
6547 XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6549 LABEL_NUSES (bp
->far_label
)++;
6553 label
= bp
->near_label
;
6554 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
6556 rtx_insn
*block
= bp
->insert_place
;
6558 if (GET_CODE (PATTERN (block
)) == RETURN
)
6559 block
= PREV_INSN (block
);
6561 block
= gen_block_redirect (block
,
6563 label
= emit_label_after (gen_label_rtx (),
6565 bp
->near_label
= label
;
6567 else if (label
&& ! NEXT_INSN (label
))
6569 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
6570 bp
->insert_place
= insn
;
6572 gen_far_branch (bp
);
6576 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
6578 bp
->near_label
= label
= gen_label_rtx ();
6579 bp
->insert_place
= insn
;
6582 ok
= redirect_jump (insn
, label
, 0);
6587 /* get_attr_length (insn) == 2 */
6588 /* Check if we have a pattern where reorg wants to redirect
6589 the branch to a label from an unconditional branch that
6591 /* We can't use JUMP_LABEL here because it might be undefined
6592 when not optimizing. */
6593 /* A syntax error might cause beyond to be NULL_RTX. */
6595 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
6600 || ((beyond
= next_active_insn (beyond
))
6601 && JUMP_P (beyond
)))
6602 && GET_CODE (PATTERN (beyond
)) == SET
6603 && recog_memoized (beyond
) == CODE_FOR_jump_compact
6605 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
6606 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6608 gen_block_redirect (beyond
,
6609 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
6612 next
= next_active_insn (insn
);
6616 || ((next
= next_active_insn (next
))
6618 && GET_CODE (PATTERN (next
)) == SET
6619 && recog_memoized (next
) == CODE_FOR_jump_compact
6621 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
6622 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
6624 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
6626 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
6628 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
6629 rtx_insn
*far_label
= 0;
6631 struct far_branch
*bp
;
6633 if (type
== TYPE_JUMP
)
6635 far_label
= as_a
<rtx_insn
*> (
6636 XEXP (SET_SRC (PATTERN (insn
)), 0));
6637 dest_uid
= get_dest_uid (far_label
, max_uid
);
6640 /* Parse errors can lead to labels outside
6642 if (! NEXT_INSN (far_label
))
6647 JUMP_LABEL (insn
) = far_label
;
6648 LABEL_NUSES (far_label
)++;
6650 redirect_jump (insn
, ret_rtx
, 1);
6654 bp
= uid_branch
[dest_uid
];
6657 bp
= (struct far_branch
*) alloca (sizeof *bp
);
6658 uid_branch
[dest_uid
] = bp
;
6659 bp
->prev
= far_branch_list
;
6660 far_branch_list
= bp
;
6662 bp
->far_label
= far_label
;
6664 LABEL_NUSES (far_label
)++;
6666 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
6667 if (addr
- bp
->address
<= CONDJUMP_MAX
)
6668 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
6671 gen_far_branch (bp
);
6677 bp
->insert_place
= insn
;
6679 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
6681 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
6684 /* Generate all pending far branches,
6685 and free our references to the far labels. */
6686 while (far_branch_list
)
6688 if (far_branch_list
->near_label
6689 && ! NEXT_INSN (far_branch_list
->near_label
))
6690 gen_far_branch (far_branch_list
);
6692 && far_branch_list
->far_label
6693 && ! --LABEL_NUSES (far_branch_list
->far_label
))
6694 delete_insn (far_branch_list
->far_label
);
6695 far_branch_list
= far_branch_list
->prev
;
6698 /* Instruction length information is no longer valid due to the new
6699 instructions that have been generated. */
6700 init_insn_lengths ();
6703 /* Dump out instruction addresses, which is useful for debugging the
6704 constant pool table stuff.
6706 If relaxing, output the label and pseudo-ops used to link together
6707 calls and the instruction which set the registers.
6709 ??? The addresses printed by this routine for insns are nonsense for
6710 insns which are inside of a sequence where none of the inner insns have
6711 variable length. This is because the second pass of shorten_branches
6712 does not bother to update them. */
6714 final_prescan_insn (rtx_insn
*insn
, rtx
*opvec ATTRIBUTE_UNUSED
,
6715 int noperands ATTRIBUTE_UNUSED
)
6717 if (TARGET_DUMPISIZE
)
6718 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
6724 note
= find_reg_note (insn
, REG_LABEL_OPERAND
, NULL_RTX
);
6729 pattern
= PATTERN (insn
);
6730 if (GET_CODE (pattern
) == PARALLEL
)
6731 pattern
= XVECEXP (pattern
, 0, 0);
6732 switch (GET_CODE (pattern
))
6735 if (GET_CODE (SET_SRC (pattern
)) != CALL
6736 && get_attr_type (insn
) != TYPE_SFUNC
)
6738 targetm
.asm_out
.internal_label
6739 (asm_out_file
, "L", CODE_LABEL_NUMBER (XEXP (note
, 0)));
6742 /* else FALLTHROUGH */
6744 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
6745 CODE_LABEL_NUMBER (XEXP (note
, 0)));
6755 /* Dump out any constants accumulated in the final pass. These will
6758 output_jump_label_table (void)
6764 fprintf (asm_out_file
, "\t.align 2\n");
6765 for (i
= 0; i
< pool_size
; i
++)
6767 pool_node
*p
= &pool_vector
[i
];
6769 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
6770 CODE_LABEL_NUMBER (p
->label
));
6771 output_asm_insn (".long %O0", &p
->value
);
6779 /* A full frame looks like:
6783 [ if current_function_anonymous_args
6796 local-0 <- fp points here.
6798 Number of bytes pushed for anonymous args, used to pass information
6799 between expand_prologue and expand_epilogue.
6801 Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6802 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6803 for an epilogue and a negative value means that it's for a sibcall
6804 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6805 all the registers that are about to be restored, and hence dead. */
6807 output_stack_adjust (int size
, rtx reg
, int epilogue_p
,
6808 HARD_REG_SET
*live_regs_mask
, bool frame_p
)
6810 rtx_insn
*(*emit_fn
) (rtx
) = frame_p
? &frame_insn
: &emit_insn
;
6813 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6815 /* This test is bogus, as output_stack_adjust is used to re-align the
6818 gcc_assert (!(size
% align
));
6821 if (CONST_OK_FOR_ADD (size
))
6822 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
6823 /* Try to do it with two partial adjustments; however, we must make
6824 sure that the stack is properly aligned at all times, in case
6825 an interrupt occurs between the two partial adjustments. */
6826 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
6827 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
6829 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
6830 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
6836 int temp
= epilogue_p
? 7 : (TARGET_SH5
? 0 : 1);
6839 /* If TEMP is invalid, we could temporarily save a general
6840 register to MACL. However, there is currently no need
6841 to handle this case, so just die when we see it. */
6843 || current_function_interrupt
6844 || ! call_really_used_regs
[temp
] || fixed_regs
[temp
])
6846 if (temp
< 0 && ! current_function_interrupt
6847 && (TARGET_SHMEDIA
|| epilogue_p
>= 0))
6850 COPY_HARD_REG_SET (temps
, call_used_reg_set
);
6851 AND_COMPL_HARD_REG_SET (temps
, call_fixed_reg_set
);
6855 if (crtl
->return_rtx
)
6858 mode
= GET_MODE (crtl
->return_rtx
);
6859 if (BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
)
6860 nreg
= HARD_REGNO_NREGS (FIRST_RET_REG
, mode
);
6862 for (i
= 0; i
< nreg
; i
++)
6863 CLEAR_HARD_REG_BIT (temps
, FIRST_RET_REG
+ i
);
6864 if (crtl
->calls_eh_return
)
6866 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_STACKADJ_REGNO
);
6867 for (i
= 0; i
<= 3; i
++)
6868 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_DATA_REGNO (i
));
6871 if (TARGET_SHMEDIA
&& epilogue_p
< 0)
6872 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
6873 CLEAR_HARD_REG_BIT (temps
, i
);
6874 if (epilogue_p
<= 0)
6876 for (i
= FIRST_PARM_REG
;
6877 i
< FIRST_PARM_REG
+ NPARM_REGS (SImode
); i
++)
6878 CLEAR_HARD_REG_BIT (temps
, i
);
6879 if (cfun
->static_chain_decl
!= NULL
)
6880 CLEAR_HARD_REG_BIT (temps
, STATIC_CHAIN_REGNUM
);
6882 temp
= scavenge_reg (&temps
);
6884 if (temp
< 0 && live_regs_mask
)
6888 COPY_HARD_REG_SET (temps
, *live_regs_mask
);
6889 CLEAR_HARD_REG_BIT (temps
, REGNO (reg
));
6890 temp
= scavenge_reg (&temps
);
6894 rtx adj_reg
, tmp_reg
, mem
;
6896 /* If we reached here, the most likely case is the (sibcall)
6897 epilogue for non SHmedia. Put a special push/pop sequence
6898 for such case as the last resort. This looks lengthy but
6899 would not be problem because it seems to be very
6902 gcc_assert (!TARGET_SHMEDIA
&& epilogue_p
);
6905 /* ??? There is still the slight possibility that r4 or
6906 r5 have been reserved as fixed registers or assigned
6907 as global registers, and they change during an
6908 interrupt. There are possible ways to handle this:
6910 - If we are adjusting the frame pointer (r14), we can do
6911 with a single temp register and an ordinary push / pop
6913 - Grab any call-used or call-saved registers (i.e. not
6914 fixed or globals) for the temps we need. We might
6915 also grab r14 if we are adjusting the stack pointer.
6916 If we can't find enough available registers, issue
6917 a diagnostic and die - the user must have reserved
6918 way too many registers.
6919 But since all this is rather unlikely to happen and
6920 would require extra testing, we just die if r4 / r5
6921 are not available. */
6922 gcc_assert (!fixed_regs
[4] && !fixed_regs
[5]
6923 && !global_regs
[4] && !global_regs
[5]);
6925 adj_reg
= gen_rtx_REG (GET_MODE (reg
), 4);
6926 tmp_reg
= gen_rtx_REG (GET_MODE (reg
), 5);
6927 emit_move_insn (gen_tmp_stack_mem (Pmode
, reg
), adj_reg
);
6928 emit_insn (GEN_MOV (adj_reg
, GEN_INT (size
)));
6929 emit_insn (GEN_ADD3 (adj_reg
, adj_reg
, reg
));
6930 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6931 emit_move_insn (mem
, tmp_reg
);
6932 emit_move_insn (tmp_reg
, gen_tmp_stack_mem (Pmode
, reg
));
6933 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
, adj_reg
));
6934 emit_move_insn (mem
, tmp_reg
);
6935 emit_move_insn (reg
, adj_reg
);
6936 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6937 emit_move_insn (adj_reg
, mem
);
6938 mem
= gen_tmp_stack_mem (Pmode
, gen_rtx_POST_INC (Pmode
, reg
));
6939 emit_move_insn (tmp_reg
, mem
);
6940 /* Tell flow the insns that pop r4/r5 aren't dead. */
6945 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
6947 /* If SIZE is negative, subtract the positive value.
6948 This sometimes allows a constant pool entry to be shared
6949 between prologue and epilogue code. */
6952 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
6953 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
6957 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
6958 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
6960 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6961 gen_rtx_SET (VOIDmode
, reg
,
6962 gen_rtx_PLUS (SImode
, reg
,
6968 /* Emit the specified insn and mark it as frame related.
6969 FIXME: Rename this to emit_frame_insn. */
6973 rtx_insn
*insn
= emit_insn (x
);
6974 RTX_FRAME_RELATED_P (insn
) = 1;
6978 /* Output RTL to push register RN onto the stack. */
6984 x
= gen_push_fpul ();
6985 else if (rn
== FPSCR_REG
)
6986 x
= gen_push_fpscr ();
6987 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
6988 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
6990 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
6992 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
6994 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
6995 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
6997 x
= gen_push (gen_rtx_REG (SImode
, rn
));
7000 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
7004 /* Output RTL to pop register RN from the stack. */
7010 x
= gen_pop_fpul ();
7011 else if (rn
== FPSCR_REG
)
7012 x
= gen_pop_fpscr ();
7013 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
7014 && ! TARGET_FPU_SINGLE
&& FP_OR_XD_REGISTER_P (rn
))
7016 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
7018 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
7020 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
7021 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
7023 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
7027 sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7028 reg
= copy_rtx (GET_CODE (PATTERN (x
)) == PARALLEL
7029 ? SET_DEST (XVECEXP (PATTERN (x
), 0, 0))
7030 : SET_DEST (PATTERN (x
)));
7031 add_reg_note (x
, REG_CFA_RESTORE
, reg
);
7032 add_reg_note (x
, REG_CFA_ADJUST_CFA
,
7033 gen_rtx_SET (SImode
, sp_reg
,
7034 plus_constant (SImode
, sp_reg
,
7035 GET_MODE_SIZE (GET_MODE (reg
)))));
7036 add_reg_note (x
, REG_INC
, gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
));
7037 RTX_FRAME_RELATED_P (x
) = 1;
7040 /* Generate code to push the regs specified in the mask. */
7042 push_regs (HARD_REG_SET
*mask
, int interrupt_handler
)
7044 int i
= interrupt_handler
? LAST_BANKED_REG
+ 1 : 0;
7047 /* Push PR last; this gives better latencies after the prologue, and
7048 candidates for the return delay slot when there are no general
7049 registers pushed. */
7050 for (; i
< FIRST_PSEUDO_REGISTER
; i
++)
7052 /* If this is an interrupt handler, and the SZ bit varies,
7053 and we have to push any floating point register, we need
7054 to switch to the correct precision first. */
7055 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
7056 && hard_reg_set_intersect_p (*mask
, reg_class_contents
[DF_REGS
]))
7058 HARD_REG_SET unsaved
;
7061 COMPL_HARD_REG_SET (unsaved
, *mask
);
7062 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), unsaved
);
7066 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
7067 && TEST_HARD_REG_BIT (*mask
, i
))
7069 /* If the ISR has RESBANK attribute assigned, don't push any of
7070 the following registers - R0-R14, MACH, MACL and GBR. */
7071 if (! (sh_cfun_resbank_handler_p ()
7072 && ((i
>= FIRST_GENERAL_REG
&& i
< LAST_GENERAL_REG
)
7080 /* Push banked registers last to improve delay slot opportunities. */
7081 if (interrupt_handler
)
7083 bool use_movml
= false;
7087 unsigned int count
= 0;
7089 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7090 if (TEST_HARD_REG_BIT (*mask
, i
))
7095 /* Use movml when all banked registers are pushed. */
7096 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
7100 if (sh_cfun_resbank_handler_p ())
7104 rtx x
, mem
, reg
, set
;
7105 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
7107 /* We must avoid scheduling multiple store insn with another
7109 emit_insn (gen_blockage ());
7110 x
= gen_movml_push_banked (sp_reg
);
7112 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7114 mem
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp_reg
, i
* 4));
7115 reg
= gen_rtx_REG (SImode
, i
);
7116 add_reg_note (x
, REG_CFA_OFFSET
, gen_rtx_SET (SImode
, mem
, reg
));
7119 set
= gen_rtx_SET (SImode
, sp_reg
,
7120 plus_constant (Pmode
, sp_reg
, - 32));
7121 add_reg_note (x
, REG_CFA_ADJUST_CFA
, set
);
7122 emit_insn (gen_blockage ());
7125 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
7126 if (TEST_HARD_REG_BIT (*mask
, i
))
7130 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
7131 if (TEST_HARD_REG_BIT (*mask
, PR_REG
) && !sh_cfun_resbank_handler_p ())
7135 /* Calculate how much extra space is needed to save all callee-saved
7137 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7139 shmedia_target_regs_stack_space (HARD_REG_SET
*live_regs_mask
)
7142 int stack_space
= 0;
7143 int interrupt_handler
= sh_cfun_interrupt_handler_p ();
7145 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
7146 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
7147 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
7148 /* Leave space to save this target register on the stack,
7149 in case target register allocation wants to use it. */
7150 stack_space
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7154 /* Decide whether we should reserve space for callee-save target registers,
7155 in case target register allocation wants to use them. REGS_SAVED is
7156 the space, in bytes, that is already required for register saves.
7157 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7159 shmedia_reserve_space_for_target_registers_p (int regs_saved
,
7160 HARD_REG_SET
*live_regs_mask
)
7164 return shmedia_target_regs_stack_space (live_regs_mask
) <= regs_saved
;
7167 /* Decide how much space to reserve for callee-save target registers
7168 in case target register allocation wants to use them.
7169 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
7171 shmedia_target_regs_stack_adjust (HARD_REG_SET
*live_regs_mask
)
7173 if (shmedia_space_reserved_for_target_registers
)
7174 return shmedia_target_regs_stack_space (live_regs_mask
);
7179 /* Work out the registers which need to be saved, both as a mask and a
7180 count of saved words. Return the count.
7182 If doing a pragma interrupt function, then push all regs used by the
7183 function, and if we call another function (we can tell by looking at PR),
7184 make sure that all the regs it clobbers are safe too. */
7186 calc_live_regs (HARD_REG_SET
*live_regs_mask
)
7191 bool interrupt_or_trapa_handler
, trapa_handler
, interrupt_handler
;
7192 bool nosave_low_regs
;
7193 int pr_live
, has_call
;
7195 attrs
= DECL_ATTRIBUTES (current_function_decl
);
7196 interrupt_or_trapa_handler
= sh_cfun_interrupt_handler_p ();
7197 trapa_handler
= lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
;
7198 interrupt_handler
= interrupt_or_trapa_handler
&& ! trapa_handler
;
7199 nosave_low_regs
= lookup_attribute ("nosave_low_regs", attrs
) != NULL_TREE
;
7201 CLEAR_HARD_REG_SET (*live_regs_mask
);
7202 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
&& interrupt_handler
7203 && df_regs_ever_live_p (FPSCR_REG
))
7204 target_flags
&= ~MASK_FPU_SINGLE
;
7205 /* If we can save a lot of saves by switching to double mode, do that. */
7206 else if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && TARGET_FMOVD
7207 && TARGET_FPU_SINGLE
)
7208 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
7209 if (df_regs_ever_live_p (reg
) && df_regs_ever_live_p (reg
+1)
7210 && (! call_really_used_regs
[reg
]
7211 || interrupt_handler
)
7214 target_flags
&= ~MASK_FPU_SINGLE
;
7217 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
7218 knows how to use it. That means the pseudo originally allocated for
7219 the initial value can become the PR_MEDIA_REG hard register, as seen for
7220 execute/20010122-1.c:test9. */
7222 /* ??? this function is called from initial_elimination_offset, hence we
7223 can't use the result of sh_media_register_for_return here. */
7224 pr_live
= sh_pr_n_sets ();
7227 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
7228 pr_live
= (pr_initial
7229 ? (!REG_P (pr_initial
)
7230 || REGNO (pr_initial
) != (PR_REG
))
7231 : df_regs_ever_live_p (PR_REG
));
7232 /* For Shcompact, if not optimizing, we end up with a memory reference
7233 using the return address pointer for __builtin_return_address even
7234 though there is no actual need to put the PR register on the stack. */
7235 pr_live
|= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM
);
7237 /* Force PR to be live if the prologue has to call the SHmedia
7238 argument decoder or register saver. */
7239 if (TARGET_SHCOMPACT
7240 && ((crtl
->args
.info
.call_cookie
7241 & ~ CALL_COOKIE_RET_TRAMP (1))
7242 || crtl
->saves_all_registers
))
7244 has_call
= TARGET_SHMEDIA
? ! leaf_function_p () : pr_live
;
7245 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
; reg
-- != 0; )
7247 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
7250 ? (/* Need to save all the regs ever live. */
7251 (df_regs_ever_live_p (reg
)
7252 || (call_really_used_regs
[reg
]
7253 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
7254 || reg
== PIC_OFFSET_TABLE_REGNUM
)
7256 || (TARGET_SHMEDIA
&& has_call
7257 && REGISTER_NATURAL_MODE (reg
) == SImode
7258 && (GENERAL_REGISTER_P (reg
) || TARGET_REGISTER_P (reg
))))
7259 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
7260 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
7261 && reg
!= T_REG
&& reg
!= GBR_REG
7262 && reg
!= FPSCR_MODES_REG
&& reg
!= FPSCR_STAT_REG
7263 /* Push fpscr only on targets which have FPU */
7264 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
7265 : (/* Only push those regs which are used and need to be saved. */
7268 && crtl
->args
.info
.call_cookie
7269 && reg
== PIC_OFFSET_TABLE_REGNUM
)
7270 || (df_regs_ever_live_p (reg
)
7271 && ((!call_really_used_regs
[reg
]
7272 && !(reg
!= PIC_OFFSET_TABLE_REGNUM
7273 && fixed_regs
[reg
] && call_used_regs
[reg
]))
7274 || (trapa_handler
&& reg
== FPSCR_REG
&& TARGET_FPU_ANY
)))
7275 || (crtl
->calls_eh_return
7276 && (reg
== EH_RETURN_DATA_REGNO (0)
7277 || reg
== EH_RETURN_DATA_REGNO (1)
7278 || reg
== EH_RETURN_DATA_REGNO (2)
7279 || reg
== EH_RETURN_DATA_REGNO (3)))
7280 || ((reg
== MACL_REG
|| reg
== MACH_REG
)
7281 && df_regs_ever_live_p (reg
)
7282 && sh_cfun_attr_renesas_p ())
7285 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
7286 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7288 if ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
|| TARGET_SH5
) && TARGET_FMOVD
7289 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
7291 if (FP_REGISTER_P (reg
))
7293 if (! TARGET_FPU_SINGLE
&& ! df_regs_ever_live_p (reg
^ 1))
7295 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
7296 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
7299 else if (XD_REGISTER_P (reg
))
7301 /* Must switch to double mode to access these registers. */
7302 target_flags
&= ~MASK_FPU_SINGLE
;
7306 if (nosave_low_regs
&& reg
== R8_REG
)
7309 /* If we have a target register optimization pass after prologue / epilogue
7310 threading, we need to assume all target registers will be live even if
7312 if (flag_branch_target_load_optimize2
7313 && TARGET_SAVE_ALL_TARGET_REGS
7314 && shmedia_space_reserved_for_target_registers
)
7315 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
7316 if ((! call_really_used_regs
[reg
] || interrupt_handler
)
7317 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
7319 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
7320 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
7322 /* If this is an interrupt handler, we don't have any call-clobbered
7323 registers we can conveniently use for target register save/restore.
7324 Make sure we save at least one general purpose register when we need
7325 to save target registers. */
7326 if (interrupt_handler
7327 && hard_reg_set_intersect_p (*live_regs_mask
,
7328 reg_class_contents
[TARGET_REGS
])
7329 && ! hard_reg_set_intersect_p (*live_regs_mask
,
7330 reg_class_contents
[GENERAL_REGS
]))
7332 SET_HARD_REG_BIT (*live_regs_mask
, R0_REG
);
7333 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG
));
7339 /* Code to generate prologue and epilogue sequences */
7341 /* PUSHED is the number of bytes that are being pushed on the
7342 stack for register saves. Return the frame size, padded
7343 appropriately so that the stack stays properly aligned. */
7344 static HOST_WIDE_INT
7345 rounded_frame_size (int pushed
)
7347 HOST_WIDE_INT size
= get_frame_size ();
7348 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7350 if (ACCUMULATE_OUTGOING_ARGS
)
7351 size
+= crtl
->outgoing_args_size
;
7353 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
7356 /* Choose a call-clobbered target-branch register that remains
7357 unchanged along the whole function. We set it up as the return
7358 value in the prologue. */
7360 sh_media_register_for_return (void)
7365 if (! crtl
->is_leaf
)
7367 if (lookup_attribute ("interrupt_handler",
7368 DECL_ATTRIBUTES (current_function_decl
)))
7370 if (sh_cfun_interrupt_handler_p ())
7373 tr0_used
= flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7375 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
7376 if (call_really_used_regs
[regno
] && ! df_regs_ever_live_p (regno
))
7382 /* The maximum registers we need to save are:
7383 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
7384 - 32 floating point registers (for each pair, we save none,
7385 one single precision value, or a double precision value).
7386 - 8 target registers
7387 - add 1 entry for a delimiter. */
7388 #define MAX_SAVED_REGS (62+32+8)
7390 typedef struct save_entry_s
7399 /* There will be a delimiter entry with VOIDmode both at the start and the
7400 end of a filled in schedule. The end delimiter has the offset of the
7401 save with the smallest (i.e. most negative) offset. */
7402 typedef struct save_schedule_s
7404 save_entry entries
[MAX_SAVED_REGS
+ 2];
7405 int temps
[MAX_TEMPS
+1];
7408 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
7409 use reverse order. Returns the last entry written to (not counting
7410 the delimiter). OFFSET_BASE is a number to be added to all offset
7413 sh5_schedule_saves (HARD_REG_SET
*live_regs_mask
, save_schedule
*schedule
,
7417 save_entry
*entry
= schedule
->entries
;
7421 if (! current_function_interrupt
)
7422 for (i
= FIRST_GENERAL_REG
; tmpx
< MAX_TEMPS
&& i
<= LAST_GENERAL_REG
; i
++)
7423 if (call_really_used_regs
[i
] && ! fixed_regs
[i
] && i
!= PR_MEDIA_REG
7424 && ! FUNCTION_ARG_REGNO_P (i
)
7425 && i
!= FIRST_RET_REG
7426 && ! (cfun
->static_chain_decl
!= NULL
&& i
== STATIC_CHAIN_REGNUM
)
7427 && ! (crtl
->calls_eh_return
7428 && (i
== EH_RETURN_STACKADJ_REGNO
7429 || ((unsigned) i
>= EH_RETURN_DATA_REGNO (0)
7430 && (unsigned) i
<= EH_RETURN_DATA_REGNO (3)))))
7431 schedule
->temps
[tmpx
++] = i
;
7433 entry
->mode
= VOIDmode
;
7434 entry
->offset
= offset_base
;
7436 /* We loop twice: first, we save 8-byte aligned registers in the
7437 higher addresses, that are known to be aligned. Then, we
7438 proceed to saving 32-bit registers that don't need 8-byte
7440 If this is an interrupt function, all registers that need saving
7441 need to be saved in full. moreover, we need to postpone saving
7442 target registers till we have saved some general purpose registers
7443 we can then use as scratch registers. */
7444 offset
= offset_base
;
7445 for (align
= 1; align
>= 0; align
--)
7447 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
7448 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
7450 machine_mode mode
= REGISTER_NATURAL_MODE (i
);
7453 if (current_function_interrupt
)
7455 if (TARGET_REGISTER_P (i
))
7457 if (GENERAL_REGISTER_P (i
))
7460 if (mode
== SFmode
&& (i
% 2) == 1
7461 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
7462 && (TEST_HARD_REG_BIT (*live_regs_mask
, (i
^ 1))))
7469 /* If we're doing the aligned pass and this is not aligned,
7470 or we're doing the unaligned pass and this is aligned,
7472 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
) == 0)
7476 if (current_function_interrupt
7477 && GENERAL_REGISTER_P (i
)
7478 && tmpx
< MAX_TEMPS
)
7479 schedule
->temps
[tmpx
++] = i
;
7481 offset
-= GET_MODE_SIZE (mode
);
7484 entry
->offset
= offset
;
7487 if (align
&& current_function_interrupt
)
7488 for (i
= LAST_TARGET_REG
; i
>= FIRST_TARGET_REG
; i
--)
7489 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
7491 offset
-= GET_MODE_SIZE (DImode
);
7493 entry
->mode
= DImode
;
7494 entry
->offset
= offset
;
7499 entry
->mode
= VOIDmode
;
7500 entry
->offset
= offset
;
7501 schedule
->temps
[tmpx
] = -1;
7505 /* Expand code for the function prologue. */
7507 sh_expand_prologue (void)
7509 HARD_REG_SET live_regs_mask
;
7512 int save_flags
= target_flags
;
7516 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
));
7518 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
7520 /* We have pretend args if we had an object sent partially in registers
7521 and partially on the stack, e.g. a large structure. */
7522 pretend_args
= crtl
->args
.pretend_args_size
;
7523 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
)
7524 && (NPARM_REGS(SImode
)
7525 > crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]))
7528 output_stack_adjust (-pretend_args
7529 - crtl
->args
.info
.stack_regs
* 8,
7530 stack_pointer_rtx
, 0, NULL
, true);
7531 stack_usage
= pretend_args
+ crtl
->args
.info
.stack_regs
* 8;
7533 if (TARGET_SHCOMPACT
&& flag_pic
&& crtl
->args
.info
.call_cookie
)
7534 /* We're going to use the PIC register to load the address of the
7535 incoming-argument decoder and/or of the return trampoline from
7536 the GOT, so make sure the PIC register is preserved and
7538 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
7540 if (TARGET_SHCOMPACT
7541 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7545 /* First, make all registers with incoming arguments that will
7546 be pushed onto the stack live, so that register renaming
7547 doesn't overwrite them. */
7548 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
7549 if (CALL_COOKIE_STACKSEQ_GET (crtl
->args
.info
.call_cookie
)
7550 >= NPARM_REGS (SImode
) - reg
)
7551 for (; reg
< NPARM_REGS (SImode
); reg
++)
7552 emit_insn (gen_shcompact_preserve_incoming_args
7553 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7554 else if (CALL_COOKIE_INT_REG_GET
7555 (crtl
->args
.info
.call_cookie
, reg
) == 1)
7556 emit_insn (gen_shcompact_preserve_incoming_args
7557 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
7559 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
7561 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
7562 GEN_INT (crtl
->args
.info
.call_cookie
));
7563 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
7564 gen_rtx_REG (SImode
, R0_REG
));
7566 else if (TARGET_SHMEDIA
)
7568 int tr
= sh_media_register_for_return ();
7571 emit_move_insn (gen_rtx_REG (DImode
, tr
),
7572 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
7575 /* Emit the code for SETUP_VARARGS. */
7578 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
7580 /* Push arg regs as if they'd been provided by caller in stack. */
7581 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
7583 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
7585 if (i
>= (NPARM_REGS(SImode
)
7586 - crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
]
7590 stack_usage
+= GET_MODE_SIZE (SImode
);
7595 /* If we're supposed to switch stacks at function entry, do so now. */
7599 /* The argument specifies a variable holding the address of the
7600 stack the interrupt function should switch to/from at entry/exit. */
7601 tree arg
= TREE_VALUE ( TREE_VALUE (sp_switch_attr
));
7603 = ggc_strdup (TREE_STRING_POINTER (arg
));
7604 rtx sp_switch
= gen_rtx_SYMBOL_REF (Pmode
, s
);
7606 lab
= add_constant (sp_switch
, SImode
, 0);
7607 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
7609 emit_insn (gen_sp_switch_1 (newsrc
));
7612 d
= calc_live_regs (&live_regs_mask
);
7613 /* ??? Maybe we could save some switching if we can move a mode switch
7614 that already happens to be at the function start into the prologue. */
7615 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7616 emit_insn (gen_toggle_sz ());
7620 int offset_base
, offset
;
7622 int offset_in_r0
= -1;
7624 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
7625 int total_size
, save_size
;
7626 save_schedule schedule
;
7630 if (call_really_used_regs
[R0_REG
] && ! fixed_regs
[R0_REG
]
7631 && ! current_function_interrupt
)
7632 r0
= gen_rtx_REG (Pmode
, R0_REG
);
7634 /* D is the actual number of bytes that we need for saving registers,
7635 however, in initial_elimination_offset we have committed to using
7636 an additional TREGS_SPACE amount of bytes - in order to keep both
7637 addresses to arguments supplied by the caller and local variables
7638 valid, we must keep this gap. Place it between the incoming
7639 arguments and the actually saved registers in a bid to optimize
7640 locality of reference. */
7641 total_size
= d
+ tregs_space
;
7642 total_size
+= rounded_frame_size (total_size
);
7643 save_size
= total_size
- rounded_frame_size (d
);
7644 if (save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
7645 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
7646 - save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
7648 /* If adjusting the stack in a single step costs nothing extra, do so.
7649 I.e. either if a single addi is enough, or we need a movi anyway,
7650 and we don't exceed the maximum offset range (the test for the
7651 latter is conservative for simplicity). */
7653 && (CONST_OK_FOR_I10 (-total_size
)
7654 || (! CONST_OK_FOR_I10 (-(save_size
+ d_rounding
))
7655 && total_size
<= 2044)))
7656 d_rounding
= total_size
- save_size
;
7658 offset_base
= d
+ d_rounding
;
7660 output_stack_adjust (-(save_size
+ d_rounding
), stack_pointer_rtx
,
7662 stack_usage
+= save_size
+ d_rounding
;
7664 sh5_schedule_saves (&live_regs_mask
, &schedule
, offset_base
);
7665 tmp_pnt
= schedule
.temps
;
7666 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
7668 machine_mode mode
= (machine_mode
) entry
->mode
;
7669 unsigned int reg
= entry
->reg
;
7670 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
7673 offset
= entry
->offset
;
7675 reg_rtx
= gen_rtx_REG (mode
, reg
);
7677 mem_rtx
= gen_frame_mem (mode
,
7678 gen_rtx_PLUS (Pmode
,
7682 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
7688 if (HAVE_PRE_DECREMENT
7689 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
7690 || mem_rtx
== NULL_RTX
7691 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
7693 pre_dec
= gen_frame_mem (mode
, gen_rtx_PRE_DEC (Pmode
, r0
));
7695 if (!memory_address_p (mode
, XEXP (pre_dec
, 0)))
7700 offset
+= GET_MODE_SIZE (mode
);
7704 if (mem_rtx
!= NULL_RTX
)
7707 if (offset_in_r0
== -1)
7709 emit_move_insn (r0
, GEN_INT (offset
));
7710 offset_in_r0
= offset
;
7712 else if (offset
!= offset_in_r0
)
7717 GEN_INT (offset
- offset_in_r0
)));
7718 offset_in_r0
+= offset
- offset_in_r0
;
7721 if (pre_dec
!= NULL_RTX
)
7727 (Pmode
, r0
, stack_pointer_rtx
));
7731 offset
-= GET_MODE_SIZE (mode
);
7732 offset_in_r0
-= GET_MODE_SIZE (mode
);
7737 mem_rtx
= gen_frame_mem (mode
, r0
);
7739 mem_rtx
= gen_frame_mem (mode
,
7740 gen_rtx_PLUS (Pmode
,
7744 /* We must not use an r0-based address for target-branch
7745 registers or for special registers without pre-dec
7746 memory addresses, since we store their values in r0
7748 gcc_assert (!TARGET_REGISTER_P (reg
)
7749 && ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
7750 || mem_rtx
== pre_dec
));
7753 orig_reg_rtx
= reg_rtx
;
7754 if (TARGET_REGISTER_P (reg
)
7755 || ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
7756 && mem_rtx
!= pre_dec
))
7758 rtx tmp_reg
= gen_rtx_REG (GET_MODE (reg_rtx
), *tmp_pnt
);
7760 emit_move_insn (tmp_reg
, reg_rtx
);
7762 if (REGNO (tmp_reg
) == R0_REG
)
7766 gcc_assert (!refers_to_regno_p
7767 (R0_REG
, R0_REG
+1, mem_rtx
, (rtx
*) 0));
7770 if (*++tmp_pnt
<= 0)
7771 tmp_pnt
= schedule
.temps
;
7778 /* Mark as interesting for dwarf cfi generator */
7779 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
7780 RTX_FRAME_RELATED_P (insn
) = 1;
7781 /* If we use an intermediate register for the save, we can't
7782 describe this exactly in cfi as a copy of the to-be-saved
7783 register into the temporary register and then the temporary
7784 register on the stack, because the temporary register can
7785 have a different natural size than the to-be-saved register.
7786 Thus, we gloss over the intermediate copy and pretend we do
7787 a direct save from the to-be-saved register. */
7788 if (REGNO (reg_rtx
) != reg
)
7792 set
= gen_rtx_SET (VOIDmode
, mem_rtx
, orig_reg_rtx
);
7793 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7796 if (TARGET_SHCOMPACT
&& (offset_in_r0
!= -1))
7798 rtx reg_rtx
= gen_rtx_REG (mode
, reg
);
7800 rtx mem_rtx
= gen_frame_mem (mode
,
7801 gen_rtx_PLUS (Pmode
,
7805 set
= gen_rtx_SET (VOIDmode
, mem_rtx
, reg_rtx
);
7806 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
7811 gcc_assert (entry
->offset
== d_rounding
);
7815 push_regs (&live_regs_mask
, current_function_interrupt
);
7819 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7820 emit_insn (gen_GOTaddr2picreg ());
7822 if (SHMEDIA_REGS_STACK_ADJUST ())
7824 /* This must NOT go through the PLT, otherwise mach and macl
7825 may be clobbered. */
7826 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7828 ? "__GCC_push_shmedia_regs"
7829 : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT
);
7830 emit_insn (gen_shmedia_save_restore_regs_compact
7831 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
7834 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7835 emit_insn (gen_toggle_sz ());
7837 target_flags
= save_flags
;
7839 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
7840 stack_pointer_rtx
, 0, NULL
, true);
7841 stack_usage
+= rounded_frame_size (d
) - d_rounding
;
7843 if (frame_pointer_needed
)
7844 frame_insn (GEN_MOV (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7846 if (TARGET_SHCOMPACT
7847 && (crtl
->args
.info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
7849 /* This must NOT go through the PLT, otherwise mach and macl
7850 may be clobbered. */
7851 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7852 "__GCC_shcompact_incoming_args", SFUNC_GOT
);
7853 emit_insn (gen_shcompact_incoming_args ());
7856 /* If we are profiling, make sure no instructions are scheduled before
7857 the call to mcount. Similarly if some call instructions are swapped
7858 before frame related insns, it'll confuse the unwinder because
7859 currently SH has no unwind info for function epilogues. */
7860 if (crtl
->profile
|| flag_exceptions
|| flag_unwind_tables
)
7861 emit_insn (gen_blockage ());
7863 if (flag_stack_usage_info
)
7864 current_function_static_stack_size
= stack_usage
;
7867 /* Expand code for the function epilogue. */
7869 sh_expand_epilogue (bool sibcall_p
)
7871 HARD_REG_SET live_regs_mask
;
7875 int save_flags
= target_flags
;
7876 int frame_size
, save_size
;
7877 int fpscr_deferred
= 0;
7878 int e
= sibcall_p
? -1 : 1;
7880 d
= calc_live_regs (&live_regs_mask
);
7883 frame_size
= rounded_frame_size (d
);
7887 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
7889 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
7890 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
7891 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
7893 total_size
= d
+ tregs_space
;
7894 total_size
+= rounded_frame_size (total_size
);
7895 save_size
= total_size
- frame_size
;
7897 /* If adjusting the stack in a single step costs nothing extra, do so.
7898 I.e. either if a single addi is enough, or we need a movi anyway,
7899 and we don't exceed the maximum offset range (the test for the
7900 latter is conservative for simplicity). */
7902 && ! frame_pointer_needed
7903 && (CONST_OK_FOR_I10 (total_size
)
7904 || (! CONST_OK_FOR_I10 (save_size
+ d_rounding
)
7905 && total_size
<= 2044)))
7906 d_rounding
= frame_size
;
7908 frame_size
-= d_rounding
;
7911 if (frame_pointer_needed
)
7913 /* We must avoid scheduling the epilogue with previous basic blocks.
7914 See PR/18032 and PR/40313. */
7915 emit_insn (gen_blockage ());
7916 output_stack_adjust (frame_size
, hard_frame_pointer_rtx
, e
,
7917 &live_regs_mask
, true);
7919 /* We must avoid moving the stack pointer adjustment past code
7920 which reads from the local frame, else an interrupt could
7921 occur after the SP adjustment and clobber data in the local
7923 emit_insn (gen_blockage ());
7924 frame_insn (GEN_MOV (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7926 else if (frame_size
)
7928 /* We must avoid moving the stack pointer adjustment past code
7929 which reads from the local frame, else an interrupt could
7930 occur after the SP adjustment and clobber data in the local
7932 emit_insn (gen_blockage ());
7933 output_stack_adjust (frame_size
, stack_pointer_rtx
, e
,
7934 &live_regs_mask
, true);
7937 if (SHMEDIA_REGS_STACK_ADJUST ())
7939 function_symbol (gen_rtx_REG (Pmode
, R0_REG
),
7941 ? "__GCC_pop_shmedia_regs"
7942 : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT
);
7943 /* This must NOT go through the PLT, otherwise mach and macl
7944 may be clobbered. */
7945 emit_insn (gen_shmedia_save_restore_regs_compact
7946 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
7949 /* Pop all the registers. */
7951 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
7952 emit_insn (gen_toggle_sz ());
7955 int offset_base
, offset
;
7956 int offset_in_r0
= -1;
7958 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
7959 save_schedule schedule
;
7963 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, d_rounding
);
7964 offset_base
= -entry
[1].offset
+ d_rounding
;
7965 tmp_pnt
= schedule
.temps
;
7966 for (; entry
->mode
!= VOIDmode
; entry
--)
7968 machine_mode mode
= (machine_mode
) entry
->mode
;
7969 int reg
= entry
->reg
;
7970 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
;
7972 offset
= offset_base
+ entry
->offset
;
7973 reg_rtx
= gen_rtx_REG (mode
, reg
);
7975 mem_rtx
= gen_frame_mem (mode
,
7976 gen_rtx_PLUS (Pmode
,
7980 if (!memory_address_p (mode
, XEXP (mem_rtx
, 0)))
7983 if (HAVE_POST_INCREMENT
7984 && (offset
== offset_in_r0
7985 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
7986 && mem_rtx
== NULL_RTX
)
7987 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
7989 post_inc
= gen_frame_mem (mode
, gen_rtx_POST_INC (Pmode
, r0
));
7991 if (!memory_address_p (mode
, XEXP (post_inc
, 0)))
7992 post_inc
= NULL_RTX
;
7997 if (mem_rtx
!= NULL_RTX
)
8000 if (offset_in_r0
== -1)
8002 emit_move_insn (r0
, GEN_INT (offset
));
8003 offset_in_r0
= offset
;
8005 else if (offset
!= offset_in_r0
)
8010 GEN_INT (offset
- offset_in_r0
)));
8011 offset_in_r0
+= offset
- offset_in_r0
;
8014 if (post_inc
!= NULL_RTX
)
8020 (Pmode
, r0
, stack_pointer_rtx
));
8026 offset_in_r0
+= GET_MODE_SIZE (mode
);
8029 mem_rtx
= gen_frame_mem (mode
, r0
);
8031 mem_rtx
= gen_frame_mem (mode
,
8032 gen_rtx_PLUS (Pmode
,
8036 gcc_assert ((reg
!= PR_REG
&& !SPECIAL_REGISTER_P (reg
))
8037 || mem_rtx
== post_inc
);
8040 if ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
8041 && mem_rtx
!= post_inc
)
8043 emit_move_insn (r0
, mem_rtx
);
8046 else if (TARGET_REGISTER_P (reg
))
8048 rtx tmp_reg
= gen_rtx_REG (mode
, *tmp_pnt
);
8050 /* Give the scheduler a bit of freedom by using up to
8051 MAX_TEMPS registers in a round-robin fashion. */
8052 emit_move_insn (tmp_reg
, mem_rtx
);
8055 tmp_pnt
= schedule
.temps
;
8058 emit_move_insn (reg_rtx
, mem_rtx
);
8061 gcc_assert (entry
->offset
+ offset_base
== d
+ d_rounding
);
8063 else /* ! TARGET_SH5 */
8068 /* For an ISR with RESBANK attribute assigned, don't pop PR
8070 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
)
8071 && !sh_cfun_resbank_handler_p ())
8073 if (!frame_pointer_needed
)
8074 emit_insn (gen_blockage ());
8078 /* Banked registers are popped first to avoid being scheduled in the
8079 delay slot. RTE switches banks before the ds instruction. */
8080 if (current_function_interrupt
)
8082 bool use_movml
= false;
8086 unsigned int count
= 0;
8088 for (i
= FIRST_BANKED_REG
; i
<= LAST_BANKED_REG
; i
++)
8089 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
8094 /* Use movml when all banked register are poped. */
8095 if (count
== LAST_BANKED_REG
- FIRST_BANKED_REG
+ 1)
8099 if (sh_cfun_resbank_handler_p ())
8103 rtx sp_reg
= gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
);
8105 /* We must avoid scheduling multiple load insn with another
8107 emit_insn (gen_blockage ());
8108 emit_insn (gen_movml_pop_banked (sp_reg
));
8109 emit_insn (gen_blockage ());
8112 for (i
= LAST_BANKED_REG
; i
>= FIRST_BANKED_REG
; i
--)
8113 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
8116 last_reg
= FIRST_PSEUDO_REGISTER
- LAST_BANKED_REG
- 1;
8119 last_reg
= FIRST_PSEUDO_REGISTER
;
8121 for (i
= 0; i
< last_reg
; i
++)
8123 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
8125 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
8126 && hard_reg_set_intersect_p (live_regs_mask
,
8127 reg_class_contents
[DF_REGS
]))
8129 /* For an ISR with RESBANK attribute assigned, don't pop
8130 following registers, R0-R14, MACH, MACL and GBR. */
8131 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
)
8132 && ! (sh_cfun_resbank_handler_p ()
8133 && ((j
>= FIRST_GENERAL_REG
8134 && j
< LAST_GENERAL_REG
)
8140 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
8144 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
8145 emit_insn (gen_toggle_sz ());
8146 target_flags
= save_flags
;
8148 output_stack_adjust (crtl
->args
.pretend_args_size
8149 + save_size
+ d_rounding
8150 + crtl
->args
.info
.stack_regs
* 8,
8151 stack_pointer_rtx
, e
, NULL
, true);
8153 if (crtl
->calls_eh_return
)
8154 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
8155 EH_RETURN_STACKADJ_RTX
));
8157 /* Switch back to the normal stack if necessary. */
8158 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl
)))
8159 emit_insn (gen_sp_switch_2 ());
8161 /* Tell flow the insn that pops PR isn't dead. */
8162 /* PR_REG will never be live in SHmedia mode, and we don't need to
8163 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
8164 by the return pattern. */
8165 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
8166 emit_use (gen_rtx_REG (SImode
, PR_REG
));
8169 /* Emit code to change the current function's return address to RA.
8170 TEMP is available as a scratch register, if needed. */
8172 sh_set_return_address (rtx ra
, rtx tmp
)
8174 HARD_REG_SET live_regs_mask
;
8176 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
8179 d
= calc_live_regs (&live_regs_mask
);
8181 /* If pr_reg isn't life, we can set it (or the register given in
8182 sh_media_register_for_return) directly. */
8183 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
8189 int rr_regno
= sh_media_register_for_return ();
8194 rr
= gen_rtx_REG (DImode
, rr_regno
);
8197 rr
= gen_rtx_REG (SImode
, pr_reg
);
8199 emit_insn (GEN_MOV (rr
, ra
));
8200 /* Tell flow the register for return isn't dead. */
8208 save_schedule schedule
;
8211 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, 0);
8212 offset
= entry
[1].offset
;
8213 for (; entry
->mode
!= VOIDmode
; entry
--)
8214 if (entry
->reg
== pr_reg
)
8217 /* We can't find pr register. */
8221 offset
= entry
->offset
- offset
;
8222 pr_offset
= (rounded_frame_size (d
) + offset
8223 + SHMEDIA_REGS_STACK_ADJUST ());
8226 pr_offset
= rounded_frame_size (d
);
8228 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
8230 if (frame_pointer_needed
)
8231 emit_insn (GEN_ADD3 (tmp
, tmp
, hard_frame_pointer_rtx
));
8233 emit_insn (GEN_ADD3 (tmp
, tmp
, stack_pointer_rtx
));
8235 tmp
= gen_frame_mem (Pmode
, tmp
);
8236 emit_insn (GEN_MOV (tmp
, ra
));
8237 /* Tell this store isn't dead. */
8241 /* Clear variables at function end. */
8243 sh_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8244 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8249 sh_builtin_saveregs (void)
8251 /* First unnamed integer register. */
8252 int first_intreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_INT
];
8253 /* Number of integer registers we need to save. */
8254 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
8255 /* First unnamed SFmode float reg */
8256 int first_floatreg
= crtl
->args
.info
.arg_count
[(int) SH_ARG_FLOAT
];
8257 /* Number of SFmode float regs to save. */
8258 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
8261 alias_set_type alias_set
;
8267 int pushregs
= n_intregs
;
8269 while (pushregs
< NPARM_REGS (SImode
) - 1
8270 && (CALL_COOKIE_INT_REG_GET
8271 (crtl
->args
.info
.call_cookie
,
8272 NPARM_REGS (SImode
) - pushregs
)
8275 crtl
->args
.info
.call_cookie
8276 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
8281 if (pushregs
== NPARM_REGS (SImode
))
8282 crtl
->args
.info
.call_cookie
8283 |= (CALL_COOKIE_INT_REG (0, 1)
8284 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
8286 crtl
->args
.info
.call_cookie
8287 |= CALL_COOKIE_STACKSEQ (pushregs
);
8289 crtl
->args
.pretend_args_size
+= 8 * n_intregs
;
8291 if (TARGET_SHCOMPACT
)
8295 if (! TARGET_SH2E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
8297 error ("__builtin_saveregs not supported by this subtarget");
8304 /* Allocate block of memory for the regs. */
8305 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
8306 Or can assign_stack_local accept a 0 SIZE argument? */
8307 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
8310 regbuf
= gen_frame_mem (BLKmode
, gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
8311 else if (n_floatregs
& 1)
8315 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
8316 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
8317 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
8318 regbuf
= change_address (regbuf
, BLKmode
, addr
);
8320 else if (STACK_BOUNDARY
< 64 && TARGET_FPU_DOUBLE
&& n_floatregs
)
8324 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
8325 addr
= copy_to_mode_reg (Pmode
, plus_constant (Pmode
,
8326 XEXP (regbuf
, 0), 4));
8327 mask
= copy_to_mode_reg (Pmode
, GEN_INT (-8));
8328 emit_insn (gen_andsi3 (addr
, addr
, mask
));
8329 regbuf
= change_address (regbuf
, BLKmode
, addr
);
8332 regbuf
= assign_stack_local (BLKmode
, bufsize
, TARGET_FPU_DOUBLE
? 64 : 0);
8333 alias_set
= get_varargs_alias_set ();
8334 set_mem_alias_set (regbuf
, alias_set
);
8337 This is optimized to only save the regs that are necessary. Explicitly
8338 named args need not be saved. */
8340 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
8341 adjust_address (regbuf
, BLKmode
,
8342 n_floatregs
* UNITS_PER_WORD
),
8346 /* Return the address of the regbuf. */
8347 return XEXP (regbuf
, 0);
8350 This is optimized to only save the regs that are necessary. Explicitly
8351 named args need not be saved.
8352 We explicitly build a pointer to the buffer because it halves the insn
8353 count when not optimizing (otherwise the pointer is built for each reg
8355 We emit the moves in reverse order so that we can use predecrement. */
8357 fpregs
= copy_to_mode_reg (Pmode
,
8358 plus_constant (Pmode
, XEXP (regbuf
, 0),
8359 n_floatregs
* UNITS_PER_WORD
));
8360 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8363 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
8365 emit_insn (gen_addsi3 (fpregs
, fpregs
,
8366 GEN_INT (-2 * UNITS_PER_WORD
)));
8367 mem
= change_address (regbuf
, DFmode
, fpregs
);
8368 emit_move_insn (mem
,
8369 gen_rtx_REG (DFmode
, BASE_ARG_REG (DFmode
) + regno
));
8371 regno
= first_floatreg
;
8374 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
8375 mem
= change_address (regbuf
, SFmode
, fpregs
);
8376 emit_move_insn (mem
,
8377 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
)
8378 + regno
- SH_REG_MSW_OFFSET
));
8382 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
8386 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (-UNITS_PER_WORD
)));
8387 mem
= change_address (regbuf
, SFmode
, fpregs
);
8388 emit_move_insn (mem
,
8389 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
8392 /* Return the address of the regbuf. */
8393 return XEXP (regbuf
, 0);
8396 /* Define the `__builtin_va_list' type for the ABI. */
8398 sh_build_builtin_va_list (void)
8400 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8401 tree record
, type_decl
;
8403 if (TARGET_SH5
|| (! TARGET_SH2E
&& ! TARGET_SH4
)
8404 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
8405 return ptr_type_node
;
8407 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
8408 type_decl
= build_decl (BUILTINS_LOCATION
,
8409 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8411 f_next_o
= build_decl (BUILTINS_LOCATION
,
8412 FIELD_DECL
, get_identifier ("__va_next_o"),
8414 f_next_o_limit
= build_decl (BUILTINS_LOCATION
,
8416 get_identifier ("__va_next_o_limit"),
8418 f_next_fp
= build_decl (BUILTINS_LOCATION
,
8419 FIELD_DECL
, get_identifier ("__va_next_fp"),
8421 f_next_fp_limit
= build_decl (BUILTINS_LOCATION
,
8423 get_identifier ("__va_next_fp_limit"),
8425 f_next_stack
= build_decl (BUILTINS_LOCATION
,
8426 FIELD_DECL
, get_identifier ("__va_next_stack"),
8429 DECL_FIELD_CONTEXT (f_next_o
) = record
;
8430 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
8431 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
8432 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
8433 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
8435 TYPE_STUB_DECL (record
) = type_decl
;
8436 TYPE_NAME (record
) = type_decl
;
8437 TYPE_FIELDS (record
) = f_next_o
;
8438 DECL_CHAIN (f_next_o
) = f_next_o_limit
;
8439 DECL_CHAIN (f_next_o_limit
) = f_next_fp
;
8440 DECL_CHAIN (f_next_fp
) = f_next_fp_limit
;
8441 DECL_CHAIN (f_next_fp_limit
) = f_next_stack
;
8443 layout_type (record
);
8448 /* Implement `va_start' for varargs and stdarg. */
8450 sh_va_start (tree valist
, rtx nextarg
)
8452 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8453 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
8459 expand_builtin_saveregs ();
8460 std_expand_builtin_va_start (valist
, nextarg
);
8464 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
8465 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
8467 std_expand_builtin_va_start (valist
, nextarg
);
8471 f_next_o
= TYPE_FIELDS (va_list_type_node
);
8472 f_next_o_limit
= DECL_CHAIN (f_next_o
);
8473 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
8474 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
8475 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
8477 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
8479 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
8480 valist
, f_next_o_limit
, NULL_TREE
);
8481 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
,
8483 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
8484 valist
, f_next_fp_limit
, NULL_TREE
);
8485 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
8486 valist
, f_next_stack
, NULL_TREE
);
8488 /* Call __builtin_saveregs. */
8489 u
= make_tree (sizetype
, expand_builtin_saveregs ());
8490 u
= fold_convert (ptr_type_node
, u
);
8491 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
8492 TREE_SIDE_EFFECTS (t
) = 1;
8493 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8495 nfp
= crtl
->args
.info
.arg_count
[SH_ARG_FLOAT
];
8500 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nfp
);
8501 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
8502 TREE_SIDE_EFFECTS (t
) = 1;
8503 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8505 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
8506 TREE_SIDE_EFFECTS (t
) = 1;
8507 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8509 nint
= crtl
->args
.info
.arg_count
[SH_ARG_INT
];
8514 u
= fold_build_pointer_plus_hwi (u
, UNITS_PER_WORD
* nint
);
8515 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
8516 TREE_SIDE_EFFECTS (t
) = 1;
8517 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8519 u
= make_tree (ptr_type_node
, nextarg
);
8520 t
= build2 (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
8521 TREE_SIDE_EFFECTS (t
) = 1;
8522 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8525 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
8526 member, return it. */
8528 find_sole_member (tree type
)
8530 tree field
, member
= NULL_TREE
;
8532 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8534 if (TREE_CODE (field
) != FIELD_DECL
)
8536 if (!DECL_SIZE (field
))
8538 if (integer_zerop (DECL_SIZE (field
)))
8547 /* Implement `va_arg'. */
8549 sh_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
8550 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8552 HOST_WIDE_INT size
, rsize
;
8553 tree tmp
, pptr_type_node
;
8554 tree addr
, lab_over
= NULL
, result
= NULL
;
8558 if (!VOID_TYPE_P (type
))
8559 pass_by_ref
= targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
);
8561 pass_by_ref
= false;
8564 type
= build_pointer_type (type
);
8566 size
= int_size_in_bytes (type
);
8567 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
8568 pptr_type_node
= build_pointer_type (ptr_type_node
);
8570 if (! TARGET_SH5
&& (TARGET_SH2E
|| TARGET_SH4
)
8571 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
8573 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
8574 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
8579 f_next_o
= TYPE_FIELDS (va_list_type_node
);
8580 f_next_o_limit
= DECL_CHAIN (f_next_o
);
8581 f_next_fp
= DECL_CHAIN (f_next_o_limit
);
8582 f_next_fp_limit
= DECL_CHAIN (f_next_fp
);
8583 f_next_stack
= DECL_CHAIN (f_next_fp_limit
);
8585 next_o
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
,
8587 next_o_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
8588 valist
, f_next_o_limit
, NULL_TREE
);
8589 next_fp
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
8590 valist
, f_next_fp
, NULL_TREE
);
8591 next_fp_limit
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
8592 valist
, f_next_fp_limit
, NULL_TREE
);
8593 next_stack
= build3 (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
8594 valist
, f_next_stack
, NULL_TREE
);
8596 /* Structures with a single member with a distinct mode are passed
8597 like their member. This is relevant if the latter has a REAL_TYPE
8598 or COMPLEX_TYPE type. */
8600 while (TREE_CODE (eff_type
) == RECORD_TYPE
8601 && (member
= find_sole_member (eff_type
))
8602 && (TREE_CODE (TREE_TYPE (member
)) == REAL_TYPE
8603 || TREE_CODE (TREE_TYPE (member
)) == COMPLEX_TYPE
8604 || TREE_CODE (TREE_TYPE (member
)) == RECORD_TYPE
))
8606 tree field_type
= TREE_TYPE (member
);
8608 if (TYPE_MODE (eff_type
) == TYPE_MODE (field_type
))
8609 eff_type
= field_type
;
8612 gcc_assert ((TYPE_ALIGN (eff_type
)
8613 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type
)))
8614 || (TYPE_ALIGN (eff_type
)
8615 > GET_MODE_BITSIZE (TYPE_MODE (field_type
))));
8620 if (TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8622 pass_as_float
= ((TREE_CODE (eff_type
) == REAL_TYPE
&& size
<= 8)
8623 || (TREE_CODE (eff_type
) == COMPLEX_TYPE
8624 && TREE_CODE (TREE_TYPE (eff_type
)) == REAL_TYPE
8629 pass_as_float
= (TREE_CODE (eff_type
) == REAL_TYPE
&& size
== 4);
8632 addr
= create_tmp_var (pptr_type_node
, NULL
);
8633 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8634 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8636 valist
= build_simple_mem_ref (addr
);
8640 tree next_fp_tmp
= create_tmp_var (TREE_TYPE (f_next_fp
), NULL
);
8642 bool is_double
= size
== 8 && TREE_CODE (eff_type
) == REAL_TYPE
;
8644 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_fp
));
8645 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8647 gimplify_assign (unshare_expr (next_fp_tmp
), valist
, pre_p
);
8648 tmp
= next_fp_limit
;
8649 if (size
> 4 && !is_double
)
8650 tmp
= fold_build_pointer_plus_hwi (unshare_expr (tmp
), 4 - size
);
8651 tmp
= build2 (GE_EXPR
, boolean_type_node
,
8652 unshare_expr (next_fp_tmp
), unshare_expr (tmp
));
8653 cmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8654 build1 (GOTO_EXPR
, void_type_node
,
8655 unshare_expr (lab_false
)), NULL_TREE
);
8657 gimplify_and_add (cmp
, pre_p
);
8659 if (TYPE_ALIGN (eff_type
) > BITS_PER_WORD
8660 || (is_double
|| size
== 16))
8662 tmp
= fold_convert (sizetype
, next_fp_tmp
);
8663 tmp
= build2 (BIT_AND_EXPR
, sizetype
, tmp
,
8664 size_int (UNITS_PER_WORD
));
8665 tmp
= fold_build_pointer_plus (unshare_expr (next_fp_tmp
), tmp
);
8666 gimplify_assign (unshare_expr (next_fp_tmp
), tmp
, pre_p
);
8669 gimplify_and_add (cmp
, pre_p
);
8671 #ifdef FUNCTION_ARG_SCmode_WART
8672 if (TYPE_MODE (eff_type
) == SCmode
8673 && TARGET_SH4
&& TARGET_LITTLE_ENDIAN
)
8675 tree subtype
= TREE_TYPE (eff_type
);
8679 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8680 imag
= get_initialized_tmp_var (imag
, pre_p
, NULL
);
8683 = std_gimplify_va_arg_expr (next_fp_tmp
, subtype
, pre_p
, NULL
);
8684 real
= get_initialized_tmp_var (real
, pre_p
, NULL
);
8686 result
= build2 (COMPLEX_EXPR
, eff_type
, real
, imag
);
8687 if (type
!= eff_type
)
8688 result
= build1 (VIEW_CONVERT_EXPR
, type
, result
);
8689 result
= get_initialized_tmp_var (result
, pre_p
, NULL
);
8691 #endif /* FUNCTION_ARG_SCmode_WART */
8693 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8694 gimplify_and_add (tmp
, pre_p
);
8696 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8697 gimplify_and_add (tmp
, pre_p
);
8699 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8700 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8701 gimplify_assign (unshare_expr (next_fp_tmp
),
8702 unshare_expr (valist
), pre_p
);
8704 gimplify_assign (unshare_expr (valist
),
8705 unshare_expr (next_fp_tmp
), post_p
);
8706 valist
= next_fp_tmp
;
8710 tmp
= fold_build_pointer_plus_hwi (unshare_expr (next_o
), rsize
);
8711 tmp
= build2 (GT_EXPR
, boolean_type_node
, tmp
,
8712 unshare_expr (next_o_limit
));
8713 tmp
= build3 (COND_EXPR
, void_type_node
, tmp
,
8714 build1 (GOTO_EXPR
, void_type_node
,
8715 unshare_expr (lab_false
)),
8717 gimplify_and_add (tmp
, pre_p
);
8719 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_o
));
8720 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8722 tmp
= build1 (GOTO_EXPR
, void_type_node
, unshare_expr (lab_over
));
8723 gimplify_and_add (tmp
, pre_p
);
8725 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_false
));
8726 gimplify_and_add (tmp
, pre_p
);
8728 if (size
> 4 && ! (TARGET_SH4
|| TARGET_SH2A
))
8729 gimplify_assign (unshare_expr (next_o
),
8730 unshare_expr (next_o_limit
), pre_p
);
8732 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, unshare_expr (next_stack
));
8733 gimplify_assign (unshare_expr (addr
), tmp
, pre_p
);
8738 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8739 gimplify_and_add (tmp
, pre_p
);
8743 /* ??? In va-sh.h, there had been code to make values larger than
8744 size 8 indirect. This does not match the FUNCTION_ARG macros. */
8746 tmp
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, NULL
);
8749 gimplify_assign (result
, tmp
, pre_p
);
8750 result
= build1 (NOP_EXPR
, TREE_TYPE (result
), result
);
8751 tmp
= build1 (LABEL_EXPR
, void_type_node
, unshare_expr (lab_over
));
8752 gimplify_and_add (tmp
, pre_p
);
8758 result
= build_va_arg_indirect_ref (result
);
8763 /* 64 bit floating points memory transfers are paired single precision loads
8764 or store. So DWARF information needs fixing in little endian (unless
8765 PR=SZ=1 in FPSCR). */
8767 sh_dwarf_register_span (rtx reg
)
8769 unsigned regno
= REGNO (reg
);
8771 if (WORDS_BIG_ENDIAN
|| GET_MODE (reg
) != DFmode
)
8775 gen_rtx_PARALLEL (VOIDmode
,
8777 gen_rtx_REG (SFmode
, regno
+ 1),
8778 gen_rtx_REG (SFmode
, regno
)));
8782 sh_promote_function_mode (const_tree type
, machine_mode mode
,
8783 int *punsignedp
, const_tree funtype
,
8786 if (sh_promote_prototypes (funtype
))
8787 return promote_mode (type
, mode
, punsignedp
);
8789 return default_promote_function_mode (type
, mode
, punsignedp
, funtype
,
8794 sh_promote_prototypes (const_tree type
)
8800 return ! sh_attr_renesas_p (type
);
8803 /* Whether an argument must be passed by reference. On SHcompact, we
8804 pretend arguments wider than 32-bits that would have been passed in
8805 registers are passed by reference, so that an SHmedia trampoline
8806 loads them into the full 64-bits registers. */
8808 shcompact_byref (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
8809 const_tree type
, bool named
)
8811 unsigned HOST_WIDE_INT size
;
8814 size
= int_size_in_bytes (type
);
8816 size
= GET_MODE_SIZE (mode
);
8818 if (cum
->arg_count
[SH_ARG_INT
] < NPARM_REGS (SImode
)
8820 || GET_SH_ARG_CLASS (mode
) == SH_ARG_INT
8821 || (GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
8822 && cum
->arg_count
[SH_ARG_FLOAT
] >= NPARM_REGS (SFmode
)))
8824 && !SHCOMPACT_FORCE_ON_STACK (mode
, type
)
8825 && !SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
8832 sh_pass_by_reference (cumulative_args_t cum_v
, machine_mode mode
,
8833 const_tree type
, bool named
)
8835 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8837 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
8840 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
8841 wants to know about pass-by-reference semantics for incoming
8846 if (TARGET_SHCOMPACT
)
8848 cum
->byref
= shcompact_byref (cum
, mode
, type
, named
);
8849 return cum
->byref
!= 0;
8856 sh_callee_copies (cumulative_args_t cum
, machine_mode mode
,
8857 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8859 /* ??? How can it possibly be correct to return true only on the
8860 caller side of the equation? Is there someplace else in the
8861 sh backend that's magically producing the copies? */
8862 return (get_cumulative_args (cum
)->outgoing
8863 && ((mode
== BLKmode
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
))
8864 % SH_MIN_ALIGN_FOR_CALLEE_COPY
== 0));
8867 /* Round a register number up to a proper boundary for an arg of mode
8869 The SH doesn't care about double alignment, so we only
8870 round doubles to even regs when asked to explicitly. */
8872 sh_round_reg (const CUMULATIVE_ARGS
& cum
, machine_mode mode
)
8874 /* FIXME: This used to be a macro and has been copy pasted into this
8875 function as is. Make this more readable. */
8877 (((TARGET_ALIGN_DOUBLE
8878 || ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8879 && (mode
== DFmode
|| mode
== DCmode
)
8880 && cum
.arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (mode
)))
8881 && GET_MODE_UNIT_SIZE (mode
) > UNITS_PER_WORD
)
8882 ? (cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
8883 + (cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)] & 1))
8884 : cum
.arg_count
[(int) GET_SH_ARG_CLASS (mode
)]);
8887 /* Return true if arg of the specified mode should be be passed in a register
8888 or false otherwise. */
8890 sh_pass_in_reg_p (const CUMULATIVE_ARGS
& cum
, machine_mode mode
,
8893 /* FIXME: This used to be a macro and has been copy pasted into this
8894 function as is. Make this more readable. */
8897 || (! TREE_ADDRESSABLE (type
)
8898 && (! (TARGET_HITACHI
|| cum
.renesas_abi
)
8899 || ! (AGGREGATE_TYPE_P (type
)
8901 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
8902 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (SFmode
)))))))
8905 ? ((mode
) == BLKmode
8906 ? ((cum
.arg_count
[(int) SH_ARG_INT
] * UNITS_PER_WORD
8907 + int_size_in_bytes (type
))
8908 <= NPARM_REGS (SImode
) * UNITS_PER_WORD
)
8909 : ((sh_round_reg (cum
, mode
)
8910 + HARD_REGNO_NREGS (BASE_ARG_REG (mode
), mode
))
8911 <= NPARM_REGS (mode
)))
8912 : sh_round_reg (cum
, mode
) < NPARM_REGS (mode
)));
8916 sh_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
8917 tree type
, bool named ATTRIBUTE_UNUSED
)
8919 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8923 && sh_pass_in_reg_p (*cum
, mode
, type
)
8924 && !(TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
8925 && (sh_round_reg (*cum
, mode
)
8927 ? CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
8928 : CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
))
8929 > NPARM_REGS (mode
)))
8930 words
= NPARM_REGS (mode
) - sh_round_reg (*cum
, mode
);
8932 else if (!TARGET_SHCOMPACT
8933 && SH5_WOULD_BE_PARTIAL_NREGS (*cum
, mode
, type
, named
))
8934 words
= NPARM_REGS (SImode
) - cum
->arg_count
[SH_ARG_INT
];
8936 return words
* UNITS_PER_WORD
;
8940 /* Define where to put the arguments to a function.
8941 Value is zero to push the argument on the stack,
8942 or a hard register in which to store the argument.
8944 MODE is the argument's machine mode.
8945 TYPE is the data type of the argument (as a tree).
8946 This is null for libcalls where that information may
8948 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8949 the preceding args and about the function being called.
8950 NAMED is nonzero if this argument is a named parameter
8951 (otherwise it is an extra parameter matching an ellipsis).
8953 On SH the first args are normally in registers
8954 and the rest are pushed. Any arg that starts within the first
8955 NPARM_REGS words is at least partially passed in a register unless
8956 its data type forbids. */
8958 sh_function_arg (cumulative_args_t ca_v
, machine_mode mode
,
8959 const_tree type
, bool named
)
8961 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
8963 if (! TARGET_SH5
&& mode
== VOIDmode
)
8964 return GEN_INT (ca
->renesas_abi
? 1 : 0);
8967 && sh_pass_in_reg_p (*ca
, mode
, type
)
8968 && (named
|| ! (TARGET_HITACHI
|| ca
->renesas_abi
)))
8972 if (mode
== SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
8973 && (! FUNCTION_ARG_SCmode_WART
|| (sh_round_reg (*ca
, mode
) & 1)))
8975 rtx r1
= gen_rtx_EXPR_LIST (VOIDmode
,
8976 gen_rtx_REG (SFmode
,
8978 + (sh_round_reg (*ca
, mode
) ^ 1)),
8980 rtx r2
= gen_rtx_EXPR_LIST (VOIDmode
,
8981 gen_rtx_REG (SFmode
,
8983 + ((sh_round_reg (*ca
, mode
) + 1) ^ 1)),
8985 return gen_rtx_PARALLEL(SCmode
, gen_rtvec(2, r1
, r2
));
8988 /* If the alignment of a DF value causes an SF register to be
8989 skipped, we will use that skipped register for the next SF
8991 if ((TARGET_HITACHI
|| ca
->renesas_abi
)
8992 && ca
->free_single_fp_reg
8994 return gen_rtx_REG (mode
, ca
->free_single_fp_reg
);
8996 regno
= (BASE_ARG_REG (mode
) + sh_round_reg (*ca
, mode
))
8997 ^ (mode
== SFmode
&& TARGET_SH4
8998 && TARGET_LITTLE_ENDIAN
8999 && ! TARGET_HITACHI
&& ! ca
->renesas_abi
);
9000 return gen_rtx_REG (mode
, regno
);
9006 if (mode
== VOIDmode
&& TARGET_SHCOMPACT
)
9007 return GEN_INT (ca
->call_cookie
);
9009 /* The following test assumes unnamed arguments are promoted to
9011 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
9012 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
, ca
->free_single_fp_reg
);
9014 if ((GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
)
9015 && (named
|| ! ca
->prototype_p
)
9016 && ca
->arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (SFmode
))
9018 if (! ca
->prototype_p
&& TARGET_SHMEDIA
)
9019 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca
, mode
);
9021 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
,
9023 + ca
->arg_count
[(int) SH_ARG_FLOAT
]);
9026 if (ca
->arg_count
[(int) SH_ARG_INT
] < NPARM_REGS (SImode
)
9027 && (! TARGET_SHCOMPACT
9028 || (! SHCOMPACT_FORCE_ON_STACK (mode
, type
)
9029 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca
, mode
,
9032 return gen_rtx_REG (mode
, (FIRST_PARM_REG
9033 + ca
->arg_count
[(int) SH_ARG_INT
]));
9042 /* Update the data in CUM to advance over an argument
9043 of mode MODE and data type TYPE.
9044 (TYPE is null for libcalls where that information may not be
9047 sh_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
9048 const_tree type
, bool named
)
9050 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
9054 else if (TARGET_SH5
)
9056 const_tree type2
= (ca
->byref
&& type
9059 machine_mode mode2
= (ca
->byref
&& type
9062 int dwords
= ((ca
->byref
9065 ? int_size_in_bytes (type2
)
9066 : GET_MODE_SIZE (mode2
)) + 7) / 8;
9067 int numregs
= MIN (dwords
, NPARM_REGS (SImode
)
9068 - ca
->arg_count
[(int) SH_ARG_INT
]);
9072 ca
->arg_count
[(int) SH_ARG_INT
] += numregs
;
9073 if (TARGET_SHCOMPACT
9074 && SHCOMPACT_FORCE_ON_STACK (mode2
, type2
))
9077 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9079 /* N.B. We want this also for outgoing. */
9080 ca
->stack_regs
+= numregs
;
9085 ca
->stack_regs
+= numregs
;
9086 ca
->byref_regs
+= numregs
;
9090 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9094 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
9097 else if (dwords
> numregs
)
9099 int pushregs
= numregs
;
9101 if (TARGET_SHCOMPACT
)
9102 ca
->stack_regs
+= numregs
;
9103 while (pushregs
< NPARM_REGS (SImode
) - 1
9104 && (CALL_COOKIE_INT_REG_GET
9106 NPARM_REGS (SImode
) - pushregs
)
9110 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
9114 if (numregs
== NPARM_REGS (SImode
))
9116 |= CALL_COOKIE_INT_REG (0, 1)
9117 | CALL_COOKIE_STACKSEQ (numregs
- 1);
9120 |= CALL_COOKIE_STACKSEQ (numregs
);
9123 if (GET_SH_ARG_CLASS (mode2
) == SH_ARG_FLOAT
9124 && (named
|| ! ca
->prototype_p
))
9126 if (mode2
== SFmode
&& ca
->free_single_fp_reg
)
9127 ca
->free_single_fp_reg
= 0;
9128 else if (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9129 < NPARM_REGS (SFmode
))
9132 = MIN ((GET_MODE_SIZE (mode2
) + 7) / 8 * 2,
9134 - ca
->arg_count
[(int) SH_ARG_FLOAT
]);
9136 ca
->arg_count
[(int) SH_ARG_FLOAT
] += numfpregs
;
9138 if (TARGET_SHCOMPACT
&& ! ca
->prototype_p
)
9140 if (ca
->outgoing
&& numregs
> 0)
9144 |= (CALL_COOKIE_INT_REG
9145 (ca
->arg_count
[(int) SH_ARG_INT
]
9146 - numregs
+ ((numfpregs
- 2) / 2),
9147 4 + (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9150 while (numfpregs
-= 2);
9152 else if (mode2
== SFmode
&& (named
)
9153 && (ca
->arg_count
[(int) SH_ARG_FLOAT
]
9154 < NPARM_REGS (SFmode
)))
9155 ca
->free_single_fp_reg
9156 = FIRST_FP_PARM_REG
- numfpregs
9157 + ca
->arg_count
[(int) SH_ARG_FLOAT
] + 1;
9163 if ((TARGET_HITACHI
|| ca
->renesas_abi
) && TARGET_FPU_DOUBLE
)
9165 /* Note that we've used the skipped register. */
9166 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
9168 ca
->free_single_fp_reg
= 0;
9171 /* When we have a DF after an SF, there's an SF register that get
9172 skipped in order to align the DF value. We note this skipped
9173 register, because the next SF value will use it, and not the
9174 SF that follows the DF. */
9176 && sh_round_reg (*ca
, DFmode
) != sh_round_reg (*ca
, SFmode
))
9178 ca
->free_single_fp_reg
= (sh_round_reg (*ca
, SFmode
)
9179 + BASE_ARG_REG (mode
));
9183 if (! ((TARGET_SH4
|| TARGET_SH2A
) || ca
->renesas_abi
)
9184 || sh_pass_in_reg_p (*ca
, mode
, type
))
9185 (ca
->arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
9186 = (sh_round_reg (*ca
, mode
)
9188 ? CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
)
9189 : CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))));
9192 /* The Renesas calling convention doesn't quite fit into this scheme since
9193 the address is passed like an invisible argument, but one that is always
9194 passed in memory. */
9196 sh_struct_value_rtx (tree fndecl
, int incoming ATTRIBUTE_UNUSED
)
9198 if (TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
9200 return gen_rtx_REG (Pmode
, 2);
9203 /* Worker function for TARGET_FUNCTION_VALUE.
9205 For the SH, this is like LIBCALL_VALUE, except that we must change the
9206 mode like PROMOTE_MODE does.
9207 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
9208 tested here has to be kept in sync with the one in
9209 explow.c:promote_mode. */
9211 sh_function_value (const_tree valtype
,
9212 const_tree fn_decl_or_type
,
9213 bool outgoing ATTRIBUTE_UNUSED
)
9216 && !DECL_P (fn_decl_or_type
))
9217 fn_decl_or_type
= NULL
;
9219 return gen_rtx_REG (
9220 ((GET_MODE_CLASS (TYPE_MODE (valtype
)) == MODE_INT
9221 && GET_MODE_SIZE (TYPE_MODE (valtype
)) < 4
9222 && (TREE_CODE (valtype
) == INTEGER_TYPE
9223 || TREE_CODE (valtype
) == ENUMERAL_TYPE
9224 || TREE_CODE (valtype
) == BOOLEAN_TYPE
9225 || TREE_CODE (valtype
) == REAL_TYPE
9226 || TREE_CODE (valtype
) == OFFSET_TYPE
))
9227 && sh_promote_prototypes (fn_decl_or_type
)
9228 ? (TARGET_SHMEDIA64
? DImode
: SImode
) : TYPE_MODE (valtype
)),
9229 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype
)));
9232 /* Worker function for TARGET_LIBCALL_VALUE. */
9234 sh_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
9236 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG (mode
));
9239 /* Return true if N is a possible register number of function value. */
9241 sh_function_value_regno_p (const unsigned int regno
)
9243 return ((regno
) == FIRST_RET_REG
9244 || (TARGET_SH2E
&& (regno
) == FIRST_FP_RET_REG
)
9245 || (TARGET_SHMEDIA_FPU
&& (regno
) == FIRST_FP_RET_REG
));
9248 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9250 sh_return_in_memory (const_tree type
, const_tree fndecl
)
9254 if (TYPE_MODE (type
) == BLKmode
)
9255 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)) > 8;
9257 return GET_MODE_SIZE (TYPE_MODE (type
)) > 8;
9261 return (TYPE_MODE (type
) == BLKmode
9262 || ((TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
9263 && TREE_CODE (type
) == RECORD_TYPE
));
9267 /* We actually emit the code in sh_expand_prologue. We used to use
9268 a static variable to flag that we need to emit this code, but that
9269 doesn't when inlining, when functions are deferred and then emitted
9270 later. Fortunately, we already have two flags that are part of struct
9271 function that tell if a function uses varargs or stdarg. */
9273 sh_setup_incoming_varargs (cumulative_args_t ca
,
9276 int *pretend_arg_size
,
9277 int second_time ATTRIBUTE_UNUSED
)
9279 gcc_assert (cfun
->stdarg
);
9280 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl
))
9282 int named_parm_regs
, anon_parm_regs
;
9284 named_parm_regs
= (sh_round_reg (*get_cumulative_args (ca
), mode
)
9286 ? CEIL (int_size_in_bytes (type
), UNITS_PER_WORD
)
9287 : CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)));
9288 anon_parm_regs
= NPARM_REGS (SImode
) - named_parm_regs
;
9289 if (anon_parm_regs
> 0)
9290 *pretend_arg_size
= anon_parm_regs
* 4;
9295 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
9301 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v
)
9303 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
9305 return ! (TARGET_HITACHI
|| ca
->renesas_abi
) && ! TARGET_SH5
;
9309 /* Define the offset between two registers, one to be eliminated, and
9310 the other its replacement, at the start of a routine. */
9312 initial_elimination_offset (int from
, int to
)
9315 int regs_saved_rounding
= 0;
9316 int total_saved_regs_space
;
9317 int total_auto_space
;
9318 int save_flags
= target_flags
;
9320 HARD_REG_SET live_regs_mask
;
9322 shmedia_space_reserved_for_target_registers
= false;
9323 regs_saved
= calc_live_regs (&live_regs_mask
);
9324 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
9326 if (shmedia_reserve_space_for_target_registers_p (regs_saved
, &live_regs_mask
))
9328 shmedia_space_reserved_for_target_registers
= true;
9329 regs_saved
+= shmedia_target_regs_stack_adjust (&live_regs_mask
);
9332 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
9333 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
9334 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
9336 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
9337 copy_flags
= target_flags
;
9338 target_flags
= save_flags
;
9340 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
9342 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9343 return total_saved_regs_space
+ total_auto_space
9344 + crtl
->args
.info
.byref_regs
* 8;
9346 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9347 return total_saved_regs_space
+ total_auto_space
9348 + crtl
->args
.info
.byref_regs
* 8;
9350 /* Initial gap between fp and sp is 0. */
9351 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9354 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9355 return rounded_frame_size (0);
9357 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9358 return rounded_frame_size (0);
9360 gcc_assert (from
== RETURN_ADDRESS_POINTER_REGNUM
9361 && (to
== HARD_FRAME_POINTER_REGNUM
9362 || to
== STACK_POINTER_REGNUM
));
9365 int n
= total_saved_regs_space
;
9366 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
9367 save_schedule schedule
;
9370 n
+= total_auto_space
;
9372 /* If it wasn't saved, there's not much we can do. */
9373 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
9376 target_flags
= copy_flags
;
9378 sh5_schedule_saves (&live_regs_mask
, &schedule
, n
);
9379 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
9380 if (entry
->reg
== pr_reg
)
9382 target_flags
= save_flags
;
9383 return entry
->offset
;
9388 return total_auto_space
;
9391 /* Parse the -mfixed-range= option string. */
9393 sh_fix_range (const char *const_str
)
9396 char *str
, *dash
, *comma
;
9398 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
9399 REG2 are either register names or register numbers. The effect
9400 of this option is to mark the registers in the range from REG1 to
9401 REG2 as ``fixed'' so they won't be used by the compiler. */
9403 i
= strlen (const_str
);
9404 str
= (char *) alloca (i
+ 1);
9405 memcpy (str
, const_str
, i
+ 1);
9409 dash
= strchr (str
, '-');
9412 warning (0, "value of -mfixed-range must have form REG1-REG2");
9416 comma
= strchr (dash
+ 1, ',');
9420 first
= decode_reg_name (str
);
9423 warning (0, "unknown register name: %s", str
);
9427 last
= decode_reg_name (dash
+ 1);
9430 warning (0, "unknown register name: %s", dash
+ 1);
9438 warning (0, "%s-%s is an empty range", str
, dash
+ 1);
9442 for (i
= first
; i
<= last
; ++i
)
9443 fixed_regs
[i
] = call_used_regs
[i
] = 1;
9453 /* Insert any deferred function attributes from earlier pragmas. */
9455 sh_insert_attributes (tree node
, tree
*attributes
)
9459 if (TREE_CODE (node
) != FUNCTION_DECL
)
9462 /* We are only interested in fields. */
9466 /* Append the attributes to the deferred attributes. */
9467 *sh_deferred_function_attributes_tail
= *attributes
;
9468 attrs
= sh_deferred_function_attributes
;
9472 /* Some attributes imply or require the interrupt attribute. */
9473 if (!lookup_attribute ("interrupt_handler", attrs
)
9474 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node
)))
9476 /* If we have a trapa_handler, but no interrupt_handler attribute,
9477 insert an interrupt_handler attribute. */
9478 if (lookup_attribute ("trapa_handler", attrs
) != NULL_TREE
)
9479 /* We can't use sh_pr_interrupt here because that's not in the
9482 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE
, attrs
);
9483 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
9484 if the interrupt attribute is missing, we ignore the attribute
9486 else if (lookup_attribute ("sp_switch", attrs
)
9487 || lookup_attribute ("trap_exit", attrs
)
9488 || lookup_attribute ("nosave_low_regs", attrs
)
9489 || lookup_attribute ("resbank", attrs
))
9493 for (tail
= attributes
; attrs
; attrs
= TREE_CHAIN (attrs
))
9495 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs
))
9496 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs
))
9497 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs
))
9498 || is_attribute_p ("resbank", TREE_PURPOSE (attrs
)))
9499 warning (OPT_Wattributes
,
9500 "%qE attribute only applies to interrupt functions",
9501 TREE_PURPOSE (attrs
));
9504 *tail
= tree_cons (TREE_PURPOSE (attrs
), NULL_TREE
,
9506 tail
= &TREE_CHAIN (*tail
);
9509 attrs
= *attributes
;
9513 /* Install the processed list. */
9514 *attributes
= attrs
;
9516 /* Clear deferred attributes. */
9517 sh_deferred_function_attributes
= NULL_TREE
;
9518 sh_deferred_function_attributes_tail
= &sh_deferred_function_attributes
;
9523 /*------------------------------------------------------------------------------
9524 Target specific attributes
9525 Supported attributes are:
9528 Specifies this function is an interrupt handler.
9531 Like interrupt_handler, but don't save all registers.
9534 Specifies an alternate stack for an interrupt handler to run on.
9537 Use a trapa to exit an interrupt function instead of rte.
9540 Don't save r0..r7 in an interrupt handler function.
9541 This is useful on SH3* and SH4*, which have a separate set of low
9542 regs for user and privileged modes.
9543 This is mainly to be used for non-reentrant interrupt handlers (i.e.
9544 those that run with interrupts disabled and thus can't be
9545 interrupted thenselves).
9548 Use Renesas calling/layout conventions (functions and structures).
9551 In case of an interrupt handler function, use a register bank to
9552 save registers R0-R14, MACH, MACL, GBR and PR.
9553 This is available only on SH2A targets.
9556 Declares a function to be called using the TBR relative addressing
9557 mode. Takes an argument that specifies the slot number in the table
9558 where this function can be looked up by the JSR/N @@(disp8,TBR) insn.
9561 /* Handle a 'resbank' attribute. */
9563 sh_handle_resbank_handler_attribute (tree
* node
, tree name
,
9564 tree args ATTRIBUTE_UNUSED
,
9565 int flags ATTRIBUTE_UNUSED
,
9566 bool * no_add_attrs
)
9570 warning (OPT_Wattributes
, "%qE attribute is supported only for SH2A",
9572 *no_add_attrs
= true;
9574 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9576 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9578 *no_add_attrs
= true;
9584 /* Handle an "interrupt_handler" attribute; arguments as in
9585 struct attribute_spec.handler. */
9587 sh_handle_interrupt_handler_attribute (tree
*node
, tree name
,
9588 tree args ATTRIBUTE_UNUSED
,
9589 int flags ATTRIBUTE_UNUSED
,
9592 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9594 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9596 *no_add_attrs
= true;
9598 else if (TARGET_SHCOMPACT
)
9600 error ("attribute interrupt_handler is not compatible with -m5-compact");
9601 *no_add_attrs
= true;
9607 /* Handle an 'function_vector' attribute; arguments as in
9608 struct attribute_spec.handler. */
9610 sh2a_handle_function_vector_handler_attribute (tree
* node
, tree name
,
9611 tree args ATTRIBUTE_UNUSED
,
9612 int flags ATTRIBUTE_UNUSED
,
9613 bool * no_add_attrs
)
9617 warning (OPT_Wattributes
, "%qE attribute only applies to SH2A",
9619 *no_add_attrs
= true;
9621 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
9623 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9625 *no_add_attrs
= true;
9627 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9629 /* The argument must be a constant integer. */
9630 warning (OPT_Wattributes
,
9631 "%qE attribute argument not an integer constant",
9633 *no_add_attrs
= true;
9635 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
9637 /* The argument value must be between 0 to 255. */
9638 warning (OPT_Wattributes
,
9639 "%qE attribute argument should be between 0 to 255",
9641 *no_add_attrs
= true;
9646 /* Returns true if current function has been assigned the attribute
9647 'function_vector'. */
9649 sh2a_is_function_vector_call (rtx x
)
9651 if (GET_CODE (x
) == SYMBOL_REF
9652 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9654 tree tr
= SYMBOL_REF_DECL (x
);
9656 if (sh2a_function_vector_p (tr
))
9663 /* Returns the function vector number, if the attribute
9664 'function_vector' is assigned, otherwise returns zero. */
9666 sh2a_get_function_vector_number (rtx x
)
9671 if ((GET_CODE (x
) == SYMBOL_REF
)
9672 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
9674 t
= SYMBOL_REF_DECL (x
);
9676 if (TREE_CODE (t
) != FUNCTION_DECL
)
9679 list
= SH_ATTRIBUTES (t
);
9682 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9684 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
9688 list
= TREE_CHAIN (list
);
9697 /* Handle an "sp_switch" attribute; arguments as in
9698 struct attribute_spec.handler. */
9700 sh_handle_sp_switch_attribute (tree
*node
, tree name
, tree args
,
9701 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9703 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9705 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9707 *no_add_attrs
= true;
9709 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
9711 /* The argument must be a constant string. */
9712 warning (OPT_Wattributes
, "%qE attribute argument not a string constant",
9714 *no_add_attrs
= true;
9720 /* Handle an "trap_exit" attribute; arguments as in
9721 struct attribute_spec.handler. */
9723 sh_handle_trap_exit_attribute (tree
*node
, tree name
, tree args
,
9724 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
9726 if (TREE_CODE (*node
) != FUNCTION_DECL
)
9728 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
9730 *no_add_attrs
= true;
9732 /* The argument specifies a trap number to be used in a trapa instruction
9733 at function exit (instead of an rte instruction). */
9734 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
9736 /* The argument must be a constant integer. */
9737 warning (OPT_Wattributes
, "%qE attribute argument not an "
9738 "integer constant", name
);
9739 *no_add_attrs
= true;
9746 sh_handle_renesas_attribute (tree
*node ATTRIBUTE_UNUSED
,
9747 tree name ATTRIBUTE_UNUSED
,
9748 tree args ATTRIBUTE_UNUSED
,
9749 int flags ATTRIBUTE_UNUSED
,
9750 bool *no_add_attrs ATTRIBUTE_UNUSED
)
9755 /* True if __attribute__((renesas)) or -mrenesas. */
9757 sh_attr_renesas_p (const_tree td
)
9761 if (td
== NULL_TREE
)
9764 td
= TREE_TYPE (td
);
9765 if (td
== error_mark_node
)
9767 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td
))
9771 /* True if __attribute__((renesas)) or -mrenesas, for the current
9774 sh_cfun_attr_renesas_p (void)
9776 return sh_attr_renesas_p (current_function_decl
);
9779 /* Returns true if the current function has the "interrupt_handler"
9782 sh_cfun_interrupt_handler_p (void)
9784 return (lookup_attribute ("interrupt_handler",
9785 DECL_ATTRIBUTES (current_function_decl
))
9789 /* Returns true if FUNC has been assigned the attribute
9790 "function_vector". */
9792 sh2a_function_vector_p (tree func
)
9795 if (TREE_CODE (func
) != FUNCTION_DECL
)
9798 list
= SH_ATTRIBUTES (func
);
9801 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
9804 list
= TREE_CHAIN (list
);
9809 /* Returns true if given tree has the "resbank" attribute set. */
9811 sh_cfun_resbank_handler_p (void)
9813 return ((lookup_attribute ("resbank",
9814 DECL_ATTRIBUTES (current_function_decl
))
9816 && (lookup_attribute ("interrupt_handler",
9817 DECL_ATTRIBUTES (current_function_decl
))
9818 != NULL_TREE
) && TARGET_SH2A
);
9821 /* Returns true if the current function has a "trap_exit" attribute set. */
9823 sh_cfun_trap_exit_p (void)
9825 return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl
))
9829 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
9831 sh_check_pch_target_flags (int old_flags
)
9833 if ((old_flags
^ target_flags
) & (MASK_SH1
| MASK_SH2
| MASK_SH3
9834 | MASK_SH_E
| MASK_HARD_SH4
9835 | MASK_FPU_SINGLE
| MASK_SH4
))
9836 return _("created and used with different architectures / ABIs");
9837 if ((old_flags
^ target_flags
) & MASK_HITACHI
)
9838 return _("created and used with different ABIs");
9839 if ((old_flags
^ target_flags
) & MASK_LITTLE_ENDIAN
)
9840 return _("created and used with different endianness");
9844 /* Predicates used by the templates. */
9846 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
9847 Used only in general_movsrc_operand. */
9849 system_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
9861 /* Returns true if OP is a floating point value with value 0.0. */
9863 fp_zero_operand (rtx op
)
9867 if (GET_MODE (op
) != SFmode
)
9870 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
9871 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
9874 /* Returns true if OP is a floating point value with value 1.0. */
9876 fp_one_operand (rtx op
)
9880 if (GET_MODE (op
) != SFmode
)
9883 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
9884 return REAL_VALUES_EQUAL (r
, dconst1
);
9887 /* Return the TLS type for TLS symbols. */
9889 tls_symbolic_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
9891 if (GET_CODE (op
) != SYMBOL_REF
)
9892 return TLS_MODEL_NONE
;
9893 return SYMBOL_REF_TLS_MODEL (op
);
9896 /* Return the destination address of a branch. */
9898 branch_dest (rtx branch
)
9900 rtx dest
= SET_SRC (PATTERN (branch
));
9903 if (GET_CODE (dest
) == IF_THEN_ELSE
)
9904 dest
= XEXP (dest
, 1);
9905 dest
= XEXP (dest
, 0);
9906 dest_uid
= INSN_UID (dest
);
9907 return INSN_ADDRESSES (dest_uid
);
9910 /* Return nonzero if REG is not used after INSN.
9911 We assume REG is a reload reg, and therefore does
9912 not live past labels. It may live past calls or jumps though. */
9914 reg_unused_after (rtx reg
, rtx_insn
*insn
)
9919 /* If the reg is set by this instruction, then it is safe for our
9920 case. Disregard the case where this is a store to memory, since
9921 we are checking a register used in the store address. */
9922 set
= single_set (insn
);
9923 if (set
&& !MEM_P (SET_DEST (set
))
9924 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9927 while ((insn
= NEXT_INSN (insn
)))
9933 code
= GET_CODE (insn
);
9936 /* If this is a label that existed before reload, then the register
9937 is dead here. However, if this is a label added by reorg, then
9938 the register may still be live here. We can't tell the difference,
9939 so we just ignore labels completely. */
9940 if (code
== CODE_LABEL
)
9945 if (code
== JUMP_INSN
)
9948 /* If this is a sequence, we must handle them all at once.
9949 We could have for instance a call that sets the target register,
9950 and an insn in a delay slot that uses the register. In this case,
9951 we must return 0. */
9952 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
9954 rtx_sequence
*seq
= as_a
<rtx_sequence
*> (PATTERN (insn
));
9958 for (i
= 0; i
< seq
->len (); i
++)
9960 rtx_insn
*this_insn
= seq
->insn (i
);
9961 rtx set
= single_set (this_insn
);
9963 if (CALL_P (this_insn
))
9965 else if (JUMP_P (this_insn
))
9967 if (INSN_ANNULLED_BRANCH_P (this_insn
))
9972 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
9974 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9976 if (!MEM_P (SET_DEST (set
)))
9982 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
9987 else if (code
== JUMP_INSN
)
9991 set
= single_set (insn
);
9992 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
9994 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
9995 return !MEM_P (SET_DEST (set
));
9996 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
9999 if (code
== CALL_INSN
&& call_really_used_regs
[REGNO (reg
)])
10007 static GTY(()) rtx t_reg_rtx
;
10009 get_t_reg_rtx (void)
10012 t_reg_rtx
= gen_rtx_REG (SImode
, T_REG
);
10016 static GTY(()) tree fpscr_values
;
10019 emit_fpu_switch (rtx scratch
, int index
)
10023 if (fpscr_values
== NULL
)
10027 t
= build_index_type (integer_one_node
);
10028 t
= build_array_type (integer_type_node
, t
);
10029 t
= build_decl (BUILTINS_LOCATION
,
10030 VAR_DECL
, get_identifier ("__fpscr_values"), t
);
10031 DECL_ARTIFICIAL (t
) = 1;
10032 DECL_IGNORED_P (t
) = 1;
10033 DECL_EXTERNAL (t
) = 1;
10034 TREE_STATIC (t
) = 1;
10035 TREE_PUBLIC (t
) = 1;
10041 src
= DECL_RTL (fpscr_values
);
10042 if (!can_create_pseudo_p ())
10044 emit_move_insn (scratch
, XEXP (src
, 0));
10046 emit_insn (gen_addsi3 (scratch
, scratch
, GEN_INT (index
* 4)));
10047 src
= adjust_automodify_address (src
, SImode
, scratch
, index
* 4);
10050 src
= adjust_address (src
, SImode
, index
* 4);
10052 emit_insn (gen_lds_fpscr (src
));
10055 static rtx
get_free_reg (HARD_REG_SET
);
10057 /* This function returns a register to use to load the address to load
10058 the fpscr from. Currently it always returns r1 or r7, but when we are
10059 able to use pseudo registers after combine, or have a better mechanism
10060 for choosing a register, it should be done here. */
10061 /* REGS_LIVE is the liveness information for the point for which we
10062 need this allocation. In some bare-bones exit blocks, r1 is live at the
10063 start. We can even have all of r0..r3 being live:
10064 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
10065 INSN before which new insns are placed with will clobber the register
10066 we return. If a basic block consists only of setting the return value
10067 register to a pseudo and using that register, the return value is not
10068 live before or after this block, yet we we'll insert our insns right in
10071 get_free_reg (HARD_REG_SET regs_live
)
10073 if (! TEST_HARD_REG_BIT (regs_live
, 1))
10074 return gen_rtx_REG (Pmode
, 1);
10076 /* Hard reg 1 is live; since this is a small register classes target,
10077 there shouldn't be anything but a jump before the function end. */
10078 gcc_assert (!TEST_HARD_REG_BIT (regs_live
, 7));
10079 return gen_rtx_REG (Pmode
, 7);
10082 /* This function will set the fpscr from memory.
10083 MODE is the mode we are setting it to. */
10085 fpscr_set_from_mem (int mode
, HARD_REG_SET regs_live
)
10087 enum attr_fp_mode fp_mode
= (enum attr_fp_mode
) mode
;
10088 enum attr_fp_mode norm_mode
= ACTUAL_NORMAL_MODE (FP_MODE
);
10091 addr_reg
= !can_create_pseudo_p () ? get_free_reg (regs_live
) : NULL_RTX
;
10092 emit_fpu_switch (addr_reg
, fp_mode
== norm_mode
);
10095 /* Is the given character a logical line separator for the assembler? */
10096 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
10097 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
10101 sequence_insn_p (rtx_insn
*insn
)
10103 rtx_insn
*prev
, *next
;
10105 prev
= PREV_INSN (insn
);
10109 next
= NEXT_INSN (prev
);
10113 return INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
;
10117 sh_insn_length_adjustment (rtx_insn
*insn
)
10119 /* Instructions with unfilled delay slots take up an extra two bytes for
10120 the nop in the delay slot. */
10121 if (((NONJUMP_INSN_P (insn
)
10122 && GET_CODE (PATTERN (insn
)) != USE
10123 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10124 || CALL_P (insn
) || JUMP_P (insn
))
10125 && ! sequence_insn_p (insn
)
10126 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
10129 /* SH2e has a bug that prevents the use of annulled branches, so if
10130 the delay slot is not filled, we'll have to put a NOP in it. */
10131 if (sh_cpu_attr
== CPU_SH2E
10133 && get_attr_type (insn
) == TYPE_CBRANCH
10134 && ! sequence_insn_p (insn
))
10137 /* sh-dsp parallel processing insn take four bytes instead of two. */
10139 if (NONJUMP_INSN_P (insn
))
10142 rtx body
= PATTERN (insn
);
10145 bool maybe_label
= true;
10147 if (GET_CODE (body
) == ASM_INPUT
)
10148 templ
= XSTR (body
, 0);
10149 else if (asm_noperands (body
) >= 0)
10151 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
, NULL
);
10156 int ppi_adjust
= 0;
10160 while (c
== ' ' || c
== '\t');
10161 /* all sh-dsp parallel-processing insns start with p.
10162 The only non-ppi sh insn starting with p is pref.
10163 The only ppi starting with pr is prnd. */
10164 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", templ
, 2))
10166 /* The repeat pseudo-insn expands two three insns, a total of
10167 six bytes in size. */
10168 else if ((c
== 'r' || c
== 'R')
10169 && ! strncasecmp ("epeat", templ
, 5))
10171 while (c
&& c
!= '\n'
10172 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
, templ
))
10174 /* If this is a label, it is obviously not a ppi insn. */
10175 if (c
== ':' && maybe_label
)
10180 else if (c
== '\'' || c
== '"')
10181 maybe_label
= false;
10185 maybe_label
= c
!= ':';
10193 /* Return TRUE for a valid displacement for the REG+disp addressing
10196 sh_legitimate_index_p (machine_mode mode
, rtx op
, bool consider_sh2a
,
10199 if (! CONST_INT_P (op
))
10202 if (TARGET_SHMEDIA
)
10206 /* Check if this is the address of an unaligned load / store. */
10207 if (mode
== VOIDmode
)
10208 return satisfies_constraint_I06 (op
);
10210 size
= GET_MODE_SIZE (mode
);
10211 return (!(INTVAL (op
) & (size
- 1))
10212 && INTVAL (op
) >= -512 * size
10213 && INTVAL (op
) < 512 * size
);
10217 const HOST_WIDE_INT offset
= INTVAL (op
);
10218 const int max_disp
= sh_max_mov_insn_displacement (mode
, consider_sh2a
);
10219 const int align_mask
= mov_insn_alignment_mask (mode
, consider_sh2a
);
10221 /* If the mode does not support any displacement always return false.
10222 Even though an index of '0' is actually always valid, it will cause
10223 troubles when e.g. a DFmode move is split into two SFmode moves,
10224 where one SFmode move will have index '0' and the other move will
10226 if (!allow_zero
&& max_disp
< 1)
10229 return offset
>= 0 && offset
<= max_disp
&& (offset
& align_mask
) == 0;
10233 /* Recognize an RTL expression that is a valid memory address for
10235 The MODE argument is the machine mode for the MEM expression
10236 that wants to use this address.
10245 sh_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
10247 if (! ALLOW_INDEXED_ADDRESS
10248 && GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0)) && REG_P (XEXP (x
, 1)))
10251 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
10254 if (MAYBE_BASE_REGISTER_RTX_P (x
, strict
))
10256 else if ((GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
10257 && ! TARGET_SHMEDIA
10258 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x
, 0), strict
))
10260 else if (GET_CODE (x
) == PLUS
)
10262 rtx xop0
= XEXP (x
, 0);
10263 rtx xop1
= XEXP (x
, 1);
10265 if (REG_P (xop0
) && REGNO (xop0
) == GBR_REG
)
10266 return gbr_displacement (xop1
, mode
);
10268 if (GET_MODE_SIZE (mode
) <= 8
10269 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
)
10270 && sh_legitimate_index_p (mode
, xop1
, TARGET_SH2A
, false))
10273 if ((ALLOW_INDEXED_ADDRESS
|| GET_MODE (x
) == DImode
10274 || ((xop0
== stack_pointer_rtx
10275 || xop0
== hard_frame_pointer_rtx
)
10276 && REG_P (xop1
) && REGNO (xop1
) == R0_REG
)
10277 || ((xop1
== stack_pointer_rtx
10278 || xop1
== hard_frame_pointer_rtx
)
10279 && REG_P (xop0
) && REGNO (xop0
) == R0_REG
))
10280 && ((!TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 4)
10281 || (TARGET_SHMEDIA
&& GET_MODE_SIZE (mode
) <= 8)
10282 || ((TARGET_SH4
|| TARGET_SH2A_DOUBLE
)
10283 && TARGET_FMOVD
&& mode
== DFmode
)))
10285 if (MAYBE_BASE_REGISTER_RTX_P (xop1
, strict
)
10286 && MAYBE_INDEX_REGISTER_RTX_P (xop0
, strict
))
10288 if (MAYBE_INDEX_REGISTER_RTX_P (xop1
, strict
)
10289 && MAYBE_BASE_REGISTER_RTX_P (xop0
, strict
))
10297 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
10298 isn't protected by a PIC unspec. */
10300 nonpic_symbol_mentioned_p (rtx x
)
10305 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
10306 || GET_CODE (x
) == PC
)
10309 /* We don't want to look into the possible MEM location of a
10310 CONST_DOUBLE, since we're not going to use it, in general. */
10311 if (GET_CODE (x
) == CONST_DOUBLE
)
10314 if (GET_CODE (x
) == UNSPEC
10315 && (XINT (x
, 1) == UNSPEC_PIC
10316 || XINT (x
, 1) == UNSPEC_GOT
10317 || XINT (x
, 1) == UNSPEC_GOTOFF
10318 || XINT (x
, 1) == UNSPEC_GOTPLT
10319 || XINT (x
, 1) == UNSPEC_GOTTPOFF
10320 || XINT (x
, 1) == UNSPEC_DTPOFF
10321 || XINT (x
, 1) == UNSPEC_TPOFF
10322 || XINT (x
, 1) == UNSPEC_PLT
10323 || XINT (x
, 1) == UNSPEC_SYMOFF
10324 || XINT (x
, 1) == UNSPEC_PCREL_SYMOFF
))
10327 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
10328 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
10333 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10334 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
10337 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
10344 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
10345 @GOTOFF in `reg'. */
10347 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
10350 if (tls_symbolic_operand (orig
, Pmode
) != TLS_MODEL_NONE
)
10353 if (GET_CODE (orig
) == LABEL_REF
10354 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
10356 if (reg
== NULL_RTX
)
10357 reg
= gen_reg_rtx (Pmode
);
10359 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
10362 else if (GET_CODE (orig
) == SYMBOL_REF
)
10364 if (reg
== NULL_RTX
)
10365 reg
= gen_reg_rtx (Pmode
);
10367 emit_insn (gen_symGOT2reg (reg
, orig
));
10373 /* Given a (logical) mode size and an offset in bytes, try to find a the
10374 appropriate displacement value for a mov insn. On SH the displacements
10375 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
10376 15 bytes in QImode. To compensate this we create a new base address by
10377 adding an adjustment value to it.
10379 If the originally requested offset is greater than 127 we prefer using
10380 values 124..127 over 128..131 to increase opportunities to use the
10383 In some cases it is possible that a requested offset might seem unaligned
10384 or inappropriate for the mode size, like offset = 2 and mode size = 4.
10385 This is compensated by adjusting the base address so that the effective
10386 address of the displacement move insn will be aligned.
10388 This is not the best possible way of rebasing the base address, as it
10389 does not look at other present displacement addressings around it.
10390 In some cases this can create more base address adjustments than would
10391 actually be necessary. */
10398 static struct disp_adjust
10399 sh_find_mov_disp_adjust (machine_mode mode
, HOST_WIDE_INT offset
)
10401 struct disp_adjust res
= { NULL_RTX
, NULL_RTX
};
10403 /* Do not try to use SH2A's large displacements here, because this would
10404 effectively disable the small displacement insns. */
10405 const int mode_sz
= GET_MODE_SIZE (mode
);
10406 const int mov_insn_sz
= mov_insn_size (mode
, false);
10407 const int max_disp
= sh_max_mov_insn_displacement (mode
, false);
10408 const int max_disp_next
= max_disp
+ mov_insn_sz
;
10409 HOST_WIDE_INT align_modifier
= offset
> 127 ? mov_insn_sz
: 0;
10410 HOST_WIDE_INT offset_adjust
;
10412 /* In some cases this actually does happen and we must check for it. */
10413 if (mode_sz
< 1 || mode_sz
> 8 || max_disp
< 1)
10416 /* Keeps the previous behavior for QImode displacement addressing.
10417 This just decides how the offset is re-based. Removing this special
10418 case will result in slightly bigger code on average, but it's not that
10420 if (mov_insn_sz
== 1)
10421 align_modifier
= 0;
10423 offset_adjust
= ((offset
+ align_modifier
) & ~max_disp
) - align_modifier
;
10425 if (mode_sz
+ offset
- offset_adjust
<= max_disp_next
)
10427 res
.offset_adjust
= GEN_INT (offset_adjust
);
10428 res
.mov_disp
= GEN_INT (offset
- offset_adjust
);
10434 /* Try to modify an illegitimate address and make it legitimate.
10435 If we find one, return the new, valid address.
10436 Otherwise, return the original address. */
10438 sh_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
10441 x
= legitimize_pic_address (oldx
, mode
, NULL_RTX
);
10443 if (TARGET_SHMEDIA
)
10446 if (((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
10447 || (TARGET_SH2E
&& mode
== SFmode
))
10450 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1))
10451 && BASE_REGISTER_RTX_P (XEXP (x
, 0)))
10453 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
,
10454 INTVAL (XEXP (x
, 1)));
10456 if (adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
10458 rtx sum
= expand_binop (Pmode
, add_optab
, XEXP (x
, 0),
10459 adj
.offset_adjust
, NULL_RTX
, 0,
10461 return gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
10467 /* Attempt to replace *p, which is an address that needs reloading, with
10468 a valid memory address for an operand of mode MODE.
10469 Like for sh_legitimize_address, for the SH we try to get a normal form
10470 of the address. That will allow inheritance of the address reloads. */
10472 sh_legitimize_reload_address (rtx
*p
, machine_mode mode
, int opnum
,
10475 enum reload_type type
= (enum reload_type
) itype
;
10476 const int mode_sz
= GET_MODE_SIZE (mode
);
10478 if (! ALLOW_INDEXED_ADDRESS
10479 && GET_CODE (*p
) == PLUS
10480 && REG_P (XEXP (*p
, 0)) && REG_P (XEXP (*p
, 1)))
10482 *p
= copy_rtx (*p
);
10483 push_reload (*p
, NULL_RTX
, p
, NULL
,
10484 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10488 if (! ALLOW_INDEXED_ADDRESS
10489 && GET_CODE (*p
) == PLUS
10490 && GET_CODE (XEXP (*p
, 0)) == PLUS
)
10492 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (XEXP (*p
, 0), 0),
10493 XEXP (XEXP (*p
, 0), 1));
10494 *p
= gen_rtx_PLUS (Pmode
, sum
, XEXP (*p
, 1));
10495 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10496 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10500 if (TARGET_SHMEDIA
)
10503 if (GET_CODE (*p
) == PLUS
&& CONST_INT_P (XEXP (*p
, 1))
10504 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p
, 0), true)
10505 && (ALLOW_INDEXED_ADDRESS
10506 || XEXP (*p
, 0) == stack_pointer_rtx
10507 || XEXP (*p
, 0) == hard_frame_pointer_rtx
))
10509 const HOST_WIDE_INT offset
= INTVAL (XEXP (*p
, 1));
10510 struct disp_adjust adj
= sh_find_mov_disp_adjust (mode
, offset
);
10512 if (TARGET_SH2A
&& mode
== DFmode
&& (offset
& 0x7))
10514 push_reload (*p
, NULL_RTX
, p
, NULL
,
10515 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10519 if (TARGET_SH2E
&& mode
== SFmode
)
10521 *p
= copy_rtx (*p
);
10522 push_reload (*p
, NULL_RTX
, p
, NULL
,
10523 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10527 /* FIXME: Do not allow to legitimize QImode and HImode displacement
10528 moves because then reload has a problem figuring the constraint
10529 that the move insn target/source reg must be R0.
10530 Or maybe some handling is wrong in sh_secondary_reload for this
10531 to work properly? */
10532 if ((mode_sz
== 4 || mode_sz
== 8)
10533 && ! (TARGET_SH4
&& mode
== DFmode
)
10534 && adj
.offset_adjust
!= NULL_RTX
&& adj
.mov_disp
!= NULL_RTX
)
10536 rtx sum
= gen_rtx_PLUS (Pmode
, XEXP (*p
, 0), adj
.offset_adjust
);
10537 *p
= gen_rtx_PLUS (Pmode
, sum
, adj
.mov_disp
);
10538 push_reload (sum
, NULL_RTX
, &XEXP (*p
, 0), NULL
,
10539 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10544 /* We must re-recognize what we created before. */
10545 if (GET_CODE (*p
) == PLUS
10546 && (mode_sz
== 4 || mode_sz
== 8)
10547 && GET_CODE (XEXP (*p
, 0)) == PLUS
10548 && CONST_INT_P (XEXP (XEXP (*p
, 0), 1))
10549 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p
, 0), 0), true)
10550 && CONST_INT_P (XEXP (*p
, 1))
10551 && ! (TARGET_SH2E
&& mode
== SFmode
))
10553 /* Because this address is so complex, we know it must have
10554 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
10555 it is already unshared, and needs no further unsharing. */
10556 push_reload (XEXP (*p
, 0), NULL_RTX
, &XEXP (*p
, 0), NULL
,
10557 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
, type
);
10564 /* In the name of slightly smaller debug output, and to cater to
10565 general assembler lossage, recognize various UNSPEC sequences
10566 and turn them back into a direct symbol reference. */
10568 sh_delegitimize_address (rtx orig_x
)
10572 orig_x
= delegitimize_mem_from_attrs (orig_x
);
10577 if (GET_CODE (x
) == CONST
)
10580 if (GET_CODE (y
) == UNSPEC
)
10582 if (XINT (y
, 1) == UNSPEC_GOT
10583 || XINT (y
, 1) == UNSPEC_GOTOFF
10584 || XINT (y
, 1) == UNSPEC_SYMOFF
)
10585 return XVECEXP (y
, 0, 0);
10586 else if (XINT (y
, 1) == UNSPEC_PCREL_SYMOFF
)
10588 if (GET_CODE (XVECEXP (y
, 0, 0)) == CONST
)
10590 rtx symplt
= XEXP (XVECEXP (y
, 0, 0), 0);
10592 if (GET_CODE (symplt
) == UNSPEC
10593 && XINT (symplt
, 1) == UNSPEC_PLT
)
10594 return XVECEXP (symplt
, 0, 0);
10597 else if (TARGET_SHMEDIA
10598 && (XINT (y
, 1) == UNSPEC_EXTRACT_S16
10599 || XINT (y
, 1) == UNSPEC_EXTRACT_U16
))
10601 rtx offset
= XVECEXP (y
, 0, 1);
10603 x
= gen_rtx_PLUS (Pmode
, XVECEXP (y
, 0, 0), offset
);
10604 if (MEM_P (orig_x
))
10605 x
= replace_equiv_address_nv (orig_x
, x
);
10614 /* Mark the use of a constant in the literal table. If the constant
10615 has multiple labels, make it unique. */
10617 mark_constant_pool_use (rtx x
)
10619 rtx_insn
*insn
, *lab
;
10625 switch (GET_CODE (x
))
10635 /* Get the first label in the list of labels for the same constant
10636 and delete another labels in the list. */
10637 lab
= as_a
<rtx_insn
*> (x
);
10638 for (insn
= PREV_INSN (lab
); insn
; insn
= PREV_INSN (insn
))
10640 if (!LABEL_P (insn
)
10641 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
10646 for (rtx insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
10647 as_a
<rtx_insn
*> (insn
)->set_deleted ();
10649 /* Mark constants in a window. */
10650 for (insn
= NEXT_INSN (as_a
<rtx_insn
*> (x
)); insn
; insn
= NEXT_INSN (insn
))
10652 if (!NONJUMP_INSN_P (insn
))
10655 pattern
= PATTERN (insn
);
10656 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
10659 switch (XINT (pattern
, 1))
10661 case UNSPECV_CONST2
:
10662 case UNSPECV_CONST4
:
10663 case UNSPECV_CONST8
:
10664 XVECEXP (pattern
, 0, 1) = const1_rtx
;
10666 case UNSPECV_WINDOW_END
:
10667 if (XVECEXP (pattern
, 0, 0) == x
)
10670 case UNSPECV_CONST_END
:
10680 /* Return true if it's possible to redirect BRANCH1 to the destination
10681 of an unconditional jump BRANCH2. We only want to do this if the
10682 resulting branch will have a short displacement. */
10684 sh_can_redirect_branch (rtx_insn
*branch1
, rtx_insn
*branch2
)
10686 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
10688 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
10692 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10693 insn
&& distance
< 256;
10694 insn
= PREV_INSN (insn
))
10699 distance
+= get_attr_length (insn
);
10701 for (distance
= 0, insn
= NEXT_INSN (branch1
);
10702 insn
&& distance
< 256;
10703 insn
= NEXT_INSN (insn
))
10708 distance
+= get_attr_length (insn
);
10714 /* Return nonzero if register old_reg can be renamed to register new_reg. */
10716 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
10717 unsigned int new_reg
)
10719 /* Interrupt functions can only use registers that have already been
10720 saved by the prologue, even if they would normally be
10722 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg
))
10728 /* Function to update the integer COST
10729 based on the relationship between INSN that is dependent on
10730 DEP_INSN through the dependence LINK. The default is to make no
10731 adjustment to COST. This can be used for example to specify to
10732 the scheduler that an output- or anti-dependence does not incur
10733 the same cost as a data-dependence. The return value should be
10734 the new value for COST. */
10736 sh_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
10737 rtx_insn
*dep_insn
, int cost
)
10741 if (TARGET_SHMEDIA
)
10743 /* On SHmedia, if the dependence is an anti-dependence or
10744 output-dependence, there is no cost. */
10745 if (REG_NOTE_KIND (link
) != 0)
10747 /* However, dependencies between target register loads and
10748 uses of the register in a subsequent block that are separated
10749 by a conditional branch are not modelled - we have to do with
10750 the anti-dependency between the target register load and the
10751 conditional branch that ends the current block. */
10752 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
10753 && GET_CODE (PATTERN (dep_insn
)) == SET
10754 && (get_attr_type (dep_insn
) == TYPE_PT_MEDIA
10755 || get_attr_type (dep_insn
) == TYPE_PTABS_MEDIA
)
10756 && get_attr_type (insn
) == TYPE_CBRANCH_MEDIA
)
10758 int orig_cost
= cost
;
10759 rtx note
= find_reg_note (insn
, REG_BR_PROB
, 0);
10760 rtx target
= ((!note
|| XINT (note
, 0) * 2 < REG_BR_PROB_BASE
)
10761 ? insn
: JUMP_LABEL (insn
));
10762 /* On the likely path, the branch costs 1, on the unlikely path,
10766 target
= next_active_insn (target
);
10767 while (target
&& ! flow_dependent_p (target
, dep_insn
)
10769 /* If two branches are executed in immediate succession, with the
10770 first branch properly predicted, this causes a stall at the
10771 second branch, hence we won't need the target for the
10772 second branch for two cycles after the launch of the first
10774 if (cost
> orig_cost
- 2)
10775 cost
= orig_cost
- 2;
10781 else if (get_attr_is_mac_media (insn
)
10782 && get_attr_is_mac_media (dep_insn
))
10785 else if (! reload_completed
10786 && GET_CODE (PATTERN (insn
)) == SET
10787 && GET_CODE (SET_SRC (PATTERN (insn
))) == FLOAT
10788 && GET_CODE (PATTERN (dep_insn
)) == SET
10789 && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn
)), VOIDmode
)
10792 /* Schedule the ptabs for a casesi_jump_media in preference to stuff
10793 that is needed at the target. */
10794 else if (get_attr_type (insn
) == TYPE_JUMP_MEDIA
10795 && ! flow_dependent_p (insn
, dep_insn
))
10798 else if (REG_NOTE_KIND (link
) == 0)
10800 enum attr_type type
;
10803 if (recog_memoized (insn
) < 0
10804 || recog_memoized (dep_insn
) < 0)
10807 dep_set
= single_set (dep_insn
);
10809 /* The latency that we specify in the scheduling description refers
10810 to the actual output, not to an auto-increment register; for that,
10811 the latency is one. */
10812 if (dep_set
&& MEM_P (SET_SRC (dep_set
)) && cost
> 1)
10814 rtx set
= single_set (insn
);
10817 && !reg_mentioned_p (SET_DEST (dep_set
), SET_SRC (set
))
10818 && (!MEM_P (SET_DEST (set
))
10819 || !reg_mentioned_p (SET_DEST (dep_set
),
10820 XEXP (SET_DEST (set
), 0))))
10823 /* The only input for a call that is timing-critical is the
10824 function's address. */
10827 rtx call
= get_call_rtx_from (insn
);
10829 /* sibcalli_thunk uses a symbol_ref in an unspec. */
10830 && (GET_CODE (XEXP (XEXP (call
, 0), 0)) == UNSPEC
10831 || ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
)))
10832 cost
-= TARGET_SH4_300
? 3 : 6;
10834 /* Likewise, the most timing critical input for an sfuncs call
10835 is the function address. However, sfuncs typically start
10836 using their arguments pretty quickly.
10837 Assume a four cycle delay for SH4 before they are needed.
10838 Cached ST40-300 calls are quicker, so assume only a one
10840 ??? Maybe we should encode the delays till input registers
10841 are needed by sfuncs into the sfunc call insn. */
10842 /* All sfunc calls are parallels with at least four components.
10843 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
10844 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
10845 && XVECLEN (PATTERN (insn
), 0) >= 4
10846 && (reg
= sfunc_uses_reg (insn
)))
10848 if (! reg_set_p (reg
, dep_insn
))
10849 cost
-= TARGET_SH4_300
? 1 : 4;
10851 if (TARGET_HARD_SH4
&& !TARGET_SH4_300
)
10853 enum attr_type dep_type
= get_attr_type (dep_insn
);
10855 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
10857 else if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
10858 && (type
= get_attr_type (insn
)) != TYPE_CALL
10859 && type
!= TYPE_SFUNC
)
10861 /* When the preceding instruction loads the shift amount of
10862 the following SHAD/SHLD, the latency of the load is increased
10864 if (get_attr_type (insn
) == TYPE_DYN_SHIFT
10865 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
10866 && reg_overlap_mentioned_p (SET_DEST (dep_set
),
10867 XEXP (SET_SRC (single_set (insn
)),
10870 /* When an LS group instruction with a latency of less than
10871 3 cycles is followed by a double-precision floating-point
10872 instruction, FIPR, or FTRV, the latency of the first
10873 instruction is increased to 3 cycles. */
10875 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
10876 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
10878 /* The lsw register of a double-precision computation is ready one
10880 else if (reload_completed
10881 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
10882 && (use_pat
= single_set (insn
))
10883 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
10884 SET_SRC (use_pat
)))
10887 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
10888 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
10891 else if (TARGET_SH4_300
)
10893 /* Stores need their input register two cycles later. */
10894 if (dep_set
&& cost
>= 1
10895 && ((type
= get_attr_type (insn
)) == TYPE_STORE
10896 || type
== TYPE_PSTORE
10897 || type
== TYPE_FSTORE
|| type
== TYPE_MAC_MEM
))
10899 rtx set
= single_set (insn
);
10901 if (!reg_mentioned_p (SET_SRC (set
), XEXP (SET_DEST (set
), 0))
10902 && rtx_equal_p (SET_SRC (set
), SET_DEST (dep_set
)))
10905 /* But don't reduce the cost below 1 if the address depends
10906 on a side effect of dep_insn. */
10908 && modified_in_p (XEXP (SET_DEST (set
), 0), dep_insn
))
10914 /* An anti-dependence penalty of two applies if the first insn is a double
10915 precision fadd / fsub / fmul. */
10916 else if (!TARGET_SH4_300
10917 && REG_NOTE_KIND (link
) == REG_DEP_ANTI
10918 && recog_memoized (dep_insn
) >= 0
10919 && (get_attr_type (dep_insn
) == TYPE_DFP_ARITH
10920 || get_attr_type (dep_insn
) == TYPE_DFP_MUL
)
10921 /* A lot of alleged anti-flow dependences are fake,
10922 so check this one is real. */
10923 && flow_dependent_p (dep_insn
, insn
))
10929 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
10930 if DEP_INSN is anti-flow dependent on INSN. */
10932 flow_dependent_p (rtx insn
, rtx dep_insn
)
10934 rtx tmp
= PATTERN (insn
);
10936 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
10937 return tmp
== NULL_RTX
;
10940 /* A helper function for flow_dependent_p called through note_stores. */
10942 flow_dependent_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
10944 rtx
* pinsn
= (rtx
*) data
;
10946 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
10950 /* For use by sh_allocate_initial_value. Note that sh.md contains some
10951 'special function' patterns (type sfunc) that clobber pr, but that
10952 do not look like function calls to leaf_function_p. Hence we must
10953 do this extra check. */
10955 sh_pr_n_sets (void)
10957 return DF_REG_DEF_COUNT (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
10960 /* Return where to allocate pseudo for a given hard register initial
10963 sh_allocate_initial_value (rtx hard_reg
)
10967 if (REGNO (hard_reg
) == (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
))
10970 && ! sh_pr_n_sets ()
10971 && ! (TARGET_SHCOMPACT
10972 && ((crtl
->args
.info
.call_cookie
10973 & ~ CALL_COOKIE_RET_TRAMP (1))
10974 || crtl
->saves_all_registers
)))
10977 x
= gen_frame_mem (Pmode
, return_address_pointer_rtx
);
10985 /* This function returns "2" to indicate dual issue for the SH4
10986 processor. To be used by the DFA pipeline description. */
10988 sh_issue_rate (void)
10990 if (TARGET_SUPERSCALAR
)
10996 /* Functions for ready queue reordering for sched1. */
10998 /* Get weight for mode for a set x. */
11000 find_set_regmode_weight (rtx x
, machine_mode mode
)
11002 if (GET_CODE (x
) == CLOBBER
&& register_operand (SET_DEST (x
), mode
))
11004 if (GET_CODE (x
) == SET
&& register_operand (SET_DEST (x
), mode
))
11006 if (REG_P (SET_DEST (x
)))
11008 if (!reg_mentioned_p (SET_DEST (x
), SET_SRC (x
)))
11018 /* Get regmode weight for insn. */
11020 find_insn_regmode_weight (rtx insn
, machine_mode mode
)
11022 short reg_weight
= 0;
11025 /* Increment weight for each register born here. */
11026 x
= PATTERN (insn
);
11027 reg_weight
+= find_set_regmode_weight (x
, mode
);
11028 if (GET_CODE (x
) == PARALLEL
)
11031 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
11033 x
= XVECEXP (PATTERN (insn
), 0, j
);
11034 reg_weight
+= find_set_regmode_weight (x
, mode
);
11037 /* Decrement weight for each register that dies here. */
11038 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
11040 if (REG_NOTE_KIND (x
) == REG_DEAD
|| REG_NOTE_KIND (x
) == REG_UNUSED
)
11042 rtx note
= XEXP (x
, 0);
11043 if (REG_P (note
) && GET_MODE (note
) == mode
)
11050 /* Calculate regmode weights for all insns of a basic block. */
11052 find_regmode_weight (basic_block b
, machine_mode mode
)
11054 rtx_insn
*insn
, *next_tail
, *head
, *tail
;
11056 get_ebb_head_tail (b
, b
, &head
, &tail
);
11057 next_tail
= NEXT_INSN (tail
);
11059 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
11061 /* Handle register life information. */
11062 if (!INSN_P (insn
))
11065 if (mode
== SFmode
)
11066 INSN_REGMODE_WEIGHT (insn
, mode
) =
11067 find_insn_regmode_weight (insn
, mode
)
11068 + 2 * find_insn_regmode_weight (insn
, DFmode
);
11069 else if (mode
== SImode
)
11070 INSN_REGMODE_WEIGHT (insn
, mode
) =
11071 find_insn_regmode_weight (insn
, mode
)
11072 + 2 * find_insn_regmode_weight (insn
, DImode
);
11076 /* Comparison function for ready queue sorting. */
11078 rank_for_reorder (const void *x
, const void *y
)
11080 rtx_insn
*tmp
= *(rtx_insn
* const *) y
;
11081 rtx_insn
*tmp2
= *(rtx_insn
* const *) x
;
11083 /* The insn in a schedule group should be issued the first. */
11084 if (SCHED_GROUP_P (tmp
) != SCHED_GROUP_P (tmp2
))
11085 return SCHED_GROUP_P (tmp2
) ? 1 : -1;
11087 /* If insns are equally good, sort by INSN_LUID (original insn order), This
11088 minimizes instruction movement, thus minimizing sched's effect on
11089 register pressure. */
11090 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
11093 /* Resort the array A in which only element at index N may be out of order. */
11095 swap_reorder (rtx_insn
**a
, int n
)
11097 rtx_insn
*insn
= a
[n
- 1];
11100 while (i
>= 0 && rank_for_reorder (a
+ i
, &insn
) >= 0)
11108 /* Sort the ready list by ascending priority. */
11110 ready_reorder (rtx_insn
**ready
, int nready
)
11113 swap_reorder (ready
, nready
);
11114 else if (nready
> 2)
11115 qsort (ready
, nready
, sizeof (rtx_insn
*), rank_for_reorder
);
11118 /* Count life regions of r0 for a block. */
11120 find_r0_life_regions (basic_block b
)
11122 rtx_insn
*end
, *insn
;
11129 if (REGNO_REG_SET_P (df_get_live_in (b
), R0_REG
))
11140 insn
= BB_HEAD (b
);
11142 r0_reg
= gen_rtx_REG (SImode
, R0_REG
);
11147 if (find_regno_note (insn
, REG_DEAD
, R0_REG
))
11153 && (pset
= single_set (insn
))
11154 && reg_overlap_mentioned_p (r0_reg
, SET_DEST (pset
))
11155 && !find_regno_note (insn
, REG_UNUSED
, R0_REG
))
11163 insn
= NEXT_INSN (insn
);
11165 return set
- death
;
11168 /* Calculate regmode weights for all insns of all basic block. */
11170 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED
,
11171 int verbose ATTRIBUTE_UNUSED
,
11176 regmode_weight
[0] = (short *) xcalloc (old_max_uid
, sizeof (short));
11177 regmode_weight
[1] = (short *) xcalloc (old_max_uid
, sizeof (short));
11178 r0_life_regions
= 0;
11180 FOR_EACH_BB_REVERSE_FN (b
, cfun
)
11182 find_regmode_weight (b
, SImode
);
11183 find_regmode_weight (b
, SFmode
);
11184 if (!reload_completed
)
11185 r0_life_regions
+= find_r0_life_regions (b
);
11188 CURR_REGMODE_PRESSURE (SImode
) = 0;
11189 CURR_REGMODE_PRESSURE (SFmode
) = 0;
11194 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
11195 int verbose ATTRIBUTE_UNUSED
)
11197 if (regmode_weight
[0])
11199 free (regmode_weight
[0]);
11200 regmode_weight
[0] = NULL
;
11202 if (regmode_weight
[1])
11204 free (regmode_weight
[1]);
11205 regmode_weight
[1] = NULL
;
11209 /* The scalar modes supported differs from the default version in TImode
11210 for 32-bit SHMEDIA. */
11212 sh_scalar_mode_supported_p (machine_mode mode
)
11214 if (TARGET_SHMEDIA32
&& mode
== TImode
)
11217 return default_scalar_mode_supported_p (mode
);
11220 /* Cache the can_issue_more so that we can return it from reorder2. Also,
11221 keep count of register pressures on SImode and SFmode. */
11223 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
11224 int sched_verbose ATTRIBUTE_UNUSED
,
11226 int can_issue_more
)
11228 if (GET_CODE (PATTERN (insn
)) != USE
11229 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
11230 cached_can_issue_more
= can_issue_more
- 1;
11232 cached_can_issue_more
= can_issue_more
;
11234 if (reload_completed
)
11235 return cached_can_issue_more
;
11237 CURR_REGMODE_PRESSURE (SImode
) += INSN_REGMODE_WEIGHT (insn
, SImode
);
11238 CURR_REGMODE_PRESSURE (SFmode
) += INSN_REGMODE_WEIGHT (insn
, SFmode
);
11240 return cached_can_issue_more
;
11244 sh_md_init (FILE *dump ATTRIBUTE_UNUSED
,
11245 int verbose ATTRIBUTE_UNUSED
,
11246 int veclen ATTRIBUTE_UNUSED
)
11248 CURR_REGMODE_PRESSURE (SImode
) = 0;
11249 CURR_REGMODE_PRESSURE (SFmode
) = 0;
11252 /* Some magic numbers. */
11253 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
11254 functions that already have high pressure on r0. */
11255 #define R0_MAX_LIFE_REGIONS 2
11256 /* Register Pressure thresholds for SImode and SFmode registers. */
11257 #define SIMODE_MAX_WEIGHT 5
11258 #define SFMODE_MAX_WEIGHT 10
11260 /* Return true if the pressure is high for MODE. */
11262 high_pressure (machine_mode mode
)
11264 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
11265 functions that already have high pressure on r0. */
11266 if (r0_life_regions
>= R0_MAX_LIFE_REGIONS
)
11269 if (mode
== SFmode
)
11270 return (CURR_REGMODE_PRESSURE (SFmode
) > SFMODE_MAX_WEIGHT
);
11272 return (CURR_REGMODE_PRESSURE (SImode
) > SIMODE_MAX_WEIGHT
);
11275 /* Reorder ready queue if register pressure is high. */
11277 sh_reorder (FILE *dump ATTRIBUTE_UNUSED
,
11278 int sched_verbose ATTRIBUTE_UNUSED
,
11281 int clock_var ATTRIBUTE_UNUSED
)
11283 if (reload_completed
)
11284 return sh_issue_rate ();
11286 if (high_pressure (SFmode
) || high_pressure (SImode
))
11288 ready_reorder (ready
, *n_readyp
);
11291 return sh_issue_rate ();
11294 /* Skip cycles if the current register pressure is high. */
11296 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
11297 int sched_verbose ATTRIBUTE_UNUSED
,
11298 rtx_insn
**ready ATTRIBUTE_UNUSED
,
11299 int *n_readyp ATTRIBUTE_UNUSED
,
11300 int clock_var ATTRIBUTE_UNUSED
)
11302 if (reload_completed
)
11303 return cached_can_issue_more
;
11305 if (high_pressure(SFmode
) || high_pressure (SImode
))
11308 return cached_can_issue_more
;
11311 /* Skip cycles without sorting the ready queue. This will move insn from
11312 Q->R. If this is the last cycle we are skipping; allow sorting of ready
11313 queue by sh_reorder. */
11315 /* Generally, skipping these many cycles are sufficient for all insns to move
11317 #define MAX_SKIPS 8
11320 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED
,
11321 int sched_verbose ATTRIBUTE_UNUSED
,
11322 rtx_insn
*insn ATTRIBUTE_UNUSED
,
11323 int last_clock_var
,
11327 if (reload_completed
)
11332 if ((clock_var
- last_clock_var
) < MAX_SKIPS
)
11337 /* If this is the last cycle we are skipping, allow reordering of R. */
11338 if ((clock_var
- last_clock_var
) == MAX_SKIPS
)
11350 /* SHmedia requires registers for branches, so we can't generate new
11351 branches past reload. */
11353 sh_cannot_modify_jumps_p (void)
11355 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
11359 sh_target_reg_class (void)
11361 return TARGET_SHMEDIA
? TARGET_REGS
: NO_REGS
;
11365 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
)
11367 if (! shmedia_space_reserved_for_target_registers
)
11369 if (after_prologue_epilogue_gen
&& ! TARGET_SAVE_ALL_TARGET_REGS
)
11372 HARD_REG_SET dummy
;
11373 if (calc_live_regs (&dummy
) >= 6 * 8)
11379 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED
)
11381 return (TARGET_SH5
|| TARGET_HITACHI
|| sh_attr_renesas_p (record_type
));
11385 On the SH1..SH4, the trampoline looks like
11386 2 0002 D202 mov.l l2,r2
11387 1 0000 D301 mov.l l1,r3
11388 3 0004 422B jmp @r2
11390 5 0008 00000000 l1: .long area
11391 6 000c 00000000 l2: .long function
11393 SH5 (compact) uses r1 instead of r3 for the static chain. */
11396 /* Emit RTL insns to initialize the variable parts of a trampoline.
11397 FNADDR is an RTX for the address of the function's pure code.
11398 CXT is an RTX for the static chain value for the function. */
11400 sh_trampoline_init (rtx tramp_mem
, tree fndecl
, rtx cxt
)
11402 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
11403 rtx tramp
= force_reg (Pmode
, XEXP (tramp_mem
, 0));
11405 if (TARGET_SHMEDIA64
)
11410 rtx movi1
= GEN_INT (0xcc000010);
11411 rtx shori1
= GEN_INT (0xc8000010);
11414 /* The following trampoline works within a +- 128 KB range for cxt:
11415 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
11416 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
11417 gettr tr1,r1; blink tr0,r63 */
11418 /* Address rounding makes it hard to compute the exact bounds of the
11419 offset for this trampoline, but we have a rather generous offset
11420 range, so frame_offset should do fine as an upper bound. */
11421 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
11423 /* ??? could optimize this trampoline initialization
11424 by writing DImode words with two insns each. */
11425 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
11426 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
11427 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
11428 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11429 /* Or in ptb/u .,tr1 pattern */
11430 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
11431 insn
= force_operand (insn
, NULL_RTX
);
11432 insn
= gen_lowpart (SImode
, insn
);
11433 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
), insn
);
11434 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
11435 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11436 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
11437 insn
= gen_lowpart (SImode
, insn
);
11438 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4), insn
);
11439 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
11440 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11441 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11442 insn
= gen_lowpart (SImode
, insn
);
11443 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), insn
);
11444 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
11445 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11446 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11447 insn
= gen_lowpart (SImode
, insn
);
11448 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), insn
);
11449 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
11450 insn
= gen_rtx_AND (DImode
, insn
, mask
);
11451 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
11452 insn
= gen_lowpart (SImode
, insn
);
11453 emit_move_insn (adjust_address (tramp_mem
, SImode
, 16), insn
);
11454 emit_move_insn (adjust_address (tramp_mem
, SImode
, 20),
11455 GEN_INT (0x6bf10600));
11456 emit_move_insn (adjust_address (tramp_mem
, SImode
, 24),
11457 GEN_INT (0x4415fc10));
11458 emit_move_insn (adjust_address (tramp_mem
, SImode
, 28),
11459 GEN_INT (0x4401fff0));
11460 emit_insn (gen_ic_invalidate_line (tramp
));
11463 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
11464 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
11466 tramp_templ
= gen_datalabel_ref (tramp_templ
);
11468 src
= gen_const_mem (BLKmode
, tramp_templ
);
11469 set_mem_align (dst
, 256);
11470 set_mem_align (src
, 64);
11471 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
11473 emit_move_insn (adjust_address (tramp_mem
, Pmode
, fixed_len
), fnaddr
);
11474 emit_move_insn (adjust_address (tramp_mem
, Pmode
,
11475 fixed_len
+ GET_MODE_SIZE (Pmode
)),
11477 emit_insn (gen_ic_invalidate_line (tramp
));
11480 else if (TARGET_SHMEDIA
)
11482 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
11483 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
11484 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
11485 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
11486 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
11487 rotated 10 right, and higher 16 bit of every 32 selected. */
11489 = force_reg (V2HImode
, (simplify_gen_subreg
11490 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
11491 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
11492 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
11494 fnaddr
= force_reg (SImode
, fnaddr
);
11495 cxt
= force_reg (SImode
, cxt
);
11496 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
11497 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
11499 emit_insn (gen_rotrdi3_mextr (quad0
, quad0
,
11500 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
11501 emit_insn (gen_ashldi3_media (quad0
, quad0
, const2_rtx
));
11502 emit_move_insn (change_address (tramp_mem
, DImode
, NULL_RTX
), quad0
);
11503 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
11504 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
11506 emit_insn (gen_rotrdi3_mextr (cxtload
, cxtload
,
11507 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
11508 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, const2_rtx
));
11509 if (TARGET_LITTLE_ENDIAN
)
11511 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
11512 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
11516 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
11517 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
11519 emit_move_insn (adjust_address (tramp_mem
, DImode
, 8), quad1
);
11520 emit_move_insn (adjust_address (tramp_mem
, DImode
, 16), quad2
);
11521 emit_insn (gen_ic_invalidate_line (tramp
));
11524 else if (TARGET_SHCOMPACT
)
11526 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
11529 emit_move_insn (change_address (tramp_mem
, SImode
, NULL_RTX
),
11530 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
11532 emit_move_insn (adjust_address (tramp_mem
, SImode
, 4),
11533 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
11535 emit_move_insn (adjust_address (tramp_mem
, SImode
, 8), cxt
);
11536 emit_move_insn (adjust_address (tramp_mem
, SImode
, 12), fnaddr
);
11537 if (TARGET_HARD_SH4
|| TARGET_SH5
)
11539 if (!TARGET_INLINE_IC_INVALIDATE
11540 || (!(TARGET_SH4A
|| TARGET_SH4_300
) && TARGET_USERMODE
))
11541 emit_library_call (function_symbol (NULL
, "__ic_invalidate",
11542 FUNCTION_ORDINARY
),
11543 LCT_NORMAL
, VOIDmode
, 1, tramp
, SImode
);
11545 emit_insn (gen_ic_invalidate_line (tramp
));
11549 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
11551 sh_trampoline_adjust_address (rtx tramp
)
11553 if (TARGET_SHMEDIA
)
11554 tramp
= expand_simple_binop (Pmode
, PLUS
, tramp
, const1_rtx
,
11555 gen_reg_rtx (Pmode
), 0, OPTAB_LIB_WIDEN
);
11559 /* FIXME: This is overly conservative. A SHcompact function that
11560 receives arguments ``by reference'' will have them stored in its
11561 own stack frame, so it must not pass pointers or references to
11562 these arguments to other functions by means of sibling calls. */
11563 /* If PIC, we cannot make sibling calls to global functions
11564 because the PLT requires r12 to be live. */
11566 sh_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
11569 && (! TARGET_SHCOMPACT
11570 || crtl
->args
.info
.stack_regs
== 0)
11571 && ! sh_cfun_interrupt_handler_p ()
11573 || (decl
&& ! TREE_PUBLIC (decl
))
11574 || (decl
&& DECL_VISIBILITY (decl
) != VISIBILITY_DEFAULT
)));
11577 /* Machine specific built-in functions. */
11579 struct builtin_description
11581 bool (* const is_enabled
) (void);
11582 const enum insn_code icode
;
11583 const char *const name
;
11589 shmedia_builtin_p (void)
11591 return TARGET_SHMEDIA
;
11594 /* This function can be used if there are any built-ins that are not for
11595 SHmedia. It's commented out to avoid the defined-but-unused warning. */
11597 sh1_builtin_p (void)
11602 /* describe number and signedness of arguments; arg[0] == result
11603 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
11604 /* 9: 64-bit pointer, 10: 32-bit pointer */
11605 static const char signature_args
[][4] =
11607 #define SH_BLTIN_V2SI2 0
11609 #define SH_BLTIN_V4HI2 1
11611 #define SH_BLTIN_V2SI3 2
11613 #define SH_BLTIN_V4HI3 3
11615 #define SH_BLTIN_V8QI3 4
11617 #define SH_BLTIN_MAC_HISI 5
11619 #define SH_BLTIN_SH_HI 6
11621 #define SH_BLTIN_SH_SI 7
11623 #define SH_BLTIN_V4HI2V2SI 8
11625 #define SH_BLTIN_V4HI2V8QI 9
11627 #define SH_BLTIN_SISF 10
11629 #define SH_BLTIN_LDUA_L 11
11631 #define SH_BLTIN_LDUA_Q 12
11633 #define SH_BLTIN_STUA_L 13
11635 #define SH_BLTIN_STUA_Q 14
11637 #define SH_BLTIN_LDUA_L64 15
11639 #define SH_BLTIN_LDUA_Q64 16
11641 #define SH_BLTIN_STUA_L64 17
11643 #define SH_BLTIN_STUA_Q64 18
11645 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
11646 #define SH_BLTIN_2 19
11647 #define SH_BLTIN_SU 19
11649 #define SH_BLTIN_3 20
11650 #define SH_BLTIN_SUS 20
11652 #define SH_BLTIN_PSSV 21
11654 #define SH_BLTIN_XXUU 22
11655 #define SH_BLTIN_UUUU 22
11657 #define SH_BLTIN_PV 23
11659 #define SH_BLTIN_VP 24
11661 #define SH_BLTIN_UV 25
11663 #define SH_BLTIN_VU 26
11666 /* mcmv: operands considered unsigned. */
11667 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
11668 /* mperm: control value considered unsigned int. */
11669 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
11670 /* mshards_q: returns signed short. */
11671 /* nsb: takes long long arg, returns unsigned char. */
11672 static struct builtin_description bdesc
[] =
11674 { shmedia_builtin_p
,
11675 CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
, 0 },
11676 { shmedia_builtin_p
,
11677 CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
, 0 },
11678 { shmedia_builtin_p
,
11679 CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
, 0 },
11680 { shmedia_builtin_p
,
11681 CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
, 0 },
11682 { shmedia_builtin_p
,
11683 CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
, 0 },
11684 { shmedia_builtin_p
,
11685 CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
, 0 },
11686 { shmedia_builtin_p
,
11687 CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
, 0 },
11688 { shmedia_builtin_p
,
11689 CODE_FOR_alloco_i
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
, 0 },
11690 { shmedia_builtin_p
,
11691 CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
, 0 },
11692 { shmedia_builtin_p
,
11693 CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
, 0 },
11694 { shmedia_builtin_p
,
11695 CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
, 0 },
11696 { shmedia_builtin_p
,
11697 CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
, 0 },
11698 { shmedia_builtin_p
,
11699 CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
, 0 },
11700 { shmedia_builtin_p
,
11701 CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
, 0 },
11702 { shmedia_builtin_p
,
11703 CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
, 0 },
11704 { shmedia_builtin_p
,
11705 CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
, 0 },
11706 { shmedia_builtin_p
,
11707 CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
, 0 },
11708 { shmedia_builtin_p
,
11709 CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
, 0 },
11710 { shmedia_builtin_p
,
11711 CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3
, 0 },
11712 { shmedia_builtin_p
,
11713 CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3
, 0 },
11714 { shmedia_builtin_p
,
11715 CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3
, 0 },
11716 { shmedia_builtin_p
,
11717 CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3
, 0 },
11718 { shmedia_builtin_p
,
11719 CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3
, 0 },
11720 { shmedia_builtin_p
,
11721 CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3
, 0 },
11722 { shmedia_builtin_p
,
11723 CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3
, 0 },
11724 { shmedia_builtin_p
,
11725 CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11726 { shmedia_builtin_p
,
11727 CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
, 0 },
11728 { shmedia_builtin_p
,
11729 CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, 0 },
11730 { shmedia_builtin_p
,
11731 CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
, 0 },
11732 { shmedia_builtin_p
,
11733 CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
, 0 },
11734 { shmedia_builtin_p
,
11735 CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
, 0 },
11736 { shmedia_builtin_p
,
11737 CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
, 0 },
11738 { shmedia_builtin_p
,
11739 CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11740 { shmedia_builtin_p
,
11741 CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
, 0 },
11742 { shmedia_builtin_p
,
11743 CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
, 0 },
11744 { shmedia_builtin_p
,
11745 CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
, 0 },
11746 { shmedia_builtin_p
,
11747 CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
, 0 },
11748 { shmedia_builtin_p
,
11749 CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
, 0 },
11750 { shmedia_builtin_p
,
11751 CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
, 0 },
11752 { shmedia_builtin_p
,
11753 CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
, 0 },
11754 { shmedia_builtin_p
,
11755 CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
, 0 },
11756 { shmedia_builtin_p
,
11757 CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
, 0 },
11758 { shmedia_builtin_p
,
11759 CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
, 0 },
11760 { shmedia_builtin_p
,
11761 CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
, 0 },
11762 { shmedia_builtin_p
,
11763 CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
, 0 },
11764 { shmedia_builtin_p
,
11765 CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
, 0 },
11766 { shmedia_builtin_p
,
11767 CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
, 0 },
11768 { shmedia_builtin_p
,
11769 CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
, 0 },
11770 { shmedia_builtin_p
,
11771 CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
, 0 },
11772 { shmedia_builtin_p
,
11773 CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
, 0 },
11774 { shmedia_builtin_p
,
11775 CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
, 0 },
11776 { shmedia_builtin_p
,
11777 CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
, 0 },
11778 { shmedia_builtin_p
,
11779 CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
, 0 },
11780 { shmedia_builtin_p
,
11781 CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
, 0 },
11782 { shmedia_builtin_p
,
11783 CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
, 0 },
11784 { shmedia_builtin_p
,
11785 CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
, 0 },
11786 { shmedia_builtin_p
,
11787 CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
, 0 },
11788 { shmedia_builtin_p
,
11789 CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
, 0 },
11790 { shmedia_builtin_p
,
11791 CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
, 0 },
11792 { shmedia_builtin_p
,
11793 CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
, 0 },
11794 { shmedia_builtin_p
,
11795 CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
, 0 },
11796 { shmedia_builtin_p
,
11797 CODE_FOR_sqrtdf2
, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2
, 0 },
11798 { shmedia_builtin_p
,
11799 CODE_FOR_sqrtsf2
, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2
, 0 },
11800 { shmedia_builtin_p
,
11801 CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
, 0 },
11802 { shmedia_builtin_p
,
11803 CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
, 0 },
11804 { shmedia_builtin_p
,
11805 CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
, 0 },
11806 { shmedia_builtin_p
,
11807 CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
, 0 },
11808 { shmedia_builtin_p
,
11809 CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
, 0 },
11810 { shmedia_builtin_p
,
11811 CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
, 0 },
11812 { shmedia_builtin_p
,
11813 CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
, 0 },
11814 { shmedia_builtin_p
,
11815 CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
, 0 },
11816 { shmedia_builtin_p
,
11817 CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
, 0 },
11818 { shmedia_builtin_p
,
11819 CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64
, 0 },
11820 { shmedia_builtin_p
,
11821 CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64
, 0 },
11822 { shmedia_builtin_p
,
11823 CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64
, 0 },
11824 { shmedia_builtin_p
,
11825 CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64
, 0 },
11826 { shmedia_builtin_p
,
11827 CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64
, 0 },
11828 { shmedia_builtin_p
,
11829 CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64
, 0 },
11830 { shmedia_builtin_p
,
11831 CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64
, 0 },
11832 { shmedia_builtin_p
,
11833 CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64
, 0 },
11834 { shmedia_builtin_p
,
11835 CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
, 0 },
11836 { shmedia_builtin_p
,
11837 CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
, 0 },
11838 { shmedia_builtin_p
,
11839 CODE_FOR_prefetch
, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV
, 0 },
11842 CODE_FOR_sts_fpscr
, "__builtin_sh_get_fpscr", SH_BLTIN_UV
, 0 },
11844 CODE_FOR_set_fpscr
, "__builtin_sh_set_fpscr", SH_BLTIN_VU
, 0 },
11848 sh_init_builtins (void)
11850 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
11851 memset (shared
, 0, sizeof shared
);
11853 for (unsigned int di
= 0; di
< ARRAY_SIZE (bdesc
); ++di
)
11855 builtin_description
* d
= &bdesc
[di
];
11857 if (!d
->is_enabled ())
11860 tree type
, arg_type
= NULL_TREE
;
11861 int signature
= d
->signature
;
11863 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
11864 type
= shared
[signature
];
11867 int has_result
= signature_args
[signature
][0] != 0;
11870 if ((signature_args
[signature
][1] & 8)
11871 && (((signature_args
[signature
][1] & 1) && TARGET_SHMEDIA32
)
11872 || ((signature_args
[signature
][1] & 2) && TARGET_SHMEDIA64
)))
11874 if (! TARGET_FPU_ANY
11875 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
11877 for (unsigned int i
= 0; i
< ARRAY_SIZE (args
); i
++)
11878 args
[i
] = NULL_TREE
;
11879 for (int i
= 3; ; i
--)
11881 int arg
= signature_args
[signature
][i
];
11882 int opno
= i
- 1 + has_result
;
11885 arg_type
= ptr_type_node
;
11887 arg_type
= (*lang_hooks
.types
.type_for_mode
)
11888 (insn_data
[d
->icode
].operand
[opno
].mode
, (arg
& 1));
11892 arg_type
= void_type_node
;
11895 args
[i
-1] = arg_type
;
11897 type
= build_function_type_list (arg_type
, args
[0], args
[1],
11898 args
[2], NULL_TREE
);
11899 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
11900 shared
[signature
] = type
;
11903 add_builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
11908 /* Implements target hook vector_mode_supported_p. */
11910 sh_vector_mode_supported_p (machine_mode mode
)
11913 && ((mode
== V2SFmode
)
11914 || (mode
== V4SFmode
)
11915 || (mode
== V16SFmode
)))
11918 else if (TARGET_SHMEDIA
11919 && ((mode
== V8QImode
)
11920 || (mode
== V2HImode
)
11921 || (mode
== V4HImode
)
11922 || (mode
== V2SImode
)))
11929 sh_frame_pointer_required (void)
11931 /* If needed override this in other tm.h files to cope with various OS
11932 lossage requiring a frame pointer. */
11933 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
11942 /* Implements target hook dwarf_calling_convention. Return an enum
11943 of dwarf_calling_convention. */
11945 sh_dwarf_calling_convention (const_tree func
)
11947 if (sh_attr_renesas_p (func
))
11948 return DW_CC_GNU_renesas_sh
;
11950 return DW_CC_normal
;
11953 /* Returns the sh builtin decl for CODE. */
11955 sh_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11957 if (code
>= ARRAY_SIZE (bdesc
))
11958 return error_mark_node
;
11960 if (!bdesc
[code
].is_enabled ())
11961 return error_mark_node
;
11963 return bdesc
[code
].fndecl
;
11966 /* Expand an expression EXP that calls a built-in function,
11967 with result going to TARGET if that's convenient
11968 (and in mode MODE if that's convenient).
11969 SUBTARGET may be used as the target for computing one of EXP's operands.
11970 IGNORE is nonzero if the value is to be ignored. */
11972 sh_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
11973 machine_mode mode ATTRIBUTE_UNUSED
, int ignore
)
11975 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11976 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11977 const struct builtin_description
*d
= &bdesc
[fcode
];
11978 enum insn_code icode
= d
->icode
;
11979 int signature
= d
->signature
;
11983 if (signature_args
[signature
][0])
11988 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11989 if (! target
|| GET_MODE (target
) != tmode
11990 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11991 target
= gen_reg_rtx (tmode
);
11992 op
[nop
++] = target
;
11997 for (int i
= 1; i
<= 3; i
++, nop
++)
12000 machine_mode opmode
, argmode
;
12003 if (! signature_args
[signature
][i
])
12005 arg
= CALL_EXPR_ARG (exp
, i
- 1);
12006 if (arg
== error_mark_node
)
12008 if (signature_args
[signature
][i
] & 8)
12011 optype
= ptr_type_node
;
12015 opmode
= insn_data
[icode
].operand
[nop
].mode
;
12016 optype
= (*lang_hooks
.types
.type_for_mode
) (opmode
, 0);
12018 argmode
= TYPE_MODE (TREE_TYPE (arg
));
12019 if (argmode
!= opmode
)
12020 arg
= build1 (NOP_EXPR
, optype
, arg
);
12021 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, EXPAND_NORMAL
);
12022 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
12023 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
12026 rtx pat
= NULL_RTX
;
12031 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
12034 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
12037 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
12040 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
12043 gcc_unreachable ();
12052 sh_expand_unop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
)
12054 rtx sel0
= const0_rtx
;
12055 rtx sel1
= const1_rtx
;
12056 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
, rtx
) = gen_unary_sf_op
;
12057 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
12059 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
12060 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
12064 sh_expand_binop_v2sf (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
12066 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
12068 emit_insn (gen_binary_sf_op0 (op0
, op1
, op2
, op
));
12069 emit_insn (gen_binary_sf_op1 (op0
, op1
, op2
, op
));
12072 /* Return true if hard register REGNO can hold a value of machine-mode MODE.
12073 We can allow any mode in any general register. The special registers
12074 only allow SImode. Don't allow any mode in the PR.
12076 We cannot hold DCmode values in the XD registers because alter_reg
12077 handles subregs of them incorrectly. We could work around this by
12078 spacing the XD registers like the DR registers, but this would require
12079 additional memory in every compilation to hold larger register vectors.
12080 We could hold SFmode / SCmode values in XD registers, but that
12081 would require a tertiary reload when reloading from / to memory,
12082 and a secondary reload to reload from / to general regs; that
12083 seems to be a losing proposition.
12085 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
12086 it won't be ferried through GP registers first. */
12088 sh_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
12090 if (SPECIAL_REGISTER_P (regno
))
12091 return mode
== SImode
;
12093 if (regno
== FPUL_REG
)
12094 return (mode
== SImode
|| mode
== SFmode
);
12096 if (FP_REGISTER_P (regno
) && mode
== SFmode
)
12099 if (mode
== V2SFmode
)
12101 if (((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 2 == 0)
12102 || GENERAL_REGISTER_P (regno
)))
12108 if (mode
== V4SFmode
)
12110 if ((FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 4 == 0)
12111 || GENERAL_REGISTER_P (regno
))
12117 if (mode
== V16SFmode
)
12119 if (TARGET_SHMEDIA
)
12121 if (FP_REGISTER_P (regno
) && (regno
- FIRST_FP_REG
) % 16 == 0)
12127 return regno
== FIRST_XD_REG
;
12130 if (FP_REGISTER_P (regno
))
12134 || ((TARGET_SH2E
|| TARGET_SHMEDIA
) && mode
== SCmode
)
12135 || ((((TARGET_SH4
|| TARGET_SH2A_DOUBLE
) && mode
== DFmode
)
12138 && (mode
== DFmode
|| mode
== DImode
12139 || mode
== V2SFmode
|| mode
== TImode
)))
12140 && ((regno
- FIRST_FP_REG
) & 1) == 0)
12141 || ((TARGET_SH4
|| TARGET_SHMEDIA
) && mode
== TImode
12142 && ((regno
- FIRST_FP_REG
) & 3) == 0))
12148 if (XD_REGISTER_P (regno
))
12149 return mode
== DFmode
;
12151 if (TARGET_REGISTER_P (regno
))
12152 return (mode
== DImode
|| mode
== SImode
|| mode
== PDImode
);
12154 if (regno
== PR_REG
)
12155 return mode
== SImode
;
12157 if (regno
== FPSCR_REG
)
12158 return mode
== SImode
;
12160 /* FIXME. This works around PR target/37633 for -O0. */
12161 if (!optimize
&& TARGET_SHMEDIA32
&& GET_MODE_SIZE (mode
) > 4)
12163 unsigned int n
= GET_MODE_SIZE (mode
) / 8;
12165 if (regno
>= FIRST_GENERAL_REG
+ 10 - n
+ 1
12166 && regno
<= FIRST_GENERAL_REG
+ 14)
12173 /* Return the class of registers for which a mode change from FROM to TO
12176 sh_cannot_change_mode_class (machine_mode from
, machine_mode to
,
12177 enum reg_class rclass
)
12179 /* We want to enable the use of SUBREGs as a means to
12180 VEC_SELECT a single element of a vector. */
12182 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
12183 This can be problematic when SFmode vector subregs need to be accessed
12184 on the stack with displacement addressing, as it happens with -O0.
12185 Thus we disallow the mode change for -O0. */
12186 if (to
== SFmode
&& VECTOR_MODE_P (from
) && GET_MODE_INNER (from
) == SFmode
)
12187 return optimize
? (reg_classes_intersect_p (GENERAL_REGS
, rclass
)) : false;
12189 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
12191 if (TARGET_LITTLE_ENDIAN
)
12193 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
12194 return reg_classes_intersect_p (DF_REGS
, rclass
);
12198 if (GET_MODE_SIZE (from
) < 8)
12199 return reg_classes_intersect_p (DF_REGS
, rclass
);
12205 /* Return true if registers in machine mode MODE will likely be
12206 allocated to registers in small register classes. */
12208 sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED
)
12210 return (! TARGET_SHMEDIA
);
12213 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
12214 that label is used. */
12216 sh_mark_label (rtx address
, int nuses
)
12218 if (GOTOFF_P (address
))
12220 /* Extract the label or symbol. */
12221 address
= XEXP (address
, 0);
12222 if (GET_CODE (address
) == PLUS
)
12223 address
= XEXP (address
, 0);
12224 address
= XVECEXP (address
, 0, 0);
12226 if (GET_CODE (address
) == LABEL_REF
12227 && LABEL_P (XEXP (address
, 0)))
12228 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
12231 /* Compute extra cost of moving data between one register class
12234 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
12235 uses this information. Hence, the general register <-> floating point
12236 register information here is not used for SFmode. */
12238 sh_register_move_cost (machine_mode mode
,
12239 reg_class_t srcclass
, reg_class_t dstclass
)
12241 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
12244 if (dstclass
== MAC_REGS
&& srcclass
== MAC_REGS
)
12247 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
12248 && REGCLASS_HAS_FP_REG (srcclass
)
12249 && REGCLASS_HAS_FP_REG (dstclass
))
12252 if (REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== T_REGS
)
12253 return ((TARGET_HARD_SH4
&& !optimize_size
) ? 10 : 7);
12255 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
12256 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
12259 if ((REGCLASS_HAS_FP_REG (dstclass
)
12260 && REGCLASS_HAS_GENERAL_REG (srcclass
))
12261 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
12262 && REGCLASS_HAS_FP_REG (srcclass
)))
12264 /* Discourage trying to use fp regs for a pointer. This also
12265 discourages fp regs with SImode because Pmode is an alias
12266 of SImode on this target. See PR target/48596. */
12267 int addend
= (mode
== Pmode
) ? 40 : 0;
12269 return (((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12) + addend
)
12270 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
12273 if ((dstclass
== FPUL_REGS
12274 && REGCLASS_HAS_GENERAL_REG (srcclass
))
12275 || (srcclass
== FPUL_REGS
12276 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
12279 if ((dstclass
== FPUL_REGS
12280 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
12281 || (srcclass
== FPUL_REGS
12282 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
12285 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
12286 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
12289 /* ??? ptabs faults on (value & 0x3) == 0x3 */
12291 && ((srcclass
) == TARGET_REGS
|| (srcclass
) == SIBCALL_REGS
))
12293 if (sh_gettrcost
>= 0)
12294 return sh_gettrcost
;
12295 else if (!TARGET_PT_FIXED
)
12299 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
12300 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
12305 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
12306 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
12307 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
12309 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
12313 emit_load_ptr (rtx reg
, rtx addr
)
12315 rtx mem
= gen_const_mem (ptr_mode
, addr
);
12317 if (Pmode
!= ptr_mode
)
12318 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
12319 return emit_move_insn (reg
, mem
);
12323 sh_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12324 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12327 CUMULATIVE_ARGS cum
;
12328 int structure_value_byref
= 0;
12329 rtx this_rtx
, this_value
, sibcall
, funexp
;
12331 tree funtype
= TREE_TYPE (function
);
12332 int simple_add
= CONST_OK_FOR_ADD (delta
);
12334 rtx scratch0
, scratch1
, scratch2
;
12337 reload_completed
= 1;
12338 epilogue_completed
= 1;
12339 crtl
->uses_only_leaf_regs
= 1;
12341 emit_note (NOTE_INSN_PROLOGUE_END
);
12343 /* Find the "this" pointer. We have such a wide range of ABIs for the
12344 SH that it's best to do this completely machine independently.
12345 "this" is passed as first argument, unless a structure return pointer
12346 comes first, in which case "this" comes second. */
12347 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0, 1);
12348 #ifndef PCC_STATIC_STRUCT_RETURN
12349 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12350 structure_value_byref
= 1;
12351 #endif /* not PCC_STATIC_STRUCT_RETURN */
12352 if (structure_value_byref
&& sh_struct_value_rtx (function
, 0) == 0)
12354 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
12356 sh_function_arg_advance (pack_cumulative_args (&cum
), Pmode
, ptype
, true);
12359 = sh_function_arg (pack_cumulative_args (&cum
), Pmode
, ptr_type_node
, true);
12361 /* For SHcompact, we only have r0 for a scratch register: r1 is the
12362 static chain pointer (even if you can't have nested virtual functions
12363 right now, someone might implement them sometime), and the rest of the
12364 registers are used for argument passing, are callee-saved, or reserved. */
12365 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
12366 -ffixed-reg has been used. */
12367 if (! call_used_regs
[0] || fixed_regs
[0])
12368 error ("r0 needs to be available as a call-clobbered register");
12369 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
12372 if (call_used_regs
[1] && ! fixed_regs
[1])
12373 scratch1
= gen_rtx_REG (ptr_mode
, 1);
12374 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
12375 pointing where to return struct values. */
12376 if (call_used_regs
[3] && ! fixed_regs
[3])
12377 scratch2
= gen_rtx_REG (Pmode
, 3);
12379 else if (TARGET_SHMEDIA
)
12381 for (i
= FIRST_GENERAL_REG
; i
<= LAST_GENERAL_REG
; i
++)
12382 if (i
!= REGNO (scratch0
) &&
12383 call_used_regs
[i
] && ! fixed_regs
[i
] && ! FUNCTION_ARG_REGNO_P (i
))
12385 scratch1
= gen_rtx_REG (ptr_mode
, i
);
12388 if (scratch1
== scratch0
)
12389 error ("need a second call-clobbered general purpose register");
12390 for (i
= FIRST_TARGET_REG
; i
<= LAST_TARGET_REG
; i
++)
12391 if (call_used_regs
[i
] && ! fixed_regs
[i
])
12393 scratch2
= gen_rtx_REG (Pmode
, i
);
12396 if (scratch2
== scratch0
)
12397 error ("need a call-clobbered target register");
12400 this_value
= plus_constant (Pmode
, this_rtx
, delta
);
12402 && (simple_add
|| scratch0
!= scratch1
)
12403 && strict_memory_address_p (ptr_mode
, this_value
))
12405 emit_load_ptr (scratch0
, this_value
);
12410 ; /* Do nothing. */
12411 else if (simple_add
)
12412 emit_move_insn (this_rtx
, this_value
);
12415 emit_move_insn (scratch1
, GEN_INT (delta
));
12416 emit_insn (gen_add2_insn (this_rtx
, scratch1
));
12424 emit_load_ptr (scratch0
, this_rtx
);
12426 offset_addr
= plus_constant (Pmode
, scratch0
, vcall_offset
);
12427 if (strict_memory_address_p (ptr_mode
, offset_addr
))
12428 ; /* Do nothing. */
12429 else if (! TARGET_SH5
&& scratch0
!= scratch1
)
12431 /* scratch0 != scratch1, and we have indexed loads. Get better
12432 schedule by loading the offset into r1 and using an indexed
12433 load - then the load of r1 can issue before the load from
12434 (this_rtx + delta) finishes. */
12435 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
12436 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
12438 else if (CONST_OK_FOR_ADD (vcall_offset
))
12440 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
12441 offset_addr
= scratch0
;
12443 else if (scratch0
!= scratch1
)
12445 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
12446 emit_insn (gen_add2_insn (scratch0
, scratch1
));
12447 offset_addr
= scratch0
;
12450 gcc_unreachable (); /* FIXME */
12451 emit_load_ptr (scratch0
, offset_addr
);
12453 if (Pmode
!= ptr_mode
)
12454 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
12455 emit_insn (gen_add2_insn (this_rtx
, scratch0
));
12458 /* Generate a tail call to the target function. */
12459 if (! TREE_USED (function
))
12461 assemble_external (function
);
12462 TREE_USED (function
) = 1;
12464 funexp
= XEXP (DECL_RTL (function
), 0);
12465 /* If the function is overridden, so is the thunk, hence we don't
12466 need GOT addressing even if this is a public symbol. */
12468 if (TARGET_SH1
&& ! flag_weak
)
12469 sibcall
= gen_sibcalli_thunk (funexp
, const0_rtx
);
12472 if (TARGET_SH2
&& flag_pic
)
12474 sibcall
= gen_sibcall_pcrel (funexp
, const0_rtx
);
12475 XEXP (XVECEXP (sibcall
, 0, 2), 0) = scratch2
;
12479 if (TARGET_SHMEDIA
&& flag_pic
)
12481 funexp
= gen_sym2PIC (funexp
);
12482 PUT_MODE (funexp
, Pmode
);
12484 emit_move_insn (scratch2
, funexp
);
12485 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
12486 sibcall
= gen_sibcall (funexp
, const0_rtx
, NULL_RTX
);
12488 sibcall
= emit_call_insn (sibcall
);
12489 SIBLING_CALL_P (sibcall
) = 1;
12490 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this_rtx
);
12493 /* Run just enough of rest_of_compilation to do scheduling and get
12494 the insns emitted. Note that use_thunk calls
12495 assemble_start_function and assemble_end_function. */
12497 insns
= get_insns ();
12503 split_all_insns_noflow ();
12507 shorten_branches (insns
);
12508 final_start_function (insns
, file
, 1);
12509 final (insns
, file
, 1);
12510 final_end_function ();
12512 reload_completed
= 0;
12513 epilogue_completed
= 0;
12517 function_symbol (rtx target
, const char *name
, enum sh_function_kind kind
)
12521 /* If this is not an ordinary function, the name usually comes from a
12522 string literal or an sprintf buffer. Make sure we use the same
12523 string consistently, so that cse will be able to unify address loads. */
12524 if (kind
!= FUNCTION_ORDINARY
)
12525 name
= IDENTIFIER_POINTER (get_identifier (name
));
12526 sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
12527 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;
12531 case FUNCTION_ORDINARY
:
12535 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
12537 emit_insn (gen_symGOT2reg (reg
, sym
));
12543 /* ??? To allow cse to work, we use GOTOFF relocations.
12544 We could add combiner patterns to transform this into
12545 straight pc-relative calls with sym2PIC / bsrf when
12546 label load and function call are still 1:1 and in the
12547 same basic block during combine. */
12548 rtx reg
= target
? target
: gen_reg_rtx (Pmode
);
12550 emit_insn (gen_symGOTOFF2reg (reg
, sym
));
12555 if (target
&& sym
!= target
)
12557 emit_move_insn (target
, sym
);
12563 /* Find the number of a general purpose register in S. */
12565 scavenge_reg (HARD_REG_SET
*s
)
12568 for (r
= FIRST_GENERAL_REG
; r
<= LAST_GENERAL_REG
; r
++)
12569 if (TEST_HARD_REG_BIT (*s
, r
))
12575 sh_get_pr_initial_val (void)
12579 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
12580 PR register on SHcompact, because it might be clobbered by the prologue.
12581 We check first if that is known to be the case. */
12582 if (TARGET_SHCOMPACT
12583 && ((crtl
->args
.info
.call_cookie
12584 & ~ CALL_COOKIE_RET_TRAMP (1))
12585 || crtl
->saves_all_registers
))
12586 return gen_frame_mem (SImode
, return_address_pointer_rtx
);
12588 /* If we haven't finished rtl generation, there might be a nonlocal label
12589 that we haven't seen yet.
12590 ??? get_hard_reg_initial_val fails if it is called after register
12591 allocation has started, unless it has been called before for the
12592 same register. And even then, we end in trouble if we didn't use
12593 the register in the same basic block before. So call
12594 get_hard_reg_initial_val now and wrap it in an unspec if we might
12595 need to replace it. */
12596 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
12597 combine can put the pseudo returned by get_hard_reg_initial_val into
12598 instructions that need a general purpose registers, which will fail to
12599 be recognized when the pseudo becomes allocated to PR. */
12601 = get_hard_reg_initial_val (Pmode
, TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
12603 return gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_RA
);
12608 sh_expand_t_scc (rtx operands
[])
12610 enum rtx_code code
= GET_CODE (operands
[1]);
12611 rtx target
= operands
[0];
12612 rtx op0
= operands
[2];
12613 rtx op1
= operands
[3];
12614 rtx result
= target
;
12617 if (!REG_P (op0
) || REGNO (op0
) != T_REG
12618 || !CONST_INT_P (op1
))
12620 if (!REG_P (result
))
12621 result
= gen_reg_rtx (SImode
);
12622 val
= INTVAL (op1
);
12623 if ((code
== EQ
&& val
== 1) || (code
== NE
&& val
== 0))
12624 emit_insn (gen_movt (result
, get_t_reg_rtx ()));
12625 else if ((code
== EQ
&& val
== 0) || (code
== NE
&& val
== 1))
12626 emit_insn (gen_movnegt (result
, get_t_reg_rtx ()));
12627 else if (code
== EQ
|| code
== NE
)
12628 emit_insn (gen_move_insn (result
, GEN_INT (code
== NE
)));
12631 if (result
!= target
)
12632 emit_move_insn (target
, result
);
12636 /* INSN is an sfunc; return the rtx that describes the address used. */
12638 extract_sfunc_addr (rtx insn
)
12640 rtx pattern
, part
= NULL_RTX
;
12643 pattern
= PATTERN (insn
);
12644 len
= XVECLEN (pattern
, 0);
12645 for (i
= 0; i
< len
; i
++)
12647 part
= XVECEXP (pattern
, 0, i
);
12648 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == Pmode
12649 && GENERAL_REGISTER_P (true_regnum (XEXP (part
, 0))))
12650 return XEXP (part
, 0);
12652 gcc_assert (GET_CODE (XVECEXP (pattern
, 0, 0)) == UNSPEC_VOLATILE
);
12653 return XVECEXP (XVECEXP (pattern
, 0, 0), 0, 1);
12656 /* Verify that the register in use_sfunc_addr still agrees with the address
12657 used in the sfunc. This prevents fill_slots_from_thread from changing
12659 INSN is the use_sfunc_addr instruction, and REG is the register it
12662 check_use_sfunc_addr (rtx_insn
*insn
, rtx reg
)
12664 /* Search for the sfunc. It should really come right after INSN. */
12665 while ((insn
= NEXT_INSN (insn
)))
12667 if (LABEL_P (insn
) || JUMP_P (insn
))
12669 if (! INSN_P (insn
))
12672 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
12673 insn
= seq
->insn (0);
12674 if (GET_CODE (PATTERN (insn
)) != PARALLEL
12675 || get_attr_type (insn
) != TYPE_SFUNC
)
12677 return rtx_equal_p (extract_sfunc_addr (insn
), reg
);
12679 gcc_unreachable ();
12682 /* This function returns a constant rtx that represents 2**15 / pi in
12683 SFmode. It's used to scale a fixed-point signed 16.16-bit fraction
12684 of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */
12685 static GTY(()) rtx sh_fsca_sf2int_rtx
;
12688 sh_fsca_sf2int (void)
12690 if (! sh_fsca_sf2int_rtx
)
12692 REAL_VALUE_TYPE rv
;
12694 real_from_string (&rv
, "10430.378350470453");
12695 sh_fsca_sf2int_rtx
= const_double_from_real_value (rv
, SFmode
);
12698 return sh_fsca_sf2int_rtx
;
12701 /* This function returns a constant rtx that represents pi / 2**15 in
12702 SFmode. It's used to scale SFmode angles, in radians, to a
12703 fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi
12704 maps to 0x10000. */
12705 static GTY(()) rtx sh_fsca_int2sf_rtx
;
12708 sh_fsca_int2sf (void)
12710 if (! sh_fsca_int2sf_rtx
)
12712 REAL_VALUE_TYPE rv
;
12714 real_from_string (&rv
, "9.587379924285257e-5");
12715 sh_fsca_int2sf_rtx
= const_double_from_real_value (rv
, SFmode
);
12718 return sh_fsca_int2sf_rtx
;
12721 /* Initialize the CUMULATIVE_ARGS structure. */
12723 sh_init_cumulative_args (CUMULATIVE_ARGS
* pcum
,
12725 rtx libname ATTRIBUTE_UNUSED
,
12727 signed int n_named_args
,
12730 pcum
->arg_count
[(int) SH_ARG_FLOAT
] = 0;
12731 pcum
->free_single_fp_reg
= 0;
12732 pcum
->stack_regs
= 0;
12733 pcum
->byref_regs
= 0;
12735 pcum
->outgoing
= (n_named_args
== -1) ? 0 : 1;
12737 /* XXX - Should we check TARGET_HITACHI here ??? */
12738 pcum
->renesas_abi
= sh_attr_renesas_p (fntype
) ? 1 : 0;
12742 pcum
->force_mem
= ((TARGET_HITACHI
|| pcum
->renesas_abi
)
12743 && aggregate_value_p (TREE_TYPE (fntype
), fndecl
));
12744 pcum
->prototype_p
= prototype_p (fntype
);
12745 pcum
->arg_count
[(int) SH_ARG_INT
]
12746 = TARGET_SH5
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
);
12749 = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12750 && pcum
->arg_count
[(int) SH_ARG_INT
] == 0
12751 && (TYPE_MODE (TREE_TYPE (fntype
)) == BLKmode
12752 ? int_size_in_bytes (TREE_TYPE (fntype
))
12753 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype
)))) > 4
12754 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype
)))
12755 == FIRST_RET_REG
));
12759 pcum
->arg_count
[(int) SH_ARG_INT
] = 0;
12760 pcum
->prototype_p
= FALSE
;
12761 if (mode
!= VOIDmode
)
12763 pcum
->call_cookie
=
12764 CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT
12765 && GET_MODE_SIZE (mode
) > 4
12766 && BASE_RETURN_VALUE_REG (mode
) == FIRST_RET_REG
);
12768 /* If the default ABI is the Renesas ABI then all library
12769 calls must assume that the library will be using the
12770 Renesas ABI. So if the function would return its result
12771 in memory then we must force the address of this memory
12772 block onto the stack. Ideally we would like to call
12773 targetm.calls.return_in_memory() here but we do not have
12774 the TYPE or the FNDECL available so we synthesize the
12775 contents of that function as best we can. */
12777 (TARGET_DEFAULT
& MASK_HITACHI
)
12778 && (mode
== BLKmode
12779 || (GET_MODE_SIZE (mode
) > 4
12780 && !(mode
== DFmode
12781 && TARGET_FPU_DOUBLE
)));
12785 pcum
->call_cookie
= 0;
12786 pcum
->force_mem
= FALSE
;
12791 /* Replace any occurrence of FROM(n) in X with TO(n). The function does
12792 not enter into CONST_DOUBLE for the replace.
12794 Note that copying is not done so X must not be shared unless all copies
12795 are to be modified.
12797 This is like replace_rtx, except that we operate on N_REPLACEMENTS
12798 replacements simultaneously - FROM(n) is replacements[n*2] and to(n) is
12799 replacements[n*2+1] - and that we take mode changes into account.
12801 If a replacement is ambiguous, return NULL_RTX.
12803 If MODIFY is zero, don't modify any rtl in place,
12804 just return zero or nonzero for failure / success. */
12806 replace_n_hard_rtx (rtx x
, rtx
*replacements
, int n_replacements
, int modify
)
12811 /* The following prevents loops occurrence when we change MEM in
12812 CONST_DOUBLE onto the same CONST_DOUBLE. */
12813 if (x
!= NULL_RTX
&& GET_CODE (x
) == CONST_DOUBLE
)
12816 for (i
= n_replacements
- 1; i
>= 0 ; i
--)
12817 if (x
== replacements
[i
*2] && GET_MODE (x
) == GET_MODE (replacements
[i
*2+1]))
12818 return replacements
[i
*2+1];
12820 /* Allow this function to make replacements in EXPR_LISTs. */
12824 if (GET_CODE (x
) == SUBREG
)
12826 rtx new_rtx
= replace_n_hard_rtx (SUBREG_REG (x
), replacements
,
12827 n_replacements
, modify
);
12829 if (CONST_INT_P (new_rtx
))
12831 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
12832 GET_MODE (SUBREG_REG (x
)),
12838 SUBREG_REG (x
) = new_rtx
;
12842 else if (REG_P (x
))
12844 unsigned regno
= REGNO (x
);
12845 unsigned nregs
= (regno
< FIRST_PSEUDO_REGISTER
12846 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
12847 rtx result
= NULL_RTX
;
12849 for (i
= n_replacements
- 1; i
>= 0; i
--)
12851 rtx from
= replacements
[i
*2];
12852 rtx to
= replacements
[i
*2+1];
12853 unsigned from_regno
, from_nregs
, to_regno
, new_regno
;
12857 from_regno
= REGNO (from
);
12858 from_nregs
= (from_regno
< FIRST_PSEUDO_REGISTER
12859 ? HARD_REGNO_NREGS (from_regno
, GET_MODE (from
)) : 1);
12860 if (regno
< from_regno
+ from_nregs
&& regno
+ nregs
> from_regno
)
12862 if (regno
< from_regno
12863 || regno
+ nregs
> from_regno
+ nregs
12867 to_regno
= REGNO (to
);
12868 if (to_regno
< FIRST_PSEUDO_REGISTER
)
12870 new_regno
= regno
+ to_regno
- from_regno
;
12871 if ((unsigned) HARD_REGNO_NREGS (new_regno
, GET_MODE (x
))
12874 result
= gen_rtx_REG (GET_MODE (x
), new_regno
);
12876 else if (GET_MODE (x
) <= GET_MODE (to
))
12877 result
= gen_lowpart_common (GET_MODE (x
), to
);
12879 result
= gen_lowpart_SUBREG (GET_MODE (x
), to
);
12882 return result
? result
: x
;
12884 else if (GET_CODE (x
) == ZERO_EXTEND
)
12886 rtx new_rtx
= replace_n_hard_rtx (XEXP (x
, 0), replacements
,
12887 n_replacements
, modify
);
12889 if (CONST_INT_P (new_rtx
))
12891 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
12892 new_rtx
, GET_MODE (XEXP (x
, 0)));
12897 XEXP (x
, 0) = new_rtx
;
12902 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12903 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
12909 new_rtx
= replace_n_hard_rtx (XEXP (x
, i
), replacements
,
12910 n_replacements
, modify
);
12914 XEXP (x
, i
) = new_rtx
;
12916 else if (fmt
[i
] == 'E')
12917 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12919 new_rtx
= replace_n_hard_rtx (XVECEXP (x
, i
, j
), replacements
,
12920 n_replacements
, modify
);
12924 XVECEXP (x
, i
, j
) = new_rtx
;
12932 sh_gen_truncate (machine_mode mode
, rtx x
, int need_sign_ext
)
12934 enum rtx_code code
= TRUNCATE
;
12936 if (GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
12938 rtx inner
= XEXP (x
, 0);
12939 machine_mode inner_mode
= GET_MODE (inner
);
12941 if (inner_mode
== mode
)
12943 else if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
12945 else if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
)
12946 && (! need_sign_ext
|| GET_CODE (x
) == SIGN_EXTEND
))
12948 code
= GET_CODE (x
);
12952 return gen_rtx_fmt_e (code
, mode
, x
);
12955 /* Look through X cleaning up truncates of registers that span multiple
12956 actual hard registers. Return the number of changes made. */
12958 shmedia_cleanup_truncate (rtx x
)
12961 subrtx_var_iterator::array_type array
;
12962 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
12965 if (GET_CODE (x
) == TRUNCATE
)
12967 rtx reg
= XEXP (x
, 0);
12968 machine_mode reg_mode
= GET_MODE (reg
);
12969 if (REG_P (reg
) && GET_MODE_SIZE (reg_mode
) > 8)
12971 int offset
= subreg_lowpart_offset (DImode
, reg_mode
);
12972 XEXP (x
, 0) = simplify_subreg (DImode
, reg
, reg_mode
, offset
);
12974 iter
.skip_subrtxes ();
12981 /* Load and store depend on the highpart of the address. However,
12982 set_attr_alternative does not give well-defined results before reload,
12983 so we must look at the rtl ourselves to see if any of the feeding
12984 registers is used in a memref.
12986 Return true iff INSN contains a MEM. */
12988 sh_contains_memref_p (rtx insn
)
12990 subrtx_iterator::array_type array
;
12991 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
12997 /* Return true iff INSN loads a banked register. */
12999 sh_loads_bankedreg_p (rtx insn
)
13001 if (GET_CODE (PATTERN (insn
)) == SET
)
13003 rtx op
= SET_DEST (PATTERN(insn
));
13004 if (REG_P (op
) && BANKED_REGISTER_P (REGNO (op
)))
13011 /* FNADDR is the MEM expression from a call expander. Return an address
13012 to use in an SHmedia insn pattern. */
13014 shmedia_prepare_call_address (rtx fnaddr
, int is_sibcall
)
13018 fnaddr
= XEXP (fnaddr
, 0);
13019 is_sym
= GET_CODE (fnaddr
) == SYMBOL_REF
;
13020 if (flag_pic
&& is_sym
)
13022 if (! SYMBOL_REF_LOCAL_P (fnaddr
))
13024 rtx reg
= gen_reg_rtx (Pmode
);
13026 /* We must not use GOTPLT for sibcalls, because PIC_REG
13027 must be restored before the PLT code gets to run. */
13029 emit_insn (gen_symGOT2reg (reg
, fnaddr
));
13031 emit_insn (gen_symGOTPLT2reg (reg
, fnaddr
));
13036 fnaddr
= gen_sym2PIC (fnaddr
);
13037 PUT_MODE (fnaddr
, Pmode
);
13040 /* If ptabs might trap, make this visible to the rest of the compiler.
13041 We generally assume that symbols pertain to valid locations, but
13042 it is possible to generate invalid symbols with asm or linker tricks.
13043 In a list of functions where each returns its successor, an invalid
13044 symbol might denote an empty list. */
13045 if (!TARGET_PT_FIXED
13046 && (!is_sym
|| TARGET_INVALID_SYMBOLS
)
13047 && (!REG_P (fnaddr
) || ! TARGET_REGISTER_P (REGNO (fnaddr
))))
13049 rtx tr
= gen_reg_rtx (PDImode
);
13051 emit_insn (gen_ptabs (tr
, fnaddr
));
13054 else if (! target_reg_operand (fnaddr
, Pmode
))
13055 fnaddr
= copy_to_mode_reg (Pmode
, fnaddr
);
13059 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
13061 sh_preferred_reload_class (rtx x
, reg_class_t rclass
)
13063 if (rclass
== NO_REGS
13065 && (CONST_DOUBLE_P (x
)
13066 || GET_CODE (x
) == SYMBOL_REF
13067 || PIC_ADDR_P (x
)))
13068 return GENERAL_REGS
;
13073 /* Implement TARGET_SECONDARY_RELOAD. */
13075 sh_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13076 machine_mode mode
, secondary_reload_info
*sri
)
13078 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13080 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
13081 && REG_P (XEXP (XEXP (x
, 0), 0))
13082 && REGNO (XEXP (XEXP (x
, 0), 0)) == GBR_REG
)
13083 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
13085 if (MEM_P (x
) && REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == GBR_REG
)
13086 return rclass
== R0_REGS
? NO_REGS
: R0_REGS
;
13088 if (REG_P (x
) && REGNO (x
) == GBR_REG
)
13093 if (REGCLASS_HAS_FP_REG (rclass
)
13094 && ! TARGET_SHMEDIA
13095 && immediate_operand ((x
), mode
)
13096 && ! ((fp_zero_operand (x
) || fp_one_operand (x
)) && mode
== SFmode
))
13100 sri
->icode
= CODE_FOR_reload_insf__frn
;
13103 sri
->icode
= CODE_FOR_reload_indf__frn
;
13106 /* ??? If we knew that we are in the appropriate mode -
13107 single precision - we could use a reload pattern directly. */
13112 if (rclass
== FPUL_REGS
13113 && ((REG_P (x
) && (REGNO (x
) == MACL_REG
|| REGNO (x
) == MACH_REG
13114 || REGNO (x
) == T_REG
))
13115 || GET_CODE (x
) == PLUS
))
13116 return GENERAL_REGS
;
13117 if (rclass
== FPUL_REGS
&& immediate_operand (x
, mode
))
13119 if (satisfies_constraint_I08 (x
) || fp_zero_operand (x
))
13120 return GENERAL_REGS
;
13121 else if (mode
== SFmode
)
13123 sri
->icode
= CODE_FOR_reload_insi__i_fpul
;
13126 if (rclass
== FPSCR_REGS
13127 && ((REG_P (x
) && REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
13128 || (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == PLUS
)))
13129 return GENERAL_REGS
;
13130 if (REGCLASS_HAS_FP_REG (rclass
)
13132 && immediate_operand (x
, mode
)
13133 && x
!= CONST0_RTX (GET_MODE (x
))
13134 && GET_MODE (x
) != V4SFmode
)
13135 return GENERAL_REGS
;
13136 if ((mode
== QImode
|| mode
== HImode
)
13137 && TARGET_SHMEDIA
&& inqhi_operand (x
, mode
))
13139 sri
->icode
= ((mode
== QImode
)
13140 ? CODE_FOR_reload_inqi
: CODE_FOR_reload_inhi
);
13143 if (TARGET_SHMEDIA
&& rclass
== GENERAL_REGS
13144 && (GET_CODE (x
) == LABEL_REF
|| PIC_ADDR_P (x
)))
13145 return TARGET_REGS
;
13146 } /* end of input-only processing. */
13148 if (((REGCLASS_HAS_FP_REG (rclass
)
13150 && (GENERAL_OR_AP_REGISTER_P (REGNO (x
))
13151 || (FP_REGISTER_P (REGNO (x
)) && mode
== SImode
13152 && TARGET_FMOVD
))))
13153 || (REGCLASS_HAS_GENERAL_REG (rclass
)
13155 && FP_REGISTER_P (REGNO (x
))))
13156 && ! TARGET_SHMEDIA
13157 && (mode
== SFmode
|| mode
== SImode
))
13159 if ((rclass
== FPUL_REGS
13160 || (REGCLASS_HAS_FP_REG (rclass
)
13161 && ! TARGET_SHMEDIA
&& mode
== SImode
))
13164 && (REGNO (x
) >= FIRST_PSEUDO_REGISTER
13165 || REGNO (x
) == T_REG
13166 || system_reg_operand (x
, VOIDmode
)))))
13168 if (rclass
== FPUL_REGS
)
13169 return GENERAL_REGS
;
13172 if ((rclass
== TARGET_REGS
13173 || (TARGET_SHMEDIA
&& rclass
== SIBCALL_REGS
))
13174 && !satisfies_constraint_Csy (x
)
13175 && (!REG_P (x
) || ! GENERAL_REGISTER_P (REGNO (x
))))
13176 return GENERAL_REGS
;
13177 if ((rclass
== MAC_REGS
|| rclass
== PR_REGS
)
13178 && REG_P (x
) && ! GENERAL_REGISTER_P (REGNO (x
))
13179 && rclass
!= REGNO_REG_CLASS (REGNO (x
)))
13180 return GENERAL_REGS
;
13181 if (rclass
!= GENERAL_REGS
&& REG_P (x
)
13182 && TARGET_REGISTER_P (REGNO (x
)))
13183 return GENERAL_REGS
;
13185 /* If here fall back to loading FPUL register through general registers.
13186 This case can happen when movsi_ie insn is picked initially to
13187 load/store the FPUL register from/to another register, and then the
13188 other register is allocated on the stack. */
13189 if (rclass
== FPUL_REGS
&& true_regnum (x
) == -1)
13190 return GENERAL_REGS
;
13192 /* Force mov.b / mov.w displacement addressing insn to use R0 as
13194 On SH2A could also just leave it alone here, which would result in a
13195 4 byte move insn being generated instead. However, for this to work
13196 the insns must have the appropriate alternatives. */
13197 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
13198 && satisfies_constraint_Sdd (x
)
13199 && sh_disp_addr_displacement (x
)
13200 <= sh_max_mov_insn_displacement (mode
, false))
13203 /* When reload is trying to address a QImode or HImode subreg on the stack,
13204 force any subreg byte into R0_REGS, as this is going to become a
13205 displacement address.
13206 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
13207 is on the stack, the memref to it might already require a displacement
13208 and that has to be added to the final address. At this point we don't
13209 know the cumulative displacement so we assume the worst case. */
13210 if ((mode
== QImode
|| mode
== HImode
) && rclass
!= R0_REGS
13211 && GET_CODE (x
) == SUBREG
&& true_regnum (x
) == -1)
13218 sh_conditional_register_usage (void)
13221 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
13222 if (! VALID_REGISTER_P (regno
))
13223 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
13224 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
13227 call_used_regs
[FIRST_GENERAL_REG
+ 8]
13228 = call_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
13229 call_really_used_regs
[FIRST_GENERAL_REG
+ 8]
13230 = call_really_used_regs
[FIRST_GENERAL_REG
+ 9] = 1;
13232 if (TARGET_SHMEDIA
)
13234 regno_reg_class
[FIRST_GENERAL_REG
] = GENERAL_REGS
;
13235 CLEAR_HARD_REG_SET (reg_class_contents
[FP0_REGS
]);
13236 regno_reg_class
[FIRST_FP_REG
] = FP_REGS
;
13240 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13241 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13243 /* Renesas saves and restores mac registers on call. */
13244 if (TARGET_HITACHI
&& ! TARGET_NOMACSAVE
)
13246 call_really_used_regs
[MACH_REG
] = 0;
13247 call_really_used_regs
[MACL_REG
] = 0;
13250 if (TARGET_SHMEDIA
)
13252 for (regno
= FIRST_TARGET_REG
; regno
<= LAST_TARGET_REG
; regno
++)
13253 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
13254 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
13257 for (regno
= FIRST_GENERAL_REG
; regno
<= LAST_GENERAL_REG
; regno
++)
13258 if (! fixed_regs
[regno
] && call_really_used_regs
[regno
])
13259 SET_HARD_REG_BIT (reg_class_contents
[SIBCALL_REGS
], regno
);
13261 call_really_used_regs
[FPSCR_MODES_REG
] = 0;
13262 call_really_used_regs
[FPSCR_STAT_REG
] = 0;
13265 /* Implement TARGET_LEGITIMATE_CONSTANT_P
13267 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
13269 sh_legitimate_constant_p (machine_mode mode
, rtx x
)
13271 return (TARGET_SHMEDIA
13272 ? ((mode
!= DFmode
&& GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
13273 || x
== CONST0_RTX (mode
)
13274 || !TARGET_SHMEDIA_FPU
13275 || TARGET_SHMEDIA64
)
13276 : (GET_CODE (x
) != CONST_DOUBLE
13277 || mode
== DFmode
|| mode
== SFmode
13278 || mode
== DImode
|| GET_MODE (x
) == VOIDmode
));
13281 enum sh_divide_strategy_e sh_div_strategy
= SH_DIV_STRATEGY_DEFAULT
;
13284 sh_init_sync_libfuncs (void)
13286 init_sync_libfuncs (UNITS_PER_WORD
);
13289 /* Return true if it is appropriate to emit `ret' instructions in the
13290 body of a function. */
13292 sh_can_use_simple_return_p (void)
13294 HARD_REG_SET live_regs_mask
;
13297 /* Some targets require special return insns. */
13299 || (TARGET_SHCOMPACT
13300 && (crtl
->args
.info
.call_cookie
& CALL_COOKIE_RET_TRAMP (1))))
13303 if (! reload_completed
|| frame_pointer_needed
)
13306 /* Moving prologue around does't reduce the size. */
13307 if (optimize_function_for_size_p (cfun
))
13310 /* Finally, allow for pr save. */
13311 d
= calc_live_regs (&live_regs_mask
);
13313 if (rounded_frame_size (d
) > 4)
13319 /*------------------------------------------------------------------------------
13320 Address mode optimization support code
13323 typedef HOST_WIDE_INT disp_t
;
13324 static const disp_t MIN_DISP
= HOST_WIDE_INT_MIN
;
13325 static const disp_t MAX_DISP
= HOST_WIDE_INT_MAX
;
13326 static const disp_t INVALID_DISP
= MAX_DISP
;
13328 /* A memory reference which is described by a base register and a
13330 class base_reg_disp
13333 base_reg_disp (rtx br
, disp_t d
);
13335 bool is_reg (void) const;
13336 bool is_disp (void) const;
13337 rtx
reg (void) const;
13338 disp_t
disp (void) const;
13346 base_reg_disp::base_reg_disp (rtx br
, disp_t d
)
13347 : reg_ (br
), disp_ (d
)
13352 base_reg_disp::is_reg (void) const
13354 return reg_
!= NULL_RTX
&& disp_
!= INVALID_DISP
;
13358 base_reg_disp::is_disp (void) const
13360 return reg_
== NULL_RTX
&& disp_
!= INVALID_DISP
;
13364 base_reg_disp::reg (void) const
13370 base_reg_disp::disp (void) const
13375 /* Find the base register and calculate the displacement for a given
13376 address rtx 'x'. */
13377 static base_reg_disp
13378 sh_find_base_reg_disp (rtx_insn
* insn
, rtx x
, disp_t disp
= 0,
13379 rtx base_reg
= NULL
)
13383 if (REGNO (x
) == GBR_REG
)
13384 return base_reg_disp (x
, disp
);
13386 /* We've reached a hard-reg. This is probably the point where
13387 function args are copied to pseudos. Do not go any further and
13388 stick to the pseudo. If the original mem addr was in a hard reg
13389 from the beginning, it will become the base reg. */
13390 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13391 return base_reg_disp (base_reg
!= NULL
? base_reg
: x
, disp
);
13393 /* Find the def of the reg and trace it. If there are more than one
13394 defs and they are not the same, assume it's not safe to proceed. */
13395 rtx_insn
* last_i
= NULL
;
13396 rtx last_set
= NULL
;
13397 for (df_ref d
= DF_REG_DEF_CHAIN (REGNO (x
)); d
!= NULL
;
13398 d
= DF_REF_NEXT_REG (d
))
13400 rtx set
= const_cast<rtx
> (set_of (x
, DF_REF_INSN (d
)));
13402 /* Accept multiple defs, as long as they are equal. */
13403 if (last_set
== NULL
|| rtx_equal_p (last_set
, set
))
13405 last_i
= DF_REF_INSN (d
);
13416 if (last_set
!= NULL
&& last_i
!= NULL
)
13417 return sh_find_base_reg_disp (last_i
, XEXP (last_set
, 1), disp
,
13418 XEXP (last_set
, 0));
13420 /* When here, no previous insn was found that sets the reg.
13421 The input reg is already the base reg. */
13422 return base_reg_disp (x
, disp
);
13425 else if (GET_CODE (x
) == PLUS
)
13427 base_reg_disp left_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 0));
13428 base_reg_disp right_val
= sh_find_base_reg_disp (insn
, XEXP (x
, 1));
13430 /* Either left or right val must be a reg.
13431 We don't handle the case of 'reg + reg' here. */
13432 if (left_val
.is_reg () && right_val
.is_disp ())
13433 return base_reg_disp (left_val
.reg (), left_val
.disp ()
13434 + right_val
.disp () + disp
);
13435 else if (right_val
.is_reg () && left_val
.is_disp ())
13436 return base_reg_disp (right_val
.reg (), right_val
.disp ()
13437 + left_val
.disp () + disp
);
13439 return base_reg_disp (base_reg
, disp
);
13442 else if (CONST_INT_P (x
))
13443 return base_reg_disp (NULL
, disp
+ INTVAL (x
));
13445 /* Didn't find anything useful. */
13446 return base_reg_disp (base_reg
, disp
);
13449 /* Given an insn and a memory operand, try to find an equivalent GBR
13450 based memory address and return the corresponding new memory address.
13451 Return NULL_RTX if not found. */
13453 sh_find_equiv_gbr_addr (rtx_insn
* insn
, rtx mem
)
13455 if (!MEM_P (mem
) || gbr_address_mem (mem
, GET_MODE (mem
)))
13458 /* Leave post/pre inc/dec or any other side effect addresses alone. */
13459 if (side_effects_p (XEXP (mem
, 0)))
13462 /* When not optimizing there might be no dataflow available. */
13466 base_reg_disp gbr_disp
= sh_find_base_reg_disp (insn
, XEXP (mem
, 0));
13468 if (gbr_disp
.is_reg () && REGNO (gbr_disp
.reg ()) == GBR_REG
)
13470 /* If GBR is marked as call clobbered we bail out if we see a call.
13471 FIXME: Actually should check if this mem refers to the gbr value
13472 before or after the call. If there is a store_gbr preceeding this
13473 mem, it's safe to use GBR for this mem.
13475 If GBR is not marked as call clobbered, but there is some other
13476 def than a call, it's probably a load_gbr upon which we also
13477 bail out to be on the safe side.
13478 FIXME: Should check if we have a use-after-def case, such as
13479 the call case above. */
13480 for (df_ref d
= DF_REG_DEF_CHAIN (GBR_REG
); d
!= NULL
;
13481 d
= DF_REF_NEXT_REG (d
))
13483 if (CALL_P (DF_REF_INSN (d
)))
13485 if (REGNO_REG_SET_P (regs_invalidated_by_call_regset
, GBR_REG
))
13494 rtx disp
= GEN_INT (gbr_disp
.disp ());
13495 if (gbr_displacement (disp
, GET_MODE (mem
)))
13496 return gen_rtx_PLUS (SImode
, gen_rtx_REG (SImode
, GBR_REG
), disp
);
13502 /*------------------------------------------------------------------------------
13503 Manual insn combine support code.
13506 /* Given a reg rtx and a start insn, try to find the insn that sets the
13507 specified reg by using the specified insn stepping function, such as
13508 'prev_nonnote_insn_bb'. When the insn is found, try to extract the rtx
13511 sh_find_set_of_reg (rtx reg
, rtx insn
, rtx_insn
*(*stepfunc
)(rtx
))
13514 result
.insn
= insn
;
13515 result
.set_rtx
= NULL_RTX
;
13516 result
.set_src
= NULL_RTX
;
13518 if (!REG_P (reg
) || insn
== NULL_RTX
)
13521 for (result
.insn
= stepfunc (insn
); result
.insn
!= NULL_RTX
;
13522 result
.insn
= stepfunc (result
.insn
))
13524 if (BARRIER_P (result
.insn
))
13526 if (!NONJUMP_INSN_P (result
.insn
))
13528 if (reg_set_p (reg
, result
.insn
))
13530 result
.set_rtx
= set_of (reg
, result
.insn
);
13532 if (result
.set_rtx
== NULL_RTX
|| GET_CODE (result
.set_rtx
) != SET
)
13535 result
.set_src
= XEXP (result
.set_rtx
, 1);
13543 /* Given an op rtx and an insn, try to find out whether the result of the
13544 specified op consists only of logical operations on T bit stores. */
13546 sh_is_logical_t_store_expr (rtx op
, rtx insn
)
13548 if (!logical_operator (op
, SImode
))
13551 rtx ops
[2] = { XEXP (op
, 0), XEXP (op
, 1) };
13552 int op_is_t_count
= 0;
13554 for (int i
= 0; i
< 2; ++i
)
13556 if (t_reg_operand (ops
[i
], VOIDmode
)
13557 || negt_reg_operand (ops
[i
], VOIDmode
))
13562 set_of_reg op_set
= sh_find_set_of_reg (ops
[i
], insn
,
13563 prev_nonnote_insn_bb
);
13564 if (op_set
.set_src
== NULL_RTX
)
13567 if (t_reg_operand (op_set
.set_src
, VOIDmode
)
13568 || negt_reg_operand (op_set
.set_src
, VOIDmode
)
13569 || sh_is_logical_t_store_expr (op_set
.set_src
, op_set
.insn
))
13574 return op_is_t_count
== 2;
13577 /* Given the operand that is extended in a sign/zero extend insn, and the
13578 insn, try to figure out whether the sign/zero extension can be replaced
13579 by a simple reg-reg copy. If so, the replacement reg rtx is returned,
13580 NULL_RTX otherwise. */
13582 sh_try_omit_signzero_extend (rtx extended_op
, rtx insn
)
13584 if (REG_P (extended_op
))
13585 extended_op
= extended_op
;
13586 else if (GET_CODE (extended_op
) == SUBREG
&& REG_P (SUBREG_REG (extended_op
)))
13587 extended_op
= SUBREG_REG (extended_op
);
13591 /* Reg moves must be of the same mode. */
13592 if (GET_MODE (extended_op
) != SImode
)
13595 set_of_reg s
= sh_find_set_of_reg (extended_op
, insn
, prev_nonnote_insn_bb
);
13596 if (s
.set_src
== NULL_RTX
)
13599 if (t_reg_operand (s
.set_src
, VOIDmode
)
13600 || negt_reg_operand (s
.set_src
, VOIDmode
))
13601 return extended_op
;
13603 /* If the zero extended reg was formed by a logical operation, check the
13604 operands of the logical operation. If both originated from T bit
13605 stores the zero extension can be eliminated. */
13606 else if (sh_is_logical_t_store_expr (s
.set_src
, s
.insn
))
13607 return extended_op
;
13613 sh_emit_mode_set (int entity ATTRIBUTE_UNUSED
, int mode
,
13614 int prev_mode
, HARD_REG_SET regs_live ATTRIBUTE_UNUSED
)
13616 if ((TARGET_SH4A_FP
|| TARGET_SH4_300
)
13617 && prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
13619 emit_insn (gen_toggle_pr ());
13621 emit_insn (gen_toggle_sz ());
13623 else if (mode
!= FP_MODE_NONE
)
13625 rtx tmp
= gen_reg_rtx (SImode
);
13626 emit_insn (gen_sts_fpscr (tmp
));
13629 const unsigned HOST_WIDE_INT fpbits
=
13630 TARGET_FMOVD
? (FPSCR_PR
| FPSCR_SZ
) : FPSCR_PR
;
13632 if (prev_mode
!= FP_MODE_NONE
&& prev_mode
!= mode
)
13633 i
= gen_xorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
13634 else if (mode
== FP_MODE_SINGLE
)
13635 i
= gen_andsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (~fpbits
)));
13636 else if (mode
== FP_MODE_DOUBLE
)
13637 i
= gen_iorsi3 (tmp
, tmp
, force_reg (SImode
, GEN_INT (fpbits
)));
13639 gcc_unreachable ();
13642 emit_insn (gen_lds_fpscr (tmp
));
13647 sh_mode_needed (int entity ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
13649 return recog_memoized (insn
) >= 0 ? get_attr_fp_mode (insn
) : FP_MODE_NONE
;
13653 sh_mode_after (int entity ATTRIBUTE_UNUSED
, int mode
, rtx_insn
*insn
)
13655 if (TARGET_HITACHI
&& recog_memoized (insn
) >= 0 &&
13656 get_attr_fp_set (insn
) != FP_SET_NONE
)
13657 return (int) get_attr_fp_set (insn
);
13663 sh_mode_entry (int entity ATTRIBUTE_UNUSED
)
13665 return NORMAL_MODE (entity
);
13669 sh_mode_exit (int entity ATTRIBUTE_UNUSED
)
13671 return sh_cfun_attr_renesas_p () ? FP_MODE_NONE
: NORMAL_MODE (entity
);
13675 sh_mode_priority (int entity ATTRIBUTE_UNUSED
, int n
)
13677 return ((TARGET_FPU_SINGLE
!= 0) ^ (n
) ? FP_MODE_SINGLE
: FP_MODE_DOUBLE
);
13680 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
13683 sh_use_by_pieces_infrastructure_p (unsigned int size
,
13684 unsigned int align
,
13685 enum by_pieces_operation op
,
13690 case MOVE_BY_PIECES
:
13691 return move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
13692 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
13693 case STORE_BY_PIECES
:
13694 case SET_BY_PIECES
:
13695 return move_by_pieces_ninsns (size
, align
, STORE_MAX_PIECES
+ 1)
13696 < (!speed_p
? 2 : (align
>= 32) ? 16 : 2);
13698 return default_use_by_pieces_infrastructure_p (size
, align
,