gcc/config/sparc/hypersparc.md

   1 ;; Scheduling description for HyperSPARC.
   2 ;;   Copyright (C) 2002-2021 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; The HyperSPARC is a dual-issue processor.  It is not all that fancy.
  21
  22 ;; ??? There are some things not modelled.  For example, sethi+or
  23 ;; ??? coming right after each other are specifically identified and
  24 ;; ??? dual-issued by the processor.  Similarly for sethi+ld[reg+lo].
  25 ;; ??? Actually, to be more precise that rule is sort of modelled now.
  26
  27 (define_automaton "hypersparc_0,hypersparc_1")
  28
  29 ;; HyperSPARC/sparclite86x scheduling
  30
  31 (define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
  32 (define_cpu_unit "hs_fpmds" "hypersparc_1")
  33
  34 (define_insn_reservation "hs_load" 1
  35   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  36     (eq_attr "type" "load,sload,fpload"))
  37   "hs_memory")
  38
  39 (define_insn_reservation "hs_store" 2
  40   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  41     (eq_attr "type" "store,fpstore"))
  42   "hs_memory, nothing")
  43
  44 (define_insn_reservation "hs_slbranch" 1
  45   (and (eq_attr "cpu" "sparclite86x")
  46     (eq_attr "type" "branch"))
  47   "hs_branch")
  48
  49 (define_insn_reservation "hs_slshift" 1
  50   (and (eq_attr "cpu" "sparclite86x")
  51     (eq_attr "type" "shift"))
  52   "hs_shift")
  53
  54 (define_insn_reservation "hs_fp_alu" 1
  55   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  56     (eq_attr "type" "fp,fpmove,fpcmp"))
  57   "hs_fpalu")
  58
  59 (define_insn_reservation "hs_fp_mult" 1
  60   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  61     (eq_attr "type" "fpmul"))
  62   "hs_fpmds")
  63
  64 (define_insn_reservation "hs_fp_divs" 8
  65   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  66     (eq_attr "type" "fpdivs"))
  67   "hs_fpmds*6, nothing*2")
  68
  69 (define_insn_reservation "hs_fp_divd" 12
  70   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  71     (eq_attr "type" "fpdivd"))
  72   "hs_fpmds*10, nothing*2")
  73
  74 (define_insn_reservation "hs_fp_sqrt" 17
  75   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  76     (eq_attr "type" "fpsqrts,fpsqrtd"))
  77   "hs_fpmds*15, nothing*2")
  78
  79 (define_insn_reservation "hs_imul" 17
  80   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
  81     (eq_attr "type" "imul"))
  82   "hs_fpmds*15, nothing*2")