1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
21 ;;- Instruction patterns. When multiple patterns apply,
22 ;;- the first one in the file is chosen.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
26 ;; UNSPEC_VOLATILE usage:
28 (define_c_enum "unspecv" [
29 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an
31 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream
32 VUNSPEC_PEM ; 'procedure_entry_mask' insn.
37 (define_c_enum "unspec" [
38 UNSPEC_SETMEM_FILL ; 'fill' operand to 'setmem' insn.
42 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer
43 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer
44 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer
45 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter
46 (VAX_PSL_REGNUM 16) ; Register 16 contains the processor status
47 ; and condition codes in particular
51 ;; Integer modes supported on VAX, with a mapping from machine mode
52 ;; to mnemonic suffix. DImode is always a special case.
53 (define_mode_iterator VAXint [QI HI SI])
54 (define_mode_iterator VAXintQH [QI HI])
55 (define_mode_iterator VAXintQHSD [QI HI SI DI])
56 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
58 ;; Similar for float modes supported on VAX.
59 (define_mode_iterator VAXfp [SF DF])
60 (define_mode_attr fsfx [(SF "f") (DF "%#")])
62 ;; Some output patterns want integer immediates with a prefix...
63 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
65 (define_mode_iterator VAXcc [CC CCN CCNZ CCZ])
66 (define_mode_iterator VAXccnz [CCN CCNZ CCZ])
68 (define_code_iterator any_extract [sign_extract zero_extract])
71 (include "constraints.md")
72 (include "predicates.md")
74 ;; Make instructions that set the N, N+Z, and Z condition codes respectively.
75 (define_subst "subst_<mode>"
76 [(set (match_operand 0 "")
78 (clobber (reg:CC VAX_PSL_REGNUM))]
80 [(set (reg:VAXccnz VAX_PSL_REGNUM)
81 (compare:VAXccnz (match_dup 1)
86 (define_subst "subst_f<VAXccnz:mode>"
87 [(set (match_operand:VAXfp 0 "")
88 (match_operand:VAXfp 1 ""))
89 (clobber (reg:CC VAX_PSL_REGNUM))]
91 [(set (reg:VAXccnz VAX_PSL_REGNUM)
92 (compare:VAXccnz (match_dup 1)
93 (const_double_zero:VAXfp)))
97 ;; Select all from the attributes below that apply to a given insn that
98 ;; has a clobber on CC for the comparison elimination pass to use it in
99 ;; place of a subsequent comparison instruction matching the mode used
100 ;; by a comparison operator in branch.
102 ;; For example a branch doing `eq' in SImode will use `*cmpsi_ccz', so
103 ;; to eliminate it a `*movsi_ccz', etc. pattern will be required via the
104 ;; `ccz' substitution. Analogously for the other CC modes.
106 ;; The general `cc' mode, which sets all of the C, N, V and Z condition
107 ;; codes, has to be handled specially as it makes no sense for the usual
108 ;; comparison against zero, so no substitution has been defined for it.
109 (define_subst_attr "ccn" "subst_ccn" "" "_ccn")
110 (define_subst_attr "ccnz" "subst_ccnz" "" "_ccnz")
111 (define_subst_attr "ccz" "subst_ccz" "" "_ccz")
112 (define_subst_attr "fccn" "subst_fccn" "" "_ccn")
113 (define_subst_attr "fccnz" "subst_fccnz" "" "_ccnz")
114 (define_subst_attr "fccz" "subst_fccz" "" "_ccz")
116 (define_insn "*cmp<VAXint:mode>_<VAXcc:mode>"
117 [(set (reg:VAXcc VAX_PSL_REGNUM)
118 (compare:VAXcc (match_operand:VAXint 0 "general_operand" "nrmT,nrmT")
119 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
123 cmp<VAXint:isfx> %0,%1")
125 ;; We don't have a CMPQ instruction, but we can set the N and Z condition
126 ;; codes with MOVQ, and also this comparison can be folded into a preceding
127 ;; operation by the post-reload comparison elimination pass.
128 (define_insn "*cmpdi_<VAXccnz:mode>"
129 [(set (reg:VAXccnz VAX_PSL_REGNUM)
130 (compare:VAXccnz (match_operand:DI 0 "general_operand" "r,nmT")
131 (match_operand:DI 1 "const_zero_operand" "I,I")))
132 (clobber (match_scratch:DI 2 "=X,r"))]
138 (define_insn "*cmp<VAXfp:mode>_<VAXccnz:mode>"
139 [(set (reg:VAXccnz VAX_PSL_REGNUM)
140 (compare:VAXccnz (match_operand:VAXfp 0 "general_operand" "gF,gF")
141 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
145 cmp<VAXfp:fsfx> %0,%1")
147 (define_insn "*bit<VAXint:mode>_<VAXccnz:mode>"
148 [(set (reg:VAXccnz VAX_PSL_REGNUM)
150 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
151 (match_operand:VAXint 1 "general_operand" "nrmT"))
154 "bit<VAXint:isfx> %0,%1")
156 ;; The VAX has no sCOND insns. It does have add/subtract with carry
157 ;; which could be used to implement the sltu and sgeu patterns. However,
158 ;; to do this properly requires a complete rewrite of the compare insns
159 ;; to keep them together with the sltu/sgeu insns until after the
160 ;; reload pass is complete. The previous implementation didn't do this
161 ;; and has been deleted.
164 (define_insn_and_split "mov<mode>"
165 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
166 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
173 (clobber (reg:CC VAX_PSL_REGNUM))])]
176 (define_insn "*mov<mode><fccn><fccnz><fccz>"
177 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
178 (match_operand:VAXfp 1 "general_operand" "G,gF"))
179 (clobber (reg:CC VAX_PSL_REGNUM))]
183 mov<VAXfp:fsfx> %1,%0")
185 ;; Some VAXen don't support this instruction.
186 ;;(define_insn_and_split "movti"
187 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
188 ;; (match_operand:TI 1 "general_operand" "g"))]
191 ;; "reload_completed"
193 ;; [(set (match_dup 0)
195 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
198 ;;(define_insn "*movti<ccn><ccnz><ccz>"
199 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
200 ;; (match_operand:TI 1 "general_operand" "g"))
201 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
202 ;; "reload_completed"
205 (define_insn_and_split "movdi"
206 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
207 (match_operand:DI 1 "general_operand" "g"))]
214 (clobber (reg:CC VAX_PSL_REGNUM))])]
217 ;; In some cases `vax_output_int_move' splits a `DImode' move into a pair
218 ;; of `SImode' moves, in which case the flags aren't usefully set. Have
219 ;; separate patterns then, for the cases where the move may and may not be
220 ;; split each. We use the outer condition only so in some cases we will
221 ;; fail to notice the move does not actually get split, but this is OK.
222 (define_insn "*movdi_maybe_split"
223 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
224 (match_operand:DI 1 "general_operand" "g"))
225 (clobber (reg:CC VAX_PSL_REGNUM))]
226 "reload_completed && vax_maybe_split_dimode_move (operands)"
227 "* return vax_output_int_move (insn, operands, DImode);")
229 (define_insn "*movdi_unsplit<ccn><ccnz><ccz>"
230 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
231 (match_operand:DI 1 "general_operand" "g"))
232 (clobber (reg:CC VAX_PSL_REGNUM))]
233 "reload_completed && !vax_maybe_split_dimode_move (operands)"
234 "* return vax_output_int_move (insn, operands, DImode);")
236 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
237 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
238 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
239 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
240 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
241 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
242 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
243 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
246 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
247 ;; but on a VAX 9000 most move and add instructions with one constant
248 ;; operand take 1 cycle).
250 ;; Loads of constants between 64 and 128 used to be done with
251 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
253 (define_expand "movsi"
254 [(set (match_operand:SI 0 "nonimmediate_operand" "")
255 (match_operand:SI 1 "general_operand" ""))]
259 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
261 && GET_CODE (operands[1]) == CONST
262 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
263 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
265 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
266 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
267 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
268 emit_move_insn (temp, symbol_ref);
269 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
275 (define_insn_and_split "movsi_2"
276 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
277 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
284 (clobber (reg:CC VAX_PSL_REGNUM))])]
287 (define_insn "*movsi_2<ccn><ccnz><ccz>"
288 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
289 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))
290 (clobber (reg:CC VAX_PSL_REGNUM))]
292 "* return vax_output_int_move (insn, operands, SImode);")
294 (define_insn_and_split "mov<mode>"
295 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
296 (match_operand:VAXintQH 1 "general_operand" "g"))]
303 (clobber (reg:CC VAX_PSL_REGNUM))])]
306 (define_insn "*mov<mode><ccn><ccnz><ccz>"
307 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
308 (match_operand:VAXintQH 1 "general_operand" "g"))
309 (clobber (reg:CC VAX_PSL_REGNUM))]
311 "* return vax_output_int_move (insn, operands, <MODE>mode);")
313 (define_insn_and_split "movstricthi"
314 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
315 (match_operand:HI 1 "general_operand" "g"))]
320 [(set (strict_low_part (match_dup 0))
322 (clobber (reg:CC VAX_PSL_REGNUM))])]
325 (define_insn "*movstricthi<ccn><ccnz><ccz>"
326 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
327 (match_operand:HI 1 "general_operand" "g"))
328 (clobber (reg:CC VAX_PSL_REGNUM))]
332 if (CONST_INT_P (operands[1]))
334 int i = INTVAL (operands[1]);
337 else if ((unsigned int)i < 64)
338 return \"movw %1,%0\";
339 else if ((unsigned int)~i < 64)
340 return \"mcomw %H1,%0\";
341 else if ((unsigned int)i < 256)
342 return \"movzbw %1,%0\";
344 return \"movw %1,%0\";
347 (define_insn_and_split "movstrictqi"
348 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
349 (match_operand:QI 1 "general_operand" "g"))]
354 [(set (strict_low_part (match_dup 0))
356 (clobber (reg:CC VAX_PSL_REGNUM))])]
359 (define_insn "*movstrictqi<ccn><ccnz><ccz>"
360 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
361 (match_operand:QI 1 "general_operand" "g"))
362 (clobber (reg:CC VAX_PSL_REGNUM))]
366 if (CONST_INT_P (operands[1]))
368 int i = INTVAL (operands[1]);
371 else if ((unsigned int)~i < 64)
372 return \"mcomb %B1,%0\";
374 return \"movb %1,%0\";
377 ;; This is here to accept 4 arguments and pass the first 3 along
378 ;; to the movmemhi1 pattern that really does the work.
379 (define_expand "cpymemhi"
380 [(set (match_operand:BLK 0 "memory_operand" "")
381 (match_operand:BLK 1 "memory_operand" ""))
382 (use (match_operand:HI 2 "general_operand" ""))
383 (match_operand 3 "" "")]
387 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
391 (define_expand "movmemhi"
392 [(set (match_operand:BLK 0 "memory_operand" "")
393 (match_operand:BLK 1 "memory_operand" ""))
394 (use (match_operand:HI 2 "general_operand" ""))
395 (match_operand 3 "" "")]
399 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
403 ;; The definition of this insn does not really explain what it does,
404 ;; but it should suffice
405 ;; that anything generated as this insn will be recognized as one
406 ;; and that it won't successfully combine with anything.
408 (define_insn_and_split "movmemhi1"
409 [(set (match_operand:BLK 0 "memory_operand" "=o")
410 (match_operand:BLK 1 "memory_operand" "o"))
411 (use (match_operand:HI 2 "general_operand" "g"))
417 (clobber (reg:SI 5))]
431 (clobber (reg:CC VAX_PSL_REGNUM))])]
434 (define_insn "*movmemhi1"
435 [(set (match_operand:BLK 0 "memory_operand" "=o")
436 (match_operand:BLK 1 "memory_operand" "o"))
437 (use (match_operand:HI 2 "general_operand" "g"))
444 (clobber (reg:CC VAX_PSL_REGNUM))]
448 ;; This is here to accept 4 arguments and pass the first 3 along
449 ;; to the setmemhi1 pattern that really does the work.
450 (define_expand "setmemhi"
451 [(set (match_operand:BLK 0 "memory_operand" "")
452 (match_operand:QI 2 "general_operand" ""))
453 (use (match_operand:HI 1 "general_operand" ""))
454 (match_operand 3 "" "")]
458 emit_insn (gen_setmemhi1 (operands[0], operands[1], operands[2]));
462 ;; The srcaddr operand of MOVC5 is not dereferenced if srclen is zero, so we
463 ;; set it to (%ap) somewhat arbitrarily chosen for the shortest encoding.
464 (define_insn_and_split "setmemhi1"
465 [(set (match_operand:BLK 0 "memory_operand" "=o")
466 (unspec:BLK [(use (match_operand:QI 2 "general_operand" "g"))]
468 (use (match_operand:HI 1 "general_operand" "g"))
474 (clobber (reg:SI 5))]
480 (unspec:BLK [(use (match_dup 2))] UNSPEC_SETMEM_FILL))
488 (clobber (reg:CC VAX_PSL_REGNUM))])]
491 (define_insn "*setmemhi1"
492 [(set (match_operand:BLK 0 "memory_operand" "=o")
493 (unspec:BLK [(use (match_operand:QI 2 "general_operand" "g"))]
495 (use (match_operand:HI 1 "general_operand" "g"))
502 (clobber (reg:CC VAX_PSL_REGNUM))]
504 "movc5 $0,(%%ap),%2,%1,%0")
506 ;; Extension and truncation insns.
508 (define_insn_and_split "truncsiqi2"
509 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
510 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
516 (truncate:QI (match_dup 1)))
517 (clobber (reg:CC VAX_PSL_REGNUM))])]
520 (define_insn "*truncsiqi2<ccn><ccnz><ccz>"
521 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
522 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
523 (clobber (reg:CC VAX_PSL_REGNUM))]
527 (define_insn_and_split "truncsihi2"
528 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
529 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
535 (truncate:HI (match_dup 1)))
536 (clobber (reg:CC VAX_PSL_REGNUM))])]
539 (define_insn "*truncsihi2<ccn><ccnz><ccz>"
540 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
541 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
542 (clobber (reg:CC VAX_PSL_REGNUM))]
546 (define_insn_and_split "trunchiqi2"
547 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
548 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
554 (truncate:QI (match_dup 1)))
555 (clobber (reg:CC VAX_PSL_REGNUM))])]
558 (define_insn "*trunchiqi2<ccn><ccnz><ccz>"
559 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
560 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))
561 (clobber (reg:CC VAX_PSL_REGNUM))]
565 (define_insn_and_split "extendhisi2"
566 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
567 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
573 (sign_extend:SI (match_dup 1)))
574 (clobber (reg:CC VAX_PSL_REGNUM))])]
577 (define_insn "*extendhisi2<ccn><ccnz><ccz>"
578 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
579 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
580 (clobber (reg:CC VAX_PSL_REGNUM))]
584 (define_insn_and_split "extendqihi2"
585 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
586 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
592 (sign_extend:HI (match_dup 1)))
593 (clobber (reg:CC VAX_PSL_REGNUM))])]
596 (define_insn "*extendqihi2<ccn><ccnz><ccz>"
597 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
598 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
599 (clobber (reg:CC VAX_PSL_REGNUM))]
603 (define_insn_and_split "extendqisi2"
604 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
605 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
611 (sign_extend:SI (match_dup 1)))
612 (clobber (reg:CC VAX_PSL_REGNUM))])]
615 (define_insn "*extendqisi2<ccn><ccnz><ccz>"
616 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
617 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
618 (clobber (reg:CC VAX_PSL_REGNUM))]
622 (define_insn_and_split "extendsfdf2"
623 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
624 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
630 (float_extend:DF (match_dup 1)))
631 (clobber (reg:CC VAX_PSL_REGNUM))])]
634 (define_insn "*extendsfdf2<fccn><fccnz><fccz>"
635 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
636 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))
637 (clobber (reg:CC VAX_PSL_REGNUM))]
641 (define_insn_and_split "truncdfsf2"
642 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
643 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
649 (float_truncate:SF (match_dup 1)))
650 (clobber (reg:CC VAX_PSL_REGNUM))])]
653 (define_insn "*truncdfsf2<fccn><fccnz><fccz>"
654 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
655 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))
656 (clobber (reg:CC VAX_PSL_REGNUM))]
660 (define_insn_and_split "zero_extendhisi2"
661 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
662 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
668 (zero_extend:SI (match_dup 1)))
669 (clobber (reg:CC VAX_PSL_REGNUM))])]
672 (define_insn "*zero_extendhisi2<ccn><ccnz><ccz>"
673 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
674 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
675 (clobber (reg:CC VAX_PSL_REGNUM))]
679 (define_insn_and_split "zero_extendqihi2"
680 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
681 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
687 (zero_extend:HI (match_dup 1)))
688 (clobber (reg:CC VAX_PSL_REGNUM))])]
691 (define_insn "*zero_extendqihi2<ccn><ccnz><ccz>"
692 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
693 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
694 (clobber (reg:CC VAX_PSL_REGNUM))]
698 (define_insn_and_split "zero_extendqisi2"
699 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
700 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
706 (zero_extend:SI (match_dup 1)))
707 (clobber (reg:CC VAX_PSL_REGNUM))])]
710 (define_insn "*zero_extendqisi2<ccn><ccnz><ccz>"
711 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
712 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
713 (clobber (reg:CC VAX_PSL_REGNUM))]
717 ;; Fix-to-float conversion insns.
719 (define_insn_and_split "float<VAXint:mode><VAXfp:mode>2"
720 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
721 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
727 (float:VAXfp (match_dup 1)))
728 (clobber (reg:CC VAX_PSL_REGNUM))])]
731 (define_insn "*float<VAXint:mode><VAXfp:mode>2<fccn><fccnz><fccz>"
732 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
733 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))
734 (clobber (reg:CC VAX_PSL_REGNUM))]
736 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
738 ;; Float-to-fix conversion insns.
740 (define_insn_and_split "fix_trunc<VAXfp:mode><VAXint:mode>2"
741 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
742 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))]
748 (fix:VAXint (match_dup 1)))
749 (clobber (reg:CC VAX_PSL_REGNUM))])]
752 (define_insn "*fix_trunc<VAXfp:mode><VAXint:mode>2<ccn><ccnz><ccz>"
753 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
754 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))
755 (clobber (reg:CC VAX_PSL_REGNUM))]
757 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
759 (define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2"
760 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
761 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))]
764 ;;- All kinds of add instructions.
766 (define_insn_and_split "add<mode>3"
767 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
768 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
769 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
775 (plus:VAXfp (match_dup 1)
777 (clobber (reg:CC VAX_PSL_REGNUM))])]
780 (define_insn "*add<mode>3<fccn><fccnz><fccz>"
781 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
782 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
783 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
784 (clobber (reg:CC VAX_PSL_REGNUM))]
787 add<VAXfp:fsfx>2 %2,%0
788 add<VAXfp:fsfx>2 %1,%0
789 add<VAXfp:fsfx>3 %1,%2,%0")
791 (define_insn_and_split "add<mode>3"
792 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
793 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
794 (match_operand:VAXint 2 "general_operand" "nrmT")))]
800 (plus:VAXint (match_dup 1)
802 (clobber (reg:CC VAX_PSL_REGNUM))])]
805 (define_insn "*add<mode>3<ccn><ccnz><ccz>"
806 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
807 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
808 (match_operand:VAXint 2 "general_operand" "nrmT")))
809 (clobber (reg:CC VAX_PSL_REGNUM))]
811 "* return vax_output_int_add (insn, operands, <MODE>mode);")
813 (define_expand "adddi3"
814 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
815 (plus:DI (match_operand:DI 1 "general_operand" "g")
816 (match_operand:DI 2 "general_operand" "g")))]
817 "!reload_in_progress"
818 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
820 (define_insn_and_split "adcdi3"
821 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
822 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
823 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
826 "&& reload_completed"
829 (plus:DI (match_dup 1)
831 (clobber (reg:CC VAX_PSL_REGNUM))])]
834 (define_insn "*adcdi3<ccn>"
835 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
836 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
837 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))
838 (clobber (reg:CC VAX_PSL_REGNUM))]
839 "TARGET_QMATH && reload_completed"
840 "* return vax_output_int_add (insn, operands, DImode);")
842 ;; The add-with-carry (adwc) instruction only accepts two operands.
843 (define_insn_and_split "adddi3_old"
844 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
845 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
846 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
849 "&& reload_completed"
852 (plus:DI (match_dup 1)
854 (clobber (reg:CC VAX_PSL_REGNUM))])]
857 (define_insn "*adddi3_old<ccn>"
858 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
859 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
860 (match_operand:DI 2 "general_operand" "Fsro,Fs")))
861 (clobber (reg:CC VAX_PSL_REGNUM))]
862 "!TARGET_QMATH && reload_completed"
863 "* return vax_output_int_add (insn, operands, DImode);")
865 ;;- All kinds of subtract instructions.
867 (define_insn_and_split "sub<mode>3"
868 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
869 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
870 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
876 (minus:VAXfp (match_dup 1)
878 (clobber (reg:CC VAX_PSL_REGNUM))])]
881 (define_insn "*sub<mode>3<fccn><fccnz><fccz>"
882 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
883 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
884 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
885 (clobber (reg:CC VAX_PSL_REGNUM))]
888 sub<VAXfp:fsfx>2 %2,%0
889 sub<VAXfp:fsfx>3 %2,%1,%0")
891 (define_insn_and_split "sub<mode>3"
892 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
893 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
894 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
900 (minus:VAXint (match_dup 1)
902 (clobber (reg:CC VAX_PSL_REGNUM))])]
905 (define_insn "*sub<mode>3<ccn><ccnz><ccz>"
906 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
907 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
908 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
909 (clobber (reg:CC VAX_PSL_REGNUM))]
912 sub<VAXint:isfx>2 %2,%0
913 sub<VAXint:isfx>3 %2,%1,%0")
915 (define_insn "*sub<mode>3_cc"
916 [(set (reg:CC VAX_PSL_REGNUM)
917 (compare:CC (match_operand:VAXint 1 "general_operand" "0,nrmT")
918 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
919 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
920 (minus:VAXint (match_dup 1)
924 sub<VAXint:isfx>2 %2,%0
925 sub<VAXint:isfx>3 %2,%1,%0")
927 (define_expand "subdi3"
928 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
929 (minus:DI (match_operand:DI 1 "general_operand" "g")
930 (match_operand:DI 2 "general_operand" "g")))]
931 "!reload_in_progress"
932 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
934 (define_insn_and_split "sbcdi3"
935 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
936 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
937 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
940 "&& reload_completed"
943 (minus:DI (match_dup 1)
945 (clobber (reg:CC VAX_PSL_REGNUM))])]
948 (define_insn "*sbcdi3<ccn>"
949 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
950 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
951 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))
952 (clobber (reg:CC VAX_PSL_REGNUM))]
953 "TARGET_QMATH && reload_completed"
954 "* return vax_output_int_subtract (insn, operands, DImode);")
956 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
957 (define_insn_and_split "subdi3_old"
958 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
959 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
960 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
963 "&& reload_completed"
966 (minus:DI (match_dup 1)
968 (clobber (reg:CC VAX_PSL_REGNUM))])]
971 (define_insn "*subdi3_old<ccn>"
972 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
973 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
974 (match_operand:DI 2 "general_operand" "Fsor,Fs")))
975 (clobber (reg:CC VAX_PSL_REGNUM))]
976 "!TARGET_QMATH && reload_completed"
977 "* return vax_output_int_subtract (insn, operands, DImode);")
979 ;;- Multiply instructions.
981 (define_insn_and_split "mul<mode>3"
982 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
983 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
984 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
990 (mult:VAXfp (match_dup 1)
992 (clobber (reg:CC VAX_PSL_REGNUM))])]
995 (define_insn "*mul<mode>3<fccn><fccnz><fccz>"
996 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
997 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
998 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
999 (clobber (reg:CC VAX_PSL_REGNUM))]
1002 mul<VAXfp:fsfx>2 %2,%0
1003 mul<VAXfp:fsfx>2 %1,%0
1004 mul<VAXfp:fsfx>3 %1,%2,%0")
1006 (define_insn_and_split "mul<mode>3"
1007 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1008 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1009 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
1015 (mult:VAXint (match_dup 1)
1017 (clobber (reg:CC VAX_PSL_REGNUM))])]
1020 (define_insn "*mul<mode>3<ccn><ccnz><ccz>"
1021 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1022 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1023 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1024 (clobber (reg:CC VAX_PSL_REGNUM))]
1027 mul<VAXint:isfx>2 %2,%0
1028 mul<VAXint:isfx>2 %1,%0
1029 mul<VAXint:isfx>3 %1,%2,%0")
1031 (define_insn_and_split "mulsidi3"
1032 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1034 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1035 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))]
1042 (sign_extend:DI (match_dup 1))
1043 (sign_extend:DI (match_dup 2))))
1044 (clobber (reg:CC VAX_PSL_REGNUM))])]
1047 (define_insn "*mulsidi3<ccn><ccnz><ccz>"
1048 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1050 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1051 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))
1052 (clobber (reg:CC VAX_PSL_REGNUM))]
1056 (define_insn_and_split "*maddsidi4"
1057 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1060 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1061 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1062 (sign_extend:DI (match_operand:SI 3 "general_operand" "g"))))]
1070 (sign_extend:DI (match_dup 1))
1071 (sign_extend:DI (match_dup 2)))
1072 (sign_extend:DI (match_dup 3))))
1073 (clobber (reg:CC VAX_PSL_REGNUM))])]
1076 (define_insn "*maddsidi4_2<ccn><ccnz><ccz>"
1077 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1080 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1081 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1082 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))
1083 (clobber (reg:CC VAX_PSL_REGNUM))]
1087 ;; 'F' constraint means type CONST_DOUBLE
1088 (define_insn_and_split "*maddsidi4_const"
1089 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1092 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1093 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1094 (match_operand:DI 3 "immediate_operand" "F")))]
1095 "GET_CODE (operands[3]) == CONST_DOUBLE
1096 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
1098 "&& reload_completed"
1103 (sign_extend:DI (match_dup 1))
1104 (sign_extend:DI (match_dup 2)))
1106 (clobber (reg:CC VAX_PSL_REGNUM))])]
1109 (define_insn "*maddsidi4_const_2<ccn><ccnz><ccz>"
1110 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1113 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1114 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1115 (match_operand:DI 3 "immediate_operand" "F")))
1116 (clobber (reg:CC VAX_PSL_REGNUM))]
1117 "GET_CODE (operands[3]) == CONST_DOUBLE
1118 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)
1119 && reload_completed"
1122 if (CONST_DOUBLE_HIGH (operands[3]))
1123 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
1124 return \"emul %1,%2,%3,%0\";
1127 ;;- Divide instructions.
1129 (define_insn_and_split "div<mode>3"
1130 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1131 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1132 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
1138 (div:VAXfp (match_dup 1)
1140 (clobber (reg:CC VAX_PSL_REGNUM))])]
1143 (define_insn "*div<mode>3<fccn><fccnz><fccz>"
1144 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1145 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1146 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
1147 (clobber (reg:CC VAX_PSL_REGNUM))]
1150 div<VAXfp:fsfx>2 %2,%0
1151 div<VAXfp:fsfx>3 %2,%1,%0")
1153 (define_insn_and_split "div<mode>3"
1154 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1155 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1156 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
1162 (div:VAXint (match_dup 1)
1164 (clobber (reg:CC VAX_PSL_REGNUM))])]
1167 (define_insn "*div<mode>3<ccn><ccnz><ccz>"
1168 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1169 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1170 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
1171 (clobber (reg:CC VAX_PSL_REGNUM))]
1174 div<VAXint:isfx>2 %2,%0
1175 div<VAXint:isfx>3 %2,%1,%0")
1177 ;; This is left out because it is very slow;
1178 ;; we are better off programming around the "lack" of this insn.
1179 ;;(define_insn_and_split "divmoddisi4"
1180 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1181 ;; (div:SI (match_operand:DI 1 "general_operand" "g")
1182 ;; (match_operand:SI 2 "general_operand" "g")))
1183 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1184 ;; (mod:SI (match_dup 1)
1188 ;; "reload_completed"
1190 ;; [(set (match_dup 0)
1191 ;; (div:SI (match_dup 1)
1193 ;; (set (match_dup 3)
1194 ;; (mod:SI (match_dup 1)
1196 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1199 ;;(define_insn "*divmoddisi4<ccn><ccnz><ccz>"
1200 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1201 ;; (div:SI (match_operand:DI 1 "general_operand" "g")
1202 ;; (match_operand:SI 2 "general_operand" "g")))
1203 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1204 ;; (mod:SI (match_dup 1)
1206 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
1207 ;; "reload_completed"
1208 ;; "ediv %2,%1,%0,%3")
1210 ;; Bit-and on the VAX is done with a clear-bits insn.
1211 (define_expand "and<mode>3"
1212 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
1213 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
1214 (match_operand:VAXint 2 "general_operand" "")))]
1218 rtx op1 = operands[1];
1220 /* If there is a constant argument, complement that one. */
1221 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
1223 operands[1] = operands[2];
1228 if (CONST_INT_P (op1))
1229 operands[1] = GEN_INT (~INTVAL (op1));
1231 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
1234 (define_insn_and_split "*and<mode>3"
1235 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1236 (and:VAXint (not:VAXint
1237 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
1238 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
1244 (and:VAXint (not:VAXint
1247 (clobber (reg:CC VAX_PSL_REGNUM))])]
1250 (define_insn "*and<mode>3_2<ccn><ccnz><ccz>"
1251 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1252 (and:VAXint (not:VAXint
1253 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
1254 (match_operand:VAXint 2 "general_operand" "0,nrmT")))
1255 (clobber (reg:CC VAX_PSL_REGNUM))]
1258 bic<VAXint:isfx>2 %1,%0
1259 bic<VAXint:isfx>3 %1,%2,%0")
1261 ;; The following used to be needed because constant propagation can
1262 ;; create them starting from the bic insn patterns above. This is no
1263 ;; longer a problem. However, having these patterns allows optimization
1264 ;; opportunities in combine.cc.
1266 (define_insn_and_split "*and<mode>3_const_int"
1267 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1268 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1269 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
1275 (and:VAXint (match_dup 1)
1277 (clobber (reg:CC VAX_PSL_REGNUM))])]
1280 (define_insn "*and<mode>3_2_const_int<ccn><ccnz><ccz>"
1281 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1282 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1283 (match_operand:VAXint 2 "const_int_operand" "n,n")))
1284 (clobber (reg:CC VAX_PSL_REGNUM))]
1287 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
1288 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
1290 ;; We have no direct AND operation and consequently the RTL sequence
1291 ;; the "and<mode>3" pattern produces does not match the instruction
1292 ;; the "*bit<mode>" pattern does for the purpose of the compare
1293 ;; elimination pass. Try to get rid of the extra operation by hand
1294 ;; and where the sequence is used to set the condition codes only
1295 ;; convert MCOM/BIC => BIT.
1298 [(set (match_operand:VAXint 0 "register_operand")
1299 (not:VAXint (match_operand:VAXint 1 "general_operand")))
1300 (clobber (reg:CC VAX_PSL_REGNUM))])
1302 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1304 (and:VAXint (not:VAXint (match_dup 0))
1305 (match_operand:VAXint 3 "general_operand"))
1307 (set (match_operand:VAXint 2 "register_operand")
1308 (and:VAXint (not:VAXint (match_dup 0))
1310 "peep2_reg_dead_p (2, operands[0]) && peep2_reg_dead_p (2, operands[2])"
1311 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1313 (and:VAXint (match_dup 1)
1318 ;;- Bit set instructions.
1320 (define_insn_and_split "ior<mode>3"
1321 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1322 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1323 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
1329 (ior:VAXint (match_dup 1)
1331 (clobber (reg:CC VAX_PSL_REGNUM))])]
1334 (define_insn "*ior<mode>3<ccn><ccnz><ccz>"
1335 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1336 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1337 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1338 (clobber (reg:CC VAX_PSL_REGNUM))]
1341 bis<VAXint:isfx>2 %2,%0
1342 bis<VAXint:isfx>2 %1,%0
1343 bis<VAXint:isfx>3 %2,%1,%0")
1345 ;;- xor instructions.
1347 (define_insn_and_split "xor<mode>3"
1348 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1349 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1350 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
1356 (xor:VAXint (match_dup 1)
1358 (clobber (reg:CC VAX_PSL_REGNUM))])]
1361 (define_insn "*xor<mode>3<ccn><ccnz><ccz>"
1362 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1363 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1364 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1365 (clobber (reg:CC VAX_PSL_REGNUM))]
1368 xor<VAXint:isfx>2 %2,%0
1369 xor<VAXint:isfx>2 %1,%0
1370 xor<VAXint:isfx>3 %2,%1,%0")
1372 (define_insn_and_split "neg<mode>2"
1373 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1374 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
1380 (neg:VAXfp (match_dup 1)))
1381 (clobber (reg:CC VAX_PSL_REGNUM))])]
1384 (define_insn "*neg<mode>2<fccn><fccnz><fccz>"
1385 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1386 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))
1387 (clobber (reg:CC VAX_PSL_REGNUM))]
1389 "mneg<VAXfp:fsfx> %1,%0")
1391 (define_insn_and_split "neg<mode>2"
1392 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1393 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
1399 (neg:VAXint (match_dup 1)))
1400 (clobber (reg:CC VAX_PSL_REGNUM))])]
1403 (define_insn "*neg<mode>2<ccn><ccnz><ccz>"
1404 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1405 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1406 (clobber (reg:CC VAX_PSL_REGNUM))]
1408 "mneg<VAXint:isfx> %1,%0")
1410 (define_insn "*neg<mode>2_cc"
1411 [(set (reg:CC VAX_PSL_REGNUM)
1412 (compare:CC (const_int 0)
1414 (match_operand:VAXint 1 "general_operand" "0,nrmT"))))
1415 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1416 (neg:VAXint (match_dup 1)))]
1418 "mneg<VAXint:isfx> %1,%0")
1420 (define_insn_and_split "one_cmpl<mode>2"
1421 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1422 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
1428 (not:VAXint (match_dup 1)))
1429 (clobber (reg:CC VAX_PSL_REGNUM))])]
1432 (define_insn "*one_cmpl<mode>2<ccn><ccnz><ccz>"
1433 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1434 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1435 (clobber (reg:CC VAX_PSL_REGNUM))]
1437 "mcom<VAXint:isfx> %1,%0")
1439 ;; Arithmetic right shift on the VAX works by negating the shift count,
1440 ;; then emitting a right shift with the shift count negated. This means
1441 ;; that all actual shift counts in the RTL will be positive. This
1442 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1443 ;; which isn't valid.
1444 (define_expand "ashrsi3"
1445 [(set (match_operand:SI 0 "general_operand" "=g")
1446 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1447 (match_operand:QI 2 "general_operand" "g")))]
1451 if (! CONST_INT_P(operands[2]))
1452 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1455 (define_insn_and_split "*ashlnegsi3_const_int"
1456 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1457 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1458 (match_operand:QI 2 "const_int_operand" "n")))]
1464 (ashiftrt:SI (match_dup 1)
1466 (clobber (reg:CC VAX_PSL_REGNUM))])]
1469 (define_insn "*ashlnegsi3_const_int_2<ccn><ccnz><ccz>"
1470 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1471 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1472 (match_operand:QI 2 "const_int_operand" "n")))
1473 (clobber (reg:CC VAX_PSL_REGNUM))]
1477 (define_insn_and_split "*ashlnegsi3"
1478 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1479 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1480 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1486 (ashiftrt:SI (match_dup 1)
1487 (neg:QI (match_dup 2))))
1488 (clobber (reg:CC VAX_PSL_REGNUM))])]
1491 (define_insn "*ashlnegsi3_2<ccn><ccnz><ccz>"
1492 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1493 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1494 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1495 (clobber (reg:CC VAX_PSL_REGNUM))]
1499 (define_insn_and_split "ashlsi3"
1500 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1501 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1502 (match_operand:QI 2 "general_operand" "g")))]
1508 (ashift:SI (match_dup 1)
1510 (clobber (reg:CC VAX_PSL_REGNUM))])]
1513 (define_insn "*ashlsi3<ccn><ccnz><ccz>"
1514 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1515 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1516 (match_operand:QI 2 "general_operand" "g")))
1517 (clobber (reg:CC VAX_PSL_REGNUM))]
1521 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1522 return \"addl2 %0,%0\";
1523 if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
1525 int i = INTVAL (operands[2]);
1527 return \"addl3 %1,%1,%0\";
1528 if (i == 2 && !optimize_size)
1530 if (push_operand (operands[0], SImode))
1531 return \"pushal 0[%1]\";
1532 return \"moval 0[%1],%0\";
1534 if (i == 3 && !optimize_size)
1536 if (push_operand (operands[0], SImode))
1537 return \"pushaq 0[%1]\";
1538 return \"movaq 0[%1],%0\";
1541 return \"ashl %2,%1,%0\";
1544 ;; Arithmetic right shift on the VAX works by negating the shift count.
1545 (define_expand "ashrdi3"
1546 [(set (match_operand:DI 0 "general_operand" "=g")
1547 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1548 (match_operand:QI 2 "general_operand" "g")))]
1552 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1555 (define_insn_and_split "ashldi3"
1556 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1557 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1558 (match_operand:QI 2 "general_operand" "g")))]
1564 (ashift:DI (match_dup 1)
1566 (clobber (reg:CC VAX_PSL_REGNUM))])]
1569 (define_insn "*ashldi3<ccn><ccnz><ccz>"
1570 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1571 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1572 (match_operand:QI 2 "general_operand" "g")))
1573 (clobber (reg:CC VAX_PSL_REGNUM))]
1577 (define_insn_and_split "*ashlnegdi3"
1578 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1579 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1580 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1586 (ashiftrt:DI (match_dup 1)
1587 (neg:QI (match_dup 2))))
1588 (clobber (reg:CC VAX_PSL_REGNUM))])]
1591 (define_insn "*ashlnegdi3_2<ccn><ccnz><ccz>"
1592 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1593 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1594 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1595 (clobber (reg:CC VAX_PSL_REGNUM))]
1599 ;; We used to have expand_shift handle logical right shifts by using extzv,
1600 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
1601 ;; only machine with this kludge, it's better to just do this with a
1602 ;; define_expand and remove that case from expand_shift.
1604 (define_expand "lshrsi3"
1606 (minus:QI (const_int 32)
1608 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
1609 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1611 (match_operand:SI 2 "register_operand" "g")))]
1615 operands[3] = gen_reg_rtx (QImode);
1616 operands[4] = gen_lowpart (QImode, operands[2]);
1619 ;; Rotate right on the VAX works by negating the shift count.
1620 (define_expand "rotrsi3"
1621 [(set (match_operand:SI 0 "general_operand" "=g")
1622 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1623 (match_operand:QI 2 "general_operand" "g")))]
1627 if (! CONST_INT_P (operands[2]))
1628 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1631 (define_insn_and_split "rotlsi3"
1632 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1633 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
1634 (match_operand:QI 2 "general_operand" "g")))]
1640 (rotate:SI (match_dup 1)
1642 (clobber (reg:CC VAX_PSL_REGNUM))])]
1645 (define_insn "*rotlsi3<ccn><ccnz><ccz>"
1646 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1647 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
1648 (match_operand:QI 2 "general_operand" "g")))
1649 (clobber (reg:CC VAX_PSL_REGNUM))]
1653 (define_insn_and_split "*rotrsi3_const_int"
1654 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1655 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1656 (match_operand:QI 2 "const_int_operand" "n")))]
1662 (rotatert:SI (match_dup 1)
1664 (clobber (reg:CC VAX_PSL_REGNUM))])]
1667 (define_insn "*rotrsi3_const_int_2<ccn><ccnz><ccz>"
1668 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1669 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1670 (match_operand:QI 2 "const_int_operand" "n")))
1671 (clobber (reg:CC VAX_PSL_REGNUM))]
1675 (define_insn_and_split "*rotrnegsi3"
1676 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1677 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1678 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1684 (rotatert:SI (match_dup 1)
1685 (neg:QI (match_dup 2))))
1686 (clobber (reg:CC VAX_PSL_REGNUM))])]
1689 (define_insn "*rotrnegsi3_2<ccn><ccnz><ccz>"
1690 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1691 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1692 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1693 (clobber (reg:CC VAX_PSL_REGNUM))]
1697 ;; This insn is probably slower than a multiply and an add.
1698 ;;(define_insn_and_split "*amulsi4"
1699 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1700 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1701 ;; (match_operand:SI 2 "general_operand" "g"))
1702 ;; (match_operand:SI 3 "general_operand" "g")))]
1705 ;; "reload_completed"
1707 ;; [(set (match_dup 0)
1708 ;; (mult:SI (plus:SI (match_dup 1)
1711 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1714 ;;(define_insn "*amulsi4_2<ccn><ccnz><ccz>"
1715 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1716 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1717 ;; (match_operand:SI 2 "general_operand" "g"))
1718 ;; (match_operand:SI 3 "general_operand" "g")))
1719 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
1720 ;; "reload_completed"
1721 ;; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1723 ;; Special cases of bit-field insns which we should
1724 ;; recognize in preference to the general case.
1725 ;; These handle aligned 8-bit and 16-bit fields
1726 ;; that can be done with move or convert instructions.
1728 (define_insn_and_split "*insv_aligned"
1729 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
1730 (match_operand:QI 1 "const_int_operand" "n")
1731 (match_operand:SI 2 "const_int_operand" "n"))
1732 (match_operand:SI 3 "general_operand" "g"))]
1733 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1734 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1735 && (!MEM_P (operands[0])
1737 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1739 && !mode_dependent_address_p (XEXP (operands[0], 0),
1740 MEM_ADDR_SPACE (operands[0]))))
1741 && (!(REG_P (operands[0])
1742 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1743 || INTVAL (operands[2]) == 0)"
1745 "&& reload_completed"
1747 [(set (zero_extract:SI (match_dup 0)
1751 (clobber (reg:CC VAX_PSL_REGNUM))])]
1754 (define_insn "*insv_aligned_2<ccn><ccnz><ccz>"
1755 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
1756 (match_operand:QI 1 "const_int_operand" "n")
1757 (match_operand:SI 2 "const_int_operand" "n"))
1758 (match_operand:SI 3 "general_operand" "g"))
1759 (clobber (reg:CC VAX_PSL_REGNUM))]
1760 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1761 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1762 && (!MEM_P (operands[0])
1764 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1766 && !mode_dependent_address_p (XEXP (operands[0], 0),
1767 MEM_ADDR_SPACE (operands[0]))))
1768 && (!(REG_P (operands[0])
1769 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1770 || INTVAL (operands[2]) == 0)
1771 && reload_completed"
1774 if (!REG_P (operands[0]))
1776 = adjust_address (operands[0],
1777 INTVAL (operands[1]) == 8 ? QImode : HImode,
1778 INTVAL (operands[2]) / 8);
1780 gcc_assert (INTVAL (operands[2]) == 0);
1782 if (INTVAL (operands[1]) == 8)
1783 return \"movb %3,%0\";
1784 return \"movw %3,%0\";
1787 (define_insn_and_split "*extzv_aligned"
1788 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1789 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1790 (match_operand:QI 2 "const_int_operand" "n")
1791 (match_operand:SI 3 "const_int_operand" "n")))]
1792 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1793 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1794 && (!MEM_P (operands[1])
1796 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1798 && !mode_dependent_address_p (XEXP (operands[1], 0),
1799 MEM_ADDR_SPACE (operands[1]))))
1800 && (!(REG_P (operands[1])
1801 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1802 || INTVAL (operands[3]) == 0)"
1804 "&& reload_completed"
1807 (zero_extract:SI (match_dup 1)
1810 (clobber (reg:CC VAX_PSL_REGNUM))])]
1813 (define_insn "*extzv_aligned_2<ccn><ccnz><ccz>"
1814 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1815 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1816 (match_operand:QI 2 "const_int_operand" "n")
1817 (match_operand:SI 3 "const_int_operand" "n")))
1818 (clobber (reg:CC VAX_PSL_REGNUM))]
1819 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1820 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1821 && (!MEM_P (operands[1])
1823 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1825 && !mode_dependent_address_p (XEXP (operands[1], 0),
1826 MEM_ADDR_SPACE (operands[1]))))
1827 && (!(REG_P (operands[1])
1828 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1829 || INTVAL (operands[3]) == 0)
1830 && reload_completed"
1833 if (!REG_P (operands[1]))
1835 = adjust_address (operands[1],
1836 INTVAL (operands[2]) == 8 ? QImode : HImode,
1837 INTVAL (operands[3]) / 8);
1839 gcc_assert (INTVAL (operands[3]) == 0);
1841 if (INTVAL (operands[2]) == 8)
1842 return \"movzbl %1,%0\";
1843 return \"movzwl %1,%0\";
1846 (define_insn_and_split "*extv_aligned"
1847 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1848 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1849 (match_operand:QI 2 "const_int_operand" "n")
1850 (match_operand:SI 3 "const_int_operand" "n")))]
1851 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1852 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1853 && (!MEM_P (operands[1])
1855 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1857 && !mode_dependent_address_p (XEXP (operands[1], 0),
1858 MEM_ADDR_SPACE (operands[1]))))
1859 && (!(REG_P (operands[1])
1860 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1861 || INTVAL (operands[3]) == 0)"
1863 "&& reload_completed"
1866 (sign_extract:SI (match_dup 1)
1869 (clobber (reg:CC VAX_PSL_REGNUM))])]
1872 (define_insn "*extv_aligned_2<ccn><ccnz><ccz>"
1873 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1874 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1875 (match_operand:QI 2 "const_int_operand" "n")
1876 (match_operand:SI 3 "const_int_operand" "n")))
1877 (clobber (reg:CC VAX_PSL_REGNUM))]
1878 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1879 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1880 && (!MEM_P (operands[1])
1882 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1884 && !mode_dependent_address_p (XEXP (operands[1], 0),
1885 MEM_ADDR_SPACE (operands[1]))))
1886 && (!(REG_P (operands[1])
1887 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1888 || INTVAL (operands[3]) == 0)
1889 && reload_completed"
1892 if (!REG_P (operands[1]))
1894 = adjust_address (operands[1],
1895 INTVAL (operands[2]) == 8 ? QImode : HImode,
1896 INTVAL (operands[3]) / 8);
1898 gcc_assert (INTVAL (operands[3]) == 0);
1900 if (INTVAL (operands[2]) == 8)
1901 return \"cvtbl %1,%0\";
1902 return \"cvtwl %1,%0\";
1905 ;; Register and non-offsettable-memory SImode cases of bit-field insns.
1907 (define_insn "*cmpv_<mode>"
1908 [(set (reg:VAXcc VAX_PSL_REGNUM)
1910 (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
1911 (match_operand:QI 1 "general_operand" "g")
1912 (match_operand:SI 2 "general_operand" "nrmT"))
1913 (match_operand:SI 3 "general_operand" "nrmT")))]
1917 (define_insn "*cmpzv_<mode>"
1918 [(set (reg:VAXcc VAX_PSL_REGNUM)
1920 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
1921 (match_operand:QI 1 "general_operand" "g")
1922 (match_operand:SI 2 "general_operand" "nrmT"))
1923 (match_operand:SI 3 "general_operand" "nrmT")))]
1925 "cmpzv %2,%1,%0,%3")
1927 ;; When the field position and size are constant and the destination
1928 ;; is a register, extv and extzv are much slower than a rotate followed
1929 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
1930 ;; anyway, we can't allow immediate values for the primary source operand.
1932 (define_insn_and_split "*extv_non_const"
1933 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1934 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1935 (match_operand:QI 2 "general_operand" "g")
1936 (match_operand:SI 3 "general_operand" "nrmT")))]
1942 (sign_extract:SI (match_dup 1)
1945 (clobber (reg:CC VAX_PSL_REGNUM))])]
1948 (define_insn "*extv_non_const_2<ccn><ccnz><ccz>"
1949 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1950 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1951 (match_operand:QI 2 "general_operand" "g")
1952 (match_operand:SI 3 "general_operand" "nrmT")))
1953 (clobber (reg:CC VAX_PSL_REGNUM))]
1957 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1958 || ! REG_P (operands[0])
1959 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1960 return \"extv %3,%2,%1,%0\";
1961 if (INTVAL (operands[2]) == 8)
1962 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1963 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1966 (define_insn_and_split "*extzv_non_const"
1967 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1968 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1969 (match_operand:QI 2 "general_operand" "g")
1970 (match_operand:SI 3 "general_operand" "nrmT")))]
1976 (zero_extract:SI (match_dup 1)
1979 (clobber (reg:CC VAX_PSL_REGNUM))])]
1982 (define_insn "*extzv_non_const_2<ccn><ccnz><ccz>"
1983 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1984 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1985 (match_operand:QI 2 "general_operand" "g")
1986 (match_operand:SI 3 "general_operand" "nrmT")))
1987 (clobber (reg:CC VAX_PSL_REGNUM))]
1991 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1992 || ! REG_P (operands[0]))
1993 return \"extzv %3,%2,%1,%0\";
1994 if (INTVAL (operands[2]) == 8)
1995 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1996 if (INTVAL (operands[2]) == 16)
1997 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1998 if (INTVAL (operands[3]) & 31)
1999 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
2000 if (rtx_equal_p (operands[0], operands[1]))
2001 return \"bicl2 %M2,%0\";
2002 return \"bicl3 %M2,%1,%0\";
2005 ;; Non-register cases.
2006 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
2007 ;; don't match these (and therefore match the cases above instead).
2009 (define_insn "*cmpv_2_<mode>"
2010 [(set (reg:VAXcc VAX_PSL_REGNUM)
2012 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
2013 (match_operand:QI 1 "general_operand" "g")
2014 (match_operand:SI 2 "general_operand" "nrmT"))
2015 (match_operand:SI 3 "general_operand" "nrmT")))]
2019 (define_insn "*cmpzv_2_<mode>"
2020 [(set (reg:VAXcc VAX_PSL_REGNUM)
2022 (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
2023 (match_operand:QI 1 "general_operand" "g")
2024 (match_operand:SI 2 "general_operand" "nrmT"))
2025 (match_operand:SI 3 "general_operand" "nrmT")))]
2027 "cmpzv %2,%1,%0,%3")
2029 (define_expand "extv"
2030 [(set (match_operand:SI 0 "general_operand" "")
2031 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
2032 (match_operand:QI 2 "general_operand" "")
2033 (match_operand:SI 3 "general_operand" "")))]
2037 (define_insn_and_split "*extv"
2038 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2039 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
2040 (match_operand:QI 2 "general_operand" "g")
2041 (match_operand:SI 3 "general_operand" "nrmT")))]
2047 (sign_extract:SI (match_dup 1)
2050 (clobber (reg:CC VAX_PSL_REGNUM))])]
2053 (define_insn "*extv_2<ccn><ccnz><ccz>"
2054 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2055 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
2056 (match_operand:QI 2 "general_operand" "g")
2057 (match_operand:SI 3 "general_operand" "nrmT")))
2058 (clobber (reg:CC VAX_PSL_REGNUM))]
2062 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
2063 || !CONST_INT_P (operands[3])
2064 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
2065 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
2066 || side_effects_p (operands[1])
2067 || (MEM_P (operands[1])
2068 && mode_dependent_address_p (XEXP (operands[1], 0),
2069 MEM_ADDR_SPACE (operands[1]))))
2070 return \"extv %3,%2,%1,%0\";
2071 if (INTVAL (operands[2]) == 8)
2072 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
2073 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
2076 (define_expand "extzv"
2077 [(set (match_operand:SI 0 "general_operand" "")
2078 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
2079 (match_operand:QI 2 "general_operand" "")
2080 (match_operand:SI 3 "general_operand" "")))]
2084 (define_insn_and_split "*extzv"
2085 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2086 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
2087 (match_operand:QI 2 "general_operand" "g")
2088 (match_operand:SI 3 "general_operand" "nrmT")))]
2094 (zero_extract:SI (match_dup 1)
2097 (clobber (reg:CC VAX_PSL_REGNUM))])]
2100 (define_insn "*extzv_2<ccn><ccnz><ccz>"
2101 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2102 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
2103 (match_operand:QI 2 "general_operand" "g")
2104 (match_operand:SI 3 "general_operand" "nrmT")))
2105 (clobber (reg:CC VAX_PSL_REGNUM))]
2109 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
2110 || !CONST_INT_P (operands[3])
2111 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
2112 || side_effects_p (operands[1])
2113 || (MEM_P (operands[1])
2114 && mode_dependent_address_p (XEXP (operands[1], 0),
2115 MEM_ADDR_SPACE (operands[1]))))
2116 return \"extzv %3,%2,%1,%0\";
2117 if (INTVAL (operands[2]) == 8)
2118 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
2119 if (INTVAL (operands[2]) == 16)
2120 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
2121 if (MEM_P (operands[1])
2122 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2123 && REG_P (XEXP (XEXP (operands[1], 0), 0))
2124 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
2125 && CONST_INT_P (operands[2])
2126 && CONST_INT_P (operands[3]))
2128 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2129 HOST_WIDE_INT l = INTVAL (operands[2]);
2130 HOST_WIDE_INT v = INTVAL (operands[3]);
2131 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2134 tmp = XEXP (XEXP (operands[1], 0), 0);
2136 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2137 operands[1] = gen_rtx_MEM (QImode, tmp);
2138 operands[3] = GEN_INT (v + (o & 3) * 8);
2141 return \"extzv %3,%2,%1,%0\";
2143 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
2146 ;; Combine EXTV/CMPL and EXTZV/CMPL sequences where the output of
2147 ;; extraction is used for the comparison only into CMPV and CMPZV
2151 [(set (match_operand:SI 0 "register_operand")
2152 (any_extract:SI (match_operand 1 "general_operand")
2153 (match_operand:QI 2 "general_operand")
2154 (match_operand:SI 3 "general_operand")))
2155 (clobber (reg:CC VAX_PSL_REGNUM))])
2156 (set (reg:VAXcc VAX_PSL_REGNUM)
2157 (compare:VAXcc (match_dup 0)
2158 (match_operand:SI 4 "general_operand")))]
2159 "peep2_reg_dead_p (2, operands[0])"
2160 [(set (reg:VAXcc VAX_PSL_REGNUM)
2162 (any_extract:SI (match_dup 1)
2168 (define_expand "insv"
2169 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
2170 (match_operand:QI 1 "general_operand" "")
2171 (match_operand:SI 2 "general_operand" ""))
2172 (match_operand:SI 3 "general_operand" ""))]
2176 ;; This one actually doesn't change CC.
2177 (define_insn "*insv"
2178 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
2179 (match_operand:QI 1 "general_operand" "g")
2180 (match_operand:SI 2 "general_operand" "nrmT"))
2181 (match_operand:SI 3 "general_operand" "nrmT"))]
2185 if (MEM_P (operands[0])
2186 && GET_CODE (XEXP (operands[0], 0)) == PLUS
2187 && REG_P (XEXP (XEXP (operands[0], 0), 0))
2188 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
2189 && CONST_INT_P (operands[1])
2190 && CONST_INT_P (operands[2]))
2192 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2193 HOST_WIDE_INT v = INTVAL (operands[2]);
2194 HOST_WIDE_INT l = INTVAL (operands[1]);
2195 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2198 tmp = XEXP (XEXP (operands[0], 0), 0);
2200 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2201 operands[0] = gen_rtx_MEM (QImode, tmp);
2202 operands[2] = GEN_INT (v + (o & 3) * 8);
2205 return \"insv %3,%2,%1,%0\";
2208 ;; This one actually doesn't change CC.
2209 (define_insn "*insv_2"
2210 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
2211 (match_operand:QI 1 "general_operand" "g")
2212 (match_operand:SI 2 "general_operand" "nrmT"))
2213 (match_operand:SI 3 "general_operand" "nrmT"))]
2217 ;; Unconditional jump
2220 (label_ref (match_operand 0 "" "")))]
2224 ;; Conditional jumps
2226 (define_expand "cbranch<mode>4"
2229 (match_operator 0 "ordered_comparison_operator"
2230 [(match_operand:VAXint 1 "general_operand" "")
2231 (match_operand:VAXint 2 "general_operand" "")])
2232 (label_ref (match_operand 3 "" ""))
2237 (define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>"
2240 (match_operator 0 "vax_<VAXcc:mode>_comparison_operator"
2241 [(match_operand:VAXint 1 "general_operand" "nrmT")
2242 (match_operand:VAXint 2 "general_operand" "nrmT")])
2243 (label_ref (match_operand 3 "" ""))
2248 [(set (reg:VAXcc VAX_PSL_REGNUM)
2249 (compare:VAXcc (match_dup 1) (match_dup 2)))
2252 (match_op_dup 0 [(reg:VAXcc VAX_PSL_REGNUM)
2254 (label_ref (match_operand 3 "" ""))
2258 (define_expand "cbranch<mode>4"
2261 (match_operator 0 "ordered_comparison_operator"
2262 [(match_operand:VAXfp 1 "general_operand" "")
2263 (match_operand:VAXfp 2 "general_operand" "")])
2264 (label_ref (match_operand 3 "" ""))
2269 (define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>"
2272 (match_operator 0 "vax_<VAXccnz:mode>_comparison_operator"
2273 [(match_operand:VAXfp 1 "general_operand" "gF")
2274 (match_operand:VAXfp 2 "general_operand" "gF")])
2275 (label_ref (match_operand 3 "" ""))
2280 [(set (reg:VAXccnz VAX_PSL_REGNUM)
2281 (compare:VAXccnz (match_dup 1) (match_dup 2)))
2284 (match_op_dup 0 [(reg:VAXccnz VAX_PSL_REGNUM)
2286 (label_ref (match_operand 3 "" ""))
2290 (define_insn "*branch_<mode>"
2292 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator"
2293 [(reg:VAXcc VAX_PSL_REGNUM)
2295 (label_ref (match_operand 1 "" ""))
2300 ;; Recognize reversed jumps.
2301 (define_insn "*branch_<mode>_reversed"
2303 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator"
2304 [(reg:VAXcc VAX_PSL_REGNUM)
2307 (label_ref (match_operand 1 "" ""))))]
2309 "j%K0 %l1") ; %K0 negates condition
2311 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
2312 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
2313 ;; memory, we use QImode in the insn. So we can't use those instructions
2314 ;; for mode-dependent addresses.
2319 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
2321 (match_operand:SI 1 "general_operand" "I,nrmT"))
2323 (label_ref (match_operand 2 "" ""))
2333 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
2335 (match_operand:SI 1 "general_operand" "I,nrmT"))
2337 (label_ref (match_operand 2 "" ""))
2347 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2349 (match_operand:SI 1 "general_operand" "I,nrmT"))
2351 (label_ref (match_operand 2 "" ""))
2361 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2363 (match_operand:SI 1 "general_operand" "I,nrmT"))
2365 (label_ref (match_operand 2 "" ""))
2372 ;; Subtract-and-jump and Add-and-jump insns.
2373 ;; These are not used when output is for the Unix assembler
2374 ;; because it does not know how to modify them to reach far.
2376 ;; Normal sob insns.
2378 (define_insn_and_split "*jsobgtr"
2381 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2384 (label_ref (match_operand 1 "" ""))
2387 (plus:SI (match_dup 0)
2391 "&& reload_completed"
2395 (gt (plus:SI (match_dup 0)
2398 (label_ref (match_dup 1))
2401 (plus:SI (match_dup 0)
2403 (clobber (reg:CC VAX_PSL_REGNUM))])]
2406 (define_insn "*jsobgtr_2"
2409 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2412 (label_ref (match_operand 1 "" ""))
2415 (plus:SI (match_dup 0)
2417 (clobber (reg:CC VAX_PSL_REGNUM))]
2418 "!TARGET_UNIX_ASM && reload_completed"
2421 (define_insn_and_split "*jsobgeq"
2424 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2427 (label_ref (match_operand 1 "" ""))
2430 (plus:SI (match_dup 0)
2434 "&& reload_completed"
2438 (ge (plus:SI (match_dup 0)
2441 (label_ref (match_dup 1))
2444 (plus:SI (match_dup 0)
2446 (clobber (reg:CC VAX_PSL_REGNUM))])]
2449 (define_insn "*jsobgeq_2"
2452 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2455 (label_ref (match_operand 1 "" ""))
2458 (plus:SI (match_dup 0)
2460 (clobber (reg:CC VAX_PSL_REGNUM))]
2461 "!TARGET_UNIX_ASM && reload_completed"
2464 ;; Normal aob insns. Define a version for when operands[1] is a constant.
2465 (define_insn_and_split "*jaoblss"
2468 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2470 (match_operand:SI 1 "general_operand" "nrmT"))
2471 (label_ref (match_operand 2 "" ""))
2474 (plus:SI (match_dup 0)
2478 "&& reload_completed"
2482 (lt (plus:SI (match_dup 0)
2485 (label_ref (match_dup 2))
2488 (plus:SI (match_dup 0)
2490 (clobber (reg:CC VAX_PSL_REGNUM))])]
2493 (define_insn "*jaoblss_2"
2496 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2498 (match_operand:SI 1 "general_operand" "nrmT"))
2499 (label_ref (match_operand 2 "" ""))
2502 (plus:SI (match_dup 0)
2504 (clobber (reg:CC VAX_PSL_REGNUM))]
2505 "!TARGET_UNIX_ASM && reload_completed"
2506 "jaoblss %1,%0,%l2")
2508 (define_insn_and_split "*jaoblss_const"
2511 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
2512 (match_operand:SI 1 "general_operand" "nrmT"))
2513 (label_ref (match_operand 2 "" ""))
2516 (plus:SI (match_dup 0)
2518 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
2520 "&& reload_completed"
2526 (label_ref (match_dup 2))
2529 (plus:SI (match_dup 0)
2531 (clobber (reg:CC VAX_PSL_REGNUM))])]
2534 (define_insn "*jaoblss_const_2"
2537 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
2538 (match_operand:SI 1 "general_operand" "nrmT"))
2539 (label_ref (match_operand 2 "" ""))
2542 (plus:SI (match_dup 0)
2544 (clobber (reg:CC VAX_PSL_REGNUM))]
2545 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
2546 "jaoblss %P1,%0,%l2")
2548 (define_insn_and_split "*jaobleq"
2551 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2553 (match_operand:SI 1 "general_operand" "nrmT"))
2554 (label_ref (match_operand 2 "" ""))
2557 (plus:SI (match_dup 0)
2561 "&& reload_completed"
2565 (le (plus:SI (match_dup 0)
2568 (label_ref (match_dup 2))
2571 (plus:SI (match_dup 0)
2573 (clobber (reg:CC VAX_PSL_REGNUM))])]
2576 (define_insn "*jaobleq_2"
2579 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2581 (match_operand:SI 1 "general_operand" "nrmT"))
2582 (label_ref (match_operand 2 "" ""))
2585 (plus:SI (match_dup 0)
2587 (clobber (reg:CC VAX_PSL_REGNUM))]
2588 "!TARGET_UNIX_ASM && reload_completed"
2589 "jaobleq %1,%0,%l2")
2591 (define_insn_and_split "*jaobleq_const"
2594 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
2595 (match_operand:SI 1 "general_operand" "nrmT"))
2596 (label_ref (match_operand 2 "" ""))
2599 (plus:SI (match_dup 0)
2601 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
2603 "&& reload_completed"
2609 (label_ref (match_dup 2))
2612 (plus:SI (match_dup 0)
2614 (clobber (reg:CC VAX_PSL_REGNUM))])]
2617 (define_insn "*jaobleq_const_2"
2620 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
2621 (match_operand:SI 1 "general_operand" "nrmT"))
2622 (label_ref (match_operand 2 "" ""))
2625 (plus:SI (match_dup 0)
2627 (clobber (reg:CC VAX_PSL_REGNUM))]
2628 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
2629 "jaobleq %P1,%0,%l2")
2631 ;; Something like a sob insn, but compares against -1.
2632 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
2634 (define_insn_and_split "*jsobneq_minus_one"
2637 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
2639 (label_ref (match_operand 1 "" ""))
2642 (plus:SI (match_dup 0)
2652 (label_ref (match_dup 1))
2655 (plus:SI (match_dup 0)
2657 (clobber (reg:CC VAX_PSL_REGNUM))])]
2660 (define_insn "*jsobneq_minus_one_2"
2663 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
2665 (label_ref (match_operand 1 "" ""))
2668 (plus:SI (match_dup 0)
2670 (clobber (reg:CC VAX_PSL_REGNUM))]
2672 "decl %0\;jgequ %l1")
2674 (define_expand "call_pop"
2675 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
2676 (match_operand:SI 1 "const_int_operand" ""))
2677 (set (reg:SI VAX_SP_REGNUM)
2678 (plus:SI (reg:SI VAX_SP_REGNUM)
2679 (match_operand:SI 3 "immediate_operand" "")))])]
2682 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
2684 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2685 during EH unwinding. We must include the argument count pushed by
2686 the calls instruction. */
2687 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
2690 (define_insn "*call_pop"
2691 [(call (match_operand:QI 0 "memory_operand" "m")
2692 (match_operand:SI 1 "const_int_operand" "n"))
2693 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2694 (match_operand:SI 2 "immediate_operand" "i")))]
2697 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
2698 return "calls %1,%0";
2701 (define_expand "call_value_pop"
2702 [(parallel [(set (match_operand 0 "" "")
2703 (call (match_operand:QI 1 "memory_operand" "")
2704 (match_operand:SI 2 "const_int_operand" "")))
2705 (set (reg:SI VAX_SP_REGNUM)
2706 (plus:SI (reg:SI VAX_SP_REGNUM)
2707 (match_operand:SI 4 "immediate_operand" "")))])]
2710 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
2712 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2713 during EH unwinding. We must include the argument count pushed by
2714 the calls instruction. */
2715 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
2718 (define_insn "*call_value_pop"
2719 [(set (match_operand 0 "" "")
2720 (call (match_operand:QI 1 "memory_operand" "m")
2721 (match_operand:SI 2 "const_int_operand" "n")))
2722 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2723 (match_operand:SI 3 "immediate_operand" "i")))]
2727 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
2728 return \"calls %2,%1\";
2731 (define_expand "call"
2732 [(call (match_operand:QI 0 "memory_operand" "")
2733 (match_operand:SI 1 "const_int_operand" ""))]
2737 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2738 during EH unwinding. We must include the argument count pushed by
2739 the calls instruction. */
2740 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
2743 (define_insn "*call"
2744 [(call (match_operand:QI 0 "memory_operand" "m")
2745 (match_operand:SI 1 "const_int_operand" ""))]
2749 (define_expand "call_value"
2750 [(set (match_operand 0 "" "")
2751 (call (match_operand:QI 1 "memory_operand" "")
2752 (match_operand:SI 2 "const_int_operand" "")))]
2756 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2757 during EH unwinding. We must include the argument count pushed by
2758 the calls instruction. */
2759 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
2762 (define_insn "*call_value"
2763 [(set (match_operand 0 "" "")
2764 (call (match_operand:QI 1 "memory_operand" "m")
2765 (match_operand:SI 2 "const_int_operand" "")))]
2769 ;; Call subroutine returning any type.
2771 (define_expand "untyped_call"
2772 [(parallel [(call (match_operand 0 "" "")
2774 (match_operand 1 "" "")
2775 (match_operand 2 "" "")])]
2781 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
2783 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2785 rtx set = XVECEXP (operands[2], 0, i);
2786 emit_move_insn (SET_DEST (set), SET_SRC (set));
2789 /* The optimizer does not know that the call sets the function value
2790 registers we stored in the result block. We avoid problems by
2791 claiming that all hard registers are used and clobbered at this
2793 emit_insn (gen_blockage ());
2798 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2799 ;; all of memory. This blocks insns from being moved across this point.
2801 (define_insn "blockage"
2802 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
2806 (define_insn "procedure_entry_mask"
2807 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)]
2811 (define_insn "return"
2816 (define_expand "prologue"
2820 vax_expand_prologue ();
2824 (define_expand "epilogue"
2829 emit_jump_insn (gen_return ());
2838 ;; This had a wider constraint once, and it had trouble.
2839 ;; If you are tempted to try `g', please don't--it's not worth
2840 ;; the risk we will reopen the same bug.
2841 (define_insn "indirect_jump"
2842 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2846 ;; This is here to accept 5 arguments (as passed by expand_end_case)
2847 ;; and pass the first 4 along to the casesi1 pattern that really does
2848 ;; the actual casesi work. We emit a jump here to the default label
2849 ;; _before_ the casesi so that we can be sure that the casesi never
2851 ;; This is suboptimal perhaps, but so is much of the rest of this
2852 ;; machine description. For what it's worth, HPPA uses the same trick.
2854 ;; operand 0 is index
2855 ;; operand 1 is the minimum bound (a const_int)
2856 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
2857 ;; operand 3 is CODE_LABEL for the table;
2858 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
2861 ;; i = index - minimum_bound
2862 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
2863 ;; casesi (i, 0, table);
2865 (define_expand "casesi"
2866 [(match_operand:SI 0 "general_operand" "")
2867 (match_operand:SI 1 "general_operand" "")
2868 (match_operand:SI 2 "general_operand" "")
2869 (match_operand 3 "" "")
2870 (match_operand 4 "" "")]
2875 /* i = index - minimum_bound;
2876 But only if the lower bound is not already zero. */
2877 if (operands[1] != const0_rtx)
2879 rtx index = gen_reg_rtx (SImode);
2880 emit_insn (gen_addsi3 (index,
2882 gen_int_mode (-INTVAL (operands[1]), SImode)));
2883 operands[0] = index;
2886 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */
2887 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
2888 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
2890 /* casesi (i, 0, table); */
2891 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
2895 ;; This insn is a bit of a lier. It actually falls through if no case
2896 ;; matches. But, we prevent that from ever happening by emitting a jump
2897 ;; before this, see the define_expand above.
2898 (define_insn_and_split "casesi1"
2899 [(match_operand:SI 1 "const_int_operand" "n")
2901 (plus:SI (sign_extend:SI
2904 (match_operand:SI 0 "general_operand" "nrmT")
2907 (label_ref:SI (match_operand 2 "" ""))))]
2914 (plus:SI (sign_extend:SI
2920 (label_ref:SI (match_dup 2))))
2921 (clobber (reg:CC VAX_PSL_REGNUM))])]
2924 (define_insn "*casesi1"
2925 [(match_operand:SI 1 "const_int_operand" "n")
2927 (plus:SI (sign_extend:SI
2930 (match_operand:SI 0 "general_operand" "nrmT")
2933 (label_ref:SI (match_operand 2 "" ""))))
2934 (clobber (reg:CC VAX_PSL_REGNUM))]
2938 (define_insn_and_split "*pushsym"
2939 [(set (match_operand:SI 0 "push_operand" "=g")
2940 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
2947 (clobber (reg:CC VAX_PSL_REGNUM))])]
2950 (define_insn "*pushsym_2<ccn><ccnz><ccz>"
2951 [(set (match_operand:SI 0 "push_operand" "=g")
2952 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2953 (clobber (reg:CC VAX_PSL_REGNUM))]
2957 (define_insn_and_split "*movsym"
2958 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2959 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
2966 (clobber (reg:CC VAX_PSL_REGNUM))])]
2969 (define_insn "*movsym_2<ccn><ccnz><ccz>"
2970 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2971 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2972 (clobber (reg:CC VAX_PSL_REGNUM))]
2976 (define_insn_and_split "*pushsymreg"
2977 [(set (match_operand:SI 0 "push_operand" "=g")
2978 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2979 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
2982 "&& reload_completed"
2985 (plus:SI (match_dup 1)
2987 (clobber (reg:CC VAX_PSL_REGNUM))])]
2990 (define_insn "*pushsymreg_2<ccn><ccnz><ccz>"
2991 [(set (match_operand:SI 0 "push_operand" "=g")
2992 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2993 (match_operand:SI 2 "pic_symbolic_operand" "A")))
2994 (clobber (reg:CC VAX_PSL_REGNUM))]
2995 "flag_pic && reload_completed"
2998 (define_insn_and_split "*movsymreg"
2999 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3000 (plus:SI (match_operand:SI 1 "register_operand" "%r")
3001 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
3004 "&& reload_completed"
3007 (plus:SI (match_dup 1)
3009 (clobber (reg:CC VAX_PSL_REGNUM))])]
3012 (define_insn "*movsymreg_2<ccn><ccnz><ccz>"
3013 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3014 (plus:SI (match_operand:SI 1 "register_operand" "%r")
3015 (match_operand:SI 2 "pic_symbolic_operand" "A")))
3016 (clobber (reg:CC VAX_PSL_REGNUM))]
3017 "flag_pic && reload_completed"
3020 ;;- load or push effective address
3021 ;; These come after the move and add/sub patterns
3022 ;; because we don't want pushl $1 turned into pushad 1.
3023 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
3025 ;; It does not work to use constraints to distinguish pushes from moves,
3026 ;; because < matches any autodecrement, not just a push.
3028 (define_insn_and_split "pushaddr<mode>"
3029 [(set (match_operand:SI 0 "push_operand" "=g")
3030 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
3037 (clobber (reg:CC VAX_PSL_REGNUM))])]
3040 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
3041 [(set (match_operand:SI 0 "push_operand" "=g")
3042 (match_operand:VAXintQHSD 1 "address_operand" "p"))
3043 (clobber (reg:CC VAX_PSL_REGNUM))]
3045 "pusha<VAXintQHSD:isfx> %a1")
3047 (define_insn_and_split "movaddr<mode>"
3048 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3049 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
3056 (clobber (reg:CC VAX_PSL_REGNUM))])]
3059 (define_insn "*movaddr<mode><ccn><ccnz><ccz>"
3060 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3061 (match_operand:VAXintQHSD 1 "address_operand" "p"))
3062 (clobber (reg:CC VAX_PSL_REGNUM))]
3064 "mova<VAXintQHSD:isfx> %a1,%0")
3066 (define_insn_and_split "pushaddr<mode>"
3067 [(set (match_operand:SI 0 "push_operand" "=g")
3068 (match_operand:VAXfp 1 "address_operand" "p"))]
3075 (clobber (reg:CC VAX_PSL_REGNUM))])]
3078 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
3079 [(set (match_operand:SI 0 "push_operand" "=g")
3080 (match_operand:VAXfp 1 "address_operand" "p"))
3081 (clobber (reg:CC VAX_PSL_REGNUM))]
3083 "pusha<VAXfp:fsfx> %a1")
3085 (define_insn_and_split "movaddr<mode>"
3086 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3087 (match_operand:VAXfp 1 "address_operand" "p"))]
3094 (clobber (reg:CC VAX_PSL_REGNUM))])]
3097 (define_insn "*movaddr<mode>"
3098 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3099 (match_operand:VAXfp 1 "address_operand" "p"))
3100 (clobber (reg:CC VAX_PSL_REGNUM))]
3102 "mova<VAXfp:fsfx> %a1,%0")
3104 ;; These used to be peepholes, but it is more straightforward to do them
3105 ;; as single insns. However, we must force the output to be a register
3106 ;; if it is not an offsettable address so that we know that we can assign
3109 ;; If we had a good way of evaluating the relative costs, these could be
3110 ;; machine-independent.
3112 ;; Optimize extzv ...,z; andl2 ...,z
3113 ;; or ashl ...,z; andl2 ...,z
3114 ;; with other operands constant. This is what the combiner converts the
3115 ;; above sequences to before attempting to recognize the new insn.
3117 (define_insn_and_split "*andashlnegsi4"
3118 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3119 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
3120 (match_operand:QI 2 "const_int_operand" "n"))
3121 (match_operand:SI 3 "const_int_operand" "n")))]
3122 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
3124 "&& reload_completed"
3127 (and:SI (ashiftrt:SI (match_dup 1)
3130 (clobber (reg:CC VAX_PSL_REGNUM))])]
3133 (define_insn "*andashlnegsi4_2<ccn><ccnz><ccz>"
3134 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3135 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
3136 (match_operand:QI 2 "const_int_operand" "n"))
3137 (match_operand:SI 3 "const_int_operand" "n")))
3138 (clobber (reg:CC VAX_PSL_REGNUM))]
3139 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0
3140 && reload_completed"
3143 unsigned long mask1 = INTVAL (operands[3]);
3144 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
3146 if ((mask1 & mask2) != mask1)
3147 operands[3] = GEN_INT (mask1 & mask2);
3149 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
3152 ;; left-shift and mask
3153 ;; The only case where `ashl' is better is if the mask only turns off
3154 ;; bits that the ashl would anyways, in which case it should have been
3157 (define_insn_and_split "*andashlsi4"
3158 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3159 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
3160 (match_operand:QI 2 "const_int_operand" "n"))
3161 (match_operand:SI 3 "const_int_operand" "n")))]
3167 (and:SI (ashift:SI (match_dup 1)
3170 (clobber (reg:CC VAX_PSL_REGNUM))])]
3173 (define_insn "*andashlsi4_2<ccn><ccnz><ccz>"
3174 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3175 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
3176 (match_operand:QI 2 "const_int_operand" "n"))
3177 (match_operand:SI 3 "const_int_operand" "n")))
3178 (clobber (reg:CC VAX_PSL_REGNUM))]
3183 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
3184 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
3187 ;; Instruction sequence to sync the VAX instruction stream.
3188 (define_insn "sync_istream"
3189 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
3191 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
3193 (define_expand "nonlocal_goto"
3194 [(use (match_operand 0 "general_operand" ""))
3195 (use (match_operand 1 "general_operand" ""))
3196 (use (match_operand 2 "general_operand" ""))
3197 (use (match_operand 3 "general_operand" ""))]
3200 rtx lab = operands[1];
3201 rtx stack = operands[2];
3202 rtx fp = operands[3];
3204 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
3205 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
3207 emit_move_insn (hard_frame_pointer_rtx, fp);
3208 emit_stack_restore (SAVE_NONLOCAL, stack);
3210 emit_use (hard_frame_pointer_rtx);
3211 emit_use (stack_pointer_rtx);
3213 /* We'll convert this to direct jump via a peephole optimization. */
3214 emit_indirect_jump (copy_to_reg (lab));
3219 (include "builtins.md")