gcc/config/visium/gr5.md

   1 ;; Scheduling description for GR5.
   2 ;; Copyright (C) 2013-2015 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; GR5 is a single-issue processor.
  21
  22 ;; CPU execution units:
  23 ;;
  24 ;; issue                  Only one instruction can be issued on a given cycle.
  25 ;;                        There is no need to model the CPU pipeline in any
  26 ;;                        more detail than this.
  27 ;;
  28 ;; mem                    Memory Unit: all accesses to memory.
  29 ;;
  30 ;; eam                    Extended Arithmetic Module: multiply, divide and
  31 ;;                        64-bit shifts.
  32 ;;
  33 ;; fp_slot[0|1|2|3]       The 4 FIFO slots of the floating-point unit.  Only
  34 ;;                        the instruction at slot 0 can execute, but an FP
  35 ;;                        instruction can issue if any of the slots is free.
  36
  37 (define_automaton "gr5,gr5_fpu")
  38
  39 (define_cpu_unit "gr5_issue" "gr5")
  40 (define_cpu_unit "gr5_mem" "gr5")
  41 (define_cpu_unit "gr5_eam" "gr5")
  42 (define_cpu_unit "gr5_fp_slot0,gr5_fp_slot1,gr5_fp_slot2,gr5_fp_slot3" "gr5_fpu")
  43
  44 ;; The CPU instructions which write to general registers and so do not totally
  45 ;; complete until they reach the store stage of the pipeline.  This is not the
  46 ;; complete storage register class: mem_reg, eam_reg and fpu_reg are excluded
  47 ;; since we must keep the reservation sets non-overlapping.
  48 (define_insn_reservation "gr5_storage_register" 1
  49   (and (eq_attr "cpu" "gr5")
  50        (eq_attr "type" "imm_reg,arith,arith2,logic,call"))
  51   "gr5_issue")
  52
  53 (define_insn_reservation "gr5_read_mem" 1
  54   (and (eq_attr "cpu" "gr5")
  55        (eq_attr "type" "mem_reg"))
  56   "gr5_issue + gr5_mem")
  57
  58 ;; The latency of 2 and the reservation of gr5_mem on the second cycle ensures
  59 ;; that no reads will be scheduled on the second cycle, which would otherwise
  60 ;; stall the pipeline for 1 cycle.
  61 (define_insn_reservation "gr5_write_mem" 2
  62   (and (eq_attr "cpu" "gr5")
  63        (eq_attr "type" "reg_mem"))
  64   "gr5_issue, gr5_mem")
  65
  66 ;; Try to avoid the pipeline hazard of addressing off a register that has
  67 ;; not yet been stored.
  68 (define_bypass 2 "gr5_storage_register" "gr5_read_mem"   "gr5_hazard_bypass_p")
  69 (define_bypass 2 "gr5_storage_register" "gr5_write_mem"  "gr5_hazard_bypass_p")
  70 (define_bypass 2 "gr5_read_mem"         "gr5_read_mem"   "gr5_hazard_bypass_p")
  71 (define_bypass 2 "gr5_read_mem"         "gr5_write_mem"  "gr5_hazard_bypass_p")
  72
  73 ;; Other CPU instructions complete by the process stage.
  74 (define_insn_reservation "gr5_cpu_other" 1
  75   (and (eq_attr "cpu" "gr5")
  76        (eq_attr "type" "abs_branch,branch,cmp,ret,rfi,dsi,nop"))
  77   "gr5_issue")
  78
  79 ;; EAM instructions.
  80
  81 (define_insn_reservation "gr5_write_eam" 1
  82   (and (eq_attr "cpu" "gr5")
  83        (eq_attr "type" "reg_eam"))
  84   "gr5_issue")
  85
  86 (define_reservation "gr5_issue_eam" "(gr5_issue + gr5_eam)")
  87
  88 (define_insn_reservation "gr5_read_eam" 1
  89   (and (eq_attr "cpu" "gr5")
  90        (eq_attr "type" "eam_reg"))
  91   "gr5_issue_eam")
  92
  93 ;; Try to avoid the pipeline hazard of addressing off a register that has
  94 ;; not yet been stored.
  95 (define_bypass 2 "gr5_read_eam" "gr5_read_mem"  "gr5_hazard_bypass_p")
  96 (define_bypass 2 "gr5_read_eam" "gr5_write_mem" "gr5_hazard_bypass_p")
  97
  98 (define_insn_reservation "gr5_shiftdi" 1
  99   (and (eq_attr "cpu" "gr5")
 100        (eq_attr "type" "shiftdi"))
 101   "gr5_issue_eam")
 102
 103 (define_insn_reservation "gr5_mul" 3
 104   (and (eq_attr "cpu" "gr5")
 105        (eq_attr "type" "mul"))
 106   "gr5_issue_eam, gr5_eam*2")
 107
 108 (define_insn_reservation "gr5_div" 34
 109   (and (eq_attr "cpu" "gr5")
 110        (eq_attr "type" "div"))
 111   "gr5_issue_eam, gr5_eam*33")
 112
 113 (define_insn_reservation "gr5_divd" 66
 114   (and (eq_attr "cpu" "gr5")
 115        (eq_attr "type" "divd"))
 116   "gr5_issue_eam, gr5_eam*65")
 117
 118 ;; FPU instructions.
 119
 120 (define_reservation "gr5_fp_slotany" "(gr5_fp_slot0 | gr5_fp_slot1 | gr5_fp_slot2 | gr5_fp_slot3)")
 121
 122 (define_insn_reservation "gr5_fp_other" 1
 123   (and (eq_attr "cpu" "gr5")
 124        (eq_attr "type" "fp_reg,reg_fp,fcmp"))
 125   "gr5_issue")
 126
 127 (define_insn_reservation "gr5_fp_1cycle" 2
 128   (and (eq_attr "cpu" "gr5")
 129        (eq_attr "type" "fmove,ftoi"))
 130   "gr5_issue + gr5_fp_slotany, gr5_fp_slot0")
 131
 132 (define_insn_reservation "gr5_fp_2cycle" 3
 133   (and (eq_attr "cpu" "gr5")
 134        (eq_attr "type" "itof"))
 135   "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*2")
 136
 137 (define_insn_reservation "gr5_fp_3cycle" 4
 138   (and (eq_attr "cpu" "gr5")
 139        (eq_attr "type" "fp"))
 140   "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*3")
 141
 142 (define_insn_reservation "gr5_fp_30cycle" 31
 143   (and (eq_attr "cpu" "gr5")
 144        (eq_attr "type" "fdiv,fsqrt"))
 145   "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*30")