1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright (C) 2001-2019 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
41 #include "diagnostic-core.h"
44 #include "fold-const.h"
45 #include "stor-layout.h"
52 #include "langhooks.h"
56 #include "hw-doloop.h"
59 /* This file should be included last. */
60 #include "target-def.h"
62 /* Enumeration for all of the relational tests, so that we can build
63 arrays indexed by the test type, and not worry about the order
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 static char xtensa_hard_regno_mode_ok_p
84 [(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
86 /* Largest block move to handle in-line. */
87 #define LARGEST_MOVE_RATIO 15
89 /* Define the structure for the machine field in struct function. */
90 struct GTY(()) machine_function
92 int accesses_prev_frame
;
96 rtx_insn
*set_frame_ptr_insn
;
97 /* Current frame size calculated by compute_frame_size. */
98 unsigned current_frame_size
;
99 /* Callee-save area size in the current frame calculated by
100 compute_frame_size. */
101 int callee_save_size
;
106 /* Vector, indexed by hard register number, which contains 1 for a
107 register that is allowable in a candidate for leaf function
110 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
112 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
118 static void xtensa_option_override (void);
119 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
120 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
121 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
122 static rtx
gen_conditional_move (enum rtx_code
, machine_mode
, rtx
, rtx
);
123 static rtx
fixup_subreg_mem (rtx
);
124 static struct machine_function
* xtensa_init_machine_status (void);
125 static rtx
xtensa_legitimize_tls_address (rtx
);
126 static rtx
xtensa_legitimize_address (rtx
, rtx
, machine_mode
);
127 static bool xtensa_mode_dependent_address_p (const_rtx
, addr_space_t
);
128 static bool xtensa_return_in_msb (const_tree
);
129 static void printx (FILE *, signed int);
130 static rtx
xtensa_builtin_saveregs (void);
131 static bool xtensa_legitimate_address_p (machine_mode
, rtx
, bool);
132 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
133 int) ATTRIBUTE_UNUSED
;
134 static section
*xtensa_select_rtx_section (machine_mode
, rtx
,
135 unsigned HOST_WIDE_INT
);
136 static bool xtensa_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
137 static int xtensa_register_move_cost (machine_mode
, reg_class_t
,
139 static int xtensa_memory_move_cost (machine_mode
, reg_class_t
, bool);
140 static tree
xtensa_build_builtin_va_list (void);
141 static bool xtensa_return_in_memory (const_tree
, const_tree
);
142 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
144 static void xtensa_function_arg_advance (cumulative_args_t
, machine_mode
,
146 static rtx
xtensa_function_arg (cumulative_args_t
, machine_mode
,
148 static rtx
xtensa_function_incoming_arg (cumulative_args_t
,
149 machine_mode
, const_tree
, bool);
150 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
151 static rtx
xtensa_libcall_value (machine_mode
, const_rtx
);
152 static bool xtensa_function_value_regno_p (const unsigned int);
153 static unsigned int xtensa_function_arg_boundary (machine_mode
,
155 static void xtensa_init_builtins (void);
156 static tree
xtensa_fold_builtin (tree
, int, tree
*, bool);
157 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
158 static void xtensa_va_start (tree
, rtx
);
159 static bool xtensa_frame_pointer_required (void);
160 static rtx
xtensa_static_chain (const_tree
, bool);
161 static void xtensa_asm_trampoline_template (FILE *);
162 static void xtensa_trampoline_init (rtx
, tree
, rtx
);
163 static bool xtensa_output_addr_const_extra (FILE *, rtx
);
164 static bool xtensa_cannot_force_const_mem (machine_mode
, rtx
);
166 static reg_class_t
xtensa_preferred_reload_class (rtx
, reg_class_t
);
167 static reg_class_t
xtensa_preferred_output_reload_class (rtx
, reg_class_t
);
168 static reg_class_t
xtensa_secondary_reload (bool, rtx
, reg_class_t
,
170 struct secondary_reload_info
*);
172 static bool constantpool_address_p (const_rtx addr
);
173 static bool xtensa_legitimate_constant_p (machine_mode
, rtx
);
174 static void xtensa_reorg (void);
175 static bool xtensa_can_use_doloop_p (const widest_int
&, const widest_int
&,
177 static const char *xtensa_invalid_within_doloop (const rtx_insn
*);
179 static bool xtensa_member_type_forces_blk (const_tree
,
182 static void xtensa_conditional_register_usage (void);
183 static unsigned int xtensa_hard_regno_nregs (unsigned int, machine_mode
);
184 static bool xtensa_hard_regno_mode_ok (unsigned int, machine_mode
);
185 static bool xtensa_modes_tieable_p (machine_mode
, machine_mode
);
186 static HOST_WIDE_INT
xtensa_constant_alignment (const_tree
, HOST_WIDE_INT
);
187 static HOST_WIDE_INT
xtensa_starting_frame_offset (void);
188 static unsigned HOST_WIDE_INT
xtensa_asan_shadow_offset (void);
192 /* These hooks specify assembly directives for creating certain kinds
193 of integer object. */
195 #undef TARGET_ASM_ALIGNED_SI_OP
196 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
198 #undef TARGET_ASM_SELECT_RTX_SECTION
199 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
201 #undef TARGET_LEGITIMIZE_ADDRESS
202 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
203 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
204 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
206 #undef TARGET_REGISTER_MOVE_COST
207 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
208 #undef TARGET_MEMORY_MOVE_COST
209 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
210 #undef TARGET_RTX_COSTS
211 #define TARGET_RTX_COSTS xtensa_rtx_costs
212 #undef TARGET_ADDRESS_COST
213 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
215 #undef TARGET_MEMBER_TYPE_FORCES_BLK
216 #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk
218 #undef TARGET_BUILD_BUILTIN_VA_LIST
219 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
221 #undef TARGET_EXPAND_BUILTIN_VA_START
222 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
224 #undef TARGET_PROMOTE_FUNCTION_MODE
225 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
226 #undef TARGET_PROMOTE_PROTOTYPES
227 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
229 #undef TARGET_RETURN_IN_MEMORY
230 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
231 #undef TARGET_FUNCTION_VALUE
232 #define TARGET_FUNCTION_VALUE xtensa_function_value
233 #undef TARGET_LIBCALL_VALUE
234 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
235 #undef TARGET_FUNCTION_VALUE_REGNO_P
236 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
238 #undef TARGET_SPLIT_COMPLEX_ARG
239 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
240 #undef TARGET_MUST_PASS_IN_STACK
241 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
242 #undef TARGET_FUNCTION_ARG_ADVANCE
243 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
244 #undef TARGET_FUNCTION_ARG
245 #define TARGET_FUNCTION_ARG xtensa_function_arg
246 #undef TARGET_FUNCTION_INCOMING_ARG
247 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
248 #undef TARGET_FUNCTION_ARG_BOUNDARY
249 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
251 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
252 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
253 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
254 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
256 #undef TARGET_RETURN_IN_MSB
257 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
259 #undef TARGET_INIT_BUILTINS
260 #define TARGET_INIT_BUILTINS xtensa_init_builtins
261 #undef TARGET_FOLD_BUILTIN
262 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
263 #undef TARGET_EXPAND_BUILTIN
264 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
266 #undef TARGET_PREFERRED_RELOAD_CLASS
267 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
268 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
269 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
271 #undef TARGET_SECONDARY_RELOAD
272 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
274 #undef TARGET_HAVE_TLS
275 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
277 #undef TARGET_CANNOT_FORCE_CONST_MEM
278 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
281 #define TARGET_LRA_P hook_bool_void_false
283 #undef TARGET_LEGITIMATE_ADDRESS_P
284 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
286 #undef TARGET_FRAME_POINTER_REQUIRED
287 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
289 #undef TARGET_STATIC_CHAIN
290 #define TARGET_STATIC_CHAIN xtensa_static_chain
291 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
292 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
293 #undef TARGET_TRAMPOLINE_INIT
294 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
296 #undef TARGET_OPTION_OVERRIDE
297 #define TARGET_OPTION_OVERRIDE xtensa_option_override
299 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
300 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
302 #undef TARGET_LEGITIMATE_CONSTANT_P
303 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p
305 #undef TARGET_MACHINE_DEPENDENT_REORG
306 #define TARGET_MACHINE_DEPENDENT_REORG xtensa_reorg
308 #undef TARGET_CAN_USE_DOLOOP_P
309 #define TARGET_CAN_USE_DOLOOP_P xtensa_can_use_doloop_p
311 #undef TARGET_INVALID_WITHIN_DOLOOP
312 #define TARGET_INVALID_WITHIN_DOLOOP xtensa_invalid_within_doloop
314 #undef TARGET_CONDITIONAL_REGISTER_USAGE
315 #define TARGET_CONDITIONAL_REGISTER_USAGE xtensa_conditional_register_usage
317 #undef TARGET_HARD_REGNO_NREGS
318 #define TARGET_HARD_REGNO_NREGS xtensa_hard_regno_nregs
319 #undef TARGET_HARD_REGNO_MODE_OK
320 #define TARGET_HARD_REGNO_MODE_OK xtensa_hard_regno_mode_ok
322 #undef TARGET_MODES_TIEABLE_P
323 #define TARGET_MODES_TIEABLE_P xtensa_modes_tieable_p
325 #undef TARGET_CONSTANT_ALIGNMENT
326 #define TARGET_CONSTANT_ALIGNMENT xtensa_constant_alignment
328 #undef TARGET_STARTING_FRAME_OFFSET
329 #define TARGET_STARTING_FRAME_OFFSET xtensa_starting_frame_offset
331 #undef TARGET_ASAN_SHADOW_OFFSET
332 #define TARGET_ASAN_SHADOW_OFFSET xtensa_asan_shadow_offset
334 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
335 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
337 struct gcc_target targetm
= TARGET_INITIALIZER
;
340 /* Functions to test Xtensa immediate operand validity. */
343 xtensa_simm8 (HOST_WIDE_INT v
)
345 return v
>= -128 && v
<= 127;
350 xtensa_simm8x256 (HOST_WIDE_INT v
)
352 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
357 xtensa_simm12b (HOST_WIDE_INT v
)
359 return v
>= -2048 && v
<= 2047;
364 xtensa_uimm8 (HOST_WIDE_INT v
)
366 return v
>= 0 && v
<= 255;
371 xtensa_uimm8x2 (HOST_WIDE_INT v
)
373 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
378 xtensa_uimm8x4 (HOST_WIDE_INT v
)
380 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
385 xtensa_b4const (HOST_WIDE_INT v
)
412 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
416 return xtensa_b4const (v
);
421 xtensa_b4constu (HOST_WIDE_INT v
)
448 xtensa_mask_immediate (HOST_WIDE_INT v
)
450 #define MAX_MASK_SIZE 16
453 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
466 /* This is just like the standard true_regnum() function except that it
467 works even when reg_renumber is not initialized. */
470 xt_true_regnum (rtx x
)
472 if (GET_CODE (x
) == REG
)
475 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
476 && reg_renumber
[REGNO (x
)] >= 0)
477 return reg_renumber
[REGNO (x
)];
480 if (GET_CODE (x
) == SUBREG
)
482 int base
= xt_true_regnum (SUBREG_REG (x
));
483 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
484 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
485 GET_MODE (SUBREG_REG (x
)),
486 SUBREG_BYTE (x
), GET_MODE (x
));
493 xtensa_valid_move (machine_mode mode
, rtx
*operands
)
495 /* Either the destination or source must be a register, and the
496 MAC16 accumulator doesn't count. */
498 if (register_operand (operands
[0], mode
))
500 int dst_regnum
= xt_true_regnum (operands
[0]);
502 if (xtensa_tls_referenced_p (operands
[1]))
505 /* The stack pointer can only be assigned with a MOVSP opcode. */
506 if (dst_regnum
== STACK_POINTER_REGNUM
)
507 return !TARGET_WINDOWED_ABI
509 && register_operand (operands
[1], mode
)
510 && !ACC_REG_P (xt_true_regnum (operands
[1])));
512 if (!ACC_REG_P (dst_regnum
))
515 if (register_operand (operands
[1], mode
))
517 int src_regnum
= xt_true_regnum (operands
[1]);
518 if (!ACC_REG_P (src_regnum
))
526 smalloffset_mem_p (rtx op
)
528 if (GET_CODE (op
) == MEM
)
530 rtx addr
= XEXP (op
, 0);
531 if (GET_CODE (addr
) == REG
)
532 return BASE_REG_P (addr
, 0);
533 if (GET_CODE (addr
) == PLUS
)
535 rtx offset
= XEXP (addr
, 0);
537 if (GET_CODE (offset
) != CONST_INT
)
538 offset
= XEXP (addr
, 1);
539 if (GET_CODE (offset
) != CONST_INT
)
542 val
= INTVAL (offset
);
543 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
551 constantpool_address_p (const_rtx addr
)
553 const_rtx sym
= addr
;
555 if (GET_CODE (addr
) == CONST
)
559 /* Only handle (PLUS (SYM, OFFSET)) form. */
560 addr
= XEXP (addr
, 0);
561 if (GET_CODE (addr
) != PLUS
)
564 /* Make sure the address is word aligned. */
565 offset
= XEXP (addr
, 1);
566 if ((!CONST_INT_P (offset
))
567 || ((INTVAL (offset
) & 3) != 0))
570 sym
= XEXP (addr
, 0);
573 if ((GET_CODE (sym
) == SYMBOL_REF
)
574 && CONSTANT_POOL_ADDRESS_P (sym
))
581 constantpool_mem_p (rtx op
)
583 if (GET_CODE (op
) == SUBREG
)
584 op
= SUBREG_REG (op
);
585 if (GET_CODE (op
) == MEM
)
586 return constantpool_address_p (XEXP (op
, 0));
591 /* Return TRUE if X is a thread-local symbol. */
594 xtensa_tls_symbol_p (rtx x
)
596 if (! TARGET_HAVE_TLS
)
599 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
604 xtensa_extend_reg (rtx dst
, rtx src
)
606 rtx temp
= gen_reg_rtx (SImode
);
607 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
609 /* Generate paradoxical subregs as needed so that the modes match. */
610 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
611 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
613 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
614 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
619 xtensa_mem_offset (unsigned v
, machine_mode mode
)
624 /* Handle the worst case for block moves. See xtensa_expand_block_move
625 where we emit an optimized block move operation if the block can be
626 moved in < "move_ratio" pieces. The worst case is when the block is
627 aligned but has a size of (3 mod 4) (does this happen?) so that the
628 last piece requires a byte load/store. */
629 return (xtensa_uimm8 (v
)
630 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
633 return xtensa_uimm8 (v
);
636 return xtensa_uimm8x2 (v
);
640 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
646 return xtensa_uimm8x4 (v
);
650 /* Make normal rtx_code into something we can index from an array. */
652 static enum internal_test
653 map_test_to_internal_test (enum rtx_code test_code
)
655 enum internal_test test
= ITEST_MAX
;
660 case EQ
: test
= ITEST_EQ
; break;
661 case NE
: test
= ITEST_NE
; break;
662 case GT
: test
= ITEST_GT
; break;
663 case GE
: test
= ITEST_GE
; break;
664 case LT
: test
= ITEST_LT
; break;
665 case LE
: test
= ITEST_LE
; break;
666 case GTU
: test
= ITEST_GTU
; break;
667 case GEU
: test
= ITEST_GEU
; break;
668 case LTU
: test
= ITEST_LTU
; break;
669 case LEU
: test
= ITEST_LEU
; break;
676 /* Generate the code to compare two integer values. The return value is
677 the comparison expression. */
680 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
681 rtx cmp0
, /* first operand to compare */
682 rtx cmp1
, /* second operand to compare */
683 int *p_invert
/* whether branch needs to reverse test */)
687 enum rtx_code test_code
; /* test code to use in insn */
688 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
689 int const_add
; /* constant to add (convert LE -> LT) */
690 int reverse_regs
; /* reverse registers in test */
691 int invert_const
; /* != 0 if invert value if cmp1 is constant */
692 int invert_reg
; /* != 0 if invert value if cmp1 is register */
693 int unsignedp
; /* != 0 for unsigned comparisons. */
696 static struct cmp_info info
[ (int)ITEST_MAX
] = {
698 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
699 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
701 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
702 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
703 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
704 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
706 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
707 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
708 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
709 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
712 enum internal_test test
;
714 struct cmp_info
*p_info
;
716 test
= map_test_to_internal_test (test_code
);
717 gcc_assert (test
!= ITEST_MAX
);
719 p_info
= &info
[ (int)test
];
721 mode
= GET_MODE (cmp0
);
722 if (mode
== VOIDmode
)
723 mode
= GET_MODE (cmp1
);
725 /* Make sure we can handle any constants given to us. */
726 if (GET_CODE (cmp1
) == CONST_INT
)
728 HOST_WIDE_INT value
= INTVAL (cmp1
);
729 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
731 /* if the immediate overflows or does not fit in the immediate field,
732 spill it to a register */
734 if ((p_info
->unsignedp
?
735 (uvalue
+ p_info
->const_add
> uvalue
) :
736 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
738 cmp1
= force_reg (mode
, cmp1
);
740 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
742 cmp1
= force_reg (mode
, cmp1
);
745 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
747 cmp1
= force_reg (mode
, cmp1
);
750 /* See if we need to invert the result. */
751 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
752 ? p_info
->invert_const
753 : p_info
->invert_reg
);
755 /* Comparison to constants, may involve adding 1 to change a LT into LE.
756 Comparison between two registers, may involve switching operands. */
757 if (GET_CODE (cmp1
) == CONST_INT
)
759 if (p_info
->const_add
!= 0)
760 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
763 else if (p_info
->reverse_regs
)
770 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
774 /* Generate the code to compare two float values. The return value is
775 the comparison expression. */
778 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
779 rtx cmp0
, /* first operand to compare */
780 rtx cmp1
/* second operand to compare */)
782 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
784 int reverse_regs
, invert
;
788 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
789 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
790 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
791 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
792 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
793 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
794 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
795 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
796 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
797 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
798 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
799 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
801 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
803 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
805 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
806 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
816 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
817 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
819 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
824 xtensa_expand_conditional_branch (rtx
*operands
, machine_mode mode
)
826 enum rtx_code test_code
= GET_CODE (operands
[0]);
827 rtx cmp0
= operands
[1];
828 rtx cmp1
= operands
[2];
837 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
841 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
845 if (!TARGET_HARD_FLOAT
)
846 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
849 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
853 /* Generate the branch. */
855 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
864 emit_jump_insn (gen_rtx_SET (pc_rtx
,
865 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
872 gen_conditional_move (enum rtx_code code
, machine_mode mode
,
879 /* Jump optimization calls get_condition() which canonicalizes
880 comparisons like (GE x <const>) to (GT x <const-1>).
881 Transform those comparisons back to GE, since that is the
882 comparison supported in Xtensa. We shouldn't have to
883 transform <LE x const> comparisons, because neither
884 xtensa_expand_conditional_branch() nor get_condition() will
887 if ((code
== GT
) && (op1
== constm1_rtx
))
892 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
894 if (boolean_operator (cmp
, VOIDmode
))
896 /* Swap the operands to make const0 second. */
897 if (op0
== const0_rtx
)
903 /* If not comparing against zero, emit a comparison (subtract). */
904 if (op1
!= const0_rtx
)
906 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
907 0, 0, OPTAB_LIB_WIDEN
);
911 else if (branch_operator (cmp
, VOIDmode
))
913 /* Swap the operands to make const0 second. */
914 if (op0
== const0_rtx
)
921 case LT
: code
= GE
; break;
922 case GE
: code
= LT
; break;
923 default: gcc_unreachable ();
927 if (op1
!= const0_rtx
)
933 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
936 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
937 return gen_float_relational (code
, op0
, op1
);
944 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
946 rtx dest
= operands
[0];
947 rtx cmp
= operands
[1];
948 machine_mode cmp_mode
= GET_MODE (XEXP (cmp
, 0));
949 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
951 if (!(cmp
= gen_conditional_move (GET_CODE (cmp
), cmp_mode
,
952 XEXP (cmp
, 0), XEXP (cmp
, 1))))
956 gen_fn
= (cmp_mode
== SImode
957 ? gen_movsfcc_internal0
958 : gen_movsfcc_internal1
);
960 gen_fn
= (cmp_mode
== SImode
961 ? gen_movsicc_internal0
962 : gen_movsicc_internal1
);
964 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), operands
[2], operands
[3], cmp
));
970 xtensa_expand_scc (rtx operands
[4], machine_mode cmp_mode
)
972 rtx dest
= operands
[0];
974 rtx one_tmp
, zero_tmp
;
975 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
977 if (!(cmp
= gen_conditional_move (GET_CODE (operands
[1]), cmp_mode
,
978 operands
[2], operands
[3])))
981 one_tmp
= gen_reg_rtx (SImode
);
982 zero_tmp
= gen_reg_rtx (SImode
);
983 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
984 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
986 gen_fn
= (cmp_mode
== SImode
987 ? gen_movsicc_internal0
988 : gen_movsicc_internal1
);
989 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
994 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
995 for the output, i.e., the input operands are twice as big as MODE. */
998 xtensa_split_operand_pair (rtx operands
[4], machine_mode mode
)
1000 switch (GET_CODE (operands
[1]))
1003 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
1004 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
1008 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
1009 operands
[2] = adjust_address (operands
[1], mode
, 0);
1014 split_double (operands
[1], &operands
[2], &operands
[3]);
1021 switch (GET_CODE (operands
[0]))
1024 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
1025 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
1029 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
1030 operands
[0] = adjust_address (operands
[0], mode
, 0);
1039 /* Emit insns to move operands[1] into operands[0].
1040 Return 1 if we have written out everything that needs to be done to
1041 do the move. Otherwise, return 0 and the caller will emit the move
1045 xtensa_emit_move_sequence (rtx
*operands
, machine_mode mode
)
1047 rtx src
= operands
[1];
1049 if (CONSTANT_P (src
)
1050 && (GET_CODE (src
) != CONST_INT
|| ! xtensa_simm12b (INTVAL (src
))))
1052 rtx dst
= operands
[0];
1054 if (xtensa_tls_referenced_p (src
))
1058 if (GET_CODE (src
) == CONST
&& GET_CODE (XEXP (src
, 0)) == PLUS
)
1060 addend
= XEXP (XEXP (src
, 0), 1);
1061 src
= XEXP (XEXP (src
, 0), 0);
1064 src
= xtensa_legitimize_tls_address (src
);
1067 src
= gen_rtx_PLUS (mode
, src
, addend
);
1068 src
= force_operand (src
, dst
);
1070 emit_move_insn (dst
, src
);
1074 if (! TARGET_AUTO_LITPOOLS
&& ! TARGET_CONST16
)
1076 src
= force_const_mem (SImode
, src
);
1080 /* PC-relative loads are always SImode, and CONST16 is only
1081 supported in the movsi pattern, so add a SUBREG for any other
1086 if (register_operand (dst
, mode
))
1088 emit_move_insn (simplify_gen_subreg (SImode
, dst
, mode
, 0), src
);
1093 src
= force_reg (SImode
, src
);
1094 src
= gen_lowpart_SUBREG (mode
, src
);
1100 if (!(reload_in_progress
| reload_completed
)
1101 && !xtensa_valid_move (mode
, operands
))
1102 operands
[1] = force_reg (mode
, operands
[1]);
1104 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
1106 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1107 instruction won't be recognized after reload, so we remove the
1108 subreg and adjust mem accordingly. */
1109 if (reload_in_progress
)
1111 operands
[0] = fixup_subreg_mem (operands
[0]);
1112 operands
[1] = fixup_subreg_mem (operands
[1]);
1119 fixup_subreg_mem (rtx x
)
1121 if (GET_CODE (x
) == SUBREG
1122 && GET_CODE (SUBREG_REG (x
)) == REG
1123 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
1126 gen_rtx_SUBREG (GET_MODE (x
),
1127 reg_equiv_mem (REGNO (SUBREG_REG (x
))),
1129 x
= alter_subreg (&temp
, true);
1135 /* Check if an incoming argument in a7 is expected to be used soon and
1136 if OPND is a register or register pair that includes a7. If so,
1137 create a new pseudo and copy a7 into that pseudo at the very
1138 beginning of the function, followed by the special "set_frame_ptr"
1139 unspec_volatile insn. The return value is either the original
1140 operand, if it is not a7, or the new pseudo containing a copy of
1141 the incoming argument. This is necessary because the register
1142 allocator will ignore conflicts with a7 and may either assign some
1143 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1144 the incoming argument in a7. By copying the argument out of a7 as
1145 the very first thing, and then immediately following that with an
1146 unspec_volatile to keep the scheduler away, we should avoid any
1147 problems. Putting the set_frame_ptr insn at the beginning, with
1148 only the a7 copy before it, also makes it easier for the prologue
1149 expander to initialize the frame pointer after the a7 copy and to
1150 fix up the a7 copy to use the stack pointer instead of the frame
1154 xtensa_copy_incoming_a7 (rtx opnd
)
1156 rtx entry_insns
= 0;
1160 if (!cfun
->machine
->need_a7_copy
)
1163 /* This function should never be called again once a7 has been copied. */
1164 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1166 mode
= GET_MODE (opnd
);
1168 /* The operand using a7 may come in a later instruction, so just return
1169 the original operand if it doesn't use a7. */
1171 if (GET_CODE (reg
) == SUBREG
)
1173 gcc_assert (SUBREG_BYTE (reg
) == 0);
1174 reg
= SUBREG_REG (reg
);
1176 if (GET_CODE (reg
) != REG
1177 || REGNO (reg
) > A7_REG
1178 || REGNO (reg
) + hard_regno_nregs (A7_REG
, mode
) <= A7_REG
)
1181 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1182 gcc_assert (REGNO (reg
) + hard_regno_nregs (A7_REG
, mode
) - 1 == A7_REG
);
1184 cfun
->machine
->need_a7_copy
= false;
1186 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1187 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1190 tmp
= gen_reg_rtx (mode
);
1196 /* Copy the value out of A7 here but keep the first word in A6 until
1197 after the set_frame_ptr insn. Otherwise, the register allocator
1198 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1200 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1201 gen_raw_REG (SImode
, A7_REG
)));
1204 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1207 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1210 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1213 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1219 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1221 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1222 if (mode
== DFmode
|| mode
== DImode
)
1223 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1224 gen_rtx_REG (SImode
, A7_REG
- 1)));
1225 entry_insns
= get_insns ();
1228 if (cfun
->machine
->vararg_a7
)
1230 /* This is called from within builtin_saveregs, which will insert the
1231 saveregs code at the function entry, ahead of anything placed at
1232 the function entry now. Instead, save the sequence to be inserted
1233 at the beginning of the saveregs code. */
1234 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1238 /* Put entry_insns after the NOTE that starts the function. If
1239 this is inside a start_sequence, make the outer-level insn
1240 chain current, so the code is placed at the start of the
1242 push_topmost_sequence ();
1243 /* Do not use entry_of_function() here. This is called from within
1244 expand_function_start, when the CFG still holds GIMPLE. */
1245 emit_insn_after (entry_insns
, get_insns ());
1246 pop_topmost_sequence ();
1253 /* Try to expand a block move operation to a sequence of RTL move
1254 instructions. If not optimizing, or if the block size is not a
1255 constant, or if the block is too large, the expansion fails and GCC
1256 falls back to calling memcpy().
1258 operands[0] is the destination
1259 operands[1] is the source
1260 operands[2] is the length
1261 operands[3] is the alignment */
1264 xtensa_expand_block_move (rtx
*operands
)
1266 static const machine_mode mode_from_align
[] =
1268 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1271 rtx dst_mem
= operands
[0];
1272 rtx src_mem
= operands
[1];
1273 HOST_WIDE_INT bytes
, align
;
1274 int num_pieces
, move_ratio
;
1276 machine_mode mode
[2];
1285 /* If this is not a fixed size move, just call memcpy. */
1286 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1289 bytes
= INTVAL (operands
[2]);
1290 align
= INTVAL (operands
[3]);
1292 /* Anything to move? */
1296 if (align
> MOVE_MAX
)
1299 /* Decide whether to expand inline based on the optimization level. */
1302 move_ratio
= LARGEST_MOVE_RATIO
;
1303 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1304 if (num_pieces
> move_ratio
)
1307 x
= XEXP (dst_mem
, 0);
1310 x
= force_reg (Pmode
, x
);
1311 dst_mem
= replace_equiv_address (dst_mem
, x
);
1314 x
= XEXP (src_mem
, 0);
1317 x
= force_reg (Pmode
, x
);
1318 src_mem
= replace_equiv_address (src_mem
, x
);
1321 active
[0] = active
[1] = false;
1332 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1333 next_amount
= MIN (next_amount
, align
);
1335 amount
[next
] = next_amount
;
1336 mode
[next
] = mode_from_align
[next_amount
];
1337 temp
[next
] = gen_reg_rtx (mode
[next
]);
1339 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1340 emit_insn (gen_rtx_SET (temp
[next
], x
));
1342 offset_ld
+= next_amount
;
1343 bytes
-= next_amount
;
1344 active
[next
] = true;
1349 active
[phase
] = false;
1351 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1352 emit_insn (gen_rtx_SET (x
, temp
[phase
]));
1354 offset_st
+= amount
[phase
];
1357 while (active
[next
]);
1364 xtensa_expand_nonlocal_goto (rtx
*operands
)
1366 rtx goto_handler
= operands
[1];
1367 rtx containing_fp
= operands
[3];
1369 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1370 is too big to generate in-line. */
1372 if (GET_CODE (containing_fp
) != REG
)
1373 containing_fp
= force_reg (Pmode
, containing_fp
);
1375 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1376 LCT_NORMAL
, VOIDmode
,
1377 containing_fp
, Pmode
,
1378 goto_handler
, Pmode
);
1382 static struct machine_function
*
1383 xtensa_init_machine_status (void)
1385 return ggc_cleared_alloc
<machine_function
> ();
1389 /* Shift VAL of mode MODE left by COUNT bits. */
1392 xtensa_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
1394 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1395 NULL_RTX
, 1, OPTAB_DIRECT
);
1396 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1397 NULL_RTX
, 1, OPTAB_DIRECT
);
1401 /* Structure to hold the initial parameters for a compare_and_swap operation
1402 in HImode and QImode. */
1404 struct alignment_context
1406 rtx memsi
; /* SI aligned memory location. */
1407 rtx shift
; /* Bit offset with regard to lsb. */
1408 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1409 rtx modemaski
; /* ~modemask */
1413 /* Initialize structure AC for word access to HI and QI mode memory. */
1416 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1418 machine_mode mode
= GET_MODE (mem
);
1419 rtx byteoffset
= NULL_RTX
;
1420 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1423 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1426 /* Alignment is unknown. */
1429 /* Force the address into a register. */
1430 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1432 /* Align it to SImode. */
1433 align
= expand_simple_binop (Pmode
, AND
, addr
,
1434 GEN_INT (-GET_MODE_SIZE (SImode
)),
1435 NULL_RTX
, 1, OPTAB_DIRECT
);
1437 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1438 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1439 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1440 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1442 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1443 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1444 NULL_RTX
, 1, OPTAB_DIRECT
);
1447 /* Calculate shiftcount. */
1448 if (TARGET_BIG_ENDIAN
)
1450 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1452 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1453 NULL_RTX
, 1, OPTAB_DIRECT
);
1458 ac
->shift
= NULL_RTX
;
1460 ac
->shift
= byteoffset
;
1463 if (ac
->shift
!= NULL_RTX
)
1465 /* Shift is the byte count, but we need the bitcount. */
1466 gcc_assert (exact_log2 (BITS_PER_UNIT
) >= 0);
1467 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
,
1468 GEN_INT (exact_log2 (BITS_PER_UNIT
)),
1469 NULL_RTX
, 1, OPTAB_DIRECT
);
1470 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1471 GEN_INT (GET_MODE_MASK (mode
)),
1473 NULL_RTX
, 1, OPTAB_DIRECT
);
1476 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1478 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1482 /* Expand an atomic compare and swap operation for HImode and QImode.
1483 MEM is the memory location, CMP the old value to compare MEM with
1484 and NEW_RTX the value to set if CMP == MEM. */
1487 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
1489 machine_mode mode
= GET_MODE (mem
);
1490 struct alignment_context ac
;
1491 rtx tmp
, cmpv
, newv
, val
;
1492 rtx oldval
= gen_reg_rtx (SImode
);
1493 rtx res
= gen_reg_rtx (SImode
);
1494 rtx_code_label
*csloop
= gen_label_rtx ();
1495 rtx_code_label
*csend
= gen_label_rtx ();
1497 init_alignment_context (&ac
, mem
);
1499 if (ac
.shift
!= NULL_RTX
)
1501 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1502 new_rtx
= xtensa_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
1505 /* Load the surrounding word into VAL with the MEM value masked out. */
1506 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1507 ac
.modemaski
, NULL_RTX
, 1,
1509 emit_label (csloop
);
1511 /* Patch CMP and NEW_RTX into VAL at correct position. */
1512 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1513 NULL_RTX
, 1, OPTAB_DIRECT
));
1514 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
1515 NULL_RTX
, 1, OPTAB_DIRECT
));
1517 /* Jump to end if we're done. */
1518 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1519 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1521 /* Check for changes outside mode. */
1522 emit_move_insn (oldval
, val
);
1523 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1524 val
, 1, OPTAB_DIRECT
);
1526 emit_move_insn (val
, tmp
);
1528 /* Loop internal if so. */
1529 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1533 /* Return the correct part of the bitfield. */
1534 convert_move (target
,
1535 (ac
.shift
== NULL_RTX
? res
1536 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1537 NULL_RTX
, 1, OPTAB_DIRECT
)),
1542 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1543 the default expansion works fine for SImode). MEM is the memory location
1544 and VAL the value to play with. If AFTER is true then store the value
1545 MEM holds after the operation, if AFTER is false then store the value MEM
1546 holds before the operation. If TARGET is zero then discard that value, else
1547 store it to TARGET. */
1550 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1553 machine_mode mode
= GET_MODE (mem
);
1554 struct alignment_context ac
;
1555 rtx_code_label
*csloop
= gen_label_rtx ();
1557 rtx old
= gen_reg_rtx (SImode
);
1558 rtx new_rtx
= gen_reg_rtx (SImode
);
1559 rtx orig
= NULL_RTX
;
1561 init_alignment_context (&ac
, mem
);
1563 /* Prepare values before the compare-and-swap loop. */
1564 if (ac
.shift
!= NULL_RTX
)
1565 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1570 orig
= gen_reg_rtx (SImode
);
1571 convert_move (orig
, val
, 1);
1579 case MULT
: /* NAND */
1581 /* val = "11..1<val>11..1" */
1582 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1583 NULL_RTX
, 1, OPTAB_DIRECT
);
1590 /* Load full word. Subsequent loads are performed by S32C1I. */
1591 cmp
= force_reg (SImode
, ac
.memsi
);
1593 emit_label (csloop
);
1594 emit_move_insn (old
, cmp
);
1600 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1601 NULL_RTX
, 1, OPTAB_DIRECT
);
1602 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1603 NULL_RTX
, 1, OPTAB_DIRECT
);
1606 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1607 NULL_RTX
, 1, OPTAB_DIRECT
);
1608 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1609 new_rtx
, 1, OPTAB_DIRECT
);
1615 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1616 new_rtx
, 1, OPTAB_DIRECT
);
1619 case MULT
: /* NAND */
1620 tmp
= expand_simple_binop (SImode
, AND
, old
, val
,
1621 NULL_RTX
, 1, OPTAB_DIRECT
);
1622 tmp
= expand_simple_binop (SImode
, XOR
, tmp
, ac
.modemask
,
1623 new_rtx
, 1, OPTAB_DIRECT
);
1631 emit_move_insn (new_rtx
, tmp
);
1632 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new_rtx
));
1633 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1637 tmp
= (after
? new_rtx
: cmp
);
1638 convert_move (target
,
1639 (ac
.shift
== NULL_RTX
? tmp
1640 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1641 NULL_RTX
, 1, OPTAB_DIRECT
)),
1648 xtensa_setup_frame_addresses (void)
1650 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1651 cfun
->machine
->accesses_prev_frame
= 1;
1653 if (TARGET_WINDOWED_ABI
)
1655 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1656 LCT_NORMAL
, VOIDmode
);
1660 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1661 a comment showing where the end of the loop is. However, if there is a
1662 label or a branch at the end of the loop then we need to place a nop
1663 there. If the loop ends with a label we need the nop so that branches
1664 targeting that label will target the nop (and thus remain in the loop),
1665 instead of targeting the instruction after the loop (and thus exiting
1666 the loop). If the loop ends with a branch, we need the nop in case the
1667 branch is targeting a location inside the loop. When the branch
1668 executes it will cause the loop count to be decremented even if it is
1669 taken (because it is the last instruction in the loop), so we need to
1670 nop after the branch to prevent the loop count from being decremented
1671 when the branch is taken. */
1674 xtensa_emit_loop_end (rtx_insn
*insn
, rtx
*operands
)
1678 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1680 switch (GET_CODE (insn
))
1687 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1693 rtx body
= PATTERN (insn
);
1697 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1700 else if ((GET_CODE (body
) != USE
)
1701 && (GET_CODE (body
) != CLOBBER
))
1708 output_asm_insn ("%1_LEND:", operands
);
1713 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1715 static char result
[64];
1719 code
= GET_CODE (operands
[3]);
1722 case EQ
: op
= inverted
? "ne" : "eq"; break;
1723 case NE
: op
= inverted
? "eq" : "ne"; break;
1724 case LT
: op
= inverted
? "ge" : "lt"; break;
1725 case GE
: op
= inverted
? "lt" : "ge"; break;
1726 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1727 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1728 default: gcc_unreachable ();
1733 if (INTVAL (operands
[1]) == 0)
1734 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1735 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1737 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1740 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1747 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1749 static char result
[64];
1752 switch (GET_CODE (operands
[3]))
1754 case EQ
: op
= inverted
? "bs" : "bc"; break;
1755 case NE
: op
= inverted
? "bc" : "bs"; break;
1756 default: gcc_unreachable ();
1761 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1762 operands
[1] = GEN_INT (bitnum
);
1763 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1766 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1773 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1775 static char result
[64];
1779 code
= GET_CODE (operands
[4]);
1784 case EQ
: op
= inverted
? "t" : "f"; break;
1785 case NE
: op
= inverted
? "f" : "t"; break;
1786 default: gcc_unreachable ();
1793 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1794 case NE
: op
= inverted
? "eqz" : "nez"; break;
1795 case LT
: op
= inverted
? "gez" : "ltz"; break;
1796 case GE
: op
= inverted
? "ltz" : "gez"; break;
1797 default: gcc_unreachable ();
1801 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1802 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1808 xtensa_emit_call (int callop
, rtx
*operands
)
1810 static char result
[64];
1811 rtx tgt
= operands
[callop
];
1813 if (GET_CODE (tgt
) == CONST_INT
)
1814 sprintf (result
, "call%d\t" HOST_WIDE_INT_PRINT_HEX
,
1815 WINDOW_SIZE
, INTVAL (tgt
));
1816 else if (register_operand (tgt
, VOIDmode
))
1817 sprintf (result
, "callx%d\t%%%d", WINDOW_SIZE
, callop
);
1819 sprintf (result
, "call%d\t%%%d", WINDOW_SIZE
, callop
);
1826 xtensa_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
1828 /* Allow constant pool addresses. */
1829 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1830 && ! TARGET_CONST16
&& constantpool_address_p (addr
)
1831 && ! xtensa_tls_referenced_p (addr
))
1834 while (GET_CODE (addr
) == SUBREG
)
1835 addr
= SUBREG_REG (addr
);
1837 /* Allow base registers. */
1838 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1841 /* Check for "register + offset" addressing. */
1842 if (GET_CODE (addr
) == PLUS
)
1844 rtx xplus0
= XEXP (addr
, 0);
1845 rtx xplus1
= XEXP (addr
, 1);
1846 enum rtx_code code0
;
1847 enum rtx_code code1
;
1849 while (GET_CODE (xplus0
) == SUBREG
)
1850 xplus0
= SUBREG_REG (xplus0
);
1851 code0
= GET_CODE (xplus0
);
1853 while (GET_CODE (xplus1
) == SUBREG
)
1854 xplus1
= SUBREG_REG (xplus1
);
1855 code1
= GET_CODE (xplus1
);
1857 /* Swap operands if necessary so the register is first. */
1858 if (code0
!= REG
&& code1
== REG
)
1860 xplus0
= XEXP (addr
, 1);
1861 xplus1
= XEXP (addr
, 0);
1862 code0
= GET_CODE (xplus0
);
1863 code1
= GET_CODE (xplus1
);
1866 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1867 && code1
== CONST_INT
1868 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1876 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1878 static GTY(()) rtx xtensa_tls_module_base_symbol
;
1881 xtensa_tls_module_base (void)
1883 if (! xtensa_tls_module_base_symbol
)
1885 xtensa_tls_module_base_symbol
=
1886 gen_rtx_SYMBOL_REF (Pmode
, "_TLS_MODULE_BASE_");
1887 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol
)
1888 |= TLS_MODEL_GLOBAL_DYNAMIC
<< SYMBOL_FLAG_TLS_SHIFT
;
1891 return xtensa_tls_module_base_symbol
;
1896 xtensa_call_tls_desc (rtx sym
, rtx
*retp
)
1899 rtx_insn
*call_insn
, *insns
;
1902 fn
= gen_reg_rtx (Pmode
);
1903 arg
= gen_reg_rtx (Pmode
);
1904 a_io
= gen_rtx_REG (Pmode
, WINDOW_SIZE
+ 2);
1906 emit_insn (gen_tls_func (fn
, sym
));
1907 emit_insn (gen_tls_arg (arg
, sym
));
1908 emit_move_insn (a_io
, arg
);
1909 call_insn
= emit_call_insn (gen_tls_call (a_io
, fn
, sym
, const1_rtx
));
1910 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), a_io
);
1911 insns
= get_insns ();
1920 xtensa_legitimize_tls_address (rtx x
)
1922 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
1923 rtx dest
, tp
, ret
, modbase
, base
, addend
;
1926 dest
= gen_reg_rtx (Pmode
);
1929 case TLS_MODEL_GLOBAL_DYNAMIC
:
1930 insns
= xtensa_call_tls_desc (x
, &ret
);
1931 emit_libcall_block (insns
, dest
, ret
, x
);
1934 case TLS_MODEL_LOCAL_DYNAMIC
:
1935 base
= gen_reg_rtx (Pmode
);
1936 modbase
= xtensa_tls_module_base ();
1937 insns
= xtensa_call_tls_desc (modbase
, &ret
);
1938 emit_libcall_block (insns
, base
, ret
, modbase
);
1939 addend
= force_reg (SImode
, gen_sym_DTPOFF (x
));
1940 emit_insn (gen_addsi3 (dest
, base
, addend
));
1943 case TLS_MODEL_INITIAL_EXEC
:
1944 case TLS_MODEL_LOCAL_EXEC
:
1945 tp
= gen_reg_rtx (SImode
);
1946 emit_insn (gen_get_thread_pointersi (tp
));
1947 addend
= force_reg (SImode
, gen_sym_TPOFF (x
));
1948 emit_insn (gen_addsi3 (dest
, tp
, addend
));
1960 xtensa_legitimize_address (rtx x
,
1961 rtx oldx ATTRIBUTE_UNUSED
,
1964 if (xtensa_tls_symbol_p (x
))
1965 return xtensa_legitimize_tls_address (x
);
1967 if (GET_CODE (x
) == PLUS
)
1969 rtx plus0
= XEXP (x
, 0);
1970 rtx plus1
= XEXP (x
, 1);
1972 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1974 plus0
= XEXP (x
, 1);
1975 plus1
= XEXP (x
, 0);
1978 /* Try to split up the offset to use an ADDMI instruction. */
1979 if (GET_CODE (plus0
) == REG
1980 && GET_CODE (plus1
) == CONST_INT
1981 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1982 && !xtensa_simm8 (INTVAL (plus1
))
1983 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1984 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1986 rtx temp
= gen_reg_rtx (Pmode
);
1987 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1988 emit_insn (gen_rtx_SET (temp
, gen_rtx_PLUS (Pmode
, plus0
,
1990 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1997 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1999 Treat constant-pool references as "mode dependent" since they can
2000 only be accessed with SImode loads. This works around a bug in the
2001 combiner where a constant pool reference is temporarily converted
2002 to an HImode load, which is then assumed to zero-extend based on
2003 our definition of LOAD_EXTEND_OP. This is wrong because the high
2004 bits of a 16-bit value in the constant pool are now sign-extended
2008 xtensa_mode_dependent_address_p (const_rtx addr
,
2009 addr_space_t as ATTRIBUTE_UNUSED
)
2011 return constantpool_address_p (addr
);
2014 /* Return TRUE if X contains any TLS symbol references. */
2017 xtensa_tls_referenced_p (rtx x
)
2019 if (! TARGET_HAVE_TLS
)
2022 subrtx_iterator::array_type array
;
2023 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
2025 const_rtx x
= *iter
;
2026 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2029 /* Ignore TLS references that have already been legitimized. */
2030 if (GET_CODE (x
) == UNSPEC
)
2031 switch (XINT (x
, 1))
2035 case UNSPEC_TLS_FUNC
:
2036 case UNSPEC_TLS_ARG
:
2037 case UNSPEC_TLS_CALL
:
2038 iter
.skip_subrtxes ();
2048 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2051 xtensa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2053 return xtensa_tls_referenced_p (x
);
2057 /* Return the debugger register number to use for 'regno'. */
2060 xtensa_dbx_register_number (int regno
)
2064 if (GP_REG_P (regno
))
2066 regno
-= GP_REG_FIRST
;
2069 else if (BR_REG_P (regno
))
2071 regno
-= BR_REG_FIRST
;
2074 else if (FP_REG_P (regno
))
2076 regno
-= FP_REG_FIRST
;
2079 else if (ACC_REG_P (regno
))
2081 first
= 0x200; /* Start of Xtensa special registers. */
2082 regno
= 16; /* ACCLO is special register 16. */
2085 /* When optimizing, we sometimes get asked about pseudo-registers
2086 that don't represent hard registers. Return 0 for these. */
2090 return first
+ regno
;
2094 /* Argument support functions. */
2096 /* Initialize CUMULATIVE_ARGS for a function. */
2099 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
2102 cum
->incoming
= incoming
;
2106 /* Advance the argument to the next argument position. */
2109 xtensa_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
2110 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2115 arg_words
= &get_cumulative_args (cum
)->arg_words
;
2116 max
= MAX_ARGS_IN_REGISTERS
;
2118 words
= (((mode
!= BLKmode
)
2119 ? (int) GET_MODE_SIZE (mode
)
2120 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2122 if (*arg_words
< max
2123 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
2124 || *arg_words
+ words
> max
))
2127 *arg_words
+= words
;
2131 /* Return an RTL expression containing the register for the given mode,
2132 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2133 if this is an incoming argument to the current function. */
2136 xtensa_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
2137 const_tree type
, bool incoming_p
)
2139 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2140 int regbase
, words
, max
;
2144 arg_words
= &cum
->arg_words
;
2145 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
2146 max
= MAX_ARGS_IN_REGISTERS
;
2148 words
= (((mode
!= BLKmode
)
2149 ? (int) GET_MODE_SIZE (mode
)
2150 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2152 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
2154 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
2155 *arg_words
= (*arg_words
+ align
- 1) & -align
;
2158 if (*arg_words
+ words
> max
)
2161 regno
= regbase
+ *arg_words
;
2163 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
2164 cfun
->machine
->need_a7_copy
= TARGET_WINDOWED_ABI
;
2166 return gen_rtx_REG (mode
, regno
);
2169 /* Implement TARGET_FUNCTION_ARG. */
2172 xtensa_function_arg (cumulative_args_t cum
, machine_mode mode
,
2173 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2175 return xtensa_function_arg_1 (cum
, mode
, type
, false);
2178 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2181 xtensa_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
2182 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2184 return xtensa_function_arg_1 (cum
, mode
, type
, true);
2188 xtensa_function_arg_boundary (machine_mode mode
, const_tree type
)
2190 unsigned int alignment
;
2192 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2193 if (alignment
< PARM_BOUNDARY
)
2194 alignment
= PARM_BOUNDARY
;
2195 if (alignment
> STACK_BOUNDARY
)
2196 alignment
= STACK_BOUNDARY
;
2202 xtensa_return_in_msb (const_tree valtype
)
2204 return (TARGET_BIG_ENDIAN
2205 && AGGREGATE_TYPE_P (valtype
)
2206 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
2211 xtensa_option_override (void)
2216 /* Use CONST16 in the absence of L32R.
2217 Set it in the TARGET_OPTION_OVERRIDE to avoid dependency on xtensa
2218 configuration in the xtensa-common.c */
2221 target_flags
|= MASK_CONST16
;
2223 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
2224 error ("boolean registers required for the floating-point option");
2226 /* Set up array giving whether a given register can hold a given mode. */
2227 for (mode
= VOIDmode
;
2228 mode
!= MAX_MACHINE_MODE
;
2229 mode
= (machine_mode
) ((int) mode
+ 1))
2231 int size
= GET_MODE_SIZE (mode
);
2232 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2234 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2238 if (ACC_REG_P (regno
))
2239 temp
= (TARGET_MAC16
2240 && (mclass
== MODE_INT
) && (size
<= UNITS_PER_WORD
));
2241 else if (GP_REG_P (regno
))
2242 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
2243 else if (FP_REG_P (regno
))
2244 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
2245 else if (BR_REG_P (regno
))
2246 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
2250 xtensa_hard_regno_mode_ok_p
[(int) mode
][regno
] = temp
;
2254 init_machine_status
= xtensa_init_machine_status
;
2256 /* Check PIC settings. PIC is only supported when using L32R
2257 instructions, and some targets need to always use PIC. */
2258 if (flag_pic
&& TARGET_CONST16
)
2259 error ("%<-f%s%> is not supported with CONST16 instructions",
2260 (flag_pic
> 1 ? "PIC" : "pic"));
2261 else if (TARGET_FORCE_NO_PIC
)
2263 else if (XTENSA_ALWAYS_PIC
)
2266 error ("PIC is required but not supported with CONST16 instructions");
2269 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2272 if (flag_pic
&& !flag_pie
)
2275 /* Hot/cold partitioning does not work on this architecture, because of
2276 constant pools (the load instruction cannot necessarily reach that far).
2277 Therefore disable it on this architecture. */
2278 if (flag_reorder_blocks_and_partition
)
2280 flag_reorder_blocks_and_partition
= 0;
2281 flag_reorder_blocks
= 1;
2285 /* Implement TARGET_HARD_REGNO_NREGS. */
2288 xtensa_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
2290 if (FP_REG_P (regno
))
2291 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_FPREG
);
2292 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
2295 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2298 xtensa_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2300 return xtensa_hard_regno_mode_ok_p
[mode
][regno
];
2303 /* Implement TARGET_MODES_TIEABLE_P. */
2306 xtensa_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2308 return ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
2309 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
2310 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
2311 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
));
2314 /* A C compound statement to output to stdio stream STREAM the
2315 assembler syntax for an instruction operand X. X is an RTL
2318 CODE is a value that can be used to specify one of several ways
2319 of printing the operand. It is used when identical operands
2320 must be printed differently depending on the context. CODE
2321 comes from the '%' specification that was used to request
2322 printing of the operand. If the specification was just '%DIGIT'
2323 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2324 is the ASCII code for LTR.
2326 If X is a register, this macro should print the register's name.
2327 The names can be found in an array 'reg_names' whose type is
2328 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2330 When the machine description has a specification '%PUNCT' (a '%'
2331 followed by a punctuation character), this macro is called with
2332 a null pointer for X and the punctuation character for CODE.
2334 'a', 'c', 'l', and 'n' are reserved.
2336 The Xtensa specific codes are:
2338 'd' CONST_INT, print as signed decimal
2339 'x' CONST_INT, print as signed hexadecimal
2340 'K' CONST_INT, print number of bits in mask for EXTUI
2341 'R' CONST_INT, print (X & 0x1f)
2342 'L' CONST_INT, print ((32 - X) & 0x1f)
2343 'D' REG, print second register of double-word register operand
2344 'N' MEM, print address of next word following a memory operand
2345 'v' MEM, if memory reference is volatile, output a MEMW before it
2346 't' any constant, add "@h" suffix for top 16 bits
2347 'b' any constant, add "@l" suffix for bottom 16 bits
2351 printx (FILE *file
, signed int val
)
2353 /* Print a hexadecimal value in a nice way. */
2354 if ((val
> -0xa) && (val
< 0xa))
2355 fprintf (file
, "%d", val
);
2357 fprintf (file
, "-0x%x", -val
);
2359 fprintf (file
, "0x%x", val
);
2364 print_operand (FILE *file
, rtx x
, int letter
)
2367 error ("PRINT_OPERAND null pointer");
2372 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2373 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2375 output_operand_lossage ("invalid %%D value");
2379 if (GET_CODE (x
) == MEM
)
2381 /* For a volatile memory reference, emit a MEMW before the
2383 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2384 fprintf (file
, "memw\n\t");
2387 output_operand_lossage ("invalid %%v value");
2391 if (GET_CODE (x
) == MEM
2392 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2394 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? E_SFmode
: E_SImode
,
2396 output_address (GET_MODE (x
), XEXP (x
, 0));
2399 output_operand_lossage ("invalid %%N value");
2403 if (GET_CODE (x
) == CONST_INT
)
2406 unsigned val
= INTVAL (x
);
2412 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2413 fatal_insn ("invalid mask", x
);
2415 fprintf (file
, "%d", num_bits
);
2418 output_operand_lossage ("invalid %%K value");
2422 if (GET_CODE (x
) == CONST_INT
)
2423 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 0x1f);
2425 output_operand_lossage ("invalid %%L value");
2429 if (GET_CODE (x
) == CONST_INT
)
2430 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x1f);
2432 output_operand_lossage ("invalid %%R value");
2436 if (GET_CODE (x
) == CONST_INT
)
2437 printx (file
, INTVAL (x
));
2439 output_operand_lossage ("invalid %%x value");
2443 if (GET_CODE (x
) == CONST_INT
)
2444 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
2446 output_operand_lossage ("invalid %%d value");
2451 if (GET_CODE (x
) == CONST_INT
)
2453 printx (file
, INTVAL (x
));
2454 fputs (letter
== 't' ? "@h" : "@l", file
);
2456 else if (GET_CODE (x
) == CONST_DOUBLE
)
2458 if (GET_MODE (x
) == SFmode
)
2461 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2462 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2465 output_operand_lossage ("invalid %%t/%%b value");
2467 else if (GET_CODE (x
) == CONST
)
2469 /* X must be a symbolic constant on ELF. Write an expression
2470 suitable for 'const16' that sets the high or low 16 bits. */
2471 if (GET_CODE (XEXP (x
, 0)) != PLUS
2472 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2473 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2474 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2475 output_operand_lossage ("invalid %%t/%%b value");
2476 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2477 fputs (letter
== 't' ? "@h" : "@l", file
);
2478 /* There must be a non-alphanumeric character between 'h' or 'l'
2479 and the number. The '-' is added by print_operand() already. */
2480 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2482 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2486 output_addr_const (file
, x
);
2487 fputs (letter
== 't' ? "@h" : "@l", file
);
2492 if (GET_CODE (x
) == CONST_DOUBLE
&&
2493 GET_MODE (x
) == SFmode
)
2496 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2497 fprintf (file
, "0x%08lx", l
);
2504 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2505 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2506 else if (GET_CODE (x
) == MEM
)
2507 output_address (GET_MODE (x
), XEXP (x
, 0));
2508 else if (GET_CODE (x
) == CONST_INT
)
2509 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
2511 output_addr_const (file
, x
);
2516 /* A C compound statement to output to stdio stream STREAM the
2517 assembler syntax for an instruction operand that is a memory
2518 reference whose address is ADDR. ADDR is an RTL expression. */
2521 print_operand_address (FILE *file
, rtx addr
)
2524 error ("PRINT_OPERAND_ADDRESS, null pointer");
2526 switch (GET_CODE (addr
))
2529 fatal_insn ("invalid address", addr
);
2533 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2539 rtx offset
= (rtx
)0;
2540 rtx arg0
= XEXP (addr
, 0);
2541 rtx arg1
= XEXP (addr
, 1);
2543 if (GET_CODE (arg0
) == REG
)
2548 else if (GET_CODE (arg1
) == REG
)
2554 fatal_insn ("no register in address", addr
);
2556 if (CONSTANT_P (offset
))
2558 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2559 output_addr_const (file
, offset
);
2562 fatal_insn ("address offset not a constant", addr
);
2570 output_addr_const (file
, addr
);
2575 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2578 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2580 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2582 switch (XINT (x
, 1))
2585 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2586 fputs ("@TPOFF", fp
);
2589 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2590 fputs ("@DTPOFF", fp
);
2595 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2608 xtensa_output_integer_literal_parts (FILE *file
, rtx x
, int size
)
2610 if (size
> 4 && !(size
& (size
- 1)))
2614 split_double (x
, &first
, &second
);
2615 xtensa_output_integer_literal_parts (file
, first
, size
/ 2);
2617 xtensa_output_integer_literal_parts (file
, second
, size
/ 2);
2621 output_addr_const (file
, x
);
2630 xtensa_output_literal (FILE *file
, rtx x
, machine_mode mode
, int labelno
)
2634 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2636 switch (GET_MODE_CLASS (mode
))
2639 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2644 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
),
2646 if (HOST_BITS_PER_LONG
> 32)
2647 value_long
[0] &= 0xffffffff;
2648 fprintf (file
, "0x%08lx\n", value_long
[0]);
2652 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
),
2654 if (HOST_BITS_PER_LONG
> 32)
2656 value_long
[0] &= 0xffffffff;
2657 value_long
[1] &= 0xffffffff;
2659 fprintf (file
, "0x%08lx, 0x%08lx\n",
2660 value_long
[0], value_long
[1]);
2670 case MODE_PARTIAL_INT
:
2671 xtensa_output_integer_literal_parts (file
, x
, GET_MODE_SIZE (mode
));
2681 xtensa_call_save_reg(int regno
)
2683 if (TARGET_WINDOWED_ABI
)
2686 if (regno
== A0_REG
)
2687 return crtl
->profile
|| !crtl
->is_leaf
|| crtl
->calls_eh_return
||
2688 df_regs_ever_live_p (regno
);
2690 if (crtl
->calls_eh_return
&& regno
>= 2 && regno
< 4)
2693 return !fixed_regs
[regno
] && !call_used_regs
[regno
] &&
2694 df_regs_ever_live_p (regno
);
2697 /* Return the bytes needed to compute the frame pointer from the current
2700 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2701 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2704 compute_frame_size (poly_int64 size
)
2708 if (reload_completed
&& cfun
->machine
->frame_laid_out
)
2709 return cfun
->machine
->current_frame_size
;
2711 /* Add space for the incoming static chain value. */
2712 if (cfun
->static_chain_decl
!= NULL
)
2713 size
+= (1 * UNITS_PER_WORD
);
2715 cfun
->machine
->callee_save_size
= 0;
2716 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2718 if (xtensa_call_save_reg(regno
))
2719 cfun
->machine
->callee_save_size
+= UNITS_PER_WORD
;
2722 cfun
->machine
->current_frame_size
=
2723 XTENSA_STACK_ALIGN (size
2724 + cfun
->machine
->callee_save_size
2725 + crtl
->outgoing_args_size
2726 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2727 cfun
->machine
->callee_save_size
=
2728 XTENSA_STACK_ALIGN (cfun
->machine
->callee_save_size
);
2729 cfun
->machine
->frame_laid_out
= true;
2730 return cfun
->machine
->current_frame_size
;
2735 xtensa_frame_pointer_required (void)
2737 /* The code to expand builtin_frame_addr and builtin_return_addr
2738 currently uses the hard_frame_pointer instead of frame_pointer.
2739 This seems wrong but maybe it's necessary for other architectures.
2740 This function is derived from the i386 code. */
2742 if (cfun
->machine
->accesses_prev_frame
)
2749 xtensa_initial_elimination_offset (int from
, int to ATTRIBUTE_UNUSED
)
2751 long frame_size
= compute_frame_size (get_frame_size ());
2752 HOST_WIDE_INT offset
;
2756 case FRAME_POINTER_REGNUM
:
2757 if (FRAME_GROWS_DOWNWARD
)
2758 offset
= frame_size
- (WINDOW_SIZE
* UNITS_PER_WORD
)
2759 - cfun
->machine
->callee_save_size
;
2763 case ARG_POINTER_REGNUM
:
2764 offset
= frame_size
;
2773 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2774 and the total number of words must be a multiple of 128 bits. */
2775 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2778 xtensa_expand_prologue (void)
2780 HOST_WIDE_INT total_size
;
2781 rtx_insn
*insn
= NULL
;
2785 total_size
= compute_frame_size (get_frame_size ());
2787 if (flag_stack_usage_info
)
2788 current_function_static_stack_size
= total_size
;
2790 if (TARGET_WINDOWED_ABI
)
2792 if (total_size
< (1 << (12+3)))
2793 insn
= emit_insn (gen_entry (GEN_INT (total_size
)));
2796 /* Use a8 as a temporary since a0-a7 may be live. */
2797 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2798 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2799 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2800 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2801 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2807 HOST_WIDE_INT offset
= 0;
2808 int callee_save_size
= cfun
->machine
->callee_save_size
;
2810 /* -128 is a limit of single addi instruction. */
2811 if (total_size
> 0 && total_size
<= 128)
2813 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2814 GEN_INT (-total_size
)));
2815 RTX_FRAME_RELATED_P (insn
) = 1;
2816 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2817 plus_constant (Pmode
, stack_pointer_rtx
,
2819 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2820 offset
= total_size
- UNITS_PER_WORD
;
2822 else if (callee_save_size
)
2824 /* 1020 is maximal s32i offset, if the frame is bigger than that
2825 * we move sp to the end of callee-saved save area, save and then
2826 * move it to its final location. */
2827 if (total_size
> 1024)
2829 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2830 GEN_INT (-callee_save_size
)));
2831 RTX_FRAME_RELATED_P (insn
) = 1;
2832 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2833 plus_constant (Pmode
, stack_pointer_rtx
,
2834 -callee_save_size
));
2835 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2836 offset
= callee_save_size
- UNITS_PER_WORD
;
2840 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2841 emit_move_insn (tmp_reg
, GEN_INT (total_size
));
2842 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
,
2843 stack_pointer_rtx
, tmp_reg
));
2844 RTX_FRAME_RELATED_P (insn
) = 1;
2845 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2846 plus_constant (Pmode
, stack_pointer_rtx
,
2848 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2849 offset
= total_size
- UNITS_PER_WORD
;
2853 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2855 if (xtensa_call_save_reg(regno
))
2857 rtx x
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
2858 rtx mem
= gen_frame_mem (SImode
, x
);
2859 rtx reg
= gen_rtx_REG (SImode
, regno
);
2861 offset
-= UNITS_PER_WORD
;
2862 insn
= emit_move_insn (mem
, reg
);
2863 RTX_FRAME_RELATED_P (insn
) = 1;
2864 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
2865 gen_rtx_SET (mem
, reg
));
2868 if (total_size
> 1024
2869 || (!callee_save_size
&& total_size
> 128))
2871 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2872 emit_move_insn (tmp_reg
, GEN_INT (total_size
-
2874 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
,
2875 stack_pointer_rtx
, tmp_reg
));
2876 RTX_FRAME_RELATED_P (insn
) = 1;
2877 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2878 plus_constant (Pmode
, stack_pointer_rtx
,
2881 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2885 if (frame_pointer_needed
)
2887 if (cfun
->machine
->set_frame_ptr_insn
)
2891 push_topmost_sequence ();
2892 first
= get_insns ();
2893 pop_topmost_sequence ();
2895 /* For all instructions prior to set_frame_ptr_insn, replace
2896 hard_frame_pointer references with stack_pointer. */
2898 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2899 insn
= NEXT_INSN (insn
))
2903 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2904 hard_frame_pointer_rtx
,
2906 df_insn_rescan (insn
);
2912 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2913 stack_pointer_rtx
));
2914 if (!TARGET_WINDOWED_ABI
)
2916 note_rtx
= gen_rtx_SET (hard_frame_pointer_rtx
,
2918 RTX_FRAME_RELATED_P (insn
) = 1;
2919 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2924 if (TARGET_WINDOWED_ABI
)
2926 /* Create a note to describe the CFA. Because this is only used to set
2927 DW_AT_frame_base for debug info, don't bother tracking changes through
2928 each instruction in the prologue. It just takes up space. */
2929 note_rtx
= gen_rtx_SET ((frame_pointer_needed
2930 ? hard_frame_pointer_rtx
2931 : stack_pointer_rtx
),
2932 plus_constant (Pmode
, stack_pointer_rtx
,
2934 RTX_FRAME_RELATED_P (insn
) = 1;
2935 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2940 xtensa_expand_epilogue (void)
2942 if (!TARGET_WINDOWED_ABI
)
2945 HOST_WIDE_INT offset
;
2947 if (cfun
->machine
->current_frame_size
> (frame_pointer_needed
? 127 : 1024))
2949 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2950 emit_move_insn (tmp_reg
, GEN_INT (cfun
->machine
->current_frame_size
-
2951 cfun
->machine
->callee_save_size
));
2952 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_needed
?
2953 hard_frame_pointer_rtx
: stack_pointer_rtx
,
2955 offset
= cfun
->machine
->callee_save_size
- UNITS_PER_WORD
;
2959 if (frame_pointer_needed
)
2960 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
2961 offset
= cfun
->machine
->current_frame_size
- UNITS_PER_WORD
;
2964 /* Prevent reordering of saved a0 update and loading it back from
2966 if (crtl
->calls_eh_return
)
2967 emit_insn (gen_blockage ());
2969 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2971 if (xtensa_call_save_reg(regno
))
2973 rtx x
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
2975 offset
-= UNITS_PER_WORD
;
2976 emit_move_insn (gen_rtx_REG (SImode
, regno
),
2977 gen_frame_mem (SImode
, x
));
2981 if (cfun
->machine
->current_frame_size
> 0)
2983 if (frame_pointer_needed
|| /* always reachable with addi */
2984 cfun
->machine
->current_frame_size
> 1024 ||
2985 cfun
->machine
->current_frame_size
<= 127)
2987 if (cfun
->machine
->current_frame_size
<= 127)
2988 offset
= cfun
->machine
->current_frame_size
;
2990 offset
= cfun
->machine
->callee_save_size
;
2992 emit_insn (gen_addsi3 (stack_pointer_rtx
,
2998 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2999 emit_move_insn (tmp_reg
,
3000 GEN_INT (cfun
->machine
->current_frame_size
));
3001 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
3006 if (crtl
->calls_eh_return
)
3007 emit_insn (gen_add3_insn (stack_pointer_rtx
,
3009 EH_RETURN_STACKADJ_RTX
));
3011 cfun
->machine
->epilogue_done
= true;
3012 emit_jump_insn (gen_return ());
3016 xtensa_use_return_instruction_p (void)
3018 if (!reload_completed
)
3020 if (TARGET_WINDOWED_ABI
)
3022 if (compute_frame_size (get_frame_size ()) == 0)
3024 return cfun
->machine
->epilogue_done
;
3028 xtensa_set_return_address (rtx address
, rtx scratch
)
3030 HOST_WIDE_INT total_size
= compute_frame_size (get_frame_size ());
3031 rtx frame
= frame_pointer_needed
?
3032 hard_frame_pointer_rtx
: stack_pointer_rtx
;
3033 rtx a0_addr
= plus_constant (Pmode
, frame
,
3034 total_size
- UNITS_PER_WORD
);
3035 rtx note
= gen_rtx_SET (gen_frame_mem (SImode
, a0_addr
),
3036 gen_rtx_REG (SImode
, A0_REG
));
3039 if (total_size
> 1024) {
3040 emit_move_insn (scratch
, GEN_INT (total_size
- UNITS_PER_WORD
));
3041 emit_insn (gen_addsi3 (scratch
, frame
, scratch
));
3045 insn
= emit_move_insn (gen_frame_mem (SImode
, a0_addr
), address
);
3046 RTX_FRAME_RELATED_P (insn
) = 1;
3047 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
3051 xtensa_return_addr (int count
, rtx frame
)
3053 rtx result
, retaddr
, curaddr
, label
;
3055 if (!TARGET_WINDOWED_ABI
)
3060 return get_hard_reg_initial_val (Pmode
, A0_REG
);
3064 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
3067 rtx addr
= plus_constant (Pmode
, frame
, -4 * UNITS_PER_WORD
);
3068 addr
= memory_address (Pmode
, addr
);
3069 retaddr
= gen_reg_rtx (Pmode
);
3070 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
3073 /* The 2 most-significant bits of the return address on Xtensa hold
3074 the register window size. To get the real return address, these
3075 bits must be replaced with the high bits from some address in the
3078 /* Get the 2 high bits of a local label in the code. */
3079 curaddr
= gen_reg_rtx (Pmode
);
3080 label
= gen_label_rtx ();
3082 LABEL_PRESERVE_P (label
) = 1;
3083 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
3084 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
3085 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
3087 /* Clear the 2 high bits of the return address. */
3088 result
= gen_reg_rtx (Pmode
);
3089 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
3090 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
3092 /* Combine them to get the result. */
3093 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
3097 /* Disable the use of word-sized or smaller complex modes for structures,
3098 and for function arguments in particular, where they cause problems with
3099 register a7. The xtensa_copy_incoming_a7 function assumes that there is
3100 a single reference to an argument in a7, but with small complex modes the
3101 real and imaginary components may be extracted separately, leading to two
3102 uses of the register, only one of which would be replaced. */
3105 xtensa_member_type_forces_blk (const_tree
, machine_mode mode
)
3107 return mode
== CQImode
|| mode
== CHImode
;
3110 /* Create the va_list data type.
3112 This structure is set up by __builtin_saveregs. The __va_reg field
3113 points to a stack-allocated region holding the contents of the
3114 incoming argument registers. The __va_ndx field is an index
3115 initialized to the position of the first unnamed (variable)
3116 argument. This same index is also used to address the arguments
3117 passed in memory. Thus, the __va_stk field is initialized to point
3118 to the position of the first argument in memory offset to account
3119 for the arguments passed in registers and to account for the size
3120 of the argument registers not being 16-byte aligned. E.G., there
3121 are 6 argument registers of 4 bytes each, but we want the __va_ndx
3122 for the first stack argument to have the maximal alignment of 16
3123 bytes, so we offset the __va_stk address by 32 bytes so that
3124 __va_stk[32] references the first argument on the stack. */
3127 xtensa_build_builtin_va_list (void)
3129 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
3131 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
3132 type_decl
= build_decl (BUILTINS_LOCATION
,
3133 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
3135 f_stk
= build_decl (BUILTINS_LOCATION
,
3136 FIELD_DECL
, get_identifier ("__va_stk"),
3138 f_reg
= build_decl (BUILTINS_LOCATION
,
3139 FIELD_DECL
, get_identifier ("__va_reg"),
3141 f_ndx
= build_decl (BUILTINS_LOCATION
,
3142 FIELD_DECL
, get_identifier ("__va_ndx"),
3145 DECL_FIELD_CONTEXT (f_stk
) = record
;
3146 DECL_FIELD_CONTEXT (f_reg
) = record
;
3147 DECL_FIELD_CONTEXT (f_ndx
) = record
;
3149 TYPE_STUB_DECL (record
) = type_decl
;
3150 TYPE_NAME (record
) = type_decl
;
3151 TYPE_FIELDS (record
) = f_stk
;
3152 DECL_CHAIN (f_stk
) = f_reg
;
3153 DECL_CHAIN (f_reg
) = f_ndx
;
3155 layout_type (record
);
3160 /* Save the incoming argument registers on the stack. Returns the
3161 address of the saved registers. */
3164 xtensa_builtin_saveregs (void)
3167 int arg_words
= crtl
->args
.info
.arg_words
;
3168 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
3173 /* Allocate the general-purpose register space. */
3174 gp_regs
= assign_stack_local
3175 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
3176 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
3178 /* Now store the incoming registers. */
3179 cfun
->machine
->need_a7_copy
= TARGET_WINDOWED_ABI
;
3180 cfun
->machine
->vararg_a7
= true;
3181 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
3182 adjust_address (gp_regs
, BLKmode
,
3183 arg_words
* UNITS_PER_WORD
),
3185 if (cfun
->machine
->vararg_a7_copy
!= 0)
3186 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
3188 return XEXP (gp_regs
, 0);
3192 /* Implement `va_start' for varargs and stdarg. We look at the
3193 current function to fill in an initial va_list. */
3196 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
3204 arg_words
= crtl
->args
.info
.arg_words
;
3206 f_stk
= TYPE_FIELDS (va_list_type_node
);
3207 f_reg
= DECL_CHAIN (f_stk
);
3208 f_ndx
= DECL_CHAIN (f_reg
);
3210 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
3211 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
3213 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
3216 /* Call __builtin_saveregs; save the result in __va_reg */
3217 u
= make_tree (sizetype
, expand_builtin_saveregs ());
3218 u
= fold_convert (ptr_type_node
, u
);
3219 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
3220 TREE_SIDE_EFFECTS (t
) = 1;
3221 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3223 /* Set the __va_stk member to ($arg_ptr - 32). */
3224 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
3225 u
= fold_build_pointer_plus_hwi (u
, -32);
3226 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
3227 TREE_SIDE_EFFECTS (t
) = 1;
3228 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3230 /* Set the __va_ndx member. If the first variable argument is on
3231 the stack, adjust __va_ndx by 2 words to account for the extra
3232 alignment offset for __va_stk. */
3233 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
3235 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
3236 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
3237 TREE_SIDE_EFFECTS (t
) = 1;
3238 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3242 /* Implement `va_arg'. */
3245 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
3246 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
3251 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
3252 tree lab_false
, lab_over
, lab_false2
;
3255 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
3257 type
= build_pointer_type (type
);
3259 /* Handle complex values as separate real and imaginary parts. */
3260 if (TREE_CODE (type
) == COMPLEX_TYPE
)
3262 tree real_part
, imag_part
;
3264 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
3266 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
3268 imag_part
= xtensa_gimplify_va_arg_expr (unshare_expr (valist
),
3271 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
3273 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
3276 f_stk
= TYPE_FIELDS (va_list_type_node
);
3277 f_reg
= DECL_CHAIN (f_stk
);
3278 f_ndx
= DECL_CHAIN (f_reg
);
3280 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
,
3282 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
3284 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
3287 type_size
= size_in_bytes (type
);
3288 va_size
= round_up (type_size
, UNITS_PER_WORD
);
3289 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
3292 /* First align __va_ndx if necessary for this arg:
3294 orig_ndx = (AP).__va_ndx;
3295 if (__alignof__ (TYPE) > 4 )
3296 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
3297 & -__alignof__ (TYPE)); */
3299 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
3301 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
3303 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
3305 t
= build2 (PLUS_EXPR
, integer_type_node
, unshare_expr (orig_ndx
),
3306 build_int_cst (integer_type_node
, align
- 1));
3307 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
3308 build_int_cst (integer_type_node
, -align
));
3309 gimplify_assign (unshare_expr (orig_ndx
), t
, pre_p
);
3313 /* Increment __va_ndx to point past the argument:
3315 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
3317 t
= fold_convert (integer_type_node
, va_size
);
3318 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
3319 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
3322 /* Check if the argument is in registers:
3324 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
3325 && !must_pass_in_stack (type))
3326 __array = (AP).__va_reg; */
3328 array
= create_tmp_var (ptr_type_node
);
3331 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
3333 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
3334 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
3336 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (ndx
),
3337 build_int_cst (integer_type_node
,
3338 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3339 t
= build3 (COND_EXPR
, void_type_node
, t
,
3340 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
3342 gimplify_and_add (t
, pre_p
);
3344 gimplify_assign (unshare_expr (array
), reg
, pre_p
);
3346 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
3347 gimplify_and_add (t
, pre_p
);
3349 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
3350 gimplify_and_add (t
, pre_p
);
3354 /* ...otherwise, the argument is on the stack (never split between
3355 registers and the stack -- change __va_ndx if necessary):
3359 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
3360 (AP).__va_ndx = 32 + __va_size (TYPE);
3361 __array = (AP).__va_stk;
3364 lab_false2
= create_artificial_label (UNKNOWN_LOCATION
);
3366 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (orig_ndx
),
3367 build_int_cst (integer_type_node
,
3368 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3369 t
= build3 (COND_EXPR
, void_type_node
, t
,
3370 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
3372 gimplify_and_add (t
, pre_p
);
3374 t
= size_binop (PLUS_EXPR
, unshare_expr (va_size
), size_int (32));
3375 t
= fold_convert (integer_type_node
, t
);
3376 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
3378 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
3379 gimplify_and_add (t
, pre_p
);
3381 gimplify_assign (array
, stk
, pre_p
);
3385 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
3386 gimplify_and_add (t
, pre_p
);
3390 /* Given the base array pointer (__array) and index to the subsequent
3391 argument (__va_ndx), find the address:
3393 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3397 The results are endian-dependent because values smaller than one word
3398 are aligned differently. */
3401 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
3403 t
= fold_build2 (GE_EXPR
, boolean_type_node
, unshare_expr (type_size
),
3404 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
3405 t
= fold_build3 (COND_EXPR
, sizetype
, t
, unshare_expr (va_size
),
3406 unshare_expr (type_size
));
3410 size
= unshare_expr (va_size
);
3412 t
= fold_convert (sizetype
, unshare_expr (ndx
));
3413 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
3414 addr
= fold_build_pointer_plus (unshare_expr (array
), t
);
3416 addr
= fold_convert (build_pointer_type (type
), addr
);
3418 addr
= build_va_arg_indirect_ref (addr
);
3419 return build_va_arg_indirect_ref (addr
);
3427 XTENSA_BUILTIN_UMULSIDI3
,
3433 xtensa_init_builtins (void)
3437 ftype
= build_function_type_list (unsigned_intDI_type_node
,
3438 unsigned_intSI_type_node
,
3439 unsigned_intSI_type_node
, NULL_TREE
);
3441 decl
= add_builtin_function ("__builtin_umulsidi3", ftype
,
3442 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
3443 "__umulsidi3", NULL_TREE
);
3444 TREE_NOTHROW (decl
) = 1;
3445 TREE_READONLY (decl
) = 1;
3450 xtensa_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
, tree
*args
,
3451 bool ignore ATTRIBUTE_UNUSED
)
3453 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3458 case XTENSA_BUILTIN_UMULSIDI3
:
3461 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
3462 || TARGET_MUL32_HIGH
)
3463 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
3464 fold_convert (unsigned_intDI_type_node
, arg0
),
3465 fold_convert (unsigned_intDI_type_node
, arg1
));
3469 internal_error ("bad builtin code");
3478 xtensa_expand_builtin (tree exp
, rtx target
,
3479 rtx subtarget ATTRIBUTE_UNUSED
,
3480 machine_mode mode ATTRIBUTE_UNUSED
,
3483 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
3484 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3488 case XTENSA_BUILTIN_UMULSIDI3
:
3489 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3490 __umulsidi3 function when the Xtensa configuration can directly
3491 implement it. If not, just call the function. */
3492 return expand_call (exp
, target
, ignore
);
3495 internal_error ("bad builtin code");
3500 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3503 xtensa_preferred_reload_class (rtx x
, reg_class_t rclass
)
3505 if (CONSTANT_P (x
) && CONST_DOUBLE_P (x
))
3508 /* Don't use the stack pointer or hard frame pointer for reloads!
3509 The hard frame pointer would normally be OK except that it may
3510 briefly hold an incoming argument in the prologue, and reload
3511 won't know that it is live because the hard frame pointer is
3512 treated specially. */
3514 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3520 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3523 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED
,
3526 /* Don't use the stack pointer or hard frame pointer for reloads!
3527 The hard frame pointer would normally be OK except that it may
3528 briefly hold an incoming argument in the prologue, and reload
3529 won't know that it is live because the hard frame pointer is
3530 treated specially. */
3532 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3538 /* Worker function for TARGET_SECONDARY_RELOAD. */
3541 xtensa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass
,
3542 machine_mode mode
, secondary_reload_info
*sri
)
3546 if (in_p
&& constantpool_mem_p (x
))
3548 if (rclass
== FP_REGS
)
3552 sri
->icode
= CODE_FOR_reloadqi_literal
;
3553 else if (mode
== HImode
)
3554 sri
->icode
= CODE_FOR_reloadhi_literal
;
3557 regno
= xt_true_regnum (x
);
3558 if (ACC_REG_P (regno
))
3559 return ((rclass
== GR_REGS
|| rclass
== RL_REGS
) ? NO_REGS
: RL_REGS
);
3560 if (rclass
== ACC_REG
)
3561 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
3568 order_regs_for_local_alloc (void)
3570 if (!leaf_function_p ())
3572 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
3574 static const int reg_nonleaf_alloc_order_call0
[FIRST_PSEUDO_REGISTER
] =
3576 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 12, 13, 14, 15,
3578 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
3583 memcpy (reg_alloc_order
, TARGET_WINDOWED_ABI
?
3584 reg_nonleaf_alloc_order
: reg_nonleaf_alloc_order_call0
,
3585 FIRST_PSEUDO_REGISTER
* sizeof (int));
3589 int i
, num_arg_regs
;
3592 /* Use the AR registers in increasing order (skipping a0 and a1)
3593 but save the incoming argument registers for a last resort. */
3594 num_arg_regs
= crtl
->args
.info
.arg_words
;
3595 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
3596 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
3597 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
3598 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
3599 for (i
= 0; i
< num_arg_regs
; i
++)
3600 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
3602 /* List the coprocessor registers in order. */
3603 for (i
= 0; i
< BR_REG_NUM
; i
++)
3604 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
3606 /* List the FP registers in order for now. */
3607 for (i
= 0; i
< 16; i
++)
3608 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
3610 /* GCC requires that we list *all* the registers.... */
3611 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
3612 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
3613 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
3614 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
3616 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
3621 /* Some Xtensa targets support multiple bss sections. If the section
3622 name ends with ".bss", add SECTION_BSS to the flags. */
3625 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
3627 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
3630 suffix
= strrchr (name
, '.');
3631 if (suffix
&& strcmp (suffix
, ".bss") == 0)
3633 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
3634 && DECL_INITIAL (decl
) == NULL_TREE
))
3635 flags
|= SECTION_BSS
; /* @nobits */
3637 warning (0, "only uninitialized variables can be placed in a "
3645 /* The literal pool stays with the function. */
3648 xtensa_select_rtx_section (machine_mode mode ATTRIBUTE_UNUSED
,
3649 rtx x ATTRIBUTE_UNUSED
,
3650 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
3652 return function_section (current_function_decl
);
3655 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3658 xtensa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3659 reg_class_t from
, reg_class_t to
)
3661 if (from
== to
&& from
!= BR_REGS
&& to
!= BR_REGS
)
3663 else if (reg_class_subset_p (from
, AR_REGS
)
3664 && reg_class_subset_p (to
, AR_REGS
))
3666 else if (reg_class_subset_p (from
, AR_REGS
) && to
== ACC_REG
)
3668 else if (from
== ACC_REG
&& reg_class_subset_p (to
, AR_REGS
))
3674 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3677 xtensa_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3678 reg_class_t rclass ATTRIBUTE_UNUSED
,
3679 bool in ATTRIBUTE_UNUSED
)
3684 /* Compute a (partial) cost for rtx X. Return true if the complete
3685 cost has been computed, and false if subexpressions should be
3686 scanned. In either case, *TOTAL contains the cost result. */
3689 xtensa_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3690 int opno ATTRIBUTE_UNUSED
,
3691 int *total
, bool speed ATTRIBUTE_UNUSED
)
3693 int code
= GET_CODE (x
);
3701 if (xtensa_simm12b (INTVAL (x
)))
3708 if (xtensa_simm8 (INTVAL (x
))
3709 || xtensa_simm8x256 (INTVAL (x
)))
3716 if (xtensa_mask_immediate (INTVAL (x
)))
3723 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
3734 /* No way to tell if X is the 2nd operand so be conservative. */
3737 if (xtensa_simm12b (INTVAL (x
)))
3739 else if (TARGET_CONST16
)
3740 *total
= COSTS_N_INSNS (2);
3749 *total
= COSTS_N_INSNS (2);
3756 *total
= COSTS_N_INSNS (4);
3764 (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
) ? 2 : 1;
3766 if (memory_address_p (mode
, XEXP ((x
), 0)))
3767 *total
= COSTS_N_INSNS (num_words
);
3769 *total
= COSTS_N_INSNS (2*num_words
);
3775 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3779 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3783 *total
= COSTS_N_INSNS (mode
== DImode
? 3 : 2);
3790 *total
= COSTS_N_INSNS (2);
3792 *total
= COSTS_N_INSNS (1);
3799 *total
= COSTS_N_INSNS (50);
3801 *total
= COSTS_N_INSNS (1);
3807 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3808 else if (mode
== DFmode
)
3809 *total
= COSTS_N_INSNS (50);
3811 *total
= COSTS_N_INSNS (4);
3819 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3820 else if (mode
== DFmode
|| mode
== DImode
)
3821 *total
= COSTS_N_INSNS (50);
3823 *total
= COSTS_N_INSNS (1);
3828 *total
= COSTS_N_INSNS (mode
== DImode
? 4 : 2);
3834 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3835 else if (mode
== DFmode
)
3836 *total
= COSTS_N_INSNS (50);
3837 else if (mode
== DImode
)
3838 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3839 else if (TARGET_MUL32
)
3840 *total
= COSTS_N_INSNS (4);
3841 else if (TARGET_MAC16
)
3842 *total
= COSTS_N_INSNS (16);
3843 else if (TARGET_MUL16
)
3844 *total
= COSTS_N_INSNS (12);
3846 *total
= COSTS_N_INSNS (50);
3855 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3858 else if (mode
== DFmode
)
3860 *total
= COSTS_N_INSNS (50);
3870 *total
= COSTS_N_INSNS (50);
3871 else if (TARGET_DIV32
)
3872 *total
= COSTS_N_INSNS (32);
3874 *total
= COSTS_N_INSNS (50);
3880 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3882 *total
= COSTS_N_INSNS (50);
3889 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3894 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3899 *total
= COSTS_N_INSNS (1);
3907 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3910 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3912 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3913 > 4 * UNITS_PER_WORD
);
3916 /* Worker function for TARGET_FUNCTION_VALUE. */
3919 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3922 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3923 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3924 ? SImode
: TYPE_MODE (valtype
),
3925 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3928 /* Worker function for TARGET_LIBCALL_VALUE. */
3931 xtensa_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
3933 return gen_rtx_REG ((GET_MODE_CLASS (mode
) == MODE_INT
3934 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3935 ? SImode
: mode
, GP_RETURN
);
3938 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3941 xtensa_function_value_regno_p (const unsigned int regno
)
3943 return (regno
== GP_RETURN
);
3946 /* The static chain is passed in memory. Provide rtx giving 'mem'
3947 expressions that denote where they are stored. */
3950 xtensa_static_chain (const_tree
ARG_UNUSED (fndecl_or_type
), bool incoming_p
)
3952 if (TARGET_WINDOWED_ABI
)
3954 rtx base
= incoming_p
? arg_pointer_rtx
: stack_pointer_rtx
;
3955 return gen_frame_mem (Pmode
, plus_constant (Pmode
, base
,
3956 -5 * UNITS_PER_WORD
));
3959 return gen_rtx_REG (Pmode
, A8_REG
);
3963 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3964 instruction with a minimal stack frame in order to get some free
3965 registers. Once the actual call target is known, the proper stack frame
3966 size is extracted from the ENTRY instruction at the target and the
3967 current frame is adjusted to match. The trampoline then transfers
3968 control to the instruction following the ENTRY at the target. Note:
3969 this assumes that the target begins with an ENTRY instruction. */
3972 xtensa_asm_trampoline_template (FILE *stream
)
3974 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3976 fprintf (stream
, "\t.begin no-transform\n");
3978 if (TARGET_WINDOWED_ABI
)
3980 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3984 /* Save the return address. */
3985 fprintf (stream
, "\tmov\ta10, a0\n");
3987 /* Use a CALL0 instruction to skip past the constants and in the
3988 process get the PC into A0. This allows PC-relative access to
3989 the constants without relying on L32R. */
3990 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3993 fprintf (stream
, "\tj\t.Lskipconsts\n");
3995 fprintf (stream
, "\t.align\t4\n");
3996 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3997 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3998 fprintf (stream
, ".Lskipconsts:\n");
4000 /* Load the static chain and function address from the trampoline. */
4003 fprintf (stream
, "\taddi\ta0, a0, 3\n");
4004 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
4005 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
4009 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
4010 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
4013 /* Store the static chain. */
4014 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
4016 /* Set the proper stack pointer value. */
4017 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
4018 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
4019 TARGET_BIG_ENDIAN
? 8 : 12);
4020 fprintf (stream
, "\tslli\ta9, a9, 3\n");
4021 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
4022 fprintf (stream
, "\tsub\ta9, sp, a9\n");
4023 fprintf (stream
, "\tmovsp\tsp, a9\n");
4026 /* Restore the return address. */
4027 fprintf (stream
, "\tmov\ta0, a10\n");
4029 /* Jump to the instruction following the ENTRY. */
4030 fprintf (stream
, "\taddi\ta8, a8, 3\n");
4031 fprintf (stream
, "\tjx\ta8\n");
4033 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
4035 fprintf (stream
, "\t.byte\t0\n");
4037 fprintf (stream
, "\tnop\n");
4043 /* Save the return address. */
4044 fprintf (stream
, "\tmov\ta10, a0\n");
4046 /* Use a CALL0 instruction to skip past the constants and in the
4047 process get the PC into A0. This allows PC-relative access to
4048 the constants without relying on L32R. */
4049 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
4052 fprintf (stream
, "\tj\t.Lskipconsts\n");
4054 fprintf (stream
, "\t.align\t4\n");
4055 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
4056 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
4057 fprintf (stream
, ".Lskipconsts:\n");
4059 /* Load the static chain and function address from the trampoline. */
4062 fprintf (stream
, "\taddi\ta0, a0, 3\n");
4063 fprintf (stream
, "\tl32i\ta8, a0, 0\n");
4064 fprintf (stream
, "\tl32i\ta9, a0, 4\n");
4065 fprintf (stream
, "\tmov\ta0, a10\n");
4069 fprintf (stream
, "\tl32r\ta8, .Lchainval\n");
4070 fprintf (stream
, "\tl32r\ta9, .Lfnaddr\n");
4072 fprintf (stream
, "\tjx\ta9\n");
4074 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
4076 fprintf (stream
, "\t.byte\t0\n");
4078 fprintf (stream
, "\tnop\n");
4080 fprintf (stream
, "\t.end no-transform\n");
4084 xtensa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain
)
4086 rtx func
= XEXP (DECL_RTL (fndecl
), 0);
4087 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
4091 if (TARGET_WINDOWED_ABI
)
4093 chain_off
= use_call0
? 12 : 8;
4094 func_off
= use_call0
? 16 : 12;
4098 chain_off
= use_call0
? 8 : 4;
4099 func_off
= use_call0
? 12 : 8;
4102 emit_block_move (m_tramp
, assemble_trampoline_template (),
4103 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4105 emit_move_insn (adjust_address (m_tramp
, SImode
, chain_off
), chain
);
4106 emit_move_insn (adjust_address (m_tramp
, SImode
, func_off
), func
);
4107 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
4108 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
4111 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
4114 xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4116 return !xtensa_tls_referenced_p (x
);
4119 /* Implement TARGET_CAN_USE_DOLOOP_P. */
4122 xtensa_can_use_doloop_p (const widest_int
&, const widest_int
&,
4123 unsigned int loop_depth
, bool entered_at_top
)
4125 /* Considering limitations in the hardware, only use doloop
4126 for innermost loops which must be entered from the top. */
4127 if (loop_depth
> 1 || !entered_at_top
)
4133 /* NULL if INSN insn is valid within a low-overhead loop.
4134 Otherwise return why doloop cannot be applied. */
4137 xtensa_invalid_within_doloop (const rtx_insn
*insn
)
4140 return "Function call in the loop.";
4142 if (JUMP_P (insn
) && INSN_CODE (insn
) == CODE_FOR_return
)
4143 return "Return from a call instruction in the loop.";
4148 /* Optimize LOOP. */
4151 hwloop_optimize (hwloop_info loop
)
4155 basic_block entry_bb
;
4157 rtx_insn
*insn
, *seq
, *entry_after
;
4159 if (loop
->depth
> 1)
4162 fprintf (dump_file
, ";; loop %d is not innermost\n",
4167 if (!loop
->incoming_dest
)
4170 fprintf (dump_file
, ";; loop %d has more than one entry\n",
4175 if (loop
->incoming_dest
!= loop
->head
)
4178 fprintf (dump_file
, ";; loop %d is not entered from head\n",
4183 if (loop
->has_call
|| loop
->has_asm
)
4186 fprintf (dump_file
, ";; loop %d has invalid insn\n",
4191 /* Scan all the blocks to make sure they don't use iter_reg. */
4192 if (loop
->iter_reg_used
|| loop
->iter_reg_used_outside
)
4195 fprintf (dump_file
, ";; loop %d uses iterator\n",
4200 /* Check if start_label appears before doloop_end. */
4201 insn
= loop
->start_label
;
4202 while (insn
&& insn
!= loop
->loop_end
)
4203 insn
= NEXT_INSN (insn
);
4208 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
4213 /* Get the loop iteration register. */
4214 iter_reg
= loop
->iter_reg
;
4216 gcc_assert (REG_P (iter_reg
));
4220 FOR_EACH_VEC_SAFE_ELT (loop
->incoming
, i
, entry_edge
)
4221 if (entry_edge
->flags
& EDGE_FALLTHRU
)
4224 if (entry_edge
== NULL
)
4227 /* Place the zero_cost_loop_start instruction before the loop. */
4228 entry_bb
= entry_edge
->src
;
4232 insn
= emit_insn (gen_zero_cost_loop_start (loop
->iter_reg
,
4238 if (!single_succ_p (entry_bb
) || vec_safe_length (loop
->incoming
) > 1)
4244 emit_insn_before (seq
, BB_HEAD (loop
->head
));
4245 seq
= emit_label_before (gen_label_rtx (), seq
);
4246 new_bb
= create_basic_block (seq
, insn
, entry_bb
);
4247 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4249 if (!(e
->flags
& EDGE_FALLTHRU
))
4250 redirect_edge_and_branch_force (e
, new_bb
);
4252 redirect_edge_succ (e
, new_bb
);
4255 make_edge (new_bb
, loop
->head
, 0);
4259 entry_after
= BB_END (entry_bb
);
4260 while (DEBUG_INSN_P (entry_after
)
4261 || (NOTE_P (entry_after
)
4262 && NOTE_KIND (entry_after
) != NOTE_INSN_BASIC_BLOCK
))
4263 entry_after
= PREV_INSN (entry_after
);
4265 emit_insn_after (seq
, entry_after
);
4273 /* A callback for the hw-doloop pass. Called when a loop we have discovered
4274 turns out not to be optimizable; we have to split the loop_end pattern into
4275 a subtract and a test. */
4278 hwloop_fail (hwloop_info loop
)
4281 rtx_insn
*insn
= loop
->loop_end
;
4283 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
4288 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
4289 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
4290 loop
->iter_reg
, const0_rtx
,
4294 JUMP_LABEL (insn
) = loop
->start_label
;
4295 LABEL_NUSES (loop
->start_label
)++;
4296 delete_insn (loop
->loop_end
);
4299 /* A callback for the hw-doloop pass. This function examines INSN; if
4300 it is a doloop_end pattern we recognize, return the reg rtx for the
4301 loop counter. Otherwise, return NULL_RTX. */
4304 hwloop_pattern_reg (rtx_insn
*insn
)
4308 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
4311 reg
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 1));
4319 static struct hw_doloop_hooks xtensa_doloop_hooks
=
4326 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4327 and tries to rewrite the RTL of these loops so that proper Xtensa
4328 hardware loops are generated. */
4331 xtensa_reorg_loops (void)
4334 reorg_loops (false, &xtensa_doloop_hooks
);
4337 /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. */
4342 /* We are freeing block_for_insn in the toplev to keep compatibility
4343 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4344 compute_bb_for_insn ();
4348 /* Doloop optimization. */
4349 xtensa_reorg_loops ();
4352 /* Update register usage after having seen the compiler flags. */
4355 xtensa_conditional_register_usage (void)
4359 c_mask
= TARGET_WINDOWED_ABI
? (1 << 1) : (1 << 2);
4361 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4363 /* Set/reset conditionally defined registers from
4364 CALL_USED_REGISTERS initializer. */
4365 if (call_used_regs
[i
] > 1)
4366 call_used_regs
[i
] = !!(call_used_regs
[i
] & c_mask
);
4369 /* Remove hard FP register from the preferred reload registers set. */
4370 CLEAR_HARD_REG_BIT (reg_class_contents
[(int)RL_REGS
],
4371 HARD_FRAME_POINTER_REGNUM
);
4374 /* Map hard register number to register class */
4376 enum reg_class
xtensa_regno_to_class (int regno
)
4378 static const enum reg_class regno_to_class
[FIRST_PSEUDO_REGISTER
] =
4380 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
4381 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4382 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4383 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4384 AR_REGS
, AR_REGS
, BR_REGS
,
4385 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4386 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4387 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4388 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4392 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4395 return regno_to_class
[regno
];
4398 /* Implement TARGET_CONSTANT_ALIGNMENT. Align string constants and
4399 constructors to at least a word boundary. The typical use of this
4400 macro is to increase alignment for string constants to be word
4401 aligned so that 'strcpy' calls that copy constants can be done
4404 static HOST_WIDE_INT
4405 xtensa_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4407 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4409 return MAX (align
, BITS_PER_WORD
);
4413 /* Implement TARGET_STARTING_FRAME_OFFSET. */
4415 static HOST_WIDE_INT
4416 xtensa_starting_frame_offset (void)
4418 if (FRAME_GROWS_DOWNWARD
)
4420 return crtl
->outgoing_args_size
;
4423 /* Implement TARGET_ASAN_SHADOW_OFFSET. */
4425 static unsigned HOST_WIDE_INT
4426 xtensa_asan_shadow_offset (void)
4428 return HOST_WIDE_INT_UC (0x10000000);
4431 #include "gt-xtensa.h"