1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright (C) 2001-2017 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "stringpool.h"
39 #include "diagnostic-core.h"
42 #include "fold-const.h"
43 #include "stor-layout.h"
50 #include "langhooks.h"
54 #include "hw-doloop.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Enumeration for all of the relational tests, so that we can build
61 arrays indexed by the test type, and not worry about the order
79 /* Array giving truth value on whether or not a given hard register
80 can support a given mode. */
81 static char xtensa_hard_regno_mode_ok_p
82 [(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
84 /* Largest block move to handle in-line. */
85 #define LARGEST_MOVE_RATIO 15
87 /* Define the structure for the machine field in struct function. */
88 struct GTY(()) machine_function
90 int accesses_prev_frame
;
94 rtx_insn
*set_frame_ptr_insn
;
95 /* Current frame size calculated by compute_frame_size. */
96 unsigned current_frame_size
;
97 /* Callee-save area size in the current frame calculated by
98 compute_frame_size. */
104 /* Vector, indexed by hard register number, which contains 1 for a
105 register that is allowable in a candidate for leaf function
108 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
110 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
116 static void xtensa_option_override (void);
117 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
118 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
119 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
120 static rtx
gen_conditional_move (enum rtx_code
, machine_mode
, rtx
, rtx
);
121 static rtx
fixup_subreg_mem (rtx
);
122 static struct machine_function
* xtensa_init_machine_status (void);
123 static rtx
xtensa_legitimize_tls_address (rtx
);
124 static rtx
xtensa_legitimize_address (rtx
, rtx
, machine_mode
);
125 static bool xtensa_mode_dependent_address_p (const_rtx
, addr_space_t
);
126 static bool xtensa_return_in_msb (const_tree
);
127 static void printx (FILE *, signed int);
128 static rtx
xtensa_builtin_saveregs (void);
129 static bool xtensa_legitimate_address_p (machine_mode
, rtx
, bool);
130 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
131 int) ATTRIBUTE_UNUSED
;
132 static section
*xtensa_select_rtx_section (machine_mode
, rtx
,
133 unsigned HOST_WIDE_INT
);
134 static bool xtensa_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
135 static int xtensa_register_move_cost (machine_mode
, reg_class_t
,
137 static int xtensa_memory_move_cost (machine_mode
, reg_class_t
, bool);
138 static tree
xtensa_build_builtin_va_list (void);
139 static bool xtensa_return_in_memory (const_tree
, const_tree
);
140 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
142 static void xtensa_function_arg_advance (cumulative_args_t
, machine_mode
,
144 static rtx
xtensa_function_arg (cumulative_args_t
, machine_mode
,
146 static rtx
xtensa_function_incoming_arg (cumulative_args_t
,
147 machine_mode
, const_tree
, bool);
148 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
149 static rtx
xtensa_libcall_value (machine_mode
, const_rtx
);
150 static bool xtensa_function_value_regno_p (const unsigned int);
151 static unsigned int xtensa_function_arg_boundary (machine_mode
,
153 static void xtensa_init_builtins (void);
154 static tree
xtensa_fold_builtin (tree
, int, tree
*, bool);
155 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
156 static void xtensa_va_start (tree
, rtx
);
157 static bool xtensa_frame_pointer_required (void);
158 static rtx
xtensa_static_chain (const_tree
, bool);
159 static void xtensa_asm_trampoline_template (FILE *);
160 static void xtensa_trampoline_init (rtx
, tree
, rtx
);
161 static bool xtensa_output_addr_const_extra (FILE *, rtx
);
162 static bool xtensa_cannot_force_const_mem (machine_mode
, rtx
);
164 static reg_class_t
xtensa_preferred_reload_class (rtx
, reg_class_t
);
165 static reg_class_t
xtensa_preferred_output_reload_class (rtx
, reg_class_t
);
166 static reg_class_t
xtensa_secondary_reload (bool, rtx
, reg_class_t
,
168 struct secondary_reload_info
*);
170 static bool constantpool_address_p (const_rtx addr
);
171 static bool xtensa_legitimate_constant_p (machine_mode
, rtx
);
172 static void xtensa_reorg (void);
173 static bool xtensa_can_use_doloop_p (const widest_int
&, const widest_int
&,
175 static const char *xtensa_invalid_within_doloop (const rtx_insn
*);
177 static bool xtensa_member_type_forces_blk (const_tree
,
180 static void xtensa_conditional_register_usage (void);
181 static unsigned int xtensa_hard_regno_nregs (unsigned int, machine_mode
);
182 static bool xtensa_hard_regno_mode_ok (unsigned int, machine_mode
);
183 static bool xtensa_modes_tieable_p (machine_mode
, machine_mode
);
184 static HOST_WIDE_INT
xtensa_constant_alignment (const_tree
, HOST_WIDE_INT
);
185 static HOST_WIDE_INT
xtensa_starting_frame_offset (void);
189 /* These hooks specify assembly directives for creating certain kinds
190 of integer object. */
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
195 #undef TARGET_ASM_SELECT_RTX_SECTION
196 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
198 #undef TARGET_LEGITIMIZE_ADDRESS
199 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
200 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
201 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
203 #undef TARGET_REGISTER_MOVE_COST
204 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
205 #undef TARGET_MEMORY_MOVE_COST
206 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
207 #undef TARGET_RTX_COSTS
208 #define TARGET_RTX_COSTS xtensa_rtx_costs
209 #undef TARGET_ADDRESS_COST
210 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
212 #undef TARGET_MEMBER_TYPE_FORCES_BLK
213 #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk
215 #undef TARGET_BUILD_BUILTIN_VA_LIST
216 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
218 #undef TARGET_EXPAND_BUILTIN_VA_START
219 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
221 #undef TARGET_PROMOTE_FUNCTION_MODE
222 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
223 #undef TARGET_PROMOTE_PROTOTYPES
224 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
226 #undef TARGET_RETURN_IN_MEMORY
227 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
228 #undef TARGET_FUNCTION_VALUE
229 #define TARGET_FUNCTION_VALUE xtensa_function_value
230 #undef TARGET_LIBCALL_VALUE
231 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
232 #undef TARGET_FUNCTION_VALUE_REGNO_P
233 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
235 #undef TARGET_SPLIT_COMPLEX_ARG
236 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
237 #undef TARGET_MUST_PASS_IN_STACK
238 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
239 #undef TARGET_FUNCTION_ARG_ADVANCE
240 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
241 #undef TARGET_FUNCTION_ARG
242 #define TARGET_FUNCTION_ARG xtensa_function_arg
243 #undef TARGET_FUNCTION_INCOMING_ARG
244 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
245 #undef TARGET_FUNCTION_ARG_BOUNDARY
246 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
248 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
249 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
250 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
251 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
253 #undef TARGET_RETURN_IN_MSB
254 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
256 #undef TARGET_INIT_BUILTINS
257 #define TARGET_INIT_BUILTINS xtensa_init_builtins
258 #undef TARGET_FOLD_BUILTIN
259 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
260 #undef TARGET_EXPAND_BUILTIN
261 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
263 #undef TARGET_PREFERRED_RELOAD_CLASS
264 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
265 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
266 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
268 #undef TARGET_SECONDARY_RELOAD
269 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
271 #undef TARGET_HAVE_TLS
272 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
274 #undef TARGET_CANNOT_FORCE_CONST_MEM
275 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
278 #define TARGET_LRA_P hook_bool_void_false
280 #undef TARGET_LEGITIMATE_ADDRESS_P
281 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
283 #undef TARGET_FRAME_POINTER_REQUIRED
284 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
286 #undef TARGET_STATIC_CHAIN
287 #define TARGET_STATIC_CHAIN xtensa_static_chain
288 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
289 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
290 #undef TARGET_TRAMPOLINE_INIT
291 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
293 #undef TARGET_OPTION_OVERRIDE
294 #define TARGET_OPTION_OVERRIDE xtensa_option_override
296 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
297 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
299 #undef TARGET_LEGITIMATE_CONSTANT_P
300 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p
302 #undef TARGET_MACHINE_DEPENDENT_REORG
303 #define TARGET_MACHINE_DEPENDENT_REORG xtensa_reorg
305 #undef TARGET_CAN_USE_DOLOOP_P
306 #define TARGET_CAN_USE_DOLOOP_P xtensa_can_use_doloop_p
308 #undef TARGET_INVALID_WITHIN_DOLOOP
309 #define TARGET_INVALID_WITHIN_DOLOOP xtensa_invalid_within_doloop
311 #undef TARGET_CONDITIONAL_REGISTER_USAGE
312 #define TARGET_CONDITIONAL_REGISTER_USAGE xtensa_conditional_register_usage
314 #undef TARGET_HARD_REGNO_NREGS
315 #define TARGET_HARD_REGNO_NREGS xtensa_hard_regno_nregs
316 #undef TARGET_HARD_REGNO_MODE_OK
317 #define TARGET_HARD_REGNO_MODE_OK xtensa_hard_regno_mode_ok
319 #undef TARGET_MODES_TIEABLE_P
320 #define TARGET_MODES_TIEABLE_P xtensa_modes_tieable_p
322 #undef TARGET_CONSTANT_ALIGNMENT
323 #define TARGET_CONSTANT_ALIGNMENT xtensa_constant_alignment
325 #undef TARGET_STARTING_FRAME_OFFSET
326 #define TARGET_STARTING_FRAME_OFFSET xtensa_starting_frame_offset
328 struct gcc_target targetm
= TARGET_INITIALIZER
;
331 /* Functions to test Xtensa immediate operand validity. */
334 xtensa_simm8 (HOST_WIDE_INT v
)
336 return v
>= -128 && v
<= 127;
341 xtensa_simm8x256 (HOST_WIDE_INT v
)
343 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
348 xtensa_simm12b (HOST_WIDE_INT v
)
350 return v
>= -2048 && v
<= 2047;
355 xtensa_uimm8 (HOST_WIDE_INT v
)
357 return v
>= 0 && v
<= 255;
362 xtensa_uimm8x2 (HOST_WIDE_INT v
)
364 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
369 xtensa_uimm8x4 (HOST_WIDE_INT v
)
371 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
376 xtensa_b4const (HOST_WIDE_INT v
)
403 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
407 return xtensa_b4const (v
);
412 xtensa_b4constu (HOST_WIDE_INT v
)
439 xtensa_mask_immediate (HOST_WIDE_INT v
)
441 #define MAX_MASK_SIZE 16
444 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
457 /* This is just like the standard true_regnum() function except that it
458 works even when reg_renumber is not initialized. */
461 xt_true_regnum (rtx x
)
463 if (GET_CODE (x
) == REG
)
466 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
467 && reg_renumber
[REGNO (x
)] >= 0)
468 return reg_renumber
[REGNO (x
)];
471 if (GET_CODE (x
) == SUBREG
)
473 int base
= xt_true_regnum (SUBREG_REG (x
));
474 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
475 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
476 GET_MODE (SUBREG_REG (x
)),
477 SUBREG_BYTE (x
), GET_MODE (x
));
484 xtensa_valid_move (machine_mode mode
, rtx
*operands
)
486 /* Either the destination or source must be a register, and the
487 MAC16 accumulator doesn't count. */
489 if (register_operand (operands
[0], mode
))
491 int dst_regnum
= xt_true_regnum (operands
[0]);
493 if (xtensa_tls_referenced_p (operands
[1]))
496 /* The stack pointer can only be assigned with a MOVSP opcode. */
497 if (dst_regnum
== STACK_POINTER_REGNUM
)
498 return !TARGET_WINDOWED_ABI
500 && register_operand (operands
[1], mode
)
501 && !ACC_REG_P (xt_true_regnum (operands
[1])));
503 if (!ACC_REG_P (dst_regnum
))
506 if (register_operand (operands
[1], mode
))
508 int src_regnum
= xt_true_regnum (operands
[1]);
509 if (!ACC_REG_P (src_regnum
))
517 smalloffset_mem_p (rtx op
)
519 if (GET_CODE (op
) == MEM
)
521 rtx addr
= XEXP (op
, 0);
522 if (GET_CODE (addr
) == REG
)
523 return BASE_REG_P (addr
, 0);
524 if (GET_CODE (addr
) == PLUS
)
526 rtx offset
= XEXP (addr
, 0);
528 if (GET_CODE (offset
) != CONST_INT
)
529 offset
= XEXP (addr
, 1);
530 if (GET_CODE (offset
) != CONST_INT
)
533 val
= INTVAL (offset
);
534 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
542 constantpool_address_p (const_rtx addr
)
544 const_rtx sym
= addr
;
546 if (GET_CODE (addr
) == CONST
)
550 /* Only handle (PLUS (SYM, OFFSET)) form. */
551 addr
= XEXP (addr
, 0);
552 if (GET_CODE (addr
) != PLUS
)
555 /* Make sure the address is word aligned. */
556 offset
= XEXP (addr
, 1);
557 if ((!CONST_INT_P (offset
))
558 || ((INTVAL (offset
) & 3) != 0))
561 sym
= XEXP (addr
, 0);
564 if ((GET_CODE (sym
) == SYMBOL_REF
)
565 && CONSTANT_POOL_ADDRESS_P (sym
))
572 constantpool_mem_p (rtx op
)
574 if (GET_CODE (op
) == SUBREG
)
575 op
= SUBREG_REG (op
);
576 if (GET_CODE (op
) == MEM
)
577 return constantpool_address_p (XEXP (op
, 0));
582 /* Return TRUE if X is a thread-local symbol. */
585 xtensa_tls_symbol_p (rtx x
)
587 if (! TARGET_HAVE_TLS
)
590 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
595 xtensa_extend_reg (rtx dst
, rtx src
)
597 rtx temp
= gen_reg_rtx (SImode
);
598 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
600 /* Generate paradoxical subregs as needed so that the modes match. */
601 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
602 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
604 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
605 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
610 xtensa_mem_offset (unsigned v
, machine_mode mode
)
615 /* Handle the worst case for block moves. See xtensa_expand_block_move
616 where we emit an optimized block move operation if the block can be
617 moved in < "move_ratio" pieces. The worst case is when the block is
618 aligned but has a size of (3 mod 4) (does this happen?) so that the
619 last piece requires a byte load/store. */
620 return (xtensa_uimm8 (v
)
621 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
624 return xtensa_uimm8 (v
);
627 return xtensa_uimm8x2 (v
);
631 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
637 return xtensa_uimm8x4 (v
);
641 /* Make normal rtx_code into something we can index from an array. */
643 static enum internal_test
644 map_test_to_internal_test (enum rtx_code test_code
)
646 enum internal_test test
= ITEST_MAX
;
651 case EQ
: test
= ITEST_EQ
; break;
652 case NE
: test
= ITEST_NE
; break;
653 case GT
: test
= ITEST_GT
; break;
654 case GE
: test
= ITEST_GE
; break;
655 case LT
: test
= ITEST_LT
; break;
656 case LE
: test
= ITEST_LE
; break;
657 case GTU
: test
= ITEST_GTU
; break;
658 case GEU
: test
= ITEST_GEU
; break;
659 case LTU
: test
= ITEST_LTU
; break;
660 case LEU
: test
= ITEST_LEU
; break;
667 /* Generate the code to compare two integer values. The return value is
668 the comparison expression. */
671 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
672 rtx cmp0
, /* first operand to compare */
673 rtx cmp1
, /* second operand to compare */
674 int *p_invert
/* whether branch needs to reverse test */)
678 enum rtx_code test_code
; /* test code to use in insn */
679 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
680 int const_add
; /* constant to add (convert LE -> LT) */
681 int reverse_regs
; /* reverse registers in test */
682 int invert_const
; /* != 0 if invert value if cmp1 is constant */
683 int invert_reg
; /* != 0 if invert value if cmp1 is register */
684 int unsignedp
; /* != 0 for unsigned comparisons. */
687 static struct cmp_info info
[ (int)ITEST_MAX
] = {
689 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
690 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
692 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
693 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
694 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
695 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
697 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
698 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
699 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
700 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
703 enum internal_test test
;
705 struct cmp_info
*p_info
;
707 test
= map_test_to_internal_test (test_code
);
708 gcc_assert (test
!= ITEST_MAX
);
710 p_info
= &info
[ (int)test
];
712 mode
= GET_MODE (cmp0
);
713 if (mode
== VOIDmode
)
714 mode
= GET_MODE (cmp1
);
716 /* Make sure we can handle any constants given to us. */
717 if (GET_CODE (cmp1
) == CONST_INT
)
719 HOST_WIDE_INT value
= INTVAL (cmp1
);
720 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
722 /* if the immediate overflows or does not fit in the immediate field,
723 spill it to a register */
725 if ((p_info
->unsignedp
?
726 (uvalue
+ p_info
->const_add
> uvalue
) :
727 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
729 cmp1
= force_reg (mode
, cmp1
);
731 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
733 cmp1
= force_reg (mode
, cmp1
);
736 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
738 cmp1
= force_reg (mode
, cmp1
);
741 /* See if we need to invert the result. */
742 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
743 ? p_info
->invert_const
744 : p_info
->invert_reg
);
746 /* Comparison to constants, may involve adding 1 to change a LT into LE.
747 Comparison between two registers, may involve switching operands. */
748 if (GET_CODE (cmp1
) == CONST_INT
)
750 if (p_info
->const_add
!= 0)
751 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
754 else if (p_info
->reverse_regs
)
761 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
765 /* Generate the code to compare two float values. The return value is
766 the comparison expression. */
769 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
770 rtx cmp0
, /* first operand to compare */
771 rtx cmp1
/* second operand to compare */)
773 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
775 int reverse_regs
, invert
;
779 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
780 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
781 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
782 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
783 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
784 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
785 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
786 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
787 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
788 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
789 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
790 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
792 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
794 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
796 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
797 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
807 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
808 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
810 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
815 xtensa_expand_conditional_branch (rtx
*operands
, machine_mode mode
)
817 enum rtx_code test_code
= GET_CODE (operands
[0]);
818 rtx cmp0
= operands
[1];
819 rtx cmp1
= operands
[2];
828 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
832 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
836 if (!TARGET_HARD_FLOAT
)
837 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
840 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
844 /* Generate the branch. */
846 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
855 emit_jump_insn (gen_rtx_SET (pc_rtx
,
856 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
863 gen_conditional_move (enum rtx_code code
, machine_mode mode
,
870 /* Jump optimization calls get_condition() which canonicalizes
871 comparisons like (GE x <const>) to (GT x <const-1>).
872 Transform those comparisons back to GE, since that is the
873 comparison supported in Xtensa. We shouldn't have to
874 transform <LE x const> comparisons, because neither
875 xtensa_expand_conditional_branch() nor get_condition() will
878 if ((code
== GT
) && (op1
== constm1_rtx
))
883 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
885 if (boolean_operator (cmp
, VOIDmode
))
887 /* Swap the operands to make const0 second. */
888 if (op0
== const0_rtx
)
894 /* If not comparing against zero, emit a comparison (subtract). */
895 if (op1
!= const0_rtx
)
897 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
898 0, 0, OPTAB_LIB_WIDEN
);
902 else if (branch_operator (cmp
, VOIDmode
))
904 /* Swap the operands to make const0 second. */
905 if (op0
== const0_rtx
)
912 case LT
: code
= GE
; break;
913 case GE
: code
= LT
; break;
914 default: gcc_unreachable ();
918 if (op1
!= const0_rtx
)
924 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
927 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
928 return gen_float_relational (code
, op0
, op1
);
935 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
937 rtx dest
= operands
[0];
938 rtx cmp
= operands
[1];
939 machine_mode cmp_mode
= GET_MODE (XEXP (cmp
, 0));
940 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
942 if (!(cmp
= gen_conditional_move (GET_CODE (cmp
), cmp_mode
,
943 XEXP (cmp
, 0), XEXP (cmp
, 1))))
947 gen_fn
= (cmp_mode
== SImode
948 ? gen_movsfcc_internal0
949 : gen_movsfcc_internal1
);
951 gen_fn
= (cmp_mode
== SImode
952 ? gen_movsicc_internal0
953 : gen_movsicc_internal1
);
955 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), operands
[2], operands
[3], cmp
));
961 xtensa_expand_scc (rtx operands
[4], machine_mode cmp_mode
)
963 rtx dest
= operands
[0];
965 rtx one_tmp
, zero_tmp
;
966 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
968 if (!(cmp
= gen_conditional_move (GET_CODE (operands
[1]), cmp_mode
,
969 operands
[2], operands
[3])))
972 one_tmp
= gen_reg_rtx (SImode
);
973 zero_tmp
= gen_reg_rtx (SImode
);
974 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
975 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
977 gen_fn
= (cmp_mode
== SImode
978 ? gen_movsicc_internal0
979 : gen_movsicc_internal1
);
980 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
985 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
986 for the output, i.e., the input operands are twice as big as MODE. */
989 xtensa_split_operand_pair (rtx operands
[4], machine_mode mode
)
991 switch (GET_CODE (operands
[1]))
994 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
995 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
999 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
1000 operands
[2] = adjust_address (operands
[1], mode
, 0);
1005 split_double (operands
[1], &operands
[2], &operands
[3]);
1012 switch (GET_CODE (operands
[0]))
1015 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
1016 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
1020 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
1021 operands
[0] = adjust_address (operands
[0], mode
, 0);
1030 /* Emit insns to move operands[1] into operands[0].
1031 Return 1 if we have written out everything that needs to be done to
1032 do the move. Otherwise, return 0 and the caller will emit the move
1036 xtensa_emit_move_sequence (rtx
*operands
, machine_mode mode
)
1038 rtx src
= operands
[1];
1040 if (CONSTANT_P (src
)
1041 && (GET_CODE (src
) != CONST_INT
|| ! xtensa_simm12b (INTVAL (src
))))
1043 rtx dst
= operands
[0];
1045 if (xtensa_tls_referenced_p (src
))
1049 if (GET_CODE (src
) == CONST
&& GET_CODE (XEXP (src
, 0)) == PLUS
)
1051 addend
= XEXP (XEXP (src
, 0), 1);
1052 src
= XEXP (XEXP (src
, 0), 0);
1055 src
= xtensa_legitimize_tls_address (src
);
1058 src
= gen_rtx_PLUS (mode
, src
, addend
);
1059 src
= force_operand (src
, dst
);
1061 emit_move_insn (dst
, src
);
1065 if (! TARGET_AUTO_LITPOOLS
&& ! TARGET_CONST16
)
1067 src
= force_const_mem (SImode
, src
);
1071 /* PC-relative loads are always SImode, and CONST16 is only
1072 supported in the movsi pattern, so add a SUBREG for any other
1077 if (register_operand (dst
, mode
))
1079 emit_move_insn (simplify_gen_subreg (SImode
, dst
, mode
, 0), src
);
1084 src
= force_reg (SImode
, src
);
1085 src
= gen_lowpart_SUBREG (mode
, src
);
1091 if (!(reload_in_progress
| reload_completed
)
1092 && !xtensa_valid_move (mode
, operands
))
1093 operands
[1] = force_reg (mode
, operands
[1]);
1095 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
1097 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1098 instruction won't be recognized after reload, so we remove the
1099 subreg and adjust mem accordingly. */
1100 if (reload_in_progress
)
1102 operands
[0] = fixup_subreg_mem (operands
[0]);
1103 operands
[1] = fixup_subreg_mem (operands
[1]);
1110 fixup_subreg_mem (rtx x
)
1112 if (GET_CODE (x
) == SUBREG
1113 && GET_CODE (SUBREG_REG (x
)) == REG
1114 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
1117 gen_rtx_SUBREG (GET_MODE (x
),
1118 reg_equiv_mem (REGNO (SUBREG_REG (x
))),
1120 x
= alter_subreg (&temp
, true);
1126 /* Check if an incoming argument in a7 is expected to be used soon and
1127 if OPND is a register or register pair that includes a7. If so,
1128 create a new pseudo and copy a7 into that pseudo at the very
1129 beginning of the function, followed by the special "set_frame_ptr"
1130 unspec_volatile insn. The return value is either the original
1131 operand, if it is not a7, or the new pseudo containing a copy of
1132 the incoming argument. This is necessary because the register
1133 allocator will ignore conflicts with a7 and may either assign some
1134 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1135 the incoming argument in a7. By copying the argument out of a7 as
1136 the very first thing, and then immediately following that with an
1137 unspec_volatile to keep the scheduler away, we should avoid any
1138 problems. Putting the set_frame_ptr insn at the beginning, with
1139 only the a7 copy before it, also makes it easier for the prologue
1140 expander to initialize the frame pointer after the a7 copy and to
1141 fix up the a7 copy to use the stack pointer instead of the frame
1145 xtensa_copy_incoming_a7 (rtx opnd
)
1147 rtx entry_insns
= 0;
1151 if (!cfun
->machine
->need_a7_copy
)
1154 /* This function should never be called again once a7 has been copied. */
1155 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1157 mode
= GET_MODE (opnd
);
1159 /* The operand using a7 may come in a later instruction, so just return
1160 the original operand if it doesn't use a7. */
1162 if (GET_CODE (reg
) == SUBREG
)
1164 gcc_assert (SUBREG_BYTE (reg
) == 0);
1165 reg
= SUBREG_REG (reg
);
1167 if (GET_CODE (reg
) != REG
1168 || REGNO (reg
) > A7_REG
1169 || REGNO (reg
) + hard_regno_nregs (A7_REG
, mode
) <= A7_REG
)
1172 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1173 gcc_assert (REGNO (reg
) + hard_regno_nregs (A7_REG
, mode
) - 1 == A7_REG
);
1175 cfun
->machine
->need_a7_copy
= false;
1177 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1178 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1181 tmp
= gen_reg_rtx (mode
);
1187 /* Copy the value out of A7 here but keep the first word in A6 until
1188 after the set_frame_ptr insn. Otherwise, the register allocator
1189 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1191 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1192 gen_raw_REG (SImode
, A7_REG
)));
1195 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1198 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1201 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1204 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1210 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1212 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1213 if (mode
== DFmode
|| mode
== DImode
)
1214 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1215 gen_rtx_REG (SImode
, A7_REG
- 1)));
1216 entry_insns
= get_insns ();
1219 if (cfun
->machine
->vararg_a7
)
1221 /* This is called from within builtin_saveregs, which will insert the
1222 saveregs code at the function entry, ahead of anything placed at
1223 the function entry now. Instead, save the sequence to be inserted
1224 at the beginning of the saveregs code. */
1225 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1229 /* Put entry_insns after the NOTE that starts the function. If
1230 this is inside a start_sequence, make the outer-level insn
1231 chain current, so the code is placed at the start of the
1233 push_topmost_sequence ();
1234 /* Do not use entry_of_function() here. This is called from within
1235 expand_function_start, when the CFG still holds GIMPLE. */
1236 emit_insn_after (entry_insns
, get_insns ());
1237 pop_topmost_sequence ();
1244 /* Try to expand a block move operation to a sequence of RTL move
1245 instructions. If not optimizing, or if the block size is not a
1246 constant, or if the block is too large, the expansion fails and GCC
1247 falls back to calling memcpy().
1249 operands[0] is the destination
1250 operands[1] is the source
1251 operands[2] is the length
1252 operands[3] is the alignment */
1255 xtensa_expand_block_move (rtx
*operands
)
1257 static const machine_mode mode_from_align
[] =
1259 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1262 rtx dst_mem
= operands
[0];
1263 rtx src_mem
= operands
[1];
1264 HOST_WIDE_INT bytes
, align
;
1265 int num_pieces
, move_ratio
;
1267 machine_mode mode
[2];
1276 /* If this is not a fixed size move, just call memcpy. */
1277 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1280 bytes
= INTVAL (operands
[2]);
1281 align
= INTVAL (operands
[3]);
1283 /* Anything to move? */
1287 if (align
> MOVE_MAX
)
1290 /* Decide whether to expand inline based on the optimization level. */
1293 move_ratio
= LARGEST_MOVE_RATIO
;
1294 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1295 if (num_pieces
> move_ratio
)
1298 x
= XEXP (dst_mem
, 0);
1301 x
= force_reg (Pmode
, x
);
1302 dst_mem
= replace_equiv_address (dst_mem
, x
);
1305 x
= XEXP (src_mem
, 0);
1308 x
= force_reg (Pmode
, x
);
1309 src_mem
= replace_equiv_address (src_mem
, x
);
1312 active
[0] = active
[1] = false;
1323 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1324 next_amount
= MIN (next_amount
, align
);
1326 amount
[next
] = next_amount
;
1327 mode
[next
] = mode_from_align
[next_amount
];
1328 temp
[next
] = gen_reg_rtx (mode
[next
]);
1330 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1331 emit_insn (gen_rtx_SET (temp
[next
], x
));
1333 offset_ld
+= next_amount
;
1334 bytes
-= next_amount
;
1335 active
[next
] = true;
1340 active
[phase
] = false;
1342 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1343 emit_insn (gen_rtx_SET (x
, temp
[phase
]));
1345 offset_st
+= amount
[phase
];
1348 while (active
[next
]);
1355 xtensa_expand_nonlocal_goto (rtx
*operands
)
1357 rtx goto_handler
= operands
[1];
1358 rtx containing_fp
= operands
[3];
1360 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1361 is too big to generate in-line. */
1363 if (GET_CODE (containing_fp
) != REG
)
1364 containing_fp
= force_reg (Pmode
, containing_fp
);
1366 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1367 LCT_NORMAL
, VOIDmode
,
1368 containing_fp
, Pmode
,
1369 goto_handler
, Pmode
);
1373 static struct machine_function
*
1374 xtensa_init_machine_status (void)
1376 return ggc_cleared_alloc
<machine_function
> ();
1380 /* Shift VAL of mode MODE left by COUNT bits. */
1383 xtensa_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
1385 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1386 NULL_RTX
, 1, OPTAB_DIRECT
);
1387 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1388 NULL_RTX
, 1, OPTAB_DIRECT
);
1392 /* Structure to hold the initial parameters for a compare_and_swap operation
1393 in HImode and QImode. */
1395 struct alignment_context
1397 rtx memsi
; /* SI aligned memory location. */
1398 rtx shift
; /* Bit offset with regard to lsb. */
1399 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1400 rtx modemaski
; /* ~modemask */
1404 /* Initialize structure AC for word access to HI and QI mode memory. */
1407 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1409 machine_mode mode
= GET_MODE (mem
);
1410 rtx byteoffset
= NULL_RTX
;
1411 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1414 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1417 /* Alignment is unknown. */
1420 /* Force the address into a register. */
1421 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1423 /* Align it to SImode. */
1424 align
= expand_simple_binop (Pmode
, AND
, addr
,
1425 GEN_INT (-GET_MODE_SIZE (SImode
)),
1426 NULL_RTX
, 1, OPTAB_DIRECT
);
1428 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1429 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1430 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1431 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1433 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1434 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1435 NULL_RTX
, 1, OPTAB_DIRECT
);
1438 /* Calculate shiftcount. */
1439 if (TARGET_BIG_ENDIAN
)
1441 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1443 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1444 NULL_RTX
, 1, OPTAB_DIRECT
);
1449 ac
->shift
= NULL_RTX
;
1451 ac
->shift
= byteoffset
;
1454 if (ac
->shift
!= NULL_RTX
)
1456 /* Shift is the byte count, but we need the bitcount. */
1457 gcc_assert (exact_log2 (BITS_PER_UNIT
) >= 0);
1458 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
,
1459 GEN_INT (exact_log2 (BITS_PER_UNIT
)),
1460 NULL_RTX
, 1, OPTAB_DIRECT
);
1461 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1462 GEN_INT (GET_MODE_MASK (mode
)),
1464 NULL_RTX
, 1, OPTAB_DIRECT
);
1467 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1469 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1473 /* Expand an atomic compare and swap operation for HImode and QImode.
1474 MEM is the memory location, CMP the old value to compare MEM with
1475 and NEW_RTX the value to set if CMP == MEM. */
1478 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
1480 machine_mode mode
= GET_MODE (mem
);
1481 struct alignment_context ac
;
1482 rtx tmp
, cmpv
, newv
, val
;
1483 rtx oldval
= gen_reg_rtx (SImode
);
1484 rtx res
= gen_reg_rtx (SImode
);
1485 rtx_code_label
*csloop
= gen_label_rtx ();
1486 rtx_code_label
*csend
= gen_label_rtx ();
1488 init_alignment_context (&ac
, mem
);
1490 if (ac
.shift
!= NULL_RTX
)
1492 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1493 new_rtx
= xtensa_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
1496 /* Load the surrounding word into VAL with the MEM value masked out. */
1497 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1498 ac
.modemaski
, NULL_RTX
, 1,
1500 emit_label (csloop
);
1502 /* Patch CMP and NEW_RTX into VAL at correct position. */
1503 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1504 NULL_RTX
, 1, OPTAB_DIRECT
));
1505 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
1506 NULL_RTX
, 1, OPTAB_DIRECT
));
1508 /* Jump to end if we're done. */
1509 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1510 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1512 /* Check for changes outside mode. */
1513 emit_move_insn (oldval
, val
);
1514 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1515 val
, 1, OPTAB_DIRECT
);
1517 emit_move_insn (val
, tmp
);
1519 /* Loop internal if so. */
1520 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1524 /* Return the correct part of the bitfield. */
1525 convert_move (target
,
1526 (ac
.shift
== NULL_RTX
? res
1527 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1528 NULL_RTX
, 1, OPTAB_DIRECT
)),
1533 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1534 the default expansion works fine for SImode). MEM is the memory location
1535 and VAL the value to play with. If AFTER is true then store the value
1536 MEM holds after the operation, if AFTER is false then store the value MEM
1537 holds before the operation. If TARGET is zero then discard that value, else
1538 store it to TARGET. */
1541 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1544 machine_mode mode
= GET_MODE (mem
);
1545 struct alignment_context ac
;
1546 rtx_code_label
*csloop
= gen_label_rtx ();
1548 rtx old
= gen_reg_rtx (SImode
);
1549 rtx new_rtx
= gen_reg_rtx (SImode
);
1550 rtx orig
= NULL_RTX
;
1552 init_alignment_context (&ac
, mem
);
1554 /* Prepare values before the compare-and-swap loop. */
1555 if (ac
.shift
!= NULL_RTX
)
1556 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1561 orig
= gen_reg_rtx (SImode
);
1562 convert_move (orig
, val
, 1);
1570 case MULT
: /* NAND */
1572 /* val = "11..1<val>11..1" */
1573 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1574 NULL_RTX
, 1, OPTAB_DIRECT
);
1581 /* Load full word. Subsequent loads are performed by S32C1I. */
1582 cmp
= force_reg (SImode
, ac
.memsi
);
1584 emit_label (csloop
);
1585 emit_move_insn (old
, cmp
);
1591 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1592 NULL_RTX
, 1, OPTAB_DIRECT
);
1593 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1594 NULL_RTX
, 1, OPTAB_DIRECT
);
1597 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1598 NULL_RTX
, 1, OPTAB_DIRECT
);
1599 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1600 new_rtx
, 1, OPTAB_DIRECT
);
1606 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1607 new_rtx
, 1, OPTAB_DIRECT
);
1610 case MULT
: /* NAND */
1611 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1612 NULL_RTX
, 1, OPTAB_DIRECT
);
1613 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1614 new_rtx
, 1, OPTAB_DIRECT
);
1622 emit_move_insn (new_rtx
, tmp
);
1623 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new_rtx
));
1624 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1628 tmp
= (after
? new_rtx
: cmp
);
1629 convert_move (target
,
1630 (ac
.shift
== NULL_RTX
? tmp
1631 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1632 NULL_RTX
, 1, OPTAB_DIRECT
)),
1639 xtensa_setup_frame_addresses (void)
1641 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1642 cfun
->machine
->accesses_prev_frame
= 1;
1644 if (TARGET_WINDOWED_ABI
)
1646 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1647 LCT_NORMAL
, VOIDmode
);
1651 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1652 a comment showing where the end of the loop is. However, if there is a
1653 label or a branch at the end of the loop then we need to place a nop
1654 there. If the loop ends with a label we need the nop so that branches
1655 targeting that label will target the nop (and thus remain in the loop),
1656 instead of targeting the instruction after the loop (and thus exiting
1657 the loop). If the loop ends with a branch, we need the nop in case the
1658 branch is targeting a location inside the loop. When the branch
1659 executes it will cause the loop count to be decremented even if it is
1660 taken (because it is the last instruction in the loop), so we need to
1661 nop after the branch to prevent the loop count from being decremented
1662 when the branch is taken. */
1665 xtensa_emit_loop_end (rtx_insn
*insn
, rtx
*operands
)
1669 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1671 switch (GET_CODE (insn
))
1678 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1684 rtx body
= PATTERN (insn
);
1688 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1691 else if ((GET_CODE (body
) != USE
)
1692 && (GET_CODE (body
) != CLOBBER
))
1699 output_asm_insn ("%1_LEND:", operands
);
1704 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1706 static char result
[64];
1710 code
= GET_CODE (operands
[3]);
1713 case EQ
: op
= inverted
? "ne" : "eq"; break;
1714 case NE
: op
= inverted
? "eq" : "ne"; break;
1715 case LT
: op
= inverted
? "ge" : "lt"; break;
1716 case GE
: op
= inverted
? "lt" : "ge"; break;
1717 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1718 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1719 default: gcc_unreachable ();
1724 if (INTVAL (operands
[1]) == 0)
1725 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1726 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1728 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1731 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1738 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1740 static char result
[64];
1743 switch (GET_CODE (operands
[3]))
1745 case EQ
: op
= inverted
? "bs" : "bc"; break;
1746 case NE
: op
= inverted
? "bc" : "bs"; break;
1747 default: gcc_unreachable ();
1752 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1753 operands
[1] = GEN_INT (bitnum
);
1754 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1757 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1764 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1766 static char result
[64];
1770 code
= GET_CODE (operands
[4]);
1775 case EQ
: op
= inverted
? "t" : "f"; break;
1776 case NE
: op
= inverted
? "f" : "t"; break;
1777 default: gcc_unreachable ();
1784 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1785 case NE
: op
= inverted
? "eqz" : "nez"; break;
1786 case LT
: op
= inverted
? "gez" : "ltz"; break;
1787 case GE
: op
= inverted
? "ltz" : "gez"; break;
1788 default: gcc_unreachable ();
1792 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1793 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1799 xtensa_emit_call (int callop
, rtx
*operands
)
1801 static char result
[64];
1802 rtx tgt
= operands
[callop
];
1804 if (GET_CODE (tgt
) == CONST_INT
)
1805 sprintf (result
, "call%d\t" HOST_WIDE_INT_PRINT_HEX
,
1806 WINDOW_SIZE
, INTVAL (tgt
));
1807 else if (register_operand (tgt
, VOIDmode
))
1808 sprintf (result
, "callx%d\t%%%d", WINDOW_SIZE
, callop
);
1810 sprintf (result
, "call%d\t%%%d", WINDOW_SIZE
, callop
);
1817 xtensa_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
1819 /* Allow constant pool addresses. */
1820 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1821 && ! TARGET_CONST16
&& constantpool_address_p (addr
)
1822 && ! xtensa_tls_referenced_p (addr
))
1825 while (GET_CODE (addr
) == SUBREG
)
1826 addr
= SUBREG_REG (addr
);
1828 /* Allow base registers. */
1829 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1832 /* Check for "register + offset" addressing. */
1833 if (GET_CODE (addr
) == PLUS
)
1835 rtx xplus0
= XEXP (addr
, 0);
1836 rtx xplus1
= XEXP (addr
, 1);
1837 enum rtx_code code0
;
1838 enum rtx_code code1
;
1840 while (GET_CODE (xplus0
) == SUBREG
)
1841 xplus0
= SUBREG_REG (xplus0
);
1842 code0
= GET_CODE (xplus0
);
1844 while (GET_CODE (xplus1
) == SUBREG
)
1845 xplus1
= SUBREG_REG (xplus1
);
1846 code1
= GET_CODE (xplus1
);
1848 /* Swap operands if necessary so the register is first. */
1849 if (code0
!= REG
&& code1
== REG
)
1851 xplus0
= XEXP (addr
, 1);
1852 xplus1
= XEXP (addr
, 0);
1853 code0
= GET_CODE (xplus0
);
1854 code1
= GET_CODE (xplus1
);
1857 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1858 && code1
== CONST_INT
1859 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1867 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1869 static GTY(()) rtx xtensa_tls_module_base_symbol
;
1872 xtensa_tls_module_base (void)
1874 if (! xtensa_tls_module_base_symbol
)
1876 xtensa_tls_module_base_symbol
=
1877 gen_rtx_SYMBOL_REF (Pmode
, "_TLS_MODULE_BASE_");
1878 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol
)
1879 |= TLS_MODEL_GLOBAL_DYNAMIC
<< SYMBOL_FLAG_TLS_SHIFT
;
1882 return xtensa_tls_module_base_symbol
;
1887 xtensa_call_tls_desc (rtx sym
, rtx
*retp
)
1890 rtx_insn
*call_insn
, *insns
;
1893 fn
= gen_reg_rtx (Pmode
);
1894 arg
= gen_reg_rtx (Pmode
);
1895 a_io
= gen_rtx_REG (Pmode
, WINDOW_SIZE
+ 2);
1897 emit_insn (gen_tls_func (fn
, sym
));
1898 emit_insn (gen_tls_arg (arg
, sym
));
1899 emit_move_insn (a_io
, arg
);
1900 call_insn
= emit_call_insn (gen_tls_call (a_io
, fn
, sym
, const1_rtx
));
1901 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), a_io
);
1902 insns
= get_insns ();
1911 xtensa_legitimize_tls_address (rtx x
)
1913 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
1914 rtx dest
, tp
, ret
, modbase
, base
, addend
;
1917 dest
= gen_reg_rtx (Pmode
);
1920 case TLS_MODEL_GLOBAL_DYNAMIC
:
1921 insns
= xtensa_call_tls_desc (x
, &ret
);
1922 emit_libcall_block (insns
, dest
, ret
, x
);
1925 case TLS_MODEL_LOCAL_DYNAMIC
:
1926 base
= gen_reg_rtx (Pmode
);
1927 modbase
= xtensa_tls_module_base ();
1928 insns
= xtensa_call_tls_desc (modbase
, &ret
);
1929 emit_libcall_block (insns
, base
, ret
, modbase
);
1930 addend
= force_reg (SImode
, gen_sym_DTPOFF (x
));
1931 emit_insn (gen_addsi3 (dest
, base
, addend
));
1934 case TLS_MODEL_INITIAL_EXEC
:
1935 case TLS_MODEL_LOCAL_EXEC
:
1936 tp
= gen_reg_rtx (SImode
);
1937 emit_insn (gen_get_thread_pointersi (tp
));
1938 addend
= force_reg (SImode
, gen_sym_TPOFF (x
));
1939 emit_insn (gen_addsi3 (dest
, tp
, addend
));
1951 xtensa_legitimize_address (rtx x
,
1952 rtx oldx ATTRIBUTE_UNUSED
,
1955 if (xtensa_tls_symbol_p (x
))
1956 return xtensa_legitimize_tls_address (x
);
1958 if (GET_CODE (x
) == PLUS
)
1960 rtx plus0
= XEXP (x
, 0);
1961 rtx plus1
= XEXP (x
, 1);
1963 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1965 plus0
= XEXP (x
, 1);
1966 plus1
= XEXP (x
, 0);
1969 /* Try to split up the offset to use an ADDMI instruction. */
1970 if (GET_CODE (plus0
) == REG
1971 && GET_CODE (plus1
) == CONST_INT
1972 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1973 && !xtensa_simm8 (INTVAL (plus1
))
1974 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1975 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1977 rtx temp
= gen_reg_rtx (Pmode
);
1978 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1979 emit_insn (gen_rtx_SET (temp
, gen_rtx_PLUS (Pmode
, plus0
,
1981 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1988 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1990 Treat constant-pool references as "mode dependent" since they can
1991 only be accessed with SImode loads. This works around a bug in the
1992 combiner where a constant pool reference is temporarily converted
1993 to an HImode load, which is then assumed to zero-extend based on
1994 our definition of LOAD_EXTEND_OP. This is wrong because the high
1995 bits of a 16-bit value in the constant pool are now sign-extended
1999 xtensa_mode_dependent_address_p (const_rtx addr
,
2000 addr_space_t as ATTRIBUTE_UNUSED
)
2002 return constantpool_address_p (addr
);
2005 /* Return TRUE if X contains any TLS symbol references. */
2008 xtensa_tls_referenced_p (rtx x
)
2010 if (! TARGET_HAVE_TLS
)
2013 subrtx_iterator::array_type array
;
2014 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
2016 const_rtx x
= *iter
;
2017 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2020 /* Ignore TLS references that have already been legitimized. */
2021 if (GET_CODE (x
) == UNSPEC
)
2022 switch (XINT (x
, 1))
2026 case UNSPEC_TLS_FUNC
:
2027 case UNSPEC_TLS_ARG
:
2028 case UNSPEC_TLS_CALL
:
2029 iter
.skip_subrtxes ();
2039 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2042 xtensa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2044 return xtensa_tls_referenced_p (x
);
2048 /* Return the debugger register number to use for 'regno'. */
2051 xtensa_dbx_register_number (int regno
)
2055 if (GP_REG_P (regno
))
2057 regno
-= GP_REG_FIRST
;
2060 else if (BR_REG_P (regno
))
2062 regno
-= BR_REG_FIRST
;
2065 else if (FP_REG_P (regno
))
2067 regno
-= FP_REG_FIRST
;
2070 else if (ACC_REG_P (regno
))
2072 first
= 0x200; /* Start of Xtensa special registers. */
2073 regno
= 16; /* ACCLO is special register 16. */
2076 /* When optimizing, we sometimes get asked about pseudo-registers
2077 that don't represent hard registers. Return 0 for these. */
2081 return first
+ regno
;
2085 /* Argument support functions. */
2087 /* Initialize CUMULATIVE_ARGS for a function. */
2090 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
2093 cum
->incoming
= incoming
;
2097 /* Advance the argument to the next argument position. */
2100 xtensa_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
2101 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2106 arg_words
= &get_cumulative_args (cum
)->arg_words
;
2107 max
= MAX_ARGS_IN_REGISTERS
;
2109 words
= (((mode
!= BLKmode
)
2110 ? (int) GET_MODE_SIZE (mode
)
2111 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2113 if (*arg_words
< max
2114 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
2115 || *arg_words
+ words
> max
))
2118 *arg_words
+= words
;
2122 /* Return an RTL expression containing the register for the given mode,
2123 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2124 if this is an incoming argument to the current function. */
2127 xtensa_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
2128 const_tree type
, bool incoming_p
)
2130 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2131 int regbase
, words
, max
;
2135 arg_words
= &cum
->arg_words
;
2136 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
2137 max
= MAX_ARGS_IN_REGISTERS
;
2139 words
= (((mode
!= BLKmode
)
2140 ? (int) GET_MODE_SIZE (mode
)
2141 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2143 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
2145 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
2146 *arg_words
= (*arg_words
+ align
- 1) & -align
;
2149 if (*arg_words
+ words
> max
)
2152 regno
= regbase
+ *arg_words
;
2154 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
2155 cfun
->machine
->need_a7_copy
= TARGET_WINDOWED_ABI
;
2157 return gen_rtx_REG (mode
, regno
);
2160 /* Implement TARGET_FUNCTION_ARG. */
2163 xtensa_function_arg (cumulative_args_t cum
, machine_mode mode
,
2164 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2166 return xtensa_function_arg_1 (cum
, mode
, type
, false);
2169 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2172 xtensa_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
2173 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2175 return xtensa_function_arg_1 (cum
, mode
, type
, true);
2179 xtensa_function_arg_boundary (machine_mode mode
, const_tree type
)
2181 unsigned int alignment
;
2183 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2184 if (alignment
< PARM_BOUNDARY
)
2185 alignment
= PARM_BOUNDARY
;
2186 if (alignment
> STACK_BOUNDARY
)
2187 alignment
= STACK_BOUNDARY
;
2193 xtensa_return_in_msb (const_tree valtype
)
2195 return (TARGET_BIG_ENDIAN
2196 && AGGREGATE_TYPE_P (valtype
)
2197 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
2202 xtensa_option_override (void)
2207 /* Use CONST16 in the absence of L32R.
2208 Set it in the TARGET_OPTION_OVERRIDE to avoid dependency on xtensa
2209 configuration in the xtensa-common.c */
2212 target_flags
|= MASK_CONST16
;
2214 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
2215 error ("boolean registers required for the floating-point option");
2217 /* Set up array giving whether a given register can hold a given mode. */
2218 for (mode
= VOIDmode
;
2219 mode
!= MAX_MACHINE_MODE
;
2220 mode
= (machine_mode
) ((int) mode
+ 1))
2222 int size
= GET_MODE_SIZE (mode
);
2223 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2225 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2229 if (ACC_REG_P (regno
))
2230 temp
= (TARGET_MAC16
2231 && (mclass
== MODE_INT
) && (size
<= UNITS_PER_WORD
));
2232 else if (GP_REG_P (regno
))
2233 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
2234 else if (FP_REG_P (regno
))
2235 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
2236 else if (BR_REG_P (regno
))
2237 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
2241 xtensa_hard_regno_mode_ok_p
[(int) mode
][regno
] = temp
;
2245 init_machine_status
= xtensa_init_machine_status
;
2247 /* Check PIC settings. PIC is only supported when using L32R
2248 instructions, and some targets need to always use PIC. */
2249 if (flag_pic
&& TARGET_CONST16
)
2250 error ("-f%s is not supported with CONST16 instructions",
2251 (flag_pic
> 1 ? "PIC" : "pic"));
2252 else if (TARGET_FORCE_NO_PIC
)
2254 else if (XTENSA_ALWAYS_PIC
)
2257 error ("PIC is required but not supported with CONST16 instructions");
2260 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2263 if (flag_pic
&& !flag_pie
)
2266 /* Hot/cold partitioning does not work on this architecture, because of
2267 constant pools (the load instruction cannot necessarily reach that far).
2268 Therefore disable it on this architecture. */
2269 if (flag_reorder_blocks_and_partition
)
2271 flag_reorder_blocks_and_partition
= 0;
2272 flag_reorder_blocks
= 1;
2276 /* Implement TARGET_HARD_REGNO_NREGS. */
2279 xtensa_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
2281 if (FP_REG_P (regno
))
2282 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_FPREG
);
2283 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
2286 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2289 xtensa_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2291 return xtensa_hard_regno_mode_ok_p
[mode
][regno
];
2294 /* Implement TARGET_MODES_TIEABLE_P. */
2297 xtensa_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2299 return ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
2300 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
2301 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
2302 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
));
2305 /* A C compound statement to output to stdio stream STREAM the
2306 assembler syntax for an instruction operand X. X is an RTL
2309 CODE is a value that can be used to specify one of several ways
2310 of printing the operand. It is used when identical operands
2311 must be printed differently depending on the context. CODE
2312 comes from the '%' specification that was used to request
2313 printing of the operand. If the specification was just '%DIGIT'
2314 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2315 is the ASCII code for LTR.
2317 If X is a register, this macro should print the register's name.
2318 The names can be found in an array 'reg_names' whose type is
2319 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2321 When the machine description has a specification '%PUNCT' (a '%'
2322 followed by a punctuation character), this macro is called with
2323 a null pointer for X and the punctuation character for CODE.
2325 'a', 'c', 'l', and 'n' are reserved.
2327 The Xtensa specific codes are:
2329 'd' CONST_INT, print as signed decimal
2330 'x' CONST_INT, print as signed hexadecimal
2331 'K' CONST_INT, print number of bits in mask for EXTUI
2332 'R' CONST_INT, print (X & 0x1f)
2333 'L' CONST_INT, print ((32 - X) & 0x1f)
2334 'D' REG, print second register of double-word register operand
2335 'N' MEM, print address of next word following a memory operand
2336 'v' MEM, if memory reference is volatile, output a MEMW before it
2337 't' any constant, add "@h" suffix for top 16 bits
2338 'b' any constant, add "@l" suffix for bottom 16 bits
2342 printx (FILE *file
, signed int val
)
2344 /* Print a hexadecimal value in a nice way. */
2345 if ((val
> -0xa) && (val
< 0xa))
2346 fprintf (file
, "%d", val
);
2348 fprintf (file
, "-0x%x", -val
);
2350 fprintf (file
, "0x%x", val
);
2355 print_operand (FILE *file
, rtx x
, int letter
)
2358 error ("PRINT_OPERAND null pointer");
2363 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2364 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2366 output_operand_lossage ("invalid %%D value");
2370 if (GET_CODE (x
) == MEM
)
2372 /* For a volatile memory reference, emit a MEMW before the
2374 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2375 fprintf (file
, "memw\n\t");
2378 output_operand_lossage ("invalid %%v value");
2382 if (GET_CODE (x
) == MEM
2383 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2385 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? E_SFmode
: E_SImode
,
2387 output_address (GET_MODE (x
), XEXP (x
, 0));
2390 output_operand_lossage ("invalid %%N value");
2394 if (GET_CODE (x
) == CONST_INT
)
2397 unsigned val
= INTVAL (x
);
2403 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2404 fatal_insn ("invalid mask", x
);
2406 fprintf (file
, "%d", num_bits
);
2409 output_operand_lossage ("invalid %%K value");
2413 if (GET_CODE (x
) == CONST_INT
)
2414 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 0x1f);
2416 output_operand_lossage ("invalid %%L value");
2420 if (GET_CODE (x
) == CONST_INT
)
2421 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x1f);
2423 output_operand_lossage ("invalid %%R value");
2427 if (GET_CODE (x
) == CONST_INT
)
2428 printx (file
, INTVAL (x
));
2430 output_operand_lossage ("invalid %%x value");
2434 if (GET_CODE (x
) == CONST_INT
)
2435 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
2437 output_operand_lossage ("invalid %%d value");
2442 if (GET_CODE (x
) == CONST_INT
)
2444 printx (file
, INTVAL (x
));
2445 fputs (letter
== 't' ? "@h" : "@l", file
);
2447 else if (GET_CODE (x
) == CONST_DOUBLE
)
2449 if (GET_MODE (x
) == SFmode
)
2452 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2453 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2456 output_operand_lossage ("invalid %%t/%%b value");
2458 else if (GET_CODE (x
) == CONST
)
2460 /* X must be a symbolic constant on ELF. Write an expression
2461 suitable for 'const16' that sets the high or low 16 bits. */
2462 if (GET_CODE (XEXP (x
, 0)) != PLUS
2463 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2464 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2465 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2466 output_operand_lossage ("invalid %%t/%%b value");
2467 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2468 fputs (letter
== 't' ? "@h" : "@l", file
);
2469 /* There must be a non-alphanumeric character between 'h' or 'l'
2470 and the number. The '-' is added by print_operand() already. */
2471 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2473 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2477 output_addr_const (file
, x
);
2478 fputs (letter
== 't' ? "@h" : "@l", file
);
2483 if (GET_CODE (x
) == CONST_DOUBLE
&&
2484 GET_MODE (x
) == SFmode
)
2487 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2488 fprintf (file
, "0x%08lx", l
);
2495 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2496 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2497 else if (GET_CODE (x
) == MEM
)
2498 output_address (GET_MODE (x
), XEXP (x
, 0));
2499 else if (GET_CODE (x
) == CONST_INT
)
2500 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
2502 output_addr_const (file
, x
);
2507 /* A C compound statement to output to stdio stream STREAM the
2508 assembler syntax for an instruction operand that is a memory
2509 reference whose address is ADDR. ADDR is an RTL expression. */
2512 print_operand_address (FILE *file
, rtx addr
)
2515 error ("PRINT_OPERAND_ADDRESS, null pointer");
2517 switch (GET_CODE (addr
))
2520 fatal_insn ("invalid address", addr
);
2524 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2530 rtx offset
= (rtx
)0;
2531 rtx arg0
= XEXP (addr
, 0);
2532 rtx arg1
= XEXP (addr
, 1);
2534 if (GET_CODE (arg0
) == REG
)
2539 else if (GET_CODE (arg1
) == REG
)
2545 fatal_insn ("no register in address", addr
);
2547 if (CONSTANT_P (offset
))
2549 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2550 output_addr_const (file
, offset
);
2553 fatal_insn ("address offset not a constant", addr
);
2561 output_addr_const (file
, addr
);
2566 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2569 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2571 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2573 switch (XINT (x
, 1))
2576 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2577 fputs ("@TPOFF", fp
);
2580 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2581 fputs ("@DTPOFF", fp
);
2586 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2599 xtensa_output_integer_literal_parts (FILE *file
, rtx x
, int size
)
2601 if (size
> 4 && !(size
& (size
- 1)))
2605 split_double (x
, &first
, &second
);
2606 xtensa_output_integer_literal_parts (file
, first
, size
/ 2);
2608 xtensa_output_integer_literal_parts (file
, second
, size
/ 2);
2612 output_addr_const (file
, x
);
2621 xtensa_output_literal (FILE *file
, rtx x
, machine_mode mode
, int labelno
)
2625 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2627 switch (GET_MODE_CLASS (mode
))
2630 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2635 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
),
2637 if (HOST_BITS_PER_LONG
> 32)
2638 value_long
[0] &= 0xffffffff;
2639 fprintf (file
, "0x%08lx\n", value_long
[0]);
2643 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
),
2645 if (HOST_BITS_PER_LONG
> 32)
2647 value_long
[0] &= 0xffffffff;
2648 value_long
[1] &= 0xffffffff;
2650 fprintf (file
, "0x%08lx, 0x%08lx\n",
2651 value_long
[0], value_long
[1]);
2661 case MODE_PARTIAL_INT
:
2662 xtensa_output_integer_literal_parts (file
, x
, GET_MODE_SIZE (mode
));
2672 xtensa_call_save_reg(int regno
)
2674 if (TARGET_WINDOWED_ABI
)
2677 if (regno
== A0_REG
)
2678 return crtl
->profile
|| !crtl
->is_leaf
|| crtl
->calls_eh_return
||
2679 df_regs_ever_live_p (regno
);
2681 if (crtl
->calls_eh_return
&& regno
>= 2 && regno
< 4)
2684 return !fixed_regs
[regno
] && !call_used_regs
[regno
] &&
2685 df_regs_ever_live_p (regno
);
2688 /* Return the bytes needed to compute the frame pointer from the current
2691 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2692 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2695 compute_frame_size (int size
)
2699 if (reload_completed
&& cfun
->machine
->frame_laid_out
)
2700 return cfun
->machine
->current_frame_size
;
2702 /* Add space for the incoming static chain value. */
2703 if (cfun
->static_chain_decl
!= NULL
)
2704 size
+= (1 * UNITS_PER_WORD
);
2706 cfun
->machine
->callee_save_size
= 0;
2707 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2709 if (xtensa_call_save_reg(regno
))
2710 cfun
->machine
->callee_save_size
+= UNITS_PER_WORD
;
2713 cfun
->machine
->current_frame_size
=
2714 XTENSA_STACK_ALIGN (size
2715 + cfun
->machine
->callee_save_size
2716 + crtl
->outgoing_args_size
2717 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2718 cfun
->machine
->callee_save_size
=
2719 XTENSA_STACK_ALIGN (cfun
->machine
->callee_save_size
);
2720 cfun
->machine
->frame_laid_out
= true;
2721 return cfun
->machine
->current_frame_size
;
2726 xtensa_frame_pointer_required (void)
2728 /* The code to expand builtin_frame_addr and builtin_return_addr
2729 currently uses the hard_frame_pointer instead of frame_pointer.
2730 This seems wrong but maybe it's necessary for other architectures.
2731 This function is derived from the i386 code. */
2733 if (cfun
->machine
->accesses_prev_frame
)
2740 xtensa_initial_elimination_offset (int from
, int to ATTRIBUTE_UNUSED
)
2742 long frame_size
= compute_frame_size (get_frame_size ());
2743 HOST_WIDE_INT offset
;
2747 case FRAME_POINTER_REGNUM
:
2748 if (FRAME_GROWS_DOWNWARD
)
2749 offset
= frame_size
- (WINDOW_SIZE
* UNITS_PER_WORD
)
2750 - cfun
->machine
->callee_save_size
;
2754 case ARG_POINTER_REGNUM
:
2755 offset
= frame_size
;
2764 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2765 and the total number of words must be a multiple of 128 bits. */
2766 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2769 xtensa_expand_prologue (void)
2771 HOST_WIDE_INT total_size
;
2772 rtx_insn
*insn
= NULL
;
2776 total_size
= compute_frame_size (get_frame_size ());
2778 if (flag_stack_usage_info
)
2779 current_function_static_stack_size
= total_size
;
2781 if (TARGET_WINDOWED_ABI
)
2783 if (total_size
< (1 << (12+3)))
2784 insn
= emit_insn (gen_entry (GEN_INT (total_size
)));
2787 /* Use a8 as a temporary since a0-a7 may be live. */
2788 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2789 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2790 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2791 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2792 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2798 HOST_WIDE_INT offset
= 0;
2799 int callee_save_size
= cfun
->machine
->callee_save_size
;
2801 /* -128 is a limit of single addi instruction. */
2802 if (total_size
> 0 && total_size
<= 128)
2804 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2805 GEN_INT (-total_size
)));
2806 RTX_FRAME_RELATED_P (insn
) = 1;
2807 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2808 plus_constant (Pmode
, stack_pointer_rtx
,
2810 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2811 offset
= total_size
- UNITS_PER_WORD
;
2813 else if (callee_save_size
)
2815 /* 1020 is maximal s32i offset, if the frame is bigger than that
2816 * we move sp to the end of callee-saved save area, save and then
2817 * move it to its final location. */
2818 if (total_size
> 1024)
2820 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2821 GEN_INT (-callee_save_size
)));
2822 RTX_FRAME_RELATED_P (insn
) = 1;
2823 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2824 plus_constant (Pmode
, stack_pointer_rtx
,
2825 -callee_save_size
));
2826 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2827 offset
= callee_save_size
- UNITS_PER_WORD
;
2831 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2832 emit_move_insn (tmp_reg
, GEN_INT (total_size
));
2833 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
,
2834 stack_pointer_rtx
, tmp_reg
));
2835 RTX_FRAME_RELATED_P (insn
) = 1;
2836 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2837 plus_constant (Pmode
, stack_pointer_rtx
,
2839 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2840 offset
= total_size
- UNITS_PER_WORD
;
2844 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2846 if (xtensa_call_save_reg(regno
))
2848 rtx x
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
2849 rtx mem
= gen_frame_mem (SImode
, x
);
2850 rtx reg
= gen_rtx_REG (SImode
, regno
);
2852 offset
-= UNITS_PER_WORD
;
2853 insn
= emit_move_insn (mem
, reg
);
2854 RTX_FRAME_RELATED_P (insn
) = 1;
2855 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
2856 gen_rtx_SET (mem
, reg
));
2859 if (total_size
> 1024)
2861 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2862 emit_move_insn (tmp_reg
, GEN_INT (total_size
-
2864 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
,
2865 stack_pointer_rtx
, tmp_reg
));
2866 RTX_FRAME_RELATED_P (insn
) = 1;
2867 note_rtx
= gen_rtx_SET (stack_pointer_rtx
,
2868 plus_constant (Pmode
, stack_pointer_rtx
,
2871 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2875 if (frame_pointer_needed
)
2877 if (cfun
->machine
->set_frame_ptr_insn
)
2881 push_topmost_sequence ();
2882 first
= get_insns ();
2883 pop_topmost_sequence ();
2885 /* For all instructions prior to set_frame_ptr_insn, replace
2886 hard_frame_pointer references with stack_pointer. */
2888 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2889 insn
= NEXT_INSN (insn
))
2893 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2894 hard_frame_pointer_rtx
,
2896 df_insn_rescan (insn
);
2902 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2903 stack_pointer_rtx
));
2904 if (!TARGET_WINDOWED_ABI
)
2906 note_rtx
= gen_rtx_SET (hard_frame_pointer_rtx
,
2908 RTX_FRAME_RELATED_P (insn
) = 1;
2909 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2914 if (TARGET_WINDOWED_ABI
)
2916 /* Create a note to describe the CFA. Because this is only used to set
2917 DW_AT_frame_base for debug info, don't bother tracking changes through
2918 each instruction in the prologue. It just takes up space. */
2919 note_rtx
= gen_rtx_SET ((frame_pointer_needed
2920 ? hard_frame_pointer_rtx
2921 : stack_pointer_rtx
),
2922 plus_constant (Pmode
, stack_pointer_rtx
,
2924 RTX_FRAME_RELATED_P (insn
) = 1;
2925 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2930 xtensa_expand_epilogue (void)
2932 if (!TARGET_WINDOWED_ABI
)
2935 HOST_WIDE_INT offset
;
2937 if (cfun
->machine
->current_frame_size
> (frame_pointer_needed
? 127 : 1024))
2939 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2940 emit_move_insn (tmp_reg
, GEN_INT (cfun
->machine
->current_frame_size
-
2941 cfun
->machine
->callee_save_size
));
2942 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_needed
?
2943 hard_frame_pointer_rtx
: stack_pointer_rtx
,
2945 offset
= cfun
->machine
->callee_save_size
- UNITS_PER_WORD
;
2949 if (frame_pointer_needed
)
2950 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
2951 offset
= cfun
->machine
->current_frame_size
- UNITS_PER_WORD
;
2954 /* Prevent reordering of saved a0 update and loading it back from
2956 if (crtl
->calls_eh_return
)
2957 emit_insn (gen_blockage ());
2959 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
2961 if (xtensa_call_save_reg(regno
))
2963 rtx x
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
2965 offset
-= UNITS_PER_WORD
;
2966 emit_move_insn (gen_rtx_REG (SImode
, regno
),
2967 gen_frame_mem (SImode
, x
));
2971 if (cfun
->machine
->current_frame_size
> 0)
2973 if (frame_pointer_needed
|| /* always reachable with addi */
2974 cfun
->machine
->current_frame_size
> 1024 ||
2975 cfun
->machine
->current_frame_size
<= 127)
2977 if (cfun
->machine
->current_frame_size
<= 127)
2978 offset
= cfun
->machine
->current_frame_size
;
2980 offset
= cfun
->machine
->callee_save_size
;
2982 emit_insn (gen_addsi3 (stack_pointer_rtx
,
2988 rtx tmp_reg
= gen_rtx_REG (Pmode
, A9_REG
);
2989 emit_move_insn (tmp_reg
,
2990 GEN_INT (cfun
->machine
->current_frame_size
));
2991 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2996 if (crtl
->calls_eh_return
)
2997 emit_insn (gen_add3_insn (stack_pointer_rtx
,
2999 EH_RETURN_STACKADJ_RTX
));
3001 cfun
->machine
->epilogue_done
= true;
3002 emit_jump_insn (gen_return ());
3006 xtensa_use_return_instruction_p (void)
3008 if (!reload_completed
)
3010 if (TARGET_WINDOWED_ABI
)
3012 if (compute_frame_size (get_frame_size ()) == 0)
3014 return cfun
->machine
->epilogue_done
;
3018 xtensa_set_return_address (rtx address
, rtx scratch
)
3020 HOST_WIDE_INT total_size
= compute_frame_size (get_frame_size ());
3021 rtx frame
= frame_pointer_needed
?
3022 hard_frame_pointer_rtx
: stack_pointer_rtx
;
3023 rtx a0_addr
= plus_constant (Pmode
, frame
,
3024 total_size
- UNITS_PER_WORD
);
3025 rtx note
= gen_rtx_SET (gen_frame_mem (SImode
, a0_addr
),
3026 gen_rtx_REG (SImode
, A0_REG
));
3029 if (total_size
> 1024) {
3030 emit_move_insn (scratch
, GEN_INT (total_size
- UNITS_PER_WORD
));
3031 emit_insn (gen_addsi3 (scratch
, frame
, scratch
));
3035 insn
= emit_move_insn (gen_frame_mem (SImode
, a0_addr
), address
);
3036 RTX_FRAME_RELATED_P (insn
) = 1;
3037 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
3041 xtensa_return_addr (int count
, rtx frame
)
3043 rtx result
, retaddr
, curaddr
, label
;
3045 if (!TARGET_WINDOWED_ABI
)
3050 return get_hard_reg_initial_val (Pmode
, A0_REG
);
3054 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
3057 rtx addr
= plus_constant (Pmode
, frame
, -4 * UNITS_PER_WORD
);
3058 addr
= memory_address (Pmode
, addr
);
3059 retaddr
= gen_reg_rtx (Pmode
);
3060 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
3063 /* The 2 most-significant bits of the return address on Xtensa hold
3064 the register window size. To get the real return address, these
3065 bits must be replaced with the high bits from some address in the
3068 /* Get the 2 high bits of a local label in the code. */
3069 curaddr
= gen_reg_rtx (Pmode
);
3070 label
= gen_label_rtx ();
3072 LABEL_PRESERVE_P (label
) = 1;
3073 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
3074 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
3075 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
3077 /* Clear the 2 high bits of the return address. */
3078 result
= gen_reg_rtx (Pmode
);
3079 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
3080 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
3082 /* Combine them to get the result. */
3083 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
3087 /* Disable the use of word-sized or smaller complex modes for structures,
3088 and for function arguments in particular, where they cause problems with
3089 register a7. The xtensa_copy_incoming_a7 function assumes that there is
3090 a single reference to an argument in a7, but with small complex modes the
3091 real and imaginary components may be extracted separately, leading to two
3092 uses of the register, only one of which would be replaced. */
3095 xtensa_member_type_forces_blk (const_tree
, machine_mode mode
)
3097 return mode
== CQImode
|| mode
== CHImode
;
3100 /* Create the va_list data type.
3102 This structure is set up by __builtin_saveregs. The __va_reg field
3103 points to a stack-allocated region holding the contents of the
3104 incoming argument registers. The __va_ndx field is an index
3105 initialized to the position of the first unnamed (variable)
3106 argument. This same index is also used to address the arguments
3107 passed in memory. Thus, the __va_stk field is initialized to point
3108 to the position of the first argument in memory offset to account
3109 for the arguments passed in registers and to account for the size
3110 of the argument registers not being 16-byte aligned. E.G., there
3111 are 6 argument registers of 4 bytes each, but we want the __va_ndx
3112 for the first stack argument to have the maximal alignment of 16
3113 bytes, so we offset the __va_stk address by 32 bytes so that
3114 __va_stk[32] references the first argument on the stack. */
3117 xtensa_build_builtin_va_list (void)
3119 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
3121 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
3122 type_decl
= build_decl (BUILTINS_LOCATION
,
3123 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
3125 f_stk
= build_decl (BUILTINS_LOCATION
,
3126 FIELD_DECL
, get_identifier ("__va_stk"),
3128 f_reg
= build_decl (BUILTINS_LOCATION
,
3129 FIELD_DECL
, get_identifier ("__va_reg"),
3131 f_ndx
= build_decl (BUILTINS_LOCATION
,
3132 FIELD_DECL
, get_identifier ("__va_ndx"),
3135 DECL_FIELD_CONTEXT (f_stk
) = record
;
3136 DECL_FIELD_CONTEXT (f_reg
) = record
;
3137 DECL_FIELD_CONTEXT (f_ndx
) = record
;
3139 TYPE_STUB_DECL (record
) = type_decl
;
3140 TYPE_NAME (record
) = type_decl
;
3141 TYPE_FIELDS (record
) = f_stk
;
3142 DECL_CHAIN (f_stk
) = f_reg
;
3143 DECL_CHAIN (f_reg
) = f_ndx
;
3145 layout_type (record
);
3150 /* Save the incoming argument registers on the stack. Returns the
3151 address of the saved registers. */
3154 xtensa_builtin_saveregs (void)
3157 int arg_words
= crtl
->args
.info
.arg_words
;
3158 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
3163 /* Allocate the general-purpose register space. */
3164 gp_regs
= assign_stack_local
3165 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
3166 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
3168 /* Now store the incoming registers. */
3169 cfun
->machine
->need_a7_copy
= TARGET_WINDOWED_ABI
;
3170 cfun
->machine
->vararg_a7
= true;
3171 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
3172 adjust_address (gp_regs
, BLKmode
,
3173 arg_words
* UNITS_PER_WORD
),
3175 if (cfun
->machine
->vararg_a7_copy
!= 0)
3176 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
3178 return XEXP (gp_regs
, 0);
3182 /* Implement `va_start' for varargs and stdarg. We look at the
3183 current function to fill in an initial va_list. */
3186 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
3194 arg_words
= crtl
->args
.info
.arg_words
;
3196 f_stk
= TYPE_FIELDS (va_list_type_node
);
3197 f_reg
= DECL_CHAIN (f_stk
);
3198 f_ndx
= DECL_CHAIN (f_reg
);
3200 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
3201 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
3203 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
3206 /* Call __builtin_saveregs; save the result in __va_reg */
3207 u
= make_tree (sizetype
, expand_builtin_saveregs ());
3208 u
= fold_convert (ptr_type_node
, u
);
3209 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
3210 TREE_SIDE_EFFECTS (t
) = 1;
3211 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3213 /* Set the __va_stk member to ($arg_ptr - 32). */
3214 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
3215 u
= fold_build_pointer_plus_hwi (u
, -32);
3216 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
3217 TREE_SIDE_EFFECTS (t
) = 1;
3218 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3220 /* Set the __va_ndx member. If the first variable argument is on
3221 the stack, adjust __va_ndx by 2 words to account for the extra
3222 alignment offset for __va_stk. */
3223 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
3225 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
3226 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
3227 TREE_SIDE_EFFECTS (t
) = 1;
3228 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3232 /* Implement `va_arg'. */
3235 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
3236 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
3241 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
3242 tree lab_false
, lab_over
, lab_false2
;
3245 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
3247 type
= build_pointer_type (type
);
3249 /* Handle complex values as separate real and imaginary parts. */
3250 if (TREE_CODE (type
) == COMPLEX_TYPE
)
3252 tree real_part
, imag_part
;
3254 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
3256 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
3258 imag_part
= xtensa_gimplify_va_arg_expr (unshare_expr (valist
),
3261 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
3263 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
3266 f_stk
= TYPE_FIELDS (va_list_type_node
);
3267 f_reg
= DECL_CHAIN (f_stk
);
3268 f_ndx
= DECL_CHAIN (f_reg
);
3270 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
,
3272 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
3274 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
3277 type_size
= size_in_bytes (type
);
3278 va_size
= round_up (type_size
, UNITS_PER_WORD
);
3279 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
3282 /* First align __va_ndx if necessary for this arg:
3284 orig_ndx = (AP).__va_ndx;
3285 if (__alignof__ (TYPE) > 4 )
3286 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
3287 & -__alignof__ (TYPE)); */
3289 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
3291 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
3293 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
3295 t
= build2 (PLUS_EXPR
, integer_type_node
, unshare_expr (orig_ndx
),
3296 build_int_cst (integer_type_node
, align
- 1));
3297 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
3298 build_int_cst (integer_type_node
, -align
));
3299 gimplify_assign (unshare_expr (orig_ndx
), t
, pre_p
);
3303 /* Increment __va_ndx to point past the argument:
3305 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
3307 t
= fold_convert (integer_type_node
, va_size
);
3308 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
3309 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
3312 /* Check if the argument is in registers:
3314 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
3315 && !must_pass_in_stack (type))
3316 __array = (AP).__va_reg; */
3318 array
= create_tmp_var (ptr_type_node
);
3321 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
3323 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
3324 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
3326 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (ndx
),
3327 build_int_cst (integer_type_node
,
3328 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3329 t
= build3 (COND_EXPR
, void_type_node
, t
,
3330 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
3332 gimplify_and_add (t
, pre_p
);
3334 gimplify_assign (unshare_expr (array
), reg
, pre_p
);
3336 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
3337 gimplify_and_add (t
, pre_p
);
3339 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
3340 gimplify_and_add (t
, pre_p
);
3344 /* ...otherwise, the argument is on the stack (never split between
3345 registers and the stack -- change __va_ndx if necessary):
3349 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
3350 (AP).__va_ndx = 32 + __va_size (TYPE);
3351 __array = (AP).__va_stk;
3354 lab_false2
= create_artificial_label (UNKNOWN_LOCATION
);
3356 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (orig_ndx
),
3357 build_int_cst (integer_type_node
,
3358 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3359 t
= build3 (COND_EXPR
, void_type_node
, t
,
3360 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
3362 gimplify_and_add (t
, pre_p
);
3364 t
= size_binop (PLUS_EXPR
, unshare_expr (va_size
), size_int (32));
3365 t
= fold_convert (integer_type_node
, t
);
3366 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
3368 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
3369 gimplify_and_add (t
, pre_p
);
3371 gimplify_assign (array
, stk
, pre_p
);
3375 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
3376 gimplify_and_add (t
, pre_p
);
3380 /* Given the base array pointer (__array) and index to the subsequent
3381 argument (__va_ndx), find the address:
3383 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3387 The results are endian-dependent because values smaller than one word
3388 are aligned differently. */
3391 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
3393 t
= fold_build2 (GE_EXPR
, boolean_type_node
, unshare_expr (type_size
),
3394 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
3395 t
= fold_build3 (COND_EXPR
, sizetype
, t
, unshare_expr (va_size
),
3396 unshare_expr (type_size
));
3400 size
= unshare_expr (va_size
);
3402 t
= fold_convert (sizetype
, unshare_expr (ndx
));
3403 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
3404 addr
= fold_build_pointer_plus (unshare_expr (array
), t
);
3406 addr
= fold_convert (build_pointer_type (type
), addr
);
3408 addr
= build_va_arg_indirect_ref (addr
);
3409 return build_va_arg_indirect_ref (addr
);
3417 XTENSA_BUILTIN_UMULSIDI3
,
3423 xtensa_init_builtins (void)
3427 ftype
= build_function_type_list (unsigned_intDI_type_node
,
3428 unsigned_intSI_type_node
,
3429 unsigned_intSI_type_node
, NULL_TREE
);
3431 decl
= add_builtin_function ("__builtin_umulsidi3", ftype
,
3432 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
3433 "__umulsidi3", NULL_TREE
);
3434 TREE_NOTHROW (decl
) = 1;
3435 TREE_READONLY (decl
) = 1;
3440 xtensa_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
, tree
*args
,
3441 bool ignore ATTRIBUTE_UNUSED
)
3443 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3448 case XTENSA_BUILTIN_UMULSIDI3
:
3451 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
3452 || TARGET_MUL32_HIGH
)
3453 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
3454 fold_convert (unsigned_intDI_type_node
, arg0
),
3455 fold_convert (unsigned_intDI_type_node
, arg1
));
3459 internal_error ("bad builtin code");
3468 xtensa_expand_builtin (tree exp
, rtx target
,
3469 rtx subtarget ATTRIBUTE_UNUSED
,
3470 machine_mode mode ATTRIBUTE_UNUSED
,
3473 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
3474 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3478 case XTENSA_BUILTIN_UMULSIDI3
:
3479 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3480 __umulsidi3 function when the Xtensa configuration can directly
3481 implement it. If not, just call the function. */
3482 return expand_call (exp
, target
, ignore
);
3485 internal_error ("bad builtin code");
3490 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3493 xtensa_preferred_reload_class (rtx x
, reg_class_t rclass
)
3495 if (CONSTANT_P (x
) && CONST_DOUBLE_P (x
))
3498 /* Don't use the stack pointer or hard frame pointer for reloads!
3499 The hard frame pointer would normally be OK except that it may
3500 briefly hold an incoming argument in the prologue, and reload
3501 won't know that it is live because the hard frame pointer is
3502 treated specially. */
3504 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3510 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3513 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED
,
3516 /* Don't use the stack pointer or hard frame pointer for reloads!
3517 The hard frame pointer would normally be OK except that it may
3518 briefly hold an incoming argument in the prologue, and reload
3519 won't know that it is live because the hard frame pointer is
3520 treated specially. */
3522 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3528 /* Worker function for TARGET_SECONDARY_RELOAD. */
3531 xtensa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass
,
3532 machine_mode mode
, secondary_reload_info
*sri
)
3536 if (in_p
&& constantpool_mem_p (x
))
3538 if (rclass
== FP_REGS
)
3542 sri
->icode
= CODE_FOR_reloadqi_literal
;
3543 else if (mode
== HImode
)
3544 sri
->icode
= CODE_FOR_reloadhi_literal
;
3547 regno
= xt_true_regnum (x
);
3548 if (ACC_REG_P (regno
))
3549 return ((rclass
== GR_REGS
|| rclass
== RL_REGS
) ? NO_REGS
: RL_REGS
);
3550 if (rclass
== ACC_REG
)
3551 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
3558 order_regs_for_local_alloc (void)
3560 if (!leaf_function_p ())
3562 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
3564 static const int reg_nonleaf_alloc_order_call0
[FIRST_PSEUDO_REGISTER
] =
3566 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 12, 13, 14, 15,
3568 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
3573 memcpy (reg_alloc_order
, TARGET_WINDOWED_ABI
?
3574 reg_nonleaf_alloc_order
: reg_nonleaf_alloc_order_call0
,
3575 FIRST_PSEUDO_REGISTER
* sizeof (int));
3579 int i
, num_arg_regs
;
3582 /* Use the AR registers in increasing order (skipping a0 and a1)
3583 but save the incoming argument registers for a last resort. */
3584 num_arg_regs
= crtl
->args
.info
.arg_words
;
3585 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
3586 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
3587 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
3588 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
3589 for (i
= 0; i
< num_arg_regs
; i
++)
3590 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
3592 /* List the coprocessor registers in order. */
3593 for (i
= 0; i
< BR_REG_NUM
; i
++)
3594 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
3596 /* List the FP registers in order for now. */
3597 for (i
= 0; i
< 16; i
++)
3598 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
3600 /* GCC requires that we list *all* the registers.... */
3601 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
3602 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
3603 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
3604 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
3606 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
3611 /* Some Xtensa targets support multiple bss sections. If the section
3612 name ends with ".bss", add SECTION_BSS to the flags. */
3615 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
3617 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
3620 suffix
= strrchr (name
, '.');
3621 if (suffix
&& strcmp (suffix
, ".bss") == 0)
3623 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
3624 && DECL_INITIAL (decl
) == NULL_TREE
))
3625 flags
|= SECTION_BSS
; /* @nobits */
3627 warning (0, "only uninitialized variables can be placed in a "
3635 /* The literal pool stays with the function. */
3638 xtensa_select_rtx_section (machine_mode mode ATTRIBUTE_UNUSED
,
3639 rtx x ATTRIBUTE_UNUSED
,
3640 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
3642 return function_section (current_function_decl
);
3645 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3648 xtensa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3649 reg_class_t from
, reg_class_t to
)
3651 if (from
== to
&& from
!= BR_REGS
&& to
!= BR_REGS
)
3653 else if (reg_class_subset_p (from
, AR_REGS
)
3654 && reg_class_subset_p (to
, AR_REGS
))
3656 else if (reg_class_subset_p (from
, AR_REGS
) && to
== ACC_REG
)
3658 else if (from
== ACC_REG
&& reg_class_subset_p (to
, AR_REGS
))
3664 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3667 xtensa_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3668 reg_class_t rclass ATTRIBUTE_UNUSED
,
3669 bool in ATTRIBUTE_UNUSED
)
3674 /* Compute a (partial) cost for rtx X. Return true if the complete
3675 cost has been computed, and false if subexpressions should be
3676 scanned. In either case, *TOTAL contains the cost result. */
3679 xtensa_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3680 int opno ATTRIBUTE_UNUSED
,
3681 int *total
, bool speed ATTRIBUTE_UNUSED
)
3683 int code
= GET_CODE (x
);
3691 if (xtensa_simm12b (INTVAL (x
)))
3698 if (xtensa_simm8 (INTVAL (x
))
3699 || xtensa_simm8x256 (INTVAL (x
)))
3706 if (xtensa_mask_immediate (INTVAL (x
)))
3713 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
3724 /* No way to tell if X is the 2nd operand so be conservative. */
3727 if (xtensa_simm12b (INTVAL (x
)))
3729 else if (TARGET_CONST16
)
3730 *total
= COSTS_N_INSNS (2);
3739 *total
= COSTS_N_INSNS (2);
3746 *total
= COSTS_N_INSNS (4);
3754 (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
) ? 2 : 1;
3756 if (memory_address_p (mode
, XEXP ((x
), 0)))
3757 *total
= COSTS_N_INSNS (num_words
);
3759 *total
= COSTS_N_INSNS (2*num_words
);
3765 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3769 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3773 *total
= COSTS_N_INSNS (mode
== DImode
? 3 : 2);
3780 *total
= COSTS_N_INSNS (2);
3782 *total
= COSTS_N_INSNS (1);
3789 *total
= COSTS_N_INSNS (50);
3791 *total
= COSTS_N_INSNS (1);
3797 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3798 else if (mode
== DFmode
)
3799 *total
= COSTS_N_INSNS (50);
3801 *total
= COSTS_N_INSNS (4);
3809 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3810 else if (mode
== DFmode
|| mode
== DImode
)
3811 *total
= COSTS_N_INSNS (50);
3813 *total
= COSTS_N_INSNS (1);
3818 *total
= COSTS_N_INSNS (mode
== DImode
? 4 : 2);
3824 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3825 else if (mode
== DFmode
)
3826 *total
= COSTS_N_INSNS (50);
3827 else if (mode
== DImode
)
3828 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3829 else if (TARGET_MUL32
)
3830 *total
= COSTS_N_INSNS (4);
3831 else if (TARGET_MAC16
)
3832 *total
= COSTS_N_INSNS (16);
3833 else if (TARGET_MUL16
)
3834 *total
= COSTS_N_INSNS (12);
3836 *total
= COSTS_N_INSNS (50);
3845 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3848 else if (mode
== DFmode
)
3850 *total
= COSTS_N_INSNS (50);
3860 *total
= COSTS_N_INSNS (50);
3861 else if (TARGET_DIV32
)
3862 *total
= COSTS_N_INSNS (32);
3864 *total
= COSTS_N_INSNS (50);
3870 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3872 *total
= COSTS_N_INSNS (50);
3879 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3884 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3889 *total
= COSTS_N_INSNS (1);
3897 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3900 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3902 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3903 > 4 * UNITS_PER_WORD
);
3906 /* Worker function for TARGET_FUNCTION_VALUE. */
3909 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3912 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3913 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3914 ? SImode
: TYPE_MODE (valtype
),
3915 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3918 /* Worker function for TARGET_LIBCALL_VALUE. */
3921 xtensa_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
3923 return gen_rtx_REG ((GET_MODE_CLASS (mode
) == MODE_INT
3924 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3925 ? SImode
: mode
, GP_RETURN
);
3928 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3931 xtensa_function_value_regno_p (const unsigned int regno
)
3933 return (regno
== GP_RETURN
);
3936 /* The static chain is passed in memory. Provide rtx giving 'mem'
3937 expressions that denote where they are stored. */
3940 xtensa_static_chain (const_tree
ARG_UNUSED (fndecl_or_type
), bool incoming_p
)
3942 if (TARGET_WINDOWED_ABI
)
3944 rtx base
= incoming_p
? arg_pointer_rtx
: stack_pointer_rtx
;
3945 return gen_frame_mem (Pmode
, plus_constant (Pmode
, base
,
3946 -5 * UNITS_PER_WORD
));
3949 return gen_rtx_REG (Pmode
, A8_REG
);
3953 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3954 instruction with a minimal stack frame in order to get some free
3955 registers. Once the actual call target is known, the proper stack frame
3956 size is extracted from the ENTRY instruction at the target and the
3957 current frame is adjusted to match. The trampoline then transfers
3958 control to the instruction following the ENTRY at the target. Note:
3959 this assumes that the target begins with an ENTRY instruction. */
3962 xtensa_asm_trampoline_template (FILE *stream
)
3964 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3966 fprintf (stream
, "\t.begin no-transform\n");
3968 if (TARGET_WINDOWED_ABI
)
3970 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3974 /* Save the return address. */
3975 fprintf (stream
, "\tmov\ta10, a0\n");
3977 /* Use a CALL0 instruction to skip past the constants and in the
3978 process get the PC into A0. This allows PC-relative access to
3979 the constants without relying on L32R. */
3980 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3983 fprintf (stream
, "\tj\t.Lskipconsts\n");
3985 fprintf (stream
, "\t.align\t4\n");
3986 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3987 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3988 fprintf (stream
, ".Lskipconsts:\n");
3990 /* Load the static chain and function address from the trampoline. */
3993 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3994 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3995 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3999 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
4000 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
4003 /* Store the static chain. */
4004 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
4006 /* Set the proper stack pointer value. */
4007 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
4008 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
4009 TARGET_BIG_ENDIAN
? 8 : 12);
4010 fprintf (stream
, "\tslli\ta9, a9, 3\n");
4011 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
4012 fprintf (stream
, "\tsub\ta9, sp, a9\n");
4013 fprintf (stream
, "\tmovsp\tsp, a9\n");
4016 /* Restore the return address. */
4017 fprintf (stream
, "\tmov\ta0, a10\n");
4019 /* Jump to the instruction following the ENTRY. */
4020 fprintf (stream
, "\taddi\ta8, a8, 3\n");
4021 fprintf (stream
, "\tjx\ta8\n");
4023 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
4025 fprintf (stream
, "\t.byte\t0\n");
4027 fprintf (stream
, "\tnop\n");
4033 /* Save the return address. */
4034 fprintf (stream
, "\tmov\ta10, a0\n");
4036 /* Use a CALL0 instruction to skip past the constants and in the
4037 process get the PC into A0. This allows PC-relative access to
4038 the constants without relying on L32R. */
4039 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
4042 fprintf (stream
, "\tj\t.Lskipconsts\n");
4044 fprintf (stream
, "\t.align\t4\n");
4045 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
4046 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
4047 fprintf (stream
, ".Lskipconsts:\n");
4049 /* Load the static chain and function address from the trampoline. */
4052 fprintf (stream
, "\taddi\ta0, a0, 3\n");
4053 fprintf (stream
, "\tl32i\ta8, a0, 0\n");
4054 fprintf (stream
, "\tl32i\ta9, a0, 4\n");
4055 fprintf (stream
, "\tmov\ta0, a10\n");
4059 fprintf (stream
, "\tl32r\ta8, .Lchainval\n");
4060 fprintf (stream
, "\tl32r\ta9, .Lfnaddr\n");
4062 fprintf (stream
, "\tjx\ta9\n");
4064 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
4066 fprintf (stream
, "\t.byte\t0\n");
4068 fprintf (stream
, "\tnop\n");
4070 fprintf (stream
, "\t.end no-transform\n");
4074 xtensa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain
)
4076 rtx func
= XEXP (DECL_RTL (fndecl
), 0);
4077 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
4081 if (TARGET_WINDOWED_ABI
)
4083 chain_off
= use_call0
? 12 : 8;
4084 func_off
= use_call0
? 16 : 12;
4088 chain_off
= use_call0
? 8 : 4;
4089 func_off
= use_call0
? 12 : 8;
4092 emit_block_move (m_tramp
, assemble_trampoline_template (),
4093 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4095 emit_move_insn (adjust_address (m_tramp
, SImode
, chain_off
), chain
);
4096 emit_move_insn (adjust_address (m_tramp
, SImode
, func_off
), func
);
4097 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
4098 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
4101 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
4104 xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4106 return !xtensa_tls_referenced_p (x
);
4109 /* Implement TARGET_CAN_USE_DOLOOP_P. */
4112 xtensa_can_use_doloop_p (const widest_int
&, const widest_int
&,
4113 unsigned int loop_depth
, bool entered_at_top
)
4115 /* Considering limitations in the hardware, only use doloop
4116 for innermost loops which must be entered from the top. */
4117 if (loop_depth
> 1 || !entered_at_top
)
4123 /* NULL if INSN insn is valid within a low-overhead loop.
4124 Otherwise return why doloop cannot be applied. */
4127 xtensa_invalid_within_doloop (const rtx_insn
*insn
)
4130 return "Function call in the loop.";
4132 if (JUMP_P (insn
) && INSN_CODE (insn
) == CODE_FOR_return
)
4133 return "Return from a call instruction in the loop.";
4138 /* Optimize LOOP. */
4141 hwloop_optimize (hwloop_info loop
)
4145 basic_block entry_bb
;
4147 rtx_insn
*insn
, *seq
, *entry_after
;
4149 if (loop
->depth
> 1)
4152 fprintf (dump_file
, ";; loop %d is not innermost\n",
4157 if (!loop
->incoming_dest
)
4160 fprintf (dump_file
, ";; loop %d has more than one entry\n",
4165 if (loop
->incoming_dest
!= loop
->head
)
4168 fprintf (dump_file
, ";; loop %d is not entered from head\n",
4173 if (loop
->has_call
|| loop
->has_asm
)
4176 fprintf (dump_file
, ";; loop %d has invalid insn\n",
4181 /* Scan all the blocks to make sure they don't use iter_reg. */
4182 if (loop
->iter_reg_used
|| loop
->iter_reg_used_outside
)
4185 fprintf (dump_file
, ";; loop %d uses iterator\n",
4190 /* Check if start_label appears before doloop_end. */
4191 insn
= loop
->start_label
;
4192 while (insn
&& insn
!= loop
->loop_end
)
4193 insn
= NEXT_INSN (insn
);
4198 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
4203 /* Get the loop iteration register. */
4204 iter_reg
= loop
->iter_reg
;
4206 gcc_assert (REG_P (iter_reg
));
4210 FOR_EACH_VEC_SAFE_ELT (loop
->incoming
, i
, entry_edge
)
4211 if (entry_edge
->flags
& EDGE_FALLTHRU
)
4214 if (entry_edge
== NULL
)
4217 /* Place the zero_cost_loop_start instruction before the loop. */
4218 entry_bb
= entry_edge
->src
;
4222 insn
= emit_insn (gen_zero_cost_loop_start (loop
->iter_reg
,
4228 if (!single_succ_p (entry_bb
) || vec_safe_length (loop
->incoming
) > 1)
4234 emit_insn_before (seq
, BB_HEAD (loop
->head
));
4235 seq
= emit_label_before (gen_label_rtx (), seq
);
4236 new_bb
= create_basic_block (seq
, insn
, entry_bb
);
4237 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4239 if (!(e
->flags
& EDGE_FALLTHRU
))
4240 redirect_edge_and_branch_force (e
, new_bb
);
4242 redirect_edge_succ (e
, new_bb
);
4245 make_edge (new_bb
, loop
->head
, 0);
4249 entry_after
= BB_END (entry_bb
);
4250 while (DEBUG_INSN_P (entry_after
)
4251 || (NOTE_P (entry_after
)
4252 && NOTE_KIND (entry_after
) != NOTE_INSN_BASIC_BLOCK
4253 /* Make sure we don't split a call and its corresponding
4254 CALL_ARG_LOCATION note. */
4255 && NOTE_KIND (entry_after
) != NOTE_INSN_CALL_ARG_LOCATION
))
4256 entry_after
= PREV_INSN (entry_after
);
4258 emit_insn_after (seq
, entry_after
);
4266 /* A callback for the hw-doloop pass. Called when a loop we have discovered
4267 turns out not to be optimizable; we have to split the loop_end pattern into
4268 a subtract and a test. */
4271 hwloop_fail (hwloop_info loop
)
4274 rtx_insn
*insn
= loop
->loop_end
;
4276 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
4281 test
= gen_rtx_NE (VOIDmode
, loop
->iter_reg
, const0_rtx
);
4282 insn
= emit_jump_insn_before (gen_cbranchsi4 (test
,
4283 loop
->iter_reg
, const0_rtx
,
4287 JUMP_LABEL (insn
) = loop
->start_label
;
4288 LABEL_NUSES (loop
->start_label
)++;
4289 delete_insn (loop
->loop_end
);
4292 /* A callback for the hw-doloop pass. This function examines INSN; if
4293 it is a doloop_end pattern we recognize, return the reg rtx for the
4294 loop counter. Otherwise, return NULL_RTX. */
4297 hwloop_pattern_reg (rtx_insn
*insn
)
4301 if (!JUMP_P (insn
) || recog_memoized (insn
) != CODE_FOR_loop_end
)
4304 reg
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 1));
4312 static struct hw_doloop_hooks xtensa_doloop_hooks
=
4319 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4320 and tries to rewrite the RTL of these loops so that proper Xtensa
4321 hardware loops are generated. */
4324 xtensa_reorg_loops (void)
4327 reorg_loops (false, &xtensa_doloop_hooks
);
4330 /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. */
4335 /* We are freeing block_for_insn in the toplev to keep compatibility
4336 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4337 compute_bb_for_insn ();
4341 /* Doloop optimization. */
4342 xtensa_reorg_loops ();
4345 /* Update register usage after having seen the compiler flags. */
4348 xtensa_conditional_register_usage (void)
4352 c_mask
= TARGET_WINDOWED_ABI
? (1 << 1) : (1 << 2);
4354 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4356 /* Set/reset conditionally defined registers from
4357 CALL_USED_REGISTERS initializer. */
4358 if (call_used_regs
[i
] > 1)
4359 call_used_regs
[i
] = !!(call_used_regs
[i
] & c_mask
);
4362 /* Remove hard FP register from the preferred reload registers set. */
4363 CLEAR_HARD_REG_BIT (reg_class_contents
[(int)RL_REGS
],
4364 HARD_FRAME_POINTER_REGNUM
);
4367 /* Map hard register number to register class */
4369 enum reg_class
xtensa_regno_to_class (int regno
)
4371 static const enum reg_class regno_to_class
[FIRST_PSEUDO_REGISTER
] =
4373 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
4374 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4375 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4376 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
4377 AR_REGS
, AR_REGS
, BR_REGS
,
4378 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4379 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4380 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4381 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
4385 if (regno
== HARD_FRAME_POINTER_REGNUM
)
4388 return regno_to_class
[regno
];
4391 /* Implement TARGET_CONSTANT_ALIGNMENT. Align string constants and
4392 constructors to at least a word boundary. The typical use of this
4393 macro is to increase alignment for string constants to be word
4394 aligned so that 'strcpy' calls that copy constants can be done
4397 static HOST_WIDE_INT
4398 xtensa_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
4400 if ((TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
4402 return MAX (align
, BITS_PER_WORD
);
4406 /* Implement TARGET_STARTING_FRAME_OFFSET. */
4408 static HOST_WIDE_INT
4409 xtensa_starting_frame_offset (void)
4411 if (FRAME_GROWS_DOWNWARD
)
4413 return crtl
->outgoing_args_size
;
4416 #include "gt-xtensa.h"