gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst

   1 ..
   2   Copyright 1988-2022 Free Software Foundation, Inc.
   3   This is part of the GCC manual.
   4   For copying conditions, see the copyright.rst file.
   5
   6 .. program:: RISC-V
   7
   8 .. index:: RISC-V Options
   9
  10 .. _risc-v-options:
  11
  12 RISC-V Options
  13 ^^^^^^^^^^^^^^
  14
  15 These command-line options are defined for RISC-V targets:
  16
  17 .. option:: -mbranch-cost={n}
  18
  19   Set the cost of branches to roughly :samp:`{n}` instructions.
  20
  21 .. option:: -mplt, -mno-plt
  22
  23   When generating PIC code, do or don't allow the use of PLTs. Ignored for
  24   non-PIC.  The default is :option:`-mplt`.
  25
  26 .. option:: -mabi={ABI-string}
  27
  28   Specify integer and floating-point calling convention.  :samp:`{ABI-string}`
  29   contains two parts: the size of integer types and the registers used for
  30   floating-point types.  For example :samp:`-march=rv64ifd -mabi=lp64d` means that
  31   :samp:`long` and pointers are 64-bit (implicitly defining :samp:`int` to be
  32   32-bit), and that floating-point values up to 64 bits wide are passed in F
  33   registers.  Contrast this with :samp:`-march=rv64ifd -mabi=lp64f`, which still
  34   allows the compiler to generate code that uses the F and D extensions but only
  35   allows floating-point values up to 32 bits long to be passed in registers; or
  36   :samp:`-march=rv64ifd -mabi=lp64`, in which no floating-point arguments will be
  37   passed in registers.
  38
  39   The default for this argument is system dependent, users who want a specific
  40   calling convention should specify one explicitly.  The valid calling
  41   conventions are: :samp:`ilp32`, :samp:`ilp32f`, :samp:`ilp32d`, :samp:`lp64`,
  42   :samp:`lp64f`, and :samp:`lp64d`.  Some calling conventions are impossible to
  43   implement on some ISAs: for example, :samp:`-march=rv32if -mabi=ilp32d` is
  44   invalid because the ABI requires 64-bit values be passed in F registers, but F
  45   registers are only 32 bits wide.  There is also the :samp:`ilp32e` ABI that can
  46   only be used with the :samp:`rv32e` architecture.  This ABI is not well
  47   specified at present, and is subject to change.
  48
  49 .. option:: -mfdiv, -mno-fdiv
  50
  51   Do or don't use hardware floating-point divide and square root instructions.
  52   This requires the F or D extensions for floating-point registers.  The default
  53   is to use them if the specified architecture has these instructions.
  54
  55 .. option:: -mdiv, -mno-div
  56
  57   Do or don't use hardware instructions for integer division.  This requires the
  58   M extension.  The default is to use them if the specified architecture has
  59   these instructions.
  60
  61 .. option:: -misa-spec={ISA-spec-string}
  62
  63   Specify the version of the RISC-V Unprivileged (formerly User-Level)
  64   ISA specification to produce code conforming to.  The possibilities
  65   for :samp:`{ISA-spec-string}` are:
  66
  67   ``2.2``
  68     Produce code conforming to version 2.2.
  69
  70   ``20190608``
  71     Produce code conforming to version 20190608.
  72
  73   ``20191213``
  74     Produce code conforming to version 20191213.
  75
  76   The default is :option:`-misa-spec=20191213` unless GCC has been configured
  77   with :option:`--with-isa-spec=` specifying a different default version.
  78
  79 .. option:: -march={ISA-string}
  80
  81   Generate code for given RISC-V ISA (e.g. :samp:`rv64im`).  ISA strings must be
  82   lower-case.  Examples include :samp:`rv64i`, :samp:`rv32g`, :samp:`rv32e`, and
  83   :samp:`rv32imaf`.
  84
  85   When :option:`-march=` is not specified, use the setting from :option:`-mcpu`.
  86
  87   If both :option:`-march` and :option:`-mcpu=` are not specified, the default for
  88   this argument is system dependent, users who want a specific architecture
  89   extensions should specify one explicitly.
  90
  91 .. option:: -mcpu={processor-string}
  92
  93   Use architecture of and optimize the output for the given processor, specified
  94   by particular CPU name.
  95   Permissible values for this option are: :samp:`sifive-e20`, :samp:`sifive-e21`,
  96   :samp:`sifive-e24`, :samp:`sifive-e31`, :samp:`sifive-e34`, :samp:`sifive-e76`,
  97   :samp:`sifive-s21`, :samp:`sifive-s51`, :samp:`sifive-s54`, :samp:`sifive-s76`,
  98   :samp:`sifive-u54`, and :samp:`sifive-u74`.
  99
 100 .. option:: -mtune={processor-string}
 101
 102   Optimize the output for the given processor, specified by microarchitecture or
 103   particular CPU name.  Permissible values for this option are: :samp:`rocket`,
 104   :samp:`sifive-3-series`, :samp:`sifive-5-series`, :samp:`sifive-7-series`,
 105   :samp:`thead-c906`, :samp:`size`, and all valid options for :option:`-mcpu=`.
 106
 107   When :option:`-mtune=` is not specified, use the setting from :option:`-mcpu`,
 108   the default is :samp:`rocket` if both are not specified.
 109
 110   The :samp:`size` choice is not intended for use by end-users.  This is used
 111   when :option:`-Os` is specified.  It overrides the instruction cost info
 112   provided by :option:`-mtune=`, but does not override the pipeline info.  This
 113   helps reduce code size while still giving good performance.
 114
 115 .. option:: -mpreferred-stack-boundary={num}
 116
 117   Attempt to keep the stack boundary aligned to a 2 raised to :samp:`{num}`
 118   byte boundary.  If :option:`-mpreferred-stack-boundary` is not specified,
 119   the default is 4 (16 bytes or 128-bits).
 120
 121   .. warning::
 122
 123     If you use this switch, then you must build all modules with
 124     the same value, including any libraries.  This includes the system libraries
 125     and startup modules.
 126
 127 .. option:: -msmall-data-limit={n}
 128
 129   Put global and static data smaller than :samp:`{n}` bytes into a special section
 130   (on some targets).
 131
 132 .. option:: -msave-restore, -mno-save-restore
 133
 134   Do or don't use smaller but slower prologue and epilogue code that uses
 135   library function calls.  The default is to use fast inline prologues and
 136   epilogues.
 137
 138 .. option:: -mshorten-memrefs, -mno-shorten-memrefs
 139
 140   Do or do not attempt to make more use of compressed load/store instructions by
 141   replacing a load/store of 'base register + large offset' with a new load/store
 142   of 'new base + small offset'.  If the new base gets stored in a compressed
 143   register, then the new load/store can be compressed.  Currently targets 32-bit
 144   integer load/stores only.
 145
 146 .. option:: -mstrict-align, -mno-strict-align
 147
 148   Do not or do generate unaligned memory accesses.  The default is set depending
 149   on whether the processor we are optimizing for supports fast unaligned access
 150   or not.
 151
 152 .. option:: -mcmodel=medlow
 153
 154   Generate code for the medium-low code model. The program and its statically
 155   defined symbols must lie within a single 2 GiB address range and must lie
 156   between absolute addresses -2 GiB and +2 GiB. Programs can be
 157   statically or dynamically linked. This is the default code model.
 158
 159 .. option:: -mcmodel=medany
 160
 161   Generate code for the medium-any code model. The program and its statically
 162   defined symbols must be within any single 2 GiB address range. Programs can be
 163   statically or dynamically linked.
 164
 165 .. option:: -mexplicit-relocs, -mno-exlicit-relocs
 166
 167   Use or do not use assembler relocation operators when dealing with symbolic
 168   addresses.  The alternative is to use assembler macros instead, which may
 169   limit optimization.
 170
 171 .. option:: -mrelax, -mno-relax
 172
 173   Take advantage of linker relaxations to reduce the number of instructions
 174   required to materialize symbol addresses. The default is to take advantage of
 175   linker relaxations.
 176
 177 .. option:: -mriscv-attribute, -mno-riscv-attribute
 178
 179   Emit (do not emit) RISC-V attribute to record extra information into ELF
 180   objects.  This feature requires at least binutils 2.32.
 181
 182 .. option:: -mcsr-check, -mno-csr-check
 183
 184   Enables or disables the CSR checking.
 185
 186 .. option:: -malign-data={type}
 187
 188   Control how GCC aligns variables and constants of array, structure, or union
 189   types.  Supported values for :samp:`{type}` are :samp:`xlen` which uses x register
 190   width as the alignment value, and :samp:`natural` which uses natural alignment.
 191   :samp:`xlen` is the default.
 192
 193 .. option:: -mbig-endian
 194
 195   Generate big-endian code.  This is the default when GCC is configured for a
 196   :samp:`riscv64be-*-*` or :samp:`riscv32be-*-*` target.
 197
 198 .. option:: -mlittle-endian
 199
 200   Generate little-endian code.  This is the default when GCC is configured for a
 201   :samp:`riscv64-*-*` or :samp:`riscv32-*-*` but not a :samp:`riscv64be-*-*` or
 202   :samp:`riscv32be-*-*` target.
 203
 204 .. option:: -mstack-protector-guard={guard}
 205
 206   Generate stack protection code using canary at :samp:`{guard}`.  Supported
 207   locations are :samp:`global` for a global canary or :samp:`tls` for per-thread
 208   canary in the TLS block.
 209
 210   With the latter choice the options
 211   :option:`-mstack-protector-guard-reg=reg` and
 212   :option:`-mstack-protector-guard-offset=offset` furthermore specify
 213   which register to use as base register for reading the canary,
 214   and from what offset from that base register. There is no default
 215   register or offset as this is entirely for use within the Linux
 216   kernel.