i386: Use "addr" attribute to limit address regclass to non-REX regs

Use "addr" attribute with "gpr8" value to limit address register class
to non-REX registers in instructions with high registers, where REX
registers can not be used in the address.

gcc/ChangeLog:

	* config/i386/constraints.md (Bc): Remove constraint.
	(Bn): Rewrite to use x86_extended_reg_mentioned_p predicate.
	* config/i386/i386.cc (ix86_memory_address_reg_class):
	Do not limit processing to TARGET_APX_EGPR.  Exit early for
	NULL insn.  Do not check recog_data.insn before calling
	extract_insn_cached.
	(ix86_insn_base_reg_class): Handle ADDR_GPR8.
	(ix86_regno_ok_for_insn_base_p): Ditto.
	(ix86_insn_index_reg_class): Ditto.
	* config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64):
	Remove insn pattern and corresponding peephole2 pattern.
	(*cmpi_ext<mode>_1): Remove (m,Q) alternative.
	Change (QBc,Q) alternative to (QBn,Q).  Add "addr" attribute.
	(*cmpqi_ext<mode>_3_mem_rex64): Remove insn pattern
	and corresponding peephole2 pattern.
	(*cmpi_ext<mode>_3): Remove (Q,m) alternative.
	Change (Q,QnBc) alternative to (Q,QnBn).  Add "addr" attribute.
	(*extzvqi_mem_rex64): Remove insn pattern and
	corresponding peephole2 pattern.
	(*extzvqi): Remove (Q,m) alternative.  Change (Q,QnBc)
	alternative to (Q,QnBn).  Add "addr" attribute.
	(*insvqi_1_mem_rex64): Remove insn pattern and
	corresponding peephole2 pattern.
	(*insvqi_1): Remove (Q,m) alternative.  Change (Q,QnBc)
	alternative to (Q,QnBn).  Add "addr" attribute.
	(@insv<mode>_1): Ditto.
	(*addqi_ext<mode>_0): Remove (m,0,Q) alternative.  Change (QBc,0,Q)
	alternative to (QBn,0,Q).  Add "addr" attribute.
	(*subqi_ext<mode>_0): Ditto.
	(*andqi_ext<mode>_0): Ditto.
	(*<any_or:code>qi_ext<mode>_0): Ditto.
	(*addqi_ext<mode>_1): Remove (Q,0,m) alternative.  Change (Q,0,QnBc)
	alternative to (Q,0,QnBn).  Add "addr" attribute.
	(*andqi_ext<mode>_1): Ditto.
	(*andqi_ext<mode>_1_cc): Ditto.
	(*<any_or:code>qi_ext<mode>_1): Ditto.
	(*xorqi_ext<mode>_1_cc): Ditto.
	* config/i386/predicates.md (nonimm_x64constmem_operand):
	Remove predicate.
	(general_x64constmem_operand): Ditto.
	(norex_memory_operand): Ditto.

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index f6275740eb22ad26453bdec34cf988f9b20f8d4e..8da8a4170c434d762acadbb974f10fd515564d08 100644 (file)
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -187,11 +187,6 @@
   "@internal Vector memory operand."
   (match_operand 0 "vector_memory_operand"))
 
-(define_special_memory_constraint "Bc"
-  "@internal Constant memory operand."
-  (and (match_operand 0 "memory_operand")
-       (match_test "constant_address_p (XEXP (op, 0))")))
-
 (define_memory_constraint "Bk"
   "@internal TLS address that allows insn using non-integer registers."
   (and (match_operand 0 "memory_operand")
@@ -199,7 +194,8 @@
 
 (define_special_memory_constraint "Bn"
   "@internal Memory operand without REX prefix."
-  (match_operand 0 "norex_memory_operand"))
+  (and (match_operand 0 "memory_operand")
+       (not (match_test "x86_extended_reg_mentioned_p (op)"))))
 
 (define_special_memory_constraint "Br"
   "@internal bcst memory operand."

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index fdc9362cf5b2d3ba165ba3fcff63ffaea5ceb949..c2bd07fced7b1d150f8eb55d95a43d83368e93a8 100644 (file)
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -11366,50 +11366,49 @@ ix86_memory_address_reg_class (rtx_insn* insn)
      return maximum register class in this case.  */
   enum attr_addr addr_rclass = ADDR_GPR32;
 
-  if (TARGET_APX_EGPR && insn)
-    {
-      if (asm_noperands (PATTERN (insn)) >= 0
-         || GET_CODE (PATTERN (insn)) == ASM_INPUT)
-       return ix86_apx_inline_asm_use_gpr32 ? ADDR_GPR32 : ADDR_GPR16;
+  if (!insn)
+    return addr_rclass;
 
-      /* Return maximum register class for unrecognized instructions.  */
-      if (INSN_CODE (insn) < 0)
-       return addr_rclass;
+  if (asm_noperands (PATTERN (insn)) >= 0
+      || GET_CODE (PATTERN (insn)) == ASM_INPUT)
+    return ix86_apx_inline_asm_use_gpr32 ? ADDR_GPR32 : ADDR_GPR16;
 
-      /* Try to recognize the insn before calling get_attr_addr.
-        Save current recog_data and current alternative.  */
-      struct recog_data_d saved_recog_data = recog_data;
-      int saved_alternative = which_alternative;
+  /* Return maximum register class for unrecognized instructions.  */
+  if (INSN_CODE (insn) < 0)
+    return addr_rclass;
 
-      /* Update recog_data for processing of alternatives.  */
-      if (recog_data.insn != insn)
-       extract_insn_cached (insn);
+  /* Try to recognize the insn before calling get_attr_addr.
+     Save current recog_data and current alternative.  */
+  struct recog_data_d saved_recog_data = recog_data;
+  int saved_alternative = which_alternative;
 
-      /* If current alternative is not set, loop throught enabled
-        alternatives and get the most limited register class.  */
-      if (saved_alternative == -1)
-       {
-         alternative_mask enabled = get_enabled_alternatives (insn);
+  /* Update recog_data for processing of alternatives.  */
+  extract_insn_cached (insn);
 
-         for (int i = 0; i < recog_data.n_alternatives; i++)
-           {
-             if (!TEST_BIT (enabled, i))
-               continue;
+  /* If current alternative is not set, loop throught enabled
+     alternatives and get the most limited register class.  */
+  if (saved_alternative == -1)
+    {
+      alternative_mask enabled = get_enabled_alternatives (insn);
 
-             which_alternative = i;
-             addr_rclass = MIN (addr_rclass, get_attr_addr (insn));
-           }
-       }
-      else
+      for (int i = 0; i < recog_data.n_alternatives; i++)
        {
-         which_alternative = saved_alternative;
-         addr_rclass = get_attr_addr (insn);
-       }
+         if (!TEST_BIT (enabled, i))
+           continue;
 
-      recog_data = saved_recog_data;
+         which_alternative = i;
+         addr_rclass = MIN (addr_rclass, get_attr_addr (insn));
+       }
+    }
+  else
+    {
       which_alternative = saved_alternative;
+      addr_rclass = get_attr_addr (insn);
     }
 
+  recog_data = saved_recog_data;
+  which_alternative = saved_alternative;
+
   return addr_rclass;
 }
 
@@ -11421,7 +11420,7 @@ ix86_insn_base_reg_class (rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_GENERAL_REGS;
     case ADDR_GPR16:
       return GENERAL_GPR16;
     case ADDR_GPR32:
@@ -11439,7 +11438,7 @@ ix86_regno_ok_for_insn_base_p (int regno, rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_INT_REGNO_P (regno);
     case ADDR_GPR16:
       return GENERAL_GPR16_REGNO_P (regno);
     case ADDR_GPR32:
@@ -11457,7 +11456,7 @@ ix86_insn_index_reg_class (rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_INDEX_REGS;
     case ADDR_GPR16:
       return INDEX_GPR16;
     case ADDR_GPR32:

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ecc74e9994e565b17655b5e7bdd7d7b182330ff2..97ab69342a50a0cf96b8b4729ea7b02016548d19 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1538,58 +1538,21 @@
   [(set_attr "type" "icmp")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*cmpqi_ext<mode>_1_mem_rex64"
-  [(set (reg FLAGS_REG)
-       (compare
-         (match_operand:QI 0 "norex_memory_operand" "Bn")
-         (subreg:QI
-           (match_operator:SWI248 2 "extract_operator"
-             [(match_operand 1 "int248_register_operand" "Q")
-              (const_int 8)
-              (const_int 8)]) 0)))]
-  "TARGET_64BIT && reload_completed
-   && ix86_match_ccmode (insn, CCmode)"
-  "cmp{b}\t{%h1, %0|%0, %h1}"
-  [(set_attr "type" "icmp")
-   (set_attr "mode" "QI")])
-
 (define_insn "*cmpqi_ext<mode>_1"
   [(set (reg FLAGS_REG)
        (compare
-         (match_operand:QI 0 "nonimmediate_operand" "QBc,m")
+         (match_operand:QI 0 "nonimmediate_operand" "QBn")
          (subreg:QI
            (match_operator:SWI248 2 "extract_operator"
-             [(match_operand 1 "int248_register_operand" "Q,Q")
+             [(match_operand 1 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%h1, %0|%0, %h1}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "icmp")
    (set_attr "mode" "QI")])
 
-(define_peephole2
-  [(set (match_operand:QI 0 "register_operand")
-       (match_operand:QI 1 "norex_memory_operand"))
-   (set (match_operand 3 "flags_reg_operand")
-       (match_operator 4 "compare_operator"
-         [(match_dup 0)
-          (subreg:QI
-            (match_operator:SWI248 5 "extract_operator"
-              [(match_operand 2 "int248_register_operand")
-               (const_int 8)
-               (const_int 8)]) 0)]))]
-  "TARGET_64BIT
-   && peep2_reg_dead_p (2, operands[0])"
-  [(set (match_dup 3)
-       (match_op_dup 4
-         [(match_dup 1)
-          (subreg:QI
-            (match_op_dup 5
-              [(match_dup 2)
-               (const_int 8)
-               (const_int 8)]) 0)]))])
-
 (define_insn "*cmpqi_ext<mode>_2"
   [(set (reg FLAGS_REG)
        (compare
@@ -1615,58 +1578,21 @@
              (const_int 8)) 0)
          (match_operand:QI 1 "const_int_operand")))])
 
-(define_insn "*cmpqi_ext<mode>_3_mem_rex64"
-  [(set (reg FLAGS_REG)
-       (compare
-         (subreg:QI
-           (match_operator:SWI248 2 "extract_operator"
-             [(match_operand 0 "int248_register_operand" "Q")
-              (const_int 8)
-              (const_int 8)]) 0)
-         (match_operand:QI 1 "norex_memory_operand" "Bn")))]
-  "TARGET_64BIT && reload_completed
-   && ix86_match_ccmode (insn, CCmode)"
-  "cmp{b}\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "icmp")
-   (set_attr "mode" "QI")])
-
 (define_insn "*cmpqi_ext<mode>_3"
   [(set (reg FLAGS_REG)
        (compare
          (subreg:QI
            (match_operator:SWI248 2 "extract_operator"
-             [(match_operand 0 "int248_register_operand" "Q,Q")
+             [(match_operand 0 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)
-         (match_operand:QI 1 "general_operand" "QnBc,m")))]
+         (match_operand:QI 1 "general_operand" "QnBn")))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "icmp")
    (set_attr "mode" "QI")])
 
-(define_peephole2
-  [(set (match_operand:QI 0 "register_operand")
-       (match_operand:QI 1 "norex_memory_operand"))
-   (set (match_operand 3 "flags_reg_operand")
-       (match_operator 4 "compare_operator"
-         [(subreg:QI
-            (match_operator:SWI248 5 "extract_operator"
-              [(match_operand 2 "int248_register_operand")
-               (const_int 8)
-               (const_int 8)]) 0)
-          (match_dup 0)]))]
-  "TARGET_64BIT
-   && peep2_reg_dead_p (2, operands[0])"
-  [(set (match_dup 3)
-       (match_op_dup 4
-         [(subreg:QI
-            (match_op_dup 5
-              [(match_dup 2)
-               (const_int 8)
-               (const_int 8)]) 0)
-          (match_dup 1)]))])
-
 (define_insn "*cmpqi_ext<mode>_4"
   [(set (reg FLAGS_REG)
        (compare
@@ -3477,23 +3403,11 @@
   [(set_attr "type" "imovx")
    (set_attr "mode" "SI")])
 
-(define_insn "*extzvqi_mem_rex64"
-  [(set (match_operand:QI 0 "norex_memory_operand" "=Bn")
-       (subreg:QI
-         (match_operator:SWI248 2 "extract_operator"
-           [(match_operand 1 "int248_register_operand" "Q")
-            (const_int 8)
-            (const_int 8)]) 0))]
-  "TARGET_64BIT && reload_completed"
-  "mov{b}\t{%h1, %0|%0, %h1}"
-  [(set_attr "type" "imov")
-   (set_attr "mode" "QI")])
-
 (define_insn "*extzvqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn,?R")
        (subreg:QI
          (match_operator:SWI248 2 "extract_operator"
-           [(match_operand 1 "int248_register_operand" "Q,Q,Q")
+           [(match_operand 1 "int248_register_operand" "Q,Q")
             (const_int 8)
             (const_int 8)]) 0))]
   ""
@@ -3506,7 +3420,7 @@
       return "mov{b}\t{%h1, %0|%0, %h1}";
     }
 }
-  [(set_attr "isa" "*,*,nox64")
+  [(set_attr "addr" "gpr8,*")
    (set (attr "type")
      (if_then_else (and (match_operand:QI 0 "register_operand")
                        (ior (not (match_operand:QI 0 "QIreg_operand"))
@@ -3518,23 +3432,6 @@
        (const_string "SI")
        (const_string "QI")))])
 
-(define_peephole2
-  [(set (match_operand:QI 0 "register_operand")
-       (subreg:QI
-         (match_operator:SWI248 3 "extract_operator"
-           [(match_operand 1 "int248_register_operand")
-            (const_int 8)
-            (const_int 8)]) 0))
-   (set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))]
-  "TARGET_64BIT
-   && peep2_reg_dead_p (2, operands[0])"
-  [(set (match_dup 2)
-       (subreg:QI
-         (match_op_dup 3
-           [(match_dup 1)
-            (const_int 8)
-            (const_int 8)]) 0))])
-
 (define_expand "insv<mode>"
   [(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand")
                             (match_operand:QI 1 "const_int_operand")
@@ -3568,61 +3465,35 @@
   DONE;
 })
 
-(define_insn "*insvqi_1_mem_rex64"
-  [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q")
-         (const_int 8)
-         (const_int 8))
-       (subreg:SWI248
-         (match_operand:QI 1 "norex_memory_operand" "Bn") 0))]
-  "TARGET_64BIT && reload_completed"
-  "mov{b}\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "imov")
-   (set_attr "mode" "QI")])
-
 (define_insn "@insv<mode>_1"
   [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
-       (match_operand:SWI248 1 "general_operand" "QnBc,m"))]
+       (match_operand:SWI248 1 "general_operand" "QnBn"))]
   ""
 {
   if (CONST_INT_P (operands[1]))
     operands[1] = gen_int_mode (INTVAL (operands[1]), QImode);
   return "mov{b}\t{%b1, %h0|%h0, %b1}";
 }
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
 (define_insn "*insvqi_1"
   [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
-         (match_operand:QI 1 "general_operand" "QnBc,m") 0))]
+         (match_operand:QI 1 "general_operand" "QnBn") 0))]
   ""
   "mov{b}\t{%1, %h0|%h0, %1}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
-(define_peephole2
-  [(set (match_operand:QI 0 "register_operand")
-       (match_operand:QI 1 "norex_memory_operand"))
-   (set (zero_extract:SWI248 (match_operand 2 "int248_register_operand")
-                            (const_int 8)
-                            (const_int 8))
-       (subreg:SWI248 (match_dup 0) 0))]
-  "TARGET_64BIT
-   && peep2_reg_dead_p (2, operands[0])"
-  [(set (zero_extract:SWI248 (match_dup 2)
-                            (const_int 8)
-                            (const_int 8))
-          (subreg:SWI248 (match_dup 1) 0))])
-
 ;; Eliminate redundant insv, e.g. xorl %eax,%eax; movb $0, %ah
 (define_peephole2
   [(parallel [(set (match_operand:SWI48 0 "general_reg_operand")
@@ -7099,18 +6970,18 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*addqi_ext<mode>_0"
-  [(set (match_operand:QI 0 "nonimm_x64constmem_operand" "=QBc,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
        (plus:QI
          (subreg:QI
            (match_operator:SWI248 3 "extract_operator"
-             [(match_operand 2 "int248_register_operand" "Q,Q")
+             [(match_operand 2 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)
-         (match_operand:QI 1 "nonimm_x64constmem_operand" "0,0")))
+         (match_operand:QI 1 "nonimmediate_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "add{b}\t{%h2, %0|%0, %h2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -7130,17 +7001,17 @@
 
 (define_insn "*addqi_ext<mode>_1"
   [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
          (plus:QI
            (subreg:QI
              (match_operator:SWI248 3 "extract_operator"
-               [(match_operand 1 "int248_register_operand" "0,0")
+               [(match_operand 1 "int248_register_operand" "0")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBn")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "/* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    rtx_equal_p (operands[0], operands[1])"
@@ -7160,7 +7031,7 @@
       return "add{b}\t{%2, %h0|%h0, %2}";
     }
 }
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set (attr "type")
      (if_then_else (match_operand:QI 2 "incdec_operand")
        (const_string "incdec")
@@ -7739,18 +7610,18 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*subqi_ext<mode>_0"
-  [(set (match_operand:QI 0 "nonimm_x64constmem_operand" "=QBc,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
        (minus:QI
-         (match_operand:QI 1 "nonimm_x64constmem_operand" "0,0")
+         (match_operand:QI 1 "nonimmediate_operand" "0")
          (subreg:QI
            (match_operator:SWI248 3 "extract_operator"
-             [(match_operand 2 "int248_register_operand" "Q,Q")
+             [(match_operand 2 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "sub{b}\t{%h2, %0|%0, %h2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -10942,14 +10813,14 @@
          (and:QI
            (subreg:QI
              (match_operator:SWI248 2 "extract_operator"
-               [(match_operand 0 "int248_register_operand" "Q,Q")
+               [(match_operand 0 "int248_register_operand" "Q")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 1 "general_x64constmem_operand" "QnBc,m"))
+           (match_operand:QI 1 "general_operand" "QnBn"))
          (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\t{%1, %h0|%h0, %1}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "test")
    (set_attr "mode" "QI")])
 
@@ -11656,18 +11527,18 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*andqi_ext<mode>_0"
-  [(set (match_operand:QI 0 "nonimm_x64constmem_operand" "=QBc,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
        (and:QI
          (subreg:QI
            (match_operator:SWI248 3 "extract_operator"
-             [(match_operand 2 "int248_register_operand" "Q,Q")
+             [(match_operand 2 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)
-         (match_operand:QI 1 "nonimm_x64constmem_operand" "0,0")))
+         (match_operand:QI 1 "nonimmediate_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "and{b}\t{%h2, %0|%0, %h2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -11687,22 +11558,22 @@
 
 (define_insn "*andqi_ext<mode>_1"
   [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
          (and:QI
            (subreg:QI
              (match_operator:SWI248 3 "extract_operator"
-               [(match_operand 1 "int248_register_operand" "0,0")
+               [(match_operand 1 "int248_register_operand" "0")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBn")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "/* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    rtx_equal_p (operands[0], operands[1])"
   "and{b}\t{%2, %h0|%h0, %2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -11714,13 +11585,13 @@
          (and:QI
            (subreg:QI
              (match_operator:SWI248 3 "extract_operator"
-               [(match_operand 1 "int248_register_operand" "0,0")
+               [(match_operand 1 "int248_register_operand" "0")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m"))
+           (match_operand:QI 2 "general_operand" "QnBn"))
          (const_int 0)))
    (set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
@@ -11735,7 +11606,7 @@
    /* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    && rtx_equal_p (operands[0], operands[1])"
   "and{b}\t{%2, %h0|%h0, %2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -12404,40 +12275,40 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*<code>qi_ext<mode>_0"
-  [(set (match_operand:QI 0 "nonimm_x64constmem_operand" "=QBc,m")
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=QBn")
        (any_or:QI
          (subreg:QI
            (match_operator:SWI248 3 "extract_operator"
-             [(match_operand 2 "int248_register_operand" "Q,Q")
+             [(match_operand 2 "int248_register_operand" "Q")
               (const_int 8)
               (const_int 8)]) 0)
-         (match_operand:QI 1 "nonimm_x64constmem_operand" "0,0")))
+         (match_operand:QI 1 "nonimmediate_operand" "0")))
    (clobber (reg:CC FLAGS_REG))]
   ""
   "<logic>{b}\t{%h2, %0|%0, %h2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
 (define_insn "*<code>qi_ext<mode>_1"
   [(set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
          (any_or:QI
            (subreg:QI
              (match_operator:SWI248 3 "extract_operator"
-               [(match_operand 1 "int248_register_operand" "0,0")
+               [(match_operand 1 "int248_register_operand" "0")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m")) 0))
+           (match_operand:QI 2 "general_operand" "QnBn")) 0))
    (clobber (reg:CC FLAGS_REG))]
   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    /* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    && rtx_equal_p (operands[0], operands[1])"
   "<logic>{b}\t{%2, %h0|%h0, %2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
@@ -12576,13 +12447,13 @@
          (xor:QI
            (subreg:QI
              (match_operator:SWI248 3 "extract_operator"
-               [(match_operand 1 "int248_register_operand" "0,0")
+               [(match_operand 1 "int248_register_operand" "0")
                 (const_int 8)
                 (const_int 8)]) 0)
-           (match_operand:QI 2 "general_x64constmem_operand" "QnBc,m"))
+           (match_operand:QI 2 "general_operand" "QnBn"))
          (const_int 0)))
    (set (zero_extract:SWI248
-         (match_operand 0 "int248_register_operand" "+Q,Q")
+         (match_operand 0 "int248_register_operand" "+Q")
          (const_int 8)
          (const_int 8))
        (subreg:SWI248
@@ -12597,7 +12468,7 @@
    /* FIXME: without this LRA can't reload this pattern, see PR82524.  */
    && rtx_equal_p (operands[0], operands[1])"
   "xor{b}\t{%2, %h0|%h0, %2}"
-  [(set_attr "isa" "*,nox64")
+  [(set_attr "addr" "gpr8")
    (set_attr "type" "alu")
    (set_attr "mode" "QI")])
 

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index e3d55f0c502223b4b56d7629459883c0ae8c69da..a63b8cd7be50f09b3d0c64fc072ef8bb8eace0b6 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -114,20 +114,6 @@
            (match_test "GET_MODE (op) == HImode")
            (match_test "GET_MODE (op) == QImode"))))
 
-;; Match nonimmediate operand, but exclude non-constant addresses for x86_64.
-(define_predicate "nonimm_x64constmem_operand"
-  (ior (match_operand 0 "register_operand")
-       (and (match_operand 0 "memory_operand")
-           (ior (not (match_test "TARGET_64BIT"))
-                (match_test "constant_address_p (XEXP (op, 0))")))))
-
-;; Match general operand, but exclude non-constant addresses for x86_64.
-(define_predicate "general_x64constmem_operand"
-  (ior (match_operand 0 "nonmemory_operand")
-       (and (match_operand 0 "memory_operand")
-           (ior (not (match_test "TARGET_64BIT"))
-                (match_test "constant_address_p (XEXP (op, 0))")))))
-
 ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
 (define_predicate "register_ssemem_operand"
   (if_then_else
@@ -1338,10 +1324,6 @@
   (ior (match_operand 0 "nonimmediate_operand")
        (match_operand 0 "const0_operand")))
 
-(define_predicate "norex_memory_operand"
-  (and (match_operand 0 "memory_operand")
-       (not (match_test "x86_extended_reg_mentioned_p (op)"))))
-
 ;; Return true for RTX codes that force SImode address.
 (define_predicate "SImode_address_operand"
   (match_code "subreg,zero_extend,and"))