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1 /* Low-level functions for atomic operations. Mips version.
2 Copyright (C) 2005-2019 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library. If not, see
17 <http://www.gnu.org/licenses/>. */
18
19 #ifndef _MIPS_ATOMIC_MACHINE_H
20 #define _MIPS_ATOMIC_MACHINE_H 1
21
22 #include <stdint.h>
23 #include <inttypes.h>
24 #include <sgidefs.h>
25
26 typedef int32_t atomic32_t;
27 typedef uint32_t uatomic32_t;
28 typedef int_fast32_t atomic_fast32_t;
29 typedef uint_fast32_t uatomic_fast32_t;
30
31 typedef int64_t atomic64_t;
32 typedef uint64_t uatomic64_t;
33 typedef int_fast64_t atomic_fast64_t;
34 typedef uint_fast64_t uatomic_fast64_t;
35
36 typedef intptr_t atomicptr_t;
37 typedef uintptr_t uatomicptr_t;
38 typedef intmax_t atomic_max_t;
39 typedef uintmax_t uatomic_max_t;
40
41 #if _MIPS_SIM == _ABIO32 && __mips < 2
42 #define MIPS_PUSH_MIPS2 ".set mips2\n\t"
43 #else
44 #define MIPS_PUSH_MIPS2
45 #endif
46
47 #if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
48 #define __HAVE_64B_ATOMICS 0
49 #else
50 #define __HAVE_64B_ATOMICS 1
51 #endif
52
53 /* See the comments in <sys/asm.h> about the use of the sync instruction. */
54 #ifndef MIPS_SYNC
55 # define MIPS_SYNC sync
56 #endif
57
58 #define MIPS_SYNC_STR_2(X) #X
59 #define MIPS_SYNC_STR_1(X) MIPS_SYNC_STR_2(X)
60 #define MIPS_SYNC_STR MIPS_SYNC_STR_1(MIPS_SYNC)
61
62 #define USE_ATOMIC_COMPILER_BUILTINS 1
63
64 /* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
65 instruction which will be used by __atomic_exchange_n. */
66 #ifdef _MIPS_ARCH_XLP
67 # define ATOMIC_EXCHANGE_USES_CAS 0
68 #else
69 # define ATOMIC_EXCHANGE_USES_CAS 1
70 #endif
71
72 /* Compare and exchange.
73 For all "bool" routines, we return FALSE if exchange succesful. */
74
75 #define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
76 (abort (), 0)
77
78 #define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
79 (abort (), 0)
80
81 #define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
82 ({ \
83 typeof (*mem) __oldval = (oldval); \
84 !__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
85 model, __ATOMIC_RELAXED); \
86 })
87
88 #define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
89 (abort (), (typeof(*mem)) 0)
90
91 #define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
92 (abort (), (typeof(*mem)) 0)
93
94 #define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
95 ({ \
96 typeof (*mem) __oldval = (oldval); \
97 __atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
98 model, __ATOMIC_RELAXED); \
99 __oldval; \
100 })
101
102 #if _MIPS_SIM == _ABIO32
103 /* We can't do an atomic 64-bit operation in O32. */
104 # define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
105 (abort (), 0)
106 # define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
107 (abort (), (typeof(*mem)) 0)
108 #else
109 # define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
110 __arch_compare_and_exchange_bool_32_int (mem, newval, oldval, model)
111 # define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
112 __arch_compare_and_exchange_val_32_int (mem, newval, oldval, model)
113 #endif
114
115 /* Compare and exchange with "acquire" semantics, ie barrier after. */
116
117 #define atomic_compare_and_exchange_bool_acq(mem, new, old) \
118 __atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
119 mem, new, old, __ATOMIC_ACQUIRE)
120
121 #define atomic_compare_and_exchange_val_acq(mem, new, old) \
122 __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
123 mem, new, old, __ATOMIC_ACQUIRE)
124
125 /* Compare and exchange with "release" semantics, ie barrier before. */
126
127 #define atomic_compare_and_exchange_val_rel(mem, new, old) \
128 __atomic_val_bysize (__arch_compare_and_exchange_val, int, \
129 mem, new, old, __ATOMIC_RELEASE)
130
131
132 /* Atomic exchange (without compare). */
133
134 #define __arch_exchange_8_int(mem, newval, model) \
135 (abort (), (typeof(*mem)) 0)
136
137 #define __arch_exchange_16_int(mem, newval, model) \
138 (abort (), (typeof(*mem)) 0)
139
140 #define __arch_exchange_32_int(mem, newval, model) \
141 __atomic_exchange_n (mem, newval, model)
142
143 #if _MIPS_SIM == _ABIO32
144 /* We can't do an atomic 64-bit operation in O32. */
145 # define __arch_exchange_64_int(mem, newval, model) \
146 (abort (), (typeof(*mem)) 0)
147 #else
148 # define __arch_exchange_64_int(mem, newval, model) \
149 __atomic_exchange_n (mem, newval, model)
150 #endif
151
152 #define atomic_exchange_acq(mem, value) \
153 __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
154
155 #define atomic_exchange_rel(mem, value) \
156 __atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
157
158
159 /* Atomically add value and return the previous (unincremented) value. */
160
161 #define __arch_exchange_and_add_8_int(mem, value, model) \
162 (abort (), (typeof(*mem)) 0)
163
164 #define __arch_exchange_and_add_16_int(mem, value, model) \
165 (abort (), (typeof(*mem)) 0)
166
167 #define __arch_exchange_and_add_32_int(mem, value, model) \
168 __atomic_fetch_add (mem, value, model)
169
170 #if _MIPS_SIM == _ABIO32
171 /* We can't do an atomic 64-bit operation in O32. */
172 # define __arch_exchange_and_add_64_int(mem, value, model) \
173 (abort (), (typeof(*mem)) 0)
174 #else
175 # define __arch_exchange_and_add_64_int(mem, value, model) \
176 __atomic_fetch_add (mem, value, model)
177 #endif
178
179 #define atomic_exchange_and_add_acq(mem, value) \
180 __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
181 __ATOMIC_ACQUIRE)
182
183 #define atomic_exchange_and_add_rel(mem, value) \
184 __atomic_val_bysize (__arch_exchange_and_add, int, mem, value, \
185 __ATOMIC_RELEASE)
186
187 /* TODO: More atomic operations could be implemented efficiently; only the
188 basic requirements are done. */
189
190 #ifdef __mips16
191 # define atomic_full_barrier() __sync_synchronize ()
192
193 #else /* !__mips16 */
194 # define atomic_full_barrier() \
195 __asm__ __volatile__ (".set push\n\t" \
196 MIPS_PUSH_MIPS2 \
197 MIPS_SYNC_STR "\n\t" \
198 ".set pop" : : : "memory")
199 #endif /* !__mips16 */
200
201 #endif /* atomic-machine.h */