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kvm uapi: Add KICK_CPU and PV_UNHALT definition to uapi
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
42bdf991
MT		 558static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
559{
560 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561 !vcpu->guest_xcr0_loaded) {
562 /* kvm_set_xcr() also depends on this */
563 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564 vcpu->guest_xcr0_loaded = 1;
565 }
566}
567
568static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
569{
570 if (vcpu->guest_xcr0_loaded) {
571 if (vcpu->arch.xcr0 != host_xcr0)
572 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573 vcpu->guest_xcr0_loaded = 0;
574 }
575}
576
2acf923e
DC		 577int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
578{
579 u64 xcr0;
580
581 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
582 if (index != XCR_XFEATURE_ENABLED_MASK)
583 return 1;
584 xcr0 = xcr;
2acf923e
DC		 585 if (!(xcr0 & XSTATE_FP))
586 return 1;
587 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
588 return 1;
589 if (xcr0 & ~host_xcr0)
590 return 1;
42bdf991 591 kvm_put_guest_xcr0(vcpu);
2acf923e 592 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 593 return 0;
594}
595
596int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
764bcbc5
Z		 598 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
599 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 600 kvm_inject_gp(vcpu, 0);
601 return 1;
602 }
603 return 0;
604}
605EXPORT_SYMBOL_GPL(kvm_set_xcr);
606
a83b29c6 607int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 608{
fc78f519 609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 612 if (cr4 & CR4_RESERVED_BITS)
613 return 1;
a03490ed 614
2acf923e
DC		 615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
616 return 1;
617
c68b734f
YW		 618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
619 return 1;
620
afcbf13f 621 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 622 return 1;
623
a03490ed 624 if (is_long_mode(vcpu)) {
0f12244f
GN		 625 if (!(cr4 & X86_CR4_PAE))
626 return 1;
a2edf57f
AK		 627 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
628 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 629 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
630 kvm_read_cr3(vcpu)))
0f12244f
GN		 631 return 1;
632
ad756a16
MJ		 633 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
634 if (!guest_cpuid_has_pcid(vcpu))
635 return 1;
636
637 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
638 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
639 return 1;
640 }
641
5e1746d6 642 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 643 return 1;
a03490ed 644
ad756a16
MJ		 645 if (((cr4 ^ old_cr4) & pdptr_bits) ||
646 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 647 kvm_mmu_reset_context(vcpu);
0f12244f 648
2acf923e 649 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 650 kvm_update_cpuid(vcpu);
2acf923e 651
0f12244f
GN		 652 return 0;
653}
2d3ad1f4 654EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 655
2390218b 656int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 657{
9f8fe504 658 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 659 kvm_mmu_sync_roots(vcpu);
d835dfec 660 kvm_mmu_flush_tlb(vcpu);
0f12244f 661 return 0;
d835dfec
AK		 662 }
663
a03490ed 664 if (is_long_mode(vcpu)) {
471842ec 665 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 666 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
667 return 1;
668 } else
669 if (cr3 & CR3_L_MODE_RESERVED_BITS)
670 return 1;
a03490ed
CO		 671 } else {
672 if (is_pae(vcpu)) {
0f12244f
GN		 673 if (cr3 & CR3_PAE_RESERVED_BITS)
674 return 1;
ff03a073
JR		 675 if (is_paging(vcpu) &&
676 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 677 return 1;
a03490ed
CO		 678 }
679 /*
680 * We don't check reserved bits in nonpae mode, because
681 * this isn't enforced, and VMware depends on this.
682 */
683 }
684
0f12244f 685 vcpu->arch.cr3 = cr3;
aff48baa 686 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 687 vcpu->arch.mmu.new_cr3(vcpu);
688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 691
eea1cff9 692int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 693{
0f12244f
GN		 694 if (cr8 & CR8_RESERVED_BITS)
695 return 1;
a03490ed
CO		 696 if (irqchip_in_kernel(vcpu->kvm))
697 kvm_lapic_set_tpr(vcpu, cr8);
698 else
ad312c7c 699 vcpu->arch.cr8 = cr8;
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 703
2d3ad1f4 704unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 705{
706 if (irqchip_in_kernel(vcpu->kvm))
707 return kvm_lapic_get_cr8(vcpu);
708 else
ad312c7c 709 return vcpu->arch.cr8;
a03490ed 710}
2d3ad1f4 711EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 712
c8639010
JK		 713static void kvm_update_dr7(struct kvm_vcpu *vcpu)
714{
715 unsigned long dr7;
716
717 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
718 dr7 = vcpu->arch.guest_debug_dr7;
719 else
720 dr7 = vcpu->arch.dr7;
721 kvm_x86_ops->set_dr7(vcpu, dr7);
722 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
723}
724
338dbc97 725static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 726{
727 switch (dr) {
728 case 0 ... 3:
729 vcpu->arch.db[dr] = val;
730 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
731 vcpu->arch.eff_db[dr] = val;
732 break;
733 case 4:
338dbc97
GN		 734 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
735 return 1; /* #UD */
020df079
GN		 736 /* fall through */
737 case 6:
338dbc97
GN		 738 if (val & 0xffffffff00000000ULL)
739 return -1; /* #GP */
020df079
GN		 740 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
741 break;
742 case 5:
338dbc97
GN		 743 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
744 return 1; /* #UD */
020df079
GN		 745 /* fall through */
746 default: /* 7 */
338dbc97
GN		 747 if (val & 0xffffffff00000000ULL)
748 return -1; /* #GP */
020df079 749 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 750 kvm_update_dr7(vcpu);
020df079
GN		 751 break;
752 }
753
754 return 0;
755}
338dbc97
GN		 756
757int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
758{
759 int res;
760
761 res = __kvm_set_dr(vcpu, dr, val);
762 if (res > 0)
763 kvm_queue_exception(vcpu, UD_VECTOR);
764 else if (res < 0)
765 kvm_inject_gp(vcpu, 0);
766
767 return res;
768}
020df079
GN		 769EXPORT_SYMBOL_GPL(kvm_set_dr);
770
338dbc97 771static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 772{
773 switch (dr) {
774 case 0 ... 3:
775 *val = vcpu->arch.db[dr];
776 break;
777 case 4:
338dbc97 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 779 return 1;
020df079
GN		 780 /* fall through */
781 case 6:
782 *val = vcpu->arch.dr6;
783 break;
784 case 5:
338dbc97 785 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 786 return 1;
020df079
GN		 787 /* fall through */
788 default: /* 7 */
789 *val = vcpu->arch.dr7;
790 break;
791 }
792
793 return 0;
794}
338dbc97
GN		 795
796int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
797{
798 if (_kvm_get_dr(vcpu, dr, val)) {
799 kvm_queue_exception(vcpu, UD_VECTOR);
800 return 1;
801 }
802 return 0;
803}
020df079
GN		 804EXPORT_SYMBOL_GPL(kvm_get_dr);
805
022cd0e8
AK		 806bool kvm_rdpmc(struct kvm_vcpu *vcpu)
807{
808 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
809 u64 data;
810 int err;
811
812 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
813 if (err)
814 return err;
815 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
816 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
817 return err;
818}
819EXPORT_SYMBOL_GPL(kvm_rdpmc);
820
043405e1
CO		 821/*
822 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
823 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
824 *
825 * This list is modified at module load time to reflect the
e3267cbb
GC		 826 * capabilities of the host cpu. This capabilities test skips MSRs that are
827 * kvm-specific. Those are put in the beginning of the list.
043405e1 828 */
e3267cbb 829
439793d4 830#define KVM_SAVE_MSRS_BEGIN 10
043405e1 831static u32 msrs_to_save[] = {
e3267cbb 832 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 833 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 834 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 835 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 836 MSR_KVM_PV_EOI_EN,
043405e1 837 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 838 MSR_STAR,
043405e1
CO		 839#ifdef CONFIG_X86_64
840 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
841#endif
b3897a49
NHE		 842 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
843 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 844};
845
846static unsigned num_msrs_to_save;
847
f1d24831 848static const u32 emulated_msrs[] = {
ba904635 849 MSR_IA32_TSC_ADJUST,
a3e06bbe 850 MSR_IA32_TSCDEADLINE,
043405e1 851 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 852 MSR_IA32_MCG_STATUS,
853 MSR_IA32_MCG_CTL,
043405e1
CO		 854};
855
384bb783 856bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 857{
b69e8cae 858 if (efer & efer_reserved_bits)
384bb783 859 return false;
15c4a640 860
1b2fd70c
AG		 861 if (efer & EFER_FFXSR) {
862 struct kvm_cpuid_entry2 *feat;
863
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 865 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 866 return false;
1b2fd70c
AG		 867 }
868
d8017474
AG		 869 if (efer & EFER_SVME) {
870 struct kvm_cpuid_entry2 *feat;
871
872 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 873 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 874 return false;
d8017474
AG		 875 }
876
384bb783
JK		 877 return true;
878}
879EXPORT_SYMBOL_GPL(kvm_valid_efer);
880
881static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
882{
883 u64 old_efer = vcpu->arch.efer;
884
885 if (!kvm_valid_efer(vcpu, efer))
886 return 1;
887
888 if (is_paging(vcpu)
889 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
890 return 1;
891
15c4a640 892 efer &= ~EFER_LMA;
f6801dff 893 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 894
a3d204e2
SY		 895 kvm_x86_ops->set_efer(vcpu, efer);
896
aad82703
SY		 897 /* Update reserved bits */
898 if ((efer ^ old_efer) & EFER_NX)
899 kvm_mmu_reset_context(vcpu);
900
b69e8cae 901 return 0;
15c4a640
CO		 902}
903
f2b4b7dd
JR		 904void kvm_enable_efer_bits(u64 mask)
905{
906 efer_reserved_bits &= ~mask;
907}
908EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
909
910
15c4a640
CO		 911/*
912 * Writes msr value into into the appropriate "register".
913 * Returns 0 on success, non-0 otherwise.
914 * Assumes vcpu_load() was already called.
915 */
8fe8ab46 916int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 917{
8fe8ab46 918 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 919}
920
313a3dc7
CO		 921/*
922 * Adapt set_msr() to msr_io()'s calling convention
923 */
924static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
925{
8fe8ab46
WA		 926 struct msr_data msr;
927
928 msr.data = *data;
929 msr.index = index;
930 msr.host_initiated = true;
931 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 932}
933
16e8d74d
MT		 934#ifdef CONFIG_X86_64
935struct pvclock_gtod_data {
936 seqcount_t seq;
937
938 struct { /* extract of a clocksource struct */
939 int vclock_mode;
940 cycle_t cycle_last;
941 cycle_t mask;
942 u32 mult;
943 u32 shift;
944 } clock;
945
946 /* open coded 'struct timespec' */
947 u64 monotonic_time_snsec;
948 time_t monotonic_time_sec;
949};
950
951static struct pvclock_gtod_data pvclock_gtod_data;
952
953static void update_pvclock_gtod(struct timekeeper *tk)
954{
955 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
956
957 write_seqcount_begin(&vdata->seq);
958
959 /* copy pvclock gtod data */
960 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
961 vdata->clock.cycle_last = tk->clock->cycle_last;
962 vdata->clock.mask = tk->clock->mask;
963 vdata->clock.mult = tk->mult;
964 vdata->clock.shift = tk->shift;
965
966 vdata->monotonic_time_sec = tk->xtime_sec
967 + tk->wall_to_monotonic.tv_sec;
968 vdata->monotonic_time_snsec = tk->xtime_nsec
969 + (tk->wall_to_monotonic.tv_nsec
970 << tk->shift);
971 while (vdata->monotonic_time_snsec >=
972 (((u64)NSEC_PER_SEC) << tk->shift)) {
973 vdata->monotonic_time_snsec -=
974 ((u64)NSEC_PER_SEC) << tk->shift;
975 vdata->monotonic_time_sec++;
976 }
977
978 write_seqcount_end(&vdata->seq);
979}
980#endif
981
982
18068523
GOC		 983static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
984{
9ed3c444
AK		 985 int version;
986 int r;
50d0a0f9 987 struct pvclock_wall_clock wc;
923de3cf 988 struct timespec boot;
18068523
GOC		 989
990 if (!wall_clock)
991 return;
992
9ed3c444
AK		 993 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
994 if (r)
995 return;
996
997 if (version & 1)
998 ++version; /* first time write, random junk */
999
1000 ++version;
18068523 1001
18068523
GOC		 1002 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1003
50d0a0f9
GH		 1004 /*
1005 * The guest calculates current wall clock time by adding
34c238a1 1006 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1007 * wall clock specified here. guest system time equals host
1008 * system time for us, thus we must fill in host boot time here.
1009 */
923de3cf 1010 getboottime(&boot);
50d0a0f9 1011
4b648665
BR		 1012 if (kvm->arch.kvmclock_offset) {
1013 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1014 boot = timespec_sub(boot, ts);
1015 }
50d0a0f9
GH		 1016 wc.sec = boot.tv_sec;
1017 wc.nsec = boot.tv_nsec;
1018 wc.version = version;
18068523
GOC		 1019
1020 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1021
1022 version++;
1023 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1024}
1025
50d0a0f9
GH		 1026static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1027{
1028 uint32_t quotient, remainder;
1029
1030 /* Don't try to replace with do_div(), this one calculates
1031 * "(dividend << 32) / divisor" */
1032 __asm__ ( "divl %4"
1033 : "=a" (quotient), "=d" (remainder)
1034 : "0" (0), "1" (dividend), "r" (divisor) );
1035 return quotient;
1036}
1037
5f4e3f88
ZA		 1038static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1039 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1040{
5f4e3f88 1041 uint64_t scaled64;
50d0a0f9
GH		 1042 int32_t shift = 0;
1043 uint64_t tps64;
1044 uint32_t tps32;
1045
5f4e3f88
ZA		 1046 tps64 = base_khz * 1000LL;
1047 scaled64 = scaled_khz * 1000LL;
50933623 1048 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1049 tps64 >>= 1;
1050 shift--;
1051 }
1052
1053 tps32 = (uint32_t)tps64;
50933623
JK		 1054 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1055 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1056 scaled64 >>= 1;
1057 else
1058 tps32 <<= 1;
50d0a0f9
GH		 1059 shift++;
1060 }
1061
5f4e3f88
ZA		 1062 *pshift = shift;
1063 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1064
5f4e3f88
ZA		 1065 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1066 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1067}
1068
759379dd
ZA		 1069static inline u64 get_kernel_ns(void)
1070{
1071 struct timespec ts;
1072
1073 WARN_ON(preemptible());
1074 ktime_get_ts(&ts);
1075 monotonic_to_bootbased(&ts);
1076 return timespec_to_ns(&ts);
50d0a0f9
GH		 1077}
1078
d828199e 1079#ifdef CONFIG_X86_64
16e8d74d 1080static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1081#endif
16e8d74d 1082
c8076604 1083static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1084unsigned long max_tsc_khz;
c8076604 1085
cc578287 1086static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1087{
cc578287
ZA		 1088 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1089 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1090}
1091
cc578287 1092static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1093{
cc578287
ZA		 1094 u64 v = (u64)khz * (1000000 + ppm);
1095 do_div(v, 1000000);
1096 return v;
1e993611
JR		 1097}
1098
cc578287 1099static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1100{
cc578287
ZA		 1101 u32 thresh_lo, thresh_hi;
1102 int use_scaling = 0;
217fc9cf 1103
03ba32ca
MT		 1104 /* tsc_khz can be zero if TSC calibration fails */
1105 if (this_tsc_khz == 0)
1106 return;
1107
c285545f
ZA		 1108 /* Compute a scale to convert nanoseconds in TSC cycles */
1109 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1110 &vcpu->arch.virtual_tsc_shift,
1111 &vcpu->arch.virtual_tsc_mult);
1112 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1113
1114 /*
1115 * Compute the variation in TSC rate which is acceptable
1116 * within the range of tolerance and decide if the
1117 * rate being applied is within that bounds of the hardware
1118 * rate. If so, no scaling or compensation need be done.
1119 */
1120 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1121 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1122 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1123 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1124 use_scaling = 1;
1125 }
1126 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1127}
1128
1129static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1130{
e26101b1 1131 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1132 vcpu->arch.virtual_tsc_mult,
1133 vcpu->arch.virtual_tsc_shift);
e26101b1 1134 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1135 return tsc;
1136}
1137
b48aa97e
MT		 1138void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1139{
1140#ifdef CONFIG_X86_64
1141 bool vcpus_matched;
1142 bool do_request = false;
1143 struct kvm_arch *ka = &vcpu->kvm->arch;
1144 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1145
1146 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1147 atomic_read(&vcpu->kvm->online_vcpus));
1148
1149 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1150 if (!ka->use_master_clock)
1151 do_request = 1;
1152
1153 if (!vcpus_matched && ka->use_master_clock)
1154 do_request = 1;
1155
1156 if (do_request)
1157 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1158
1159 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1160 atomic_read(&vcpu->kvm->online_vcpus),
1161 ka->use_master_clock, gtod->clock.vclock_mode);
1162#endif
1163}
1164
ba904635
WA		 1165static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1166{
1167 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1168 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1169}
1170
8fe8ab46 1171void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1172{
1173 struct kvm *kvm = vcpu->kvm;
f38e098f 1174 u64 offset, ns, elapsed;
99e3e30a 1175 unsigned long flags;
02626b6a 1176 s64 usdiff;
b48aa97e 1177 bool matched;
8fe8ab46 1178 u64 data = msr->data;
99e3e30a 1179
038f8c11 1180 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1181 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1182 ns = get_kernel_ns();
f38e098f 1183 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1184
03ba32ca 1185 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1186 int faulted = 0;
1187
03ba32ca
MT		 1188 /* n.b - signed multiplication and division required */
1189 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1190#ifdef CONFIG_X86_64
03ba32ca 1191 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1192#else
03ba32ca 1193 /* do_div() only does unsigned */
8915aa27
MT		 1194 asm("1: idivl %[divisor]\n"
1195 "2: xor %%edx, %%edx\n"
1196 " movl $0, %[faulted]\n"
1197 "3:\n"
1198 ".section .fixup,\"ax\"\n"
1199 "4: movl $1, %[faulted]\n"
1200 " jmp 3b\n"
1201 ".previous\n"
1202
1203 _ASM_EXTABLE(1b, 4b)
1204
1205 : "=A"(usdiff), [faulted] "=r" (faulted)
1206 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1207
5d3cb0f6 1208#endif
03ba32ca
MT		 1209 do_div(elapsed, 1000);
1210 usdiff -= elapsed;
1211 if (usdiff < 0)
1212 usdiff = -usdiff;
8915aa27
MT		 1213
1214 /* idivl overflow => difference is larger than USEC_PER_SEC */
1215 if (faulted)
1216 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1217 } else
1218 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1219
1220 /*
5d3cb0f6
ZA		 1221 * Special case: TSC write with a small delta (1 second) of virtual
1222 * cycle time against real time is interpreted as an attempt to
1223 * synchronize the CPU.
1224 *
1225 * For a reliable TSC, we can match TSC offsets, and for an unstable
1226 * TSC, we add elapsed time in this computation. We could let the
1227 * compensation code attempt to catch up if we fall behind, but
1228 * it's better to try to match offsets from the beginning.
1229 */
02626b6a 1230 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1231 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1232 if (!check_tsc_unstable()) {
e26101b1 1233 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1234 pr_debug("kvm: matched tsc offset for %llu\n", data);
1235 } else {
857e4099 1236 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1237 data += delta;
1238 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1239 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1240 }
b48aa97e 1241 matched = true;
e26101b1
ZA		 1242 } else {
1243 /*
1244 * We split periods of matched TSC writes into generations.
1245 * For each generation, we track the original measured
1246 * nanosecond time, offset, and write, so if TSCs are in
1247 * sync, we can match exact offset, and if not, we can match
4a969980 1248 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1249 *
1250 * These values are tracked in kvm->arch.cur_xxx variables.
1251 */
1252 kvm->arch.cur_tsc_generation++;
1253 kvm->arch.cur_tsc_nsec = ns;
1254 kvm->arch.cur_tsc_write = data;
1255 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1256 matched = false;
e26101b1
ZA		 1257 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1258 kvm->arch.cur_tsc_generation, data);
f38e098f 1259 }
e26101b1
ZA		 1260
1261 /*
1262 * We also track th most recent recorded KHZ, write and time to
1263 * allow the matching interval to be extended at each write.
1264 */
f38e098f
ZA		 1265 kvm->arch.last_tsc_nsec = ns;
1266 kvm->arch.last_tsc_write = data;
5d3cb0f6 1267 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1268
1269 /* Reset of TSC must disable overshoot protection below */
1270 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1271 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1272
1273 /* Keep track of which generation this VCPU has synchronized to */
1274 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1275 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1276 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1277
ba904635
WA		 1278 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1279 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1280 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1281 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1282
1283 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1284 if (matched)
1285 kvm->arch.nr_vcpus_matched_tsc++;
1286 else
1287 kvm->arch.nr_vcpus_matched_tsc = 0;
1288
1289 kvm_track_tsc_matching(vcpu);
1290 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1291}
e26101b1 1292
99e3e30a
ZA		 1293EXPORT_SYMBOL_GPL(kvm_write_tsc);
1294
d828199e
MT		 1295#ifdef CONFIG_X86_64
1296
1297static cycle_t read_tsc(void)
1298{
1299 cycle_t ret;
1300 u64 last;
1301
1302 /*
1303 * Empirically, a fence (of type that depends on the CPU)
1304 * before rdtsc is enough to ensure that rdtsc is ordered
1305 * with respect to loads. The various CPU manuals are unclear
1306 * as to whether rdtsc can be reordered with later loads,
1307 * but no one has ever seen it happen.
1308 */
1309 rdtsc_barrier();
1310 ret = (cycle_t)vget_cycles();
1311
1312 last = pvclock_gtod_data.clock.cycle_last;
1313
1314 if (likely(ret >= last))
1315 return ret;
1316
1317 /*
1318 * GCC likes to generate cmov here, but this branch is extremely
1319 * predictable (it's just a funciton of time and the likely is
1320 * very likely) and there's a data dependence, so force GCC
1321 * to generate a branch instead. I don't barrier() because
1322 * we don't actually need a barrier, and if this function
1323 * ever gets inlined it will generate worse code.
1324 */
1325 asm volatile ("");
1326 return last;
1327}
1328
1329static inline u64 vgettsc(cycle_t *cycle_now)
1330{
1331 long v;
1332 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1333
1334 *cycle_now = read_tsc();
1335
1336 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1337 return v * gtod->clock.mult;
1338}
1339
1340static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1341{
1342 unsigned long seq;
1343 u64 ns;
1344 int mode;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 ts->tv_nsec = 0;
1348 do {
1349 seq = read_seqcount_begin(&gtod->seq);
1350 mode = gtod->clock.vclock_mode;
1351 ts->tv_sec = gtod->monotonic_time_sec;
1352 ns = gtod->monotonic_time_snsec;
1353 ns += vgettsc(cycle_now);
1354 ns >>= gtod->clock.shift;
1355 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1356 timespec_add_ns(ts, ns);
1357
1358 return mode;
1359}
1360
1361/* returns true if host is using tsc clocksource */
1362static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1363{
1364 struct timespec ts;
1365
1366 /* checked again under seqlock below */
1367 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1368 return false;
1369
1370 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1371 return false;
1372
1373 monotonic_to_bootbased(&ts);
1374 *kernel_ns = timespec_to_ns(&ts);
1375
1376 return true;
1377}
1378#endif
1379
1380/*
1381 *
b48aa97e
MT		 1382 * Assuming a stable TSC across physical CPUS, and a stable TSC
1383 * across virtual CPUs, the following condition is possible.
1384 * Each numbered line represents an event visible to both
d828199e
MT		 1385 * CPUs at the next numbered event.
1386 *
1387 * "timespecX" represents host monotonic time. "tscX" represents
1388 * RDTSC value.
1389 *
1390 * VCPU0 on CPU0 | VCPU1 on CPU1
1391 *
1392 * 1. read timespec0,tsc0
1393 * 2. | timespec1 = timespec0 + N
1394 * | tsc1 = tsc0 + M
1395 * 3. transition to guest | transition to guest
1396 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1397 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1398 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1399 *
1400 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1401 *
1402 * - ret0 < ret1
1403 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1404 * ...
1405 * - 0 < N - M => M < N
1406 *
1407 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1408 * always the case (the difference between two distinct xtime instances
1409 * might be smaller then the difference between corresponding TSC reads,
1410 * when updating guest vcpus pvclock areas).
1411 *
1412 * To avoid that problem, do not allow visibility of distinct
1413 * system_timestamp/tsc_timestamp values simultaneously: use a master
1414 * copy of host monotonic time values. Update that master copy
1415 * in lockstep.
1416 *
b48aa97e 1417 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1418 *
1419 */
1420
1421static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1422{
1423#ifdef CONFIG_X86_64
1424 struct kvm_arch *ka = &kvm->arch;
1425 int vclock_mode;
b48aa97e
MT		 1426 bool host_tsc_clocksource, vcpus_matched;
1427
1428 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1429 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1430
1431 /*
1432 * If the host uses TSC clock, then passthrough TSC as stable
1433 * to the guest.
1434 */
b48aa97e 1435 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1436 &ka->master_kernel_ns,
1437 &ka->master_cycle_now);
1438
b48aa97e
MT		 1439 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1440
d828199e
MT		 1441 if (ka->use_master_clock)
1442 atomic_set(&kvm_guest_has_master_clock, 1);
1443
1444 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1445 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1446 vcpus_matched);
d828199e
MT		 1447#endif
1448}
1449
34c238a1 1450static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1451{
d828199e 1452 unsigned long flags, this_tsc_khz;
18068523 1453 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1454 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1455 s64 kernel_ns, max_kernel_ns;
d828199e 1456 u64 tsc_timestamp, host_tsc;
0b79459b 1457 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1458 u8 pvclock_flags;
d828199e
MT		 1459 bool use_master_clock;
1460
1461 kernel_ns = 0;
1462 host_tsc = 0;
18068523 1463
d828199e
MT		 1464 /*
1465 * If the host uses TSC clock, then passthrough TSC as stable
1466 * to the guest.
1467 */
1468 spin_lock(&ka->pvclock_gtod_sync_lock);
1469 use_master_clock = ka->use_master_clock;
1470 if (use_master_clock) {
1471 host_tsc = ka->master_cycle_now;
1472 kernel_ns = ka->master_kernel_ns;
1473 }
1474 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1475
1476 /* Keep irq disabled to prevent changes to the clock */
1477 local_irq_save(flags);
1478 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1479 if (unlikely(this_tsc_khz == 0)) {
1480 local_irq_restore(flags);
1481 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1482 return 1;
1483 }
d828199e
MT		 1484 if (!use_master_clock) {
1485 host_tsc = native_read_tsc();
1486 kernel_ns = get_kernel_ns();
1487 }
1488
1489 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1490
c285545f
ZA		 1491 /*
1492 * We may have to catch up the TSC to match elapsed wall clock
1493 * time for two reasons, even if kvmclock is used.
1494 * 1) CPU could have been running below the maximum TSC rate
1495 * 2) Broken TSC compensation resets the base at each VCPU
1496 * entry to avoid unknown leaps of TSC even when running
1497 * again on the same CPU. This may cause apparent elapsed
1498 * time to disappear, and the guest to stand still or run
1499 * very slowly.
1500 */
1501 if (vcpu->tsc_catchup) {
1502 u64 tsc = compute_guest_tsc(v, kernel_ns);
1503 if (tsc > tsc_timestamp) {
f1e2b260 1504 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1505 tsc_timestamp = tsc;
1506 }
50d0a0f9
GH		 1507 }
1508
18068523
GOC		 1509 local_irq_restore(flags);
1510
0b79459b 1511 if (!vcpu->pv_time_enabled)
c285545f 1512 return 0;
18068523 1513
1d5f066e
ZA		 1514 /*
1515 * Time as measured by the TSC may go backwards when resetting the base
1516 * tsc_timestamp. The reason for this is that the TSC resolution is
1517 * higher than the resolution of the other clock scales. Thus, many
1518 * possible measurments of the TSC correspond to one measurement of any
1519 * other clock, and so a spread of values is possible. This is not a
1520 * problem for the computation of the nanosecond clock; with TSC rates
1521 * around 1GHZ, there can only be a few cycles which correspond to one
1522 * nanosecond value, and any path through this code will inevitably
1523 * take longer than that. However, with the kernel_ns value itself,
1524 * the precision may be much lower, down to HZ granularity. If the
1525 * first sampling of TSC against kernel_ns ends in the low part of the
1526 * range, and the second in the high end of the range, we can get:
1527 *
1528 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1529 *
1530 * As the sampling errors potentially range in the thousands of cycles,
1531 * it is possible such a time value has already been observed by the
1532 * guest. To protect against this, we must compute the system time as
1533 * observed by the guest and ensure the new system time is greater.
1534 */
1535 max_kernel_ns = 0;
b183aa58 1536 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1537 max_kernel_ns = vcpu->last_guest_tsc -
1538 vcpu->hv_clock.tsc_timestamp;
1539 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1540 vcpu->hv_clock.tsc_to_system_mul,
1541 vcpu->hv_clock.tsc_shift);
1542 max_kernel_ns += vcpu->last_kernel_ns;
1543 }
afbcf7ab 1544
e48672fa 1545 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1546 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1547 &vcpu->hv_clock.tsc_shift,
1548 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1549 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1550 }
1551
d828199e
MT		 1552 /* with a master <monotonic time, tsc value> tuple,
1553 * pvclock clock reads always increase at the (scaled) rate
1554 * of guest TSC - no need to deal with sampling errors.
1555 */
1556 if (!use_master_clock) {
1557 if (max_kernel_ns > kernel_ns)
1558 kernel_ns = max_kernel_ns;
1559 }
8cfdc000 1560 /* With all the info we got, fill in the values */
1d5f066e 1561 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1562 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1563 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1564 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1565
18068523
GOC		 1566 /*
1567 * The interface expects us to write an even number signaling that the
1568 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1569 * state, we just increase by 2 at the end.
18068523 1570 */
50d0a0f9 1571 vcpu->hv_clock.version += 2;
18068523 1572
0b79459b
AH		 1573 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1574 &guest_hv_clock, sizeof(guest_hv_clock))))
1575 return 0;
78c0337a
MT		 1576
1577 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1578 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1579
1580 if (vcpu->pvclock_set_guest_stopped_request) {
1581 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1582 vcpu->pvclock_set_guest_stopped_request = false;
1583 }
1584
d828199e
MT		 1585 /* If the host uses TSC clocksource, then it is stable */
1586 if (use_master_clock)
1587 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1588
78c0337a
MT		 1589 vcpu->hv_clock.flags = pvclock_flags;
1590
0b79459b
AH		 1591 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1592 &vcpu->hv_clock,
1593 sizeof(vcpu->hv_clock));
8cfdc000 1594 return 0;
c8076604
GH		 1595}
1596
0061d53d
MT		 1597/*
1598 * kvmclock updates which are isolated to a given vcpu, such as
1599 * vcpu->cpu migration, should not allow system_timestamp from
1600 * the rest of the vcpus to remain static. Otherwise ntp frequency
1601 * correction applies to one vcpu's system_timestamp but not
1602 * the others.
1603 *
1604 * So in those cases, request a kvmclock update for all vcpus.
1605 * The worst case for a remote vcpu to update its kvmclock
1606 * is then bounded by maximum nohz sleep latency.
1607 */
1608
1609static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1610{
1611 int i;
1612 struct kvm *kvm = v->kvm;
1613 struct kvm_vcpu *vcpu;
1614
1615 kvm_for_each_vcpu(i, vcpu, kvm) {
1616 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1617 kvm_vcpu_kick(vcpu);
1618 }
1619}
1620
9ba075a6
AK		 1621static bool msr_mtrr_valid(unsigned msr)
1622{
1623 switch (msr) {
1624 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1625 case MSR_MTRRfix64K_00000:
1626 case MSR_MTRRfix16K_80000:
1627 case MSR_MTRRfix16K_A0000:
1628 case MSR_MTRRfix4K_C0000:
1629 case MSR_MTRRfix4K_C8000:
1630 case MSR_MTRRfix4K_D0000:
1631 case MSR_MTRRfix4K_D8000:
1632 case MSR_MTRRfix4K_E0000:
1633 case MSR_MTRRfix4K_E8000:
1634 case MSR_MTRRfix4K_F0000:
1635 case MSR_MTRRfix4K_F8000:
1636 case MSR_MTRRdefType:
1637 case MSR_IA32_CR_PAT:
1638 return true;
1639 case 0x2f8:
1640 return true;
1641 }
1642 return false;
1643}
1644
d6289b93
MT		 1645static bool valid_pat_type(unsigned t)
1646{
1647 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1648}
1649
1650static bool valid_mtrr_type(unsigned t)
1651{
1652 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1653}
1654
1655static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1656{
1657 int i;
1658
1659 if (!msr_mtrr_valid(msr))
1660 return false;
1661
1662 if (msr == MSR_IA32_CR_PAT) {
1663 for (i = 0; i < 8; i++)
1664 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1665 return false;
1666 return true;
1667 } else if (msr == MSR_MTRRdefType) {
1668 if (data & ~0xcff)
1669 return false;
1670 return valid_mtrr_type(data & 0xff);
1671 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1672 for (i = 0; i < 8 ; i++)
1673 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1674 return false;
1675 return true;
1676 }
1677
1678 /* variable MTRRs */
1679 return valid_mtrr_type(data & 0xff);
1680}
1681
9ba075a6
AK		 1682static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1683{
0bed3b56
SY		 1684 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1685
d6289b93 1686 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1687 return 1;
1688
0bed3b56
SY		 1689 if (msr == MSR_MTRRdefType) {
1690 vcpu->arch.mtrr_state.def_type = data;
1691 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1692 } else if (msr == MSR_MTRRfix64K_00000)
1693 p[0] = data;
1694 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1695 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1696 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1697 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1698 else if (msr == MSR_IA32_CR_PAT)
1699 vcpu->arch.pat = data;
1700 else { /* Variable MTRRs */
1701 int idx, is_mtrr_mask;
1702 u64 *pt;
1703
1704 idx = (msr - 0x200) / 2;
1705 is_mtrr_mask = msr - 0x200 - 2 * idx;
1706 if (!is_mtrr_mask)
1707 pt =
1708 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1709 else
1710 pt =
1711 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1712 *pt = data;
1713 }
1714
1715 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1716 return 0;
1717}
15c4a640 1718
890ca9ae 1719static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1720{
890ca9ae
HY		 1721 u64 mcg_cap = vcpu->arch.mcg_cap;
1722 unsigned bank_num = mcg_cap & 0xff;
1723
15c4a640 1724 switch (msr) {
15c4a640 1725 case MSR_IA32_MCG_STATUS:
890ca9ae 1726 vcpu->arch.mcg_status = data;
15c4a640 1727 break;
c7ac679c 1728 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1729 if (!(mcg_cap & MCG_CTL_P))
1730 return 1;
1731 if (data != 0 && data != ~(u64)0)
1732 return -1;
1733 vcpu->arch.mcg_ctl = data;
1734 break;
1735 default:
1736 if (msr >= MSR_IA32_MC0_CTL &&
1737 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1738 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1739 /* only 0 or all 1s can be written to IA32_MCi_CTL
1740 * some Linux kernels though clear bit 10 in bank 4 to
1741 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1742 * this to avoid an uncatched #GP in the guest
1743 */
890ca9ae 1744 if ((offset & 0x3) == 0 &&
114be429 1745 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1746 return -1;
1747 vcpu->arch.mce_banks[offset] = data;
1748 break;
1749 }
1750 return 1;
1751 }
1752 return 0;
1753}
1754
ffde22ac
ES		 1755static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1756{
1757 struct kvm *kvm = vcpu->kvm;
1758 int lm = is_long_mode(vcpu);
1759 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1760 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1761 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1762 : kvm->arch.xen_hvm_config.blob_size_32;
1763 u32 page_num = data & ~PAGE_MASK;
1764 u64 page_addr = data & PAGE_MASK;
1765 u8 *page;
1766 int r;
1767
1768 r = -E2BIG;
1769 if (page_num >= blob_size)
1770 goto out;
1771 r = -ENOMEM;
ff5c2c03
SL		 1772 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1773 if (IS_ERR(page)) {
1774 r = PTR_ERR(page);
ffde22ac 1775 goto out;
ff5c2c03 1776 }
ffde22ac
ES		 1777 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1778 goto out_free;
1779 r = 0;
1780out_free:
1781 kfree(page);
1782out:
1783 return r;
1784}
1785
55cd8e5a
GN		 1786static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1787{
1788 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1789}
1790
1791static bool kvm_hv_msr_partition_wide(u32 msr)
1792{
1793 bool r = false;
1794 switch (msr) {
1795 case HV_X64_MSR_GUEST_OS_ID:
1796 case HV_X64_MSR_HYPERCALL:
1797 r = true;
1798 break;
1799 }
1800
1801 return r;
1802}
1803
1804static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1805{
1806 struct kvm *kvm = vcpu->kvm;
1807
1808 switch (msr) {
1809 case HV_X64_MSR_GUEST_OS_ID:
1810 kvm->arch.hv_guest_os_id = data;
1811 /* setting guest os id to zero disables hypercall page */
1812 if (!kvm->arch.hv_guest_os_id)
1813 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1814 break;
1815 case HV_X64_MSR_HYPERCALL: {
1816 u64 gfn;
1817 unsigned long addr;
1818 u8 instructions[4];
1819
1820 /* if guest os id is not set hypercall should remain disabled */
1821 if (!kvm->arch.hv_guest_os_id)
1822 break;
1823 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1824 kvm->arch.hv_hypercall = data;
1825 break;
1826 }
1827 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1828 addr = gfn_to_hva(kvm, gfn);
1829 if (kvm_is_error_hva(addr))
1830 return 1;
1831 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1832 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1833 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1834 return 1;
1835 kvm->arch.hv_hypercall = data;
1836 break;
1837 }
1838 default:
a737f256
CD		 1839 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1840 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1841 return 1;
1842 }
1843 return 0;
1844}
1845
1846static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1847{
10388a07
GN		 1848 switch (msr) {
1849 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1850 unsigned long addr;
55cd8e5a 1851
10388a07
GN		 1852 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1853 vcpu->arch.hv_vapic = data;
1854 break;
1855 }
1856 addr = gfn_to_hva(vcpu->kvm, data >>
1857 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1858 if (kvm_is_error_hva(addr))
1859 return 1;
8b0cedff 1860 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1861 return 1;
1862 vcpu->arch.hv_vapic = data;
1863 break;
1864 }
1865 case HV_X64_MSR_EOI:
1866 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1867 case HV_X64_MSR_ICR:
1868 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1869 case HV_X64_MSR_TPR:
1870 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1871 default:
a737f256
CD		 1872 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1873 "data 0x%llx\n", msr, data);
10388a07
GN		 1874 return 1;
1875 }
1876
1877 return 0;
55cd8e5a
GN		 1878}
1879
344d9588
GN		 1880static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1881{
1882 gpa_t gpa = data & ~0x3f;
1883
4a969980 1884 /* Bits 2:5 are reserved, Should be zero */
6adba527 1885 if (data & 0x3c)
344d9588
GN		 1886 return 1;
1887
1888 vcpu->arch.apf.msr_val = data;
1889
1890 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1891 kvm_clear_async_pf_completion_queue(vcpu);
1892 kvm_async_pf_hash_reset(vcpu);
1893 return 0;
1894 }
1895
8f964525
AH		 1896 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1897 sizeof(u32)))
344d9588
GN		 1898 return 1;
1899
6adba527 1900 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1901 kvm_async_pf_wakeup_all(vcpu);
1902 return 0;
1903}
1904
12f9a48f
GC		 1905static void kvmclock_reset(struct kvm_vcpu *vcpu)
1906{
0b79459b 1907 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1908}
1909
c9aaa895
GC		 1910static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1911{
1912 u64 delta;
1913
1914 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1915 return;
1916
1917 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1918 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1919 vcpu->arch.st.accum_steal = delta;
1920}
1921
1922static void record_steal_time(struct kvm_vcpu *vcpu)
1923{
1924 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1925 return;
1926
1927 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1928 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1929 return;
1930
1931 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1932 vcpu->arch.st.steal.version += 2;
1933 vcpu->arch.st.accum_steal = 0;
1934
1935 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1936 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1937}
1938
8fe8ab46 1939int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1940{
5753785f 1941 bool pr = false;
8fe8ab46
WA		 1942 u32 msr = msr_info->index;
1943 u64 data = msr_info->data;
5753785f 1944
15c4a640 1945 switch (msr) {
2e32b719
BP		 1946 case MSR_AMD64_NB_CFG:
1947 case MSR_IA32_UCODE_REV:
1948 case MSR_IA32_UCODE_WRITE:
1949 case MSR_VM_HSAVE_PA:
1950 case MSR_AMD64_PATCH_LOADER:
1951 case MSR_AMD64_BU_CFG2:
1952 break;
1953
15c4a640 1954 case MSR_EFER:
b69e8cae 1955 return set_efer(vcpu, data);
8f1589d9
AP		 1956 case MSR_K7_HWCR:
1957 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1958 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1959 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1960 if (data != 0) {
a737f256
CD		 1961 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1962 data);
8f1589d9
AP		 1963 return 1;
1964 }
15c4a640 1965 break;
f7c6d140
AP		 1966 case MSR_FAM10H_MMIO_CONF_BASE:
1967 if (data != 0) {
a737f256
CD		 1968 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1969 "0x%llx\n", data);
f7c6d140
AP		 1970 return 1;
1971 }
15c4a640 1972 break;
b5e2fec0
AG		 1973 case MSR_IA32_DEBUGCTLMSR:
1974 if (!data) {
1975 /* We support the non-activated case already */
1976 break;
1977 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1978 /* Values other than LBR and BTF are vendor-specific,
1979 thus reserved and should throw a #GP */
1980 return 1;
1981 }
a737f256
CD		 1982 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1983 __func__, data);
b5e2fec0 1984 break;
9ba075a6
AK		 1985 case 0x200 ... 0x2ff:
1986 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1987 case MSR_IA32_APICBASE:
1988 kvm_set_apic_base(vcpu, data);
1989 break;
0105d1a5
GN		 1990 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1991 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1992 case MSR_IA32_TSCDEADLINE:
1993 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1994 break;
ba904635
WA		 1995 case MSR_IA32_TSC_ADJUST:
1996 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1997 if (!msr_info->host_initiated) {
1998 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1999 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2000 }
2001 vcpu->arch.ia32_tsc_adjust_msr = data;
2002 }
2003 break;
15c4a640 2004 case MSR_IA32_MISC_ENABLE:
ad312c7c 2005 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2006 break;
11c6bffa 2007 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2008 case MSR_KVM_WALL_CLOCK:
2009 vcpu->kvm->arch.wall_clock = data;
2010 kvm_write_wall_clock(vcpu->kvm, data);
2011 break;
11c6bffa 2012 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2013 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2014 u64 gpa_offset;
12f9a48f 2015 kvmclock_reset(vcpu);
18068523
GOC		 2016
2017 vcpu->arch.time = data;
0061d53d 2018 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2019
2020 /* we verify if the enable bit is set... */
2021 if (!(data & 1))
2022 break;
2023
0b79459b 2024 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2025
0b79459b 2026 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2027 &vcpu->arch.pv_time, data & ~1ULL,
2028 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2029 vcpu->arch.pv_time_enabled = false;
2030 else
2031 vcpu->arch.pv_time_enabled = true;
32cad84f 2032
18068523
GOC		 2033 break;
2034 }
344d9588
GN		 2035 case MSR_KVM_ASYNC_PF_EN:
2036 if (kvm_pv_enable_async_pf(vcpu, data))
2037 return 1;
2038 break;
c9aaa895
GC		 2039 case MSR_KVM_STEAL_TIME:
2040
2041 if (unlikely(!sched_info_on()))
2042 return 1;
2043
2044 if (data & KVM_STEAL_RESERVED_MASK)
2045 return 1;
2046
2047 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2048 data & KVM_STEAL_VALID_BITS,
2049 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2050 return 1;
2051
2052 vcpu->arch.st.msr_val = data;
2053
2054 if (!(data & KVM_MSR_ENABLED))
2055 break;
2056
2057 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2058
2059 preempt_disable();
2060 accumulate_steal_time(vcpu);
2061 preempt_enable();
2062
2063 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2064
2065 break;
ae7a2a3f
MT		 2066 case MSR_KVM_PV_EOI_EN:
2067 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2068 return 1;
2069 break;
c9aaa895 2070
890ca9ae
HY		 2071 case MSR_IA32_MCG_CTL:
2072 case MSR_IA32_MCG_STATUS:
2073 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2074 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2075
2076 /* Performance counters are not protected by a CPUID bit,
2077 * so we should check all of them in the generic path for the sake of
2078 * cross vendor migration.
2079 * Writing a zero into the event select MSRs disables them,
2080 * which we perfectly emulate ;-). Any other value should be at least
2081 * reported, some guests depend on them.
2082 */
71db6023
AP		 2083 case MSR_K7_EVNTSEL0:
2084 case MSR_K7_EVNTSEL1:
2085 case MSR_K7_EVNTSEL2:
2086 case MSR_K7_EVNTSEL3:
2087 if (data != 0)
a737f256
CD		 2088 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2089 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2090 break;
2091 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2092 * so we ignore writes to make it happy.
2093 */
71db6023
AP		 2094 case MSR_K7_PERFCTR0:
2095 case MSR_K7_PERFCTR1:
2096 case MSR_K7_PERFCTR2:
2097 case MSR_K7_PERFCTR3:
a737f256
CD		 2098 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2099 "0x%x data 0x%llx\n", msr, data);
71db6023 2100 break;
5753785f
GN		 2101 case MSR_P6_PERFCTR0:
2102 case MSR_P6_PERFCTR1:
2103 pr = true;
2104 case MSR_P6_EVNTSEL0:
2105 case MSR_P6_EVNTSEL1:
2106 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2107 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2108
2109 if (pr || data != 0)
a737f256
CD		 2110 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2111 "0x%x data 0x%llx\n", msr, data);
5753785f 2112 break;
84e0cefa
JS		 2113 case MSR_K7_CLK_CTL:
2114 /*
2115 * Ignore all writes to this no longer documented MSR.
2116 * Writes are only relevant for old K7 processors,
2117 * all pre-dating SVM, but a recommended workaround from
4a969980 2118 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2119 * affected processor models on the command line, hence
2120 * the need to ignore the workaround.
2121 */
2122 break;
55cd8e5a
GN		 2123 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2124 if (kvm_hv_msr_partition_wide(msr)) {
2125 int r;
2126 mutex_lock(&vcpu->kvm->lock);
2127 r = set_msr_hyperv_pw(vcpu, msr, data);
2128 mutex_unlock(&vcpu->kvm->lock);
2129 return r;
2130 } else
2131 return set_msr_hyperv(vcpu, msr, data);
2132 break;
91c9c3ed 2133 case MSR_IA32_BBL_CR_CTL3:
2134 /* Drop writes to this legacy MSR -- see rdmsr
2135 * counterpart for further detail.
2136 */
a737f256 2137 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2138 break;
2b036c6b
BO		 2139 case MSR_AMD64_OSVW_ID_LENGTH:
2140 if (!guest_cpuid_has_osvw(vcpu))
2141 return 1;
2142 vcpu->arch.osvw.length = data;
2143 break;
2144 case MSR_AMD64_OSVW_STATUS:
2145 if (!guest_cpuid_has_osvw(vcpu))
2146 return 1;
2147 vcpu->arch.osvw.status = data;
2148 break;
15c4a640 2149 default:
ffde22ac
ES		 2150 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2151 return xen_hvm_config(vcpu, data);
f5132b01 2152 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2153 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2154 if (!ignore_msrs) {
a737f256
CD		 2155 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2156 msr, data);
ed85c068
AP		 2157 return 1;
2158 } else {
a737f256
CD		 2159 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2160 msr, data);
ed85c068
AP		 2161 break;
2162 }
15c4a640
CO		 2163 }
2164 return 0;
2165}
2166EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2167
2168
2169/*
2170 * Reads an msr value (of 'msr_index') into 'pdata'.
2171 * Returns 0 on success, non-0 otherwise.
2172 * Assumes vcpu_load() was already called.
2173 */
2174int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2175{
2176 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2177}
2178
9ba075a6
AK		 2179static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2180{
0bed3b56
SY		 2181 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2182
9ba075a6
AK		 2183 if (!msr_mtrr_valid(msr))
2184 return 1;
2185
0bed3b56
SY		 2186 if (msr == MSR_MTRRdefType)
2187 *pdata = vcpu->arch.mtrr_state.def_type +
2188 (vcpu->arch.mtrr_state.enabled << 10);
2189 else if (msr == MSR_MTRRfix64K_00000)
2190 *pdata = p[0];
2191 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2192 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2193 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2194 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2195 else if (msr == MSR_IA32_CR_PAT)
2196 *pdata = vcpu->arch.pat;
2197 else { /* Variable MTRRs */
2198 int idx, is_mtrr_mask;
2199 u64 *pt;
2200
2201 idx = (msr - 0x200) / 2;
2202 is_mtrr_mask = msr - 0x200 - 2 * idx;
2203 if (!is_mtrr_mask)
2204 pt =
2205 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2206 else
2207 pt =
2208 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2209 *pdata = *pt;
2210 }
2211
9ba075a6
AK		 2212 return 0;
2213}
2214
890ca9ae 2215static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2216{
2217 u64 data;
890ca9ae
HY		 2218 u64 mcg_cap = vcpu->arch.mcg_cap;
2219 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2220
2221 switch (msr) {
15c4a640
CO		 2222 case MSR_IA32_P5_MC_ADDR:
2223 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2224 data = 0;
2225 break;
15c4a640 2226 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2227 data = vcpu->arch.mcg_cap;
2228 break;
c7ac679c 2229 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2230 if (!(mcg_cap & MCG_CTL_P))
2231 return 1;
2232 data = vcpu->arch.mcg_ctl;
2233 break;
2234 case MSR_IA32_MCG_STATUS:
2235 data = vcpu->arch.mcg_status;
2236 break;
2237 default:
2238 if (msr >= MSR_IA32_MC0_CTL &&
2239 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2240 u32 offset = msr - MSR_IA32_MC0_CTL;
2241 data = vcpu->arch.mce_banks[offset];
2242 break;
2243 }
2244 return 1;
2245 }
2246 *pdata = data;
2247 return 0;
2248}
2249
55cd8e5a
GN		 2250static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2251{
2252 u64 data = 0;
2253 struct kvm *kvm = vcpu->kvm;
2254
2255 switch (msr) {
2256 case HV_X64_MSR_GUEST_OS_ID:
2257 data = kvm->arch.hv_guest_os_id;
2258 break;
2259 case HV_X64_MSR_HYPERCALL:
2260 data = kvm->arch.hv_hypercall;
2261 break;
2262 default:
a737f256 2263 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2264 return 1;
2265 }
2266
2267 *pdata = data;
2268 return 0;
2269}
2270
2271static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2272{
2273 u64 data = 0;
2274
2275 switch (msr) {
2276 case HV_X64_MSR_VP_INDEX: {
2277 int r;
2278 struct kvm_vcpu *v;
2279 kvm_for_each_vcpu(r, v, vcpu->kvm)
2280 if (v == vcpu)
2281 data = r;
2282 break;
2283 }
10388a07
GN		 2284 case HV_X64_MSR_EOI:
2285 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2286 case HV_X64_MSR_ICR:
2287 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2288 case HV_X64_MSR_TPR:
2289 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2290 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2291 data = vcpu->arch.hv_vapic;
2292 break;
55cd8e5a 2293 default:
a737f256 2294 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2295 return 1;
2296 }
2297 *pdata = data;
2298 return 0;
2299}
2300
890ca9ae
HY		 2301int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2302{
2303 u64 data;
2304
2305 switch (msr) {
890ca9ae 2306 case MSR_IA32_PLATFORM_ID:
15c4a640 2307 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2308 case MSR_IA32_DEBUGCTLMSR:
2309 case MSR_IA32_LASTBRANCHFROMIP:
2310 case MSR_IA32_LASTBRANCHTOIP:
2311 case MSR_IA32_LASTINTFROMIP:
2312 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2313 case MSR_K8_SYSCFG:
2314 case MSR_K7_HWCR:
61a6bd67 2315 case MSR_VM_HSAVE_PA:
9e699624 2316 case MSR_K7_EVNTSEL0:
1f3ee616 2317 case MSR_K7_PERFCTR0:
1fdbd48c 2318 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2319 case MSR_AMD64_NB_CFG:
f7c6d140 2320 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2321 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2322 data = 0;
2323 break;
5753785f
GN		 2324 case MSR_P6_PERFCTR0:
2325 case MSR_P6_PERFCTR1:
2326 case MSR_P6_EVNTSEL0:
2327 case MSR_P6_EVNTSEL1:
2328 if (kvm_pmu_msr(vcpu, msr))
2329 return kvm_pmu_get_msr(vcpu, msr, pdata);
2330 data = 0;
2331 break;
742bc670
MT		 2332 case MSR_IA32_UCODE_REV:
2333 data = 0x100000000ULL;
2334 break;
9ba075a6
AK		 2335 case MSR_MTRRcap:
2336 data = 0x500 | KVM_NR_VAR_MTRR;
2337 break;
2338 case 0x200 ... 0x2ff:
2339 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2340 case 0xcd: /* fsb frequency */
2341 data = 3;
2342 break;
7b914098
JS		 2343 /*
2344 * MSR_EBC_FREQUENCY_ID
2345 * Conservative value valid for even the basic CPU models.
2346 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2347 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2348 * and 266MHz for model 3, or 4. Set Core Clock
2349 * Frequency to System Bus Frequency Ratio to 1 (bits
2350 * 31:24) even though these are only valid for CPU
2351 * models > 2, however guests may end up dividing or
2352 * multiplying by zero otherwise.
2353 */
2354 case MSR_EBC_FREQUENCY_ID:
2355 data = 1 << 24;
2356 break;
15c4a640
CO		 2357 case MSR_IA32_APICBASE:
2358 data = kvm_get_apic_base(vcpu);
2359 break;
0105d1a5
GN		 2360 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2361 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2362 break;
a3e06bbe
LJ		 2363 case MSR_IA32_TSCDEADLINE:
2364 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2365 break;
ba904635
WA		 2366 case MSR_IA32_TSC_ADJUST:
2367 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2368 break;
15c4a640 2369 case MSR_IA32_MISC_ENABLE:
ad312c7c 2370 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2371 break;
847f0ad8
AG		 2372 case MSR_IA32_PERF_STATUS:
2373 /* TSC increment by tick */
2374 data = 1000ULL;
2375 /* CPU multiplier */
2376 data |= (((uint64_t)4ULL) << 40);
2377 break;
15c4a640 2378 case MSR_EFER:
f6801dff 2379 data = vcpu->arch.efer;
15c4a640 2380 break;
18068523 2381 case MSR_KVM_WALL_CLOCK:
11c6bffa 2382 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2383 data = vcpu->kvm->arch.wall_clock;
2384 break;
2385 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2386 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2387 data = vcpu->arch.time;
2388 break;
344d9588
GN		 2389 case MSR_KVM_ASYNC_PF_EN:
2390 data = vcpu->arch.apf.msr_val;
2391 break;
c9aaa895
GC		 2392 case MSR_KVM_STEAL_TIME:
2393 data = vcpu->arch.st.msr_val;
2394 break;
1d92128f
MT		 2395 case MSR_KVM_PV_EOI_EN:
2396 data = vcpu->arch.pv_eoi.msr_val;
2397 break;
890ca9ae
HY		 2398 case MSR_IA32_P5_MC_ADDR:
2399 case MSR_IA32_P5_MC_TYPE:
2400 case MSR_IA32_MCG_CAP:
2401 case MSR_IA32_MCG_CTL:
2402 case MSR_IA32_MCG_STATUS:
2403 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2404 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2405 case MSR_K7_CLK_CTL:
2406 /*
2407 * Provide expected ramp-up count for K7. All other
2408 * are set to zero, indicating minimum divisors for
2409 * every field.
2410 *
2411 * This prevents guest kernels on AMD host with CPU
2412 * type 6, model 8 and higher from exploding due to
2413 * the rdmsr failing.
2414 */
2415 data = 0x20000000;
2416 break;
55cd8e5a
GN		 2417 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2418 if (kvm_hv_msr_partition_wide(msr)) {
2419 int r;
2420 mutex_lock(&vcpu->kvm->lock);
2421 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2422 mutex_unlock(&vcpu->kvm->lock);
2423 return r;
2424 } else
2425 return get_msr_hyperv(vcpu, msr, pdata);
2426 break;
91c9c3ed 2427 case MSR_IA32_BBL_CR_CTL3:
2428 /* This legacy MSR exists but isn't fully documented in current
2429 * silicon. It is however accessed by winxp in very narrow
2430 * scenarios where it sets bit #19, itself documented as
2431 * a "reserved" bit. Best effort attempt to source coherent
2432 * read data here should the balance of the register be
2433 * interpreted by the guest:
2434 *
2435 * L2 cache control register 3: 64GB range, 256KB size,
2436 * enabled, latency 0x1, configured
2437 */
2438 data = 0xbe702111;
2439 break;
2b036c6b
BO		 2440 case MSR_AMD64_OSVW_ID_LENGTH:
2441 if (!guest_cpuid_has_osvw(vcpu))
2442 return 1;
2443 data = vcpu->arch.osvw.length;
2444 break;
2445 case MSR_AMD64_OSVW_STATUS:
2446 if (!guest_cpuid_has_osvw(vcpu))
2447 return 1;
2448 data = vcpu->arch.osvw.status;
2449 break;
15c4a640 2450 default:
f5132b01
GN		 2451 if (kvm_pmu_msr(vcpu, msr))
2452 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2453 if (!ignore_msrs) {
a737f256 2454 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2455 return 1;
2456 } else {
a737f256 2457 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2458 data = 0;
2459 }
2460 break;
15c4a640
CO		 2461 }
2462 *pdata = data;
2463 return 0;
2464}
2465EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2466
313a3dc7
CO		 2467/*
2468 * Read or write a bunch of msrs. All parameters are kernel addresses.
2469 *
2470 * @return number of msrs set successfully.
2471 */
2472static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2473 struct kvm_msr_entry *entries,
2474 int (*do_msr)(struct kvm_vcpu *vcpu,
2475 unsigned index, u64 *data))
2476{
f656ce01 2477 int i, idx;
313a3dc7 2478
f656ce01 2479 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2480 for (i = 0; i < msrs->nmsrs; ++i)
2481 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2482 break;
f656ce01 2483 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2484
313a3dc7
CO		 2485 return i;
2486}
2487
2488/*
2489 * Read or write a bunch of msrs. Parameters are user addresses.
2490 *
2491 * @return number of msrs set successfully.
2492 */
2493static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2494 int (*do_msr)(struct kvm_vcpu *vcpu,
2495 unsigned index, u64 *data),
2496 int writeback)
2497{
2498 struct kvm_msrs msrs;
2499 struct kvm_msr_entry *entries;
2500 int r, n;
2501 unsigned size;
2502
2503 r = -EFAULT;
2504 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2505 goto out;
2506
2507 r = -E2BIG;
2508 if (msrs.nmsrs >= MAX_IO_MSRS)
2509 goto out;
2510
313a3dc7 2511 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2512 entries = memdup_user(user_msrs->entries, size);
2513 if (IS_ERR(entries)) {
2514 r = PTR_ERR(entries);
313a3dc7 2515 goto out;
ff5c2c03 2516 }
313a3dc7
CO		 2517
2518 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2519 if (r < 0)
2520 goto out_free;
2521
2522 r = -EFAULT;
2523 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2524 goto out_free;
2525
2526 r = n;
2527
2528out_free:
7a73c028 2529 kfree(entries);
313a3dc7
CO		 2530out:
2531 return r;
2532}
2533
018d00d2
ZX		 2534int kvm_dev_ioctl_check_extension(long ext)
2535{
2536 int r;
2537
2538 switch (ext) {
2539 case KVM_CAP_IRQCHIP:
2540 case KVM_CAP_HLT:
2541 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2542 case KVM_CAP_SET_TSS_ADDR:
07716717 2543 case KVM_CAP_EXT_CPUID:
c8076604 2544 case KVM_CAP_CLOCKSOURCE:
7837699f 2545 case KVM_CAP_PIT:
a28e4f5a 2546 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2547 case KVM_CAP_MP_STATE:
ed848624 2548 case KVM_CAP_SYNC_MMU:
a355c85c 2549 case KVM_CAP_USER_NMI:
52d939a0 2550 case KVM_CAP_REINJECT_CONTROL:
4925663a 2551 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2552 case KVM_CAP_IRQFD:
d34e6b17 2553 case KVM_CAP_IOEVENTFD:
c5ff41ce 2554 case KVM_CAP_PIT2:
e9f42757 2555 case KVM_CAP_PIT_STATE2:
b927a3ce 2556 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2557 case KVM_CAP_XEN_HVM:
afbcf7ab 2558 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2559 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2560 case KVM_CAP_HYPERV:
10388a07 2561 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2562 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2563 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2564 case KVM_CAP_DEBUGREGS:
d2be1651 2565 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2566 case KVM_CAP_XSAVE:
344d9588 2567 case KVM_CAP_ASYNC_PF:
92a1f12d 2568 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2569 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2570 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2571#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2572 case KVM_CAP_ASSIGN_DEV_IRQ:
2573 case KVM_CAP_PCI_2_3:
2574#endif
018d00d2
ZX		 2575 r = 1;
2576 break;
542472b5
LV		 2577 case KVM_CAP_COALESCED_MMIO:
2578 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2579 break;
774ead3a
AK		 2580 case KVM_CAP_VAPIC:
2581 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2582 break;
f725230a 2583 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2584 r = KVM_SOFT_MAX_VCPUS;
2585 break;
2586 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2587 r = KVM_MAX_VCPUS;
2588 break;
a988b910 2589 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2590 r = KVM_USER_MEM_SLOTS;
a988b910 2591 break;
a68a6a72
MT		 2592 case KVM_CAP_PV_MMU: /* obsolete */
2593 r = 0;
2f333bcb 2594 break;
4cee4b72 2595#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2596 case KVM_CAP_IOMMU:
a1b60c1c 2597 r = iommu_present(&pci_bus_type);
62c476c7 2598 break;
4cee4b72 2599#endif
890ca9ae
HY		 2600 case KVM_CAP_MCE:
2601 r = KVM_MAX_MCE_BANKS;
2602 break;
2d5b5a66
SY		 2603 case KVM_CAP_XCRS:
2604 r = cpu_has_xsave;
2605 break;
92a1f12d
JR		 2606 case KVM_CAP_TSC_CONTROL:
2607 r = kvm_has_tsc_control;
2608 break;
4d25a066
JK		 2609 case KVM_CAP_TSC_DEADLINE_TIMER:
2610 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2611 break;
018d00d2
ZX		 2612 default:
2613 r = 0;
2614 break;
2615 }
2616 return r;
2617
2618}
2619
043405e1
CO		 2620long kvm_arch_dev_ioctl(struct file *filp,
2621 unsigned int ioctl, unsigned long arg)
2622{
2623 void __user *argp = (void __user *)arg;
2624 long r;
2625
2626 switch (ioctl) {
2627 case KVM_GET_MSR_INDEX_LIST: {
2628 struct kvm_msr_list __user *user_msr_list = argp;
2629 struct kvm_msr_list msr_list;
2630 unsigned n;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2634 goto out;
2635 n = msr_list.nmsrs;
2636 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2637 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2638 goto out;
2639 r = -E2BIG;
e125e7b6 2640 if (n < msr_list.nmsrs)
043405e1
CO		 2641 goto out;
2642 r = -EFAULT;
2643 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2644 num_msrs_to_save * sizeof(u32)))
2645 goto out;
e125e7b6 2646 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2647 &emulated_msrs,
2648 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2649 goto out;
2650 r = 0;
2651 break;
2652 }
674eea0f
AK		 2653 case KVM_GET_SUPPORTED_CPUID: {
2654 struct kvm_cpuid2 __user *cpuid_arg = argp;
2655 struct kvm_cpuid2 cpuid;
2656
2657 r = -EFAULT;
2658 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2659 goto out;
2660 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2661 cpuid_arg->entries);
674eea0f
AK		 2662 if (r)
2663 goto out;
2664
2665 r = -EFAULT;
2666 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2667 goto out;
2668 r = 0;
2669 break;
2670 }
890ca9ae
HY		 2671 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2672 u64 mce_cap;
2673
2674 mce_cap = KVM_MCE_CAP_SUPPORTED;
2675 r = -EFAULT;
2676 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2677 goto out;
2678 r = 0;
2679 break;
2680 }
043405e1
CO		 2681 default:
2682 r = -EINVAL;
2683 }
2684out:
2685 return r;
2686}
2687
f5f48ee1
SY		 2688static void wbinvd_ipi(void *garbage)
2689{
2690 wbinvd();
2691}
2692
2693static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2694{
2695 return vcpu->kvm->arch.iommu_domain &&
2696 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2697}
2698
313a3dc7
CO		 2699void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2700{
f5f48ee1
SY		 2701 /* Address WBINVD may be executed by guest */
2702 if (need_emulate_wbinvd(vcpu)) {
2703 if (kvm_x86_ops->has_wbinvd_exit())
2704 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2705 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2706 smp_call_function_single(vcpu->cpu,
2707 wbinvd_ipi, NULL, 1);
2708 }
2709
313a3dc7 2710 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2711
0dd6a6ed
ZA		 2712 /* Apply any externally detected TSC adjustments (due to suspend) */
2713 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2714 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2715 vcpu->arch.tsc_offset_adjustment = 0;
2716 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2717 }
8f6055cb 2718
48434c20 2719 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2720 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2721 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2722 if (tsc_delta < 0)
2723 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2724 if (check_tsc_unstable()) {
b183aa58
ZA		 2725 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2726 vcpu->arch.last_guest_tsc);
2727 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2728 vcpu->arch.tsc_catchup = 1;
c285545f 2729 }
d98d07ca
MT		 2730 /*
2731 * On a host with synchronized TSC, there is no need to update
2732 * kvmclock on vcpu->cpu migration
2733 */
2734 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2735 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2736 if (vcpu->cpu != cpu)
2737 kvm_migrate_timers(vcpu);
e48672fa 2738 vcpu->cpu = cpu;
6b7d7e76 2739 }
c9aaa895
GC		 2740
2741 accumulate_steal_time(vcpu);
2742 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2743}
2744
2745void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2746{
02daab21 2747 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2748 kvm_put_guest_fpu(vcpu);
6f526ec5 2749 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2750}
2751
313a3dc7
CO		 2752static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2753 struct kvm_lapic_state *s)
2754{
5a71785d 2755 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2756 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2757
2758 return 0;
2759}
2760
2761static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2762 struct kvm_lapic_state *s)
2763{
64eb0620 2764 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2765 update_cr8_intercept(vcpu);
313a3dc7
CO		 2766
2767 return 0;
2768}
2769
f77bc6a4
ZX		 2770static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2771 struct kvm_interrupt *irq)
2772{
02cdb50f 2773 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2774 return -EINVAL;
2775 if (irqchip_in_kernel(vcpu->kvm))
2776 return -ENXIO;
f77bc6a4 2777
66fd3f7f 2778 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2779 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2780
f77bc6a4
ZX		 2781 return 0;
2782}
2783
c4abb7c9
JK		 2784static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2785{
c4abb7c9 2786 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2787
2788 return 0;
2789}
2790
b209749f
AK		 2791static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2792 struct kvm_tpr_access_ctl *tac)
2793{
2794 if (tac->flags)
2795 return -EINVAL;
2796 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2797 return 0;
2798}
2799
890ca9ae
HY		 2800static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2801 u64 mcg_cap)
2802{
2803 int r;
2804 unsigned bank_num = mcg_cap & 0xff, bank;
2805
2806 r = -EINVAL;
a9e38c3e 2807 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2808 goto out;
2809 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2810 goto out;
2811 r = 0;
2812 vcpu->arch.mcg_cap = mcg_cap;
2813 /* Init IA32_MCG_CTL to all 1s */
2814 if (mcg_cap & MCG_CTL_P)
2815 vcpu->arch.mcg_ctl = ~(u64)0;
2816 /* Init IA32_MCi_CTL to all 1s */
2817 for (bank = 0; bank < bank_num; bank++)
2818 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2819out:
2820 return r;
2821}
2822
2823static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2824 struct kvm_x86_mce *mce)
2825{
2826 u64 mcg_cap = vcpu->arch.mcg_cap;
2827 unsigned bank_num = mcg_cap & 0xff;
2828 u64 *banks = vcpu->arch.mce_banks;
2829
2830 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2831 return -EINVAL;
2832 /*
2833 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2834 * reporting is disabled
2835 */
2836 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2837 vcpu->arch.mcg_ctl != ~(u64)0)
2838 return 0;
2839 banks += 4 * mce->bank;
2840 /*
2841 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2842 * reporting is disabled for the bank
2843 */
2844 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2845 return 0;
2846 if (mce->status & MCI_STATUS_UC) {
2847 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2848 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2849 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2850 return 0;
2851 }
2852 if (banks[1] & MCI_STATUS_VAL)
2853 mce->status |= MCI_STATUS_OVER;
2854 banks[2] = mce->addr;
2855 banks[3] = mce->misc;
2856 vcpu->arch.mcg_status = mce->mcg_status;
2857 banks[1] = mce->status;
2858 kvm_queue_exception(vcpu, MC_VECTOR);
2859 } else if (!(banks[1] & MCI_STATUS_VAL)
2860 || !(banks[1] & MCI_STATUS_UC)) {
2861 if (banks[1] & MCI_STATUS_VAL)
2862 mce->status |= MCI_STATUS_OVER;
2863 banks[2] = mce->addr;
2864 banks[3] = mce->misc;
2865 banks[1] = mce->status;
2866 } else
2867 banks[1] |= MCI_STATUS_OVER;
2868 return 0;
2869}
2870
3cfc3092
JK		 2871static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2872 struct kvm_vcpu_events *events)
2873{
7460fb4a 2874 process_nmi(vcpu);
03b82a30
JK		 2875 events->exception.injected =
2876 vcpu->arch.exception.pending &&
2877 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2878 events->exception.nr = vcpu->arch.exception.nr;
2879 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2880 events->exception.pad = 0;
3cfc3092
JK		 2881 events->exception.error_code = vcpu->arch.exception.error_code;
2882
03b82a30
JK		 2883 events->interrupt.injected =
2884 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2885 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2886 events->interrupt.soft = 0;
48005f64
JK		 2887 events->interrupt.shadow =
2888 kvm_x86_ops->get_interrupt_shadow(vcpu,
2889 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2890
2891 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2892 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2893 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2894 events->nmi.pad = 0;
3cfc3092 2895
66450a21 2896 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2897
dab4b911 2898 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2899 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2900 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2901}
2902
2903static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2904 struct kvm_vcpu_events *events)
2905{
dab4b911 2906 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2907 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2908 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2909 return -EINVAL;
2910
7460fb4a 2911 process_nmi(vcpu);
3cfc3092
JK		 2912 vcpu->arch.exception.pending = events->exception.injected;
2913 vcpu->arch.exception.nr = events->exception.nr;
2914 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2915 vcpu->arch.exception.error_code = events->exception.error_code;
2916
2917 vcpu->arch.interrupt.pending = events->interrupt.injected;
2918 vcpu->arch.interrupt.nr = events->interrupt.nr;
2919 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2920 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2921 kvm_x86_ops->set_interrupt_shadow(vcpu,
2922 events->interrupt.shadow);
3cfc3092
JK		 2923
2924 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2925 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2926 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2927 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2928
66450a21
JK		 2929 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2930 kvm_vcpu_has_lapic(vcpu))
2931 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2932
3842d135
AK		 2933 kvm_make_request(KVM_REQ_EVENT, vcpu);
2934
3cfc3092
JK		 2935 return 0;
2936}
2937
a1efbe77
JK		 2938static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2939 struct kvm_debugregs *dbgregs)
2940{
a1efbe77
JK		 2941 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2942 dbgregs->dr6 = vcpu->arch.dr6;
2943 dbgregs->dr7 = vcpu->arch.dr7;
2944 dbgregs->flags = 0;
97e69aa6 2945 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2946}
2947
2948static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2949 struct kvm_debugregs *dbgregs)
2950{
2951 if (dbgregs->flags)
2952 return -EINVAL;
2953
a1efbe77
JK		 2954 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2955 vcpu->arch.dr6 = dbgregs->dr6;
2956 vcpu->arch.dr7 = dbgregs->dr7;
2957
a1efbe77
JK		 2958 return 0;
2959}
2960
2d5b5a66
SY		 2961static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2962 struct kvm_xsave *guest_xsave)
2963{
2964 if (cpu_has_xsave)
2965 memcpy(guest_xsave->region,
2966 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2967 xstate_size);
2d5b5a66
SY		 2968 else {
2969 memcpy(guest_xsave->region,
2970 &vcpu->arch.guest_fpu.state->fxsave,
2971 sizeof(struct i387_fxsave_struct));
2972 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2973 XSTATE_FPSSE;
2974 }
2975}
2976
2977static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2978 struct kvm_xsave *guest_xsave)
2979{
2980 u64 xstate_bv =
2981 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2982
2983 if (cpu_has_xsave)
2984 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2985 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2986 else {
2987 if (xstate_bv & ~XSTATE_FPSSE)
2988 return -EINVAL;
2989 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2990 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2991 }
2992 return 0;
2993}
2994
2995static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2996 struct kvm_xcrs *guest_xcrs)
2997{
2998 if (!cpu_has_xsave) {
2999 guest_xcrs->nr_xcrs = 0;
3000 return;
3001 }
3002
3003 guest_xcrs->nr_xcrs = 1;
3004 guest_xcrs->flags = 0;
3005 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3006 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3007}
3008
3009static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3010 struct kvm_xcrs *guest_xcrs)
3011{
3012 int i, r = 0;
3013
3014 if (!cpu_has_xsave)
3015 return -EINVAL;
3016
3017 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3018 return -EINVAL;
3019
3020 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3021 /* Only support XCR0 currently */
3022 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3023 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3024 guest_xcrs->xcrs[0].value);
3025 break;
3026 }
3027 if (r)
3028 r = -EINVAL;
3029 return r;
3030}
3031
1c0b28c2
EM		 3032/*
3033 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3034 * stopped by the hypervisor. This function will be called from the host only.
3035 * EINVAL is returned when the host attempts to set the flag for a guest that
3036 * does not support pv clocks.
3037 */
3038static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3039{
0b79459b 3040 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3041 return -EINVAL;
51d59c6b 3042 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3044 return 0;
3045}
3046
313a3dc7
CO		 3047long kvm_arch_vcpu_ioctl(struct file *filp,
3048 unsigned int ioctl, unsigned long arg)
3049{
3050 struct kvm_vcpu *vcpu = filp->private_data;
3051 void __user *argp = (void __user *)arg;
3052 int r;
d1ac91d8
AK		 3053 union {
3054 struct kvm_lapic_state *lapic;
3055 struct kvm_xsave *xsave;
3056 struct kvm_xcrs *xcrs;
3057 void *buffer;
3058 } u;
3059
3060 u.buffer = NULL;
313a3dc7
CO		 3061 switch (ioctl) {
3062 case KVM_GET_LAPIC: {
2204ae3c
MT		 3063 r = -EINVAL;
3064 if (!vcpu->arch.apic)
3065 goto out;
d1ac91d8 3066 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3067
b772ff36 3068 r = -ENOMEM;
d1ac91d8 3069 if (!u.lapic)
b772ff36 3070 goto out;
d1ac91d8 3071 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3072 if (r)
3073 goto out;
3074 r = -EFAULT;
d1ac91d8 3075 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3076 goto out;
3077 r = 0;
3078 break;
3079 }
3080 case KVM_SET_LAPIC: {
2204ae3c
MT		 3081 r = -EINVAL;
3082 if (!vcpu->arch.apic)
3083 goto out;
ff5c2c03 3084 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3085 if (IS_ERR(u.lapic))
3086 return PTR_ERR(u.lapic);
ff5c2c03 3087
d1ac91d8 3088 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3089 break;
3090 }
f77bc6a4
ZX		 3091 case KVM_INTERRUPT: {
3092 struct kvm_interrupt irq;
3093
3094 r = -EFAULT;
3095 if (copy_from_user(&irq, argp, sizeof irq))
3096 goto out;
3097 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3098 break;
3099 }
c4abb7c9
JK		 3100 case KVM_NMI: {
3101 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3102 break;
3103 }
313a3dc7
CO		 3104 case KVM_SET_CPUID: {
3105 struct kvm_cpuid __user *cpuid_arg = argp;
3106 struct kvm_cpuid cpuid;
3107
3108 r = -EFAULT;
3109 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3110 goto out;
3111 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3112 break;
3113 }
07716717
DK		 3114 case KVM_SET_CPUID2: {
3115 struct kvm_cpuid2 __user *cpuid_arg = argp;
3116 struct kvm_cpuid2 cpuid;
3117
3118 r = -EFAULT;
3119 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3120 goto out;
3121 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3122 cpuid_arg->entries);
07716717
DK		 3123 break;
3124 }
3125 case KVM_GET_CPUID2: {
3126 struct kvm_cpuid2 __user *cpuid_arg = argp;
3127 struct kvm_cpuid2 cpuid;
3128
3129 r = -EFAULT;
3130 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3131 goto out;
3132 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3133 cpuid_arg->entries);
07716717
DK		 3134 if (r)
3135 goto out;
3136 r = -EFAULT;
3137 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3138 goto out;
3139 r = 0;
3140 break;
3141 }
313a3dc7
CO		 3142 case KVM_GET_MSRS:
3143 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3144 break;
3145 case KVM_SET_MSRS:
3146 r = msr_io(vcpu, argp, do_set_msr, 0);
3147 break;
b209749f
AK		 3148 case KVM_TPR_ACCESS_REPORTING: {
3149 struct kvm_tpr_access_ctl tac;
3150
3151 r = -EFAULT;
3152 if (copy_from_user(&tac, argp, sizeof tac))
3153 goto out;
3154 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3155 if (r)
3156 goto out;
3157 r = -EFAULT;
3158 if (copy_to_user(argp, &tac, sizeof tac))
3159 goto out;
3160 r = 0;
3161 break;
3162 };
b93463aa
AK		 3163 case KVM_SET_VAPIC_ADDR: {
3164 struct kvm_vapic_addr va;
3165
3166 r = -EINVAL;
3167 if (!irqchip_in_kernel(vcpu->kvm))
3168 goto out;
3169 r = -EFAULT;
3170 if (copy_from_user(&va, argp, sizeof va))
3171 goto out;
3172 r = 0;
3173 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3174 break;
3175 }
890ca9ae
HY		 3176 case KVM_X86_SETUP_MCE: {
3177 u64 mcg_cap;
3178
3179 r = -EFAULT;
3180 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3181 goto out;
3182 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3183 break;
3184 }
3185 case KVM_X86_SET_MCE: {
3186 struct kvm_x86_mce mce;
3187
3188 r = -EFAULT;
3189 if (copy_from_user(&mce, argp, sizeof mce))
3190 goto out;
3191 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3192 break;
3193 }
3cfc3092
JK		 3194 case KVM_GET_VCPU_EVENTS: {
3195 struct kvm_vcpu_events events;
3196
3197 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3198
3199 r = -EFAULT;
3200 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3201 break;
3202 r = 0;
3203 break;
3204 }
3205 case KVM_SET_VCPU_EVENTS: {
3206 struct kvm_vcpu_events events;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3210 break;
3211
3212 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3213 break;
3214 }
a1efbe77
JK		 3215 case KVM_GET_DEBUGREGS: {
3216 struct kvm_debugregs dbgregs;
3217
3218 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3219
3220 r = -EFAULT;
3221 if (copy_to_user(argp, &dbgregs,
3222 sizeof(struct kvm_debugregs)))
3223 break;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_DEBUGREGS: {
3228 struct kvm_debugregs dbgregs;
3229
3230 r = -EFAULT;
3231 if (copy_from_user(&dbgregs, argp,
3232 sizeof(struct kvm_debugregs)))
3233 break;
3234
3235 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3236 break;
3237 }
2d5b5a66 3238 case KVM_GET_XSAVE: {
d1ac91d8 3239 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3240 r = -ENOMEM;
d1ac91d8 3241 if (!u.xsave)
2d5b5a66
SY		 3242 break;
3243
d1ac91d8 3244 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3245
3246 r = -EFAULT;
d1ac91d8 3247 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3248 break;
3249 r = 0;
3250 break;
3251 }
3252 case KVM_SET_XSAVE: {
ff5c2c03 3253 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3254 if (IS_ERR(u.xsave))
3255 return PTR_ERR(u.xsave);
2d5b5a66 3256
d1ac91d8 3257 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3258 break;
3259 }
3260 case KVM_GET_XCRS: {
d1ac91d8 3261 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3262 r = -ENOMEM;
d1ac91d8 3263 if (!u.xcrs)
2d5b5a66
SY		 3264 break;
3265
d1ac91d8 3266 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3267
3268 r = -EFAULT;
d1ac91d8 3269 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3270 sizeof(struct kvm_xcrs)))
3271 break;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_SET_XCRS: {
ff5c2c03 3276 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3277 if (IS_ERR(u.xcrs))
3278 return PTR_ERR(u.xcrs);
2d5b5a66 3279
d1ac91d8 3280 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3281 break;
3282 }
92a1f12d
JR		 3283 case KVM_SET_TSC_KHZ: {
3284 u32 user_tsc_khz;
3285
3286 r = -EINVAL;
92a1f12d
JR		 3287 user_tsc_khz = (u32)arg;
3288
3289 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3290 goto out;
3291
cc578287
ZA		 3292 if (user_tsc_khz == 0)
3293 user_tsc_khz = tsc_khz;
3294
3295 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3296
3297 r = 0;
3298 goto out;
3299 }
3300 case KVM_GET_TSC_KHZ: {
cc578287 3301 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3302 goto out;
3303 }
1c0b28c2
EM		 3304 case KVM_KVMCLOCK_CTRL: {
3305 r = kvm_set_guest_paused(vcpu);
3306 goto out;
3307 }
313a3dc7
CO		 3308 default:
3309 r = -EINVAL;
3310 }
3311out:
d1ac91d8 3312 kfree(u.buffer);
313a3dc7
CO		 3313 return r;
3314}
3315
5b1c1493
CO		 3316int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3317{
3318 return VM_FAULT_SIGBUS;
3319}
3320
1fe779f8
CO		 3321static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3322{
3323 int ret;
3324
3325 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3326 return -EINVAL;
1fe779f8
CO		 3327 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3328 return ret;
3329}
3330
b927a3ce
SY		 3331static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3332 u64 ident_addr)
3333{
3334 kvm->arch.ept_identity_map_addr = ident_addr;
3335 return 0;
3336}
3337
1fe779f8
CO		 3338static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3339 u32 kvm_nr_mmu_pages)
3340{
3341 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3342 return -EINVAL;
3343
79fac95e 3344 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3345
3346 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3347 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3348
79fac95e 3349 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3350 return 0;
3351}
3352
3353static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3354{
39de71ec 3355 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3356}
3357
1fe779f8
CO		 3358static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3359{
3360 int r;
3361
3362 r = 0;
3363 switch (chip->chip_id) {
3364 case KVM_IRQCHIP_PIC_MASTER:
3365 memcpy(&chip->chip.pic,
3366 &pic_irqchip(kvm)->pics[0],
3367 sizeof(struct kvm_pic_state));
3368 break;
3369 case KVM_IRQCHIP_PIC_SLAVE:
3370 memcpy(&chip->chip.pic,
3371 &pic_irqchip(kvm)->pics[1],
3372 sizeof(struct kvm_pic_state));
3373 break;
3374 case KVM_IRQCHIP_IOAPIC:
eba0226b 3375 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3376 break;
3377 default:
3378 r = -EINVAL;
3379 break;
3380 }
3381 return r;
3382}
3383
3384static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3385{
3386 int r;
3387
3388 r = 0;
3389 switch (chip->chip_id) {
3390 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3391 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3392 memcpy(&pic_irqchip(kvm)->pics[0],
3393 &chip->chip.pic,
3394 sizeof(struct kvm_pic_state));
f4f51050 3395 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3396 break;
3397 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3398 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3399 memcpy(&pic_irqchip(kvm)->pics[1],
3400 &chip->chip.pic,
3401 sizeof(struct kvm_pic_state));
f4f51050 3402 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3403 break;
3404 case KVM_IRQCHIP_IOAPIC:
eba0226b 3405 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3406 break;
3407 default:
3408 r = -EINVAL;
3409 break;
3410 }
3411 kvm_pic_update_irq(pic_irqchip(kvm));
3412 return r;
3413}
3414
e0f63cb9
SY		 3415static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3416{
3417 int r = 0;
3418
894a9c55 3419 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3420 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3421 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3422 return r;
3423}
3424
3425static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3426{
3427 int r = 0;
3428
894a9c55 3429 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3430 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3431 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3432 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3433 return r;
3434}
3435
3436static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3437{
3438 int r = 0;
3439
3440 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3441 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3442 sizeof(ps->channels));
3443 ps->flags = kvm->arch.vpit->pit_state.flags;
3444 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3445 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3446 return r;
3447}
3448
3449static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3450{
3451 int r = 0, start = 0;
3452 u32 prev_legacy, cur_legacy;
3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3454 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3455 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3456 if (!prev_legacy && cur_legacy)
3457 start = 1;
3458 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3459 sizeof(kvm->arch.vpit->pit_state.channels));
3460 kvm->arch.vpit->pit_state.flags = ps->flags;
3461 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3462 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3463 return r;
3464}
3465
52d939a0
MT		 3466static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3467 struct kvm_reinject_control *control)
3468{
3469 if (!kvm->arch.vpit)
3470 return -ENXIO;
894a9c55 3471 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3472 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3473 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3474 return 0;
3475}
3476
95d4c16c 3477/**
60c34612
TY		 3478 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3479 * @kvm: kvm instance
3480 * @log: slot id and address to which we copy the log
95d4c16c 3481 *
60c34612
TY		 3482 * We need to keep it in mind that VCPU threads can write to the bitmap
3483 * concurrently. So, to avoid losing data, we keep the following order for
3484 * each bit:
95d4c16c 3485 *
60c34612
TY		 3486 * 1. Take a snapshot of the bit and clear it if needed.
3487 * 2. Write protect the corresponding page.
3488 * 3. Flush TLB's if needed.
3489 * 4. Copy the snapshot to the userspace.
95d4c16c 3490 *
60c34612
TY		 3491 * Between 2 and 3, the guest may write to the page using the remaining TLB
3492 * entry. This is not a problem because the page will be reported dirty at
3493 * step 4 using the snapshot taken before and step 3 ensures that successive
3494 * writes will be logged for the next call.
5bb064dc 3495 */
60c34612 3496int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3497{
7850ac54 3498 int r;
5bb064dc 3499 struct kvm_memory_slot *memslot;
60c34612
TY		 3500 unsigned long n, i;
3501 unsigned long *dirty_bitmap;
3502 unsigned long *dirty_bitmap_buffer;
3503 bool is_dirty = false;
5bb064dc 3504
79fac95e 3505 mutex_lock(&kvm->slots_lock);
5bb064dc 3506
b050b015 3507 r = -EINVAL;
bbacc0c1 3508 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3509 goto out;
3510
28a37544 3511 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3512
3513 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3514 r = -ENOENT;
60c34612 3515 if (!dirty_bitmap)
b050b015
MT		 3516 goto out;
3517
87bf6e7d 3518 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3519
60c34612
TY		 3520 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3521 memset(dirty_bitmap_buffer, 0, n);
b050b015 3522
60c34612 3523 spin_lock(&kvm->mmu_lock);
b050b015 3524
60c34612
TY		 3525 for (i = 0; i < n / sizeof(long); i++) {
3526 unsigned long mask;
3527 gfn_t offset;
cdfca7b3 3528
60c34612
TY		 3529 if (!dirty_bitmap[i])
3530 continue;
b050b015 3531
60c34612 3532 is_dirty = true;
914ebccd 3533
60c34612
TY		 3534 mask = xchg(&dirty_bitmap[i], 0);
3535 dirty_bitmap_buffer[i] = mask;
edde99ce 3536
60c34612
TY		 3537 offset = i * BITS_PER_LONG;
3538 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3539 }
60c34612
TY		 3540 if (is_dirty)
3541 kvm_flush_remote_tlbs(kvm);
3542
3543 spin_unlock(&kvm->mmu_lock);
3544
3545 r = -EFAULT;
3546 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3547 goto out;
b050b015 3548
5bb064dc
ZX		 3549 r = 0;
3550out:
79fac95e 3551 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3552 return r;
3553}
3554
aa2fbe6d
YZ		 3555int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3556 bool line_status)
23d43cf9
CD		 3557{
3558 if (!irqchip_in_kernel(kvm))
3559 return -ENXIO;
3560
3561 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3562 irq_event->irq, irq_event->level,
3563 line_status);
23d43cf9
CD		 3564 return 0;
3565}
3566
1fe779f8
CO		 3567long kvm_arch_vm_ioctl(struct file *filp,
3568 unsigned int ioctl, unsigned long arg)
3569{
3570 struct kvm *kvm = filp->private_data;
3571 void __user *argp = (void __user *)arg;
367e1319 3572 int r = -ENOTTY;
f0d66275
DH		 3573 /*
3574 * This union makes it completely explicit to gcc-3.x
3575 * that these two variables' stack usage should be
3576 * combined, not added together.
3577 */
3578 union {
3579 struct kvm_pit_state ps;
e9f42757 3580 struct kvm_pit_state2 ps2;
c5ff41ce 3581 struct kvm_pit_config pit_config;
f0d66275 3582 } u;
1fe779f8
CO		 3583
3584 switch (ioctl) {
3585 case KVM_SET_TSS_ADDR:
3586 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3587 break;
b927a3ce
SY		 3588 case KVM_SET_IDENTITY_MAP_ADDR: {
3589 u64 ident_addr;
3590
3591 r = -EFAULT;
3592 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3593 goto out;
3594 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3595 break;
3596 }
1fe779f8
CO		 3597 case KVM_SET_NR_MMU_PAGES:
3598 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3599 break;
3600 case KVM_GET_NR_MMU_PAGES:
3601 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3602 break;
3ddea128
MT		 3603 case KVM_CREATE_IRQCHIP: {
3604 struct kvm_pic *vpic;
3605
3606 mutex_lock(&kvm->lock);
3607 r = -EEXIST;
3608 if (kvm->arch.vpic)
3609 goto create_irqchip_unlock;
3e515705
AK		 3610 r = -EINVAL;
3611 if (atomic_read(&kvm->online_vcpus))
3612 goto create_irqchip_unlock;
1fe779f8 3613 r = -ENOMEM;
3ddea128
MT		 3614 vpic = kvm_create_pic(kvm);
3615 if (vpic) {
1fe779f8
CO		 3616 r = kvm_ioapic_init(kvm);
3617 if (r) {
175504cd 3618 mutex_lock(&kvm->slots_lock);
72bb2fcd 3619 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3620 &vpic->dev_master);
3621 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3622 &vpic->dev_slave);
3623 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3624 &vpic->dev_eclr);
175504cd 3625 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3626 kfree(vpic);
3627 goto create_irqchip_unlock;
1fe779f8
CO		 3628 }
3629 } else
3ddea128
MT		 3630 goto create_irqchip_unlock;
3631 smp_wmb();
3632 kvm->arch.vpic = vpic;
3633 smp_wmb();
399ec807
AK		 3634 r = kvm_setup_default_irq_routing(kvm);
3635 if (r) {
175504cd 3636 mutex_lock(&kvm->slots_lock);
3ddea128 3637 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3638 kvm_ioapic_destroy(kvm);
3639 kvm_destroy_pic(kvm);
3ddea128 3640 mutex_unlock(&kvm->irq_lock);
175504cd 3641 mutex_unlock(&kvm->slots_lock);
399ec807 3642 }
3ddea128
MT		 3643 create_irqchip_unlock:
3644 mutex_unlock(&kvm->lock);
1fe779f8 3645 break;
3ddea128 3646 }
7837699f 3647 case KVM_CREATE_PIT:
c5ff41ce
JK		 3648 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3649 goto create_pit;
3650 case KVM_CREATE_PIT2:
3651 r = -EFAULT;
3652 if (copy_from_user(&u.pit_config, argp,
3653 sizeof(struct kvm_pit_config)))
3654 goto out;
3655 create_pit:
79fac95e 3656 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3657 r = -EEXIST;
3658 if (kvm->arch.vpit)
3659 goto create_pit_unlock;
7837699f 3660 r = -ENOMEM;
c5ff41ce 3661 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3662 if (kvm->arch.vpit)
3663 r = 0;
269e05e4 3664 create_pit_unlock:
79fac95e 3665 mutex_unlock(&kvm->slots_lock);
7837699f 3666 break;
1fe779f8
CO		 3667 case KVM_GET_IRQCHIP: {
3668 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3669 struct kvm_irqchip *chip;
1fe779f8 3670
ff5c2c03
SL		 3671 chip = memdup_user(argp, sizeof(*chip));
3672 if (IS_ERR(chip)) {
3673 r = PTR_ERR(chip);
1fe779f8 3674 goto out;
ff5c2c03
SL		 3675 }
3676
1fe779f8
CO		 3677 r = -ENXIO;
3678 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3679 goto get_irqchip_out;
3680 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3681 if (r)
f0d66275 3682 goto get_irqchip_out;
1fe779f8 3683 r = -EFAULT;
f0d66275
DH		 3684 if (copy_to_user(argp, chip, sizeof *chip))
3685 goto get_irqchip_out;
1fe779f8 3686 r = 0;
f0d66275
DH		 3687 get_irqchip_out:
3688 kfree(chip);
1fe779f8
CO		 3689 break;
3690 }
3691 case KVM_SET_IRQCHIP: {
3692 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3693 struct kvm_irqchip *chip;
1fe779f8 3694
ff5c2c03
SL		 3695 chip = memdup_user(argp, sizeof(*chip));
3696 if (IS_ERR(chip)) {
3697 r = PTR_ERR(chip);
1fe779f8 3698 goto out;
ff5c2c03
SL		 3699 }
3700
1fe779f8
CO		 3701 r = -ENXIO;
3702 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3703 goto set_irqchip_out;
3704 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3705 if (r)
f0d66275 3706 goto set_irqchip_out;
1fe779f8 3707 r = 0;
f0d66275
DH		 3708 set_irqchip_out:
3709 kfree(chip);
1fe779f8
CO		 3710 break;
3711 }
e0f63cb9 3712 case KVM_GET_PIT: {
e0f63cb9 3713 r = -EFAULT;
f0d66275 3714 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3715 goto out;
3716 r = -ENXIO;
3717 if (!kvm->arch.vpit)
3718 goto out;
f0d66275 3719 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3720 if (r)
3721 goto out;
3722 r = -EFAULT;
f0d66275 3723 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3724 goto out;
3725 r = 0;
3726 break;
3727 }
3728 case KVM_SET_PIT: {
e0f63cb9 3729 r = -EFAULT;
f0d66275 3730 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3731 goto out;
3732 r = -ENXIO;
3733 if (!kvm->arch.vpit)
3734 goto out;
f0d66275 3735 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3736 break;
3737 }
e9f42757
BK		 3738 case KVM_GET_PIT2: {
3739 r = -ENXIO;
3740 if (!kvm->arch.vpit)
3741 goto out;
3742 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3743 if (r)
3744 goto out;
3745 r = -EFAULT;
3746 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3747 goto out;
3748 r = 0;
3749 break;
3750 }
3751 case KVM_SET_PIT2: {
3752 r = -EFAULT;
3753 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3754 goto out;
3755 r = -ENXIO;
3756 if (!kvm->arch.vpit)
3757 goto out;
3758 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3759 break;
3760 }
52d939a0
MT		 3761 case KVM_REINJECT_CONTROL: {
3762 struct kvm_reinject_control control;
3763 r = -EFAULT;
3764 if (copy_from_user(&control, argp, sizeof(control)))
3765 goto out;
3766 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3767 break;
3768 }
ffde22ac
ES		 3769 case KVM_XEN_HVM_CONFIG: {
3770 r = -EFAULT;
3771 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3772 sizeof(struct kvm_xen_hvm_config)))
3773 goto out;
3774 r = -EINVAL;
3775 if (kvm->arch.xen_hvm_config.flags)
3776 goto out;
3777 r = 0;
3778 break;
3779 }
afbcf7ab 3780 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3781 struct kvm_clock_data user_ns;
3782 u64 now_ns;
3783 s64 delta;
3784
3785 r = -EFAULT;
3786 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3787 goto out;
3788
3789 r = -EINVAL;
3790 if (user_ns.flags)
3791 goto out;
3792
3793 r = 0;
395c6b0a 3794 local_irq_disable();
759379dd 3795 now_ns = get_kernel_ns();
afbcf7ab 3796 delta = user_ns.clock - now_ns;
395c6b0a 3797 local_irq_enable();
afbcf7ab
GC		 3798 kvm->arch.kvmclock_offset = delta;
3799 break;
3800 }
3801 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3802 struct kvm_clock_data user_ns;
3803 u64 now_ns;
3804
395c6b0a 3805 local_irq_disable();
759379dd 3806 now_ns = get_kernel_ns();
afbcf7ab 3807 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3808 local_irq_enable();
afbcf7ab 3809 user_ns.flags = 0;
97e69aa6 3810 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3811
3812 r = -EFAULT;
3813 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3814 goto out;
3815 r = 0;
3816 break;
3817 }
3818
1fe779f8
CO		 3819 default:
3820 ;
3821 }
3822out:
3823 return r;
3824}
3825
a16b043c 3826static void kvm_init_msr_list(void)
043405e1
CO		 3827{
3828 u32 dummy[2];
3829 unsigned i, j;
3830
e3267cbb
GC		 3831 /* skip the first msrs in the list. KVM-specific */
3832 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3833 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3834 continue;
3835 if (j < i)
3836 msrs_to_save[j] = msrs_to_save[i];
3837 j++;
3838 }
3839 num_msrs_to_save = j;
3840}
3841
bda9020e
MT		 3842static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3843 const void *v)
bbd9b64e 3844{
70252a10
AK		 3845 int handled = 0;
3846 int n;
3847
3848 do {
3849 n = min(len, 8);
3850 if (!(vcpu->arch.apic &&
3851 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3852 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3853 break;
3854 handled += n;
3855 addr += n;
3856 len -= n;
3857 v += n;
3858 } while (len);
bbd9b64e 3859
70252a10 3860 return handled;
bbd9b64e
CO		 3861}
3862
bda9020e 3863static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3864{
70252a10
AK		 3865 int handled = 0;
3866 int n;
3867
3868 do {
3869 n = min(len, 8);
3870 if (!(vcpu->arch.apic &&
3871 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3872 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3873 break;
3874 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3875 handled += n;
3876 addr += n;
3877 len -= n;
3878 v += n;
3879 } while (len);
bbd9b64e 3880
70252a10 3881 return handled;
bbd9b64e
CO		 3882}
3883
2dafc6c2
GN		 3884static void kvm_set_segment(struct kvm_vcpu *vcpu,
3885 struct kvm_segment *var, int seg)
3886{
3887 kvm_x86_ops->set_segment(vcpu, var, seg);
3888}
3889
3890void kvm_get_segment(struct kvm_vcpu *vcpu,
3891 struct kvm_segment *var, int seg)
3892{
3893 kvm_x86_ops->get_segment(vcpu, var, seg);
3894}
3895
e459e322 3896gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3897{
3898 gpa_t t_gpa;
ab9ae313 3899 struct x86_exception exception;
02f59dc9
JR		 3900
3901 BUG_ON(!mmu_is_nested(vcpu));
3902
3903 /* NPT walks are always user-walks */
3904 access |= PFERR_USER_MASK;
ab9ae313 3905 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3906
3907 return t_gpa;
3908}
3909
ab9ae313
AK		 3910gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3911 struct x86_exception *exception)
1871c602
GN		 3912{
3913 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3914 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3915}
3916
ab9ae313
AK		 3917 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3918 struct x86_exception *exception)
1871c602
GN		 3919{
3920 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3921 access |= PFERR_FETCH_MASK;
ab9ae313 3922 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3923}
3924
ab9ae313
AK		 3925gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3926 struct x86_exception *exception)
1871c602
GN		 3927{
3928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3929 access |= PFERR_WRITE_MASK;
ab9ae313 3930 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3931}
3932
3933/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3934gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3935 struct x86_exception *exception)
1871c602 3936{
ab9ae313 3937 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3938}
3939
3940static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3941 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3942 struct x86_exception *exception)
bbd9b64e
CO		 3943{
3944 void *data = val;
10589a46 3945 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3946
3947 while (bytes) {
14dfe855 3948 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3949 exception);
bbd9b64e 3950 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3951 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3952 int ret;
3953
bcc55cba 3954 if (gpa == UNMAPPED_GVA)
ab9ae313 3955 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3956 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3957 if (ret < 0) {
c3cd7ffa 3958 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3959 goto out;
3960 }
bbd9b64e 3961
77c2002e
IE		 3962 bytes -= toread;
3963 data += toread;
3964 addr += toread;
bbd9b64e 3965 }
10589a46 3966out:
10589a46 3967 return r;
bbd9b64e 3968}
77c2002e 3969
1871c602 3970/* used for instruction fetching */
0f65dd70
AK		 3971static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3972 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3973 struct x86_exception *exception)
1871c602 3974{
0f65dd70 3975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3976 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3977
1871c602 3978 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3979 access | PFERR_FETCH_MASK,
3980 exception);
1871c602
GN		 3981}
3982
064aea77 3983int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3984 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3985 struct x86_exception *exception)
1871c602 3986{
0f65dd70 3987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3988 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3989
1871c602 3990 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3991 exception);
1871c602 3992}
064aea77 3993EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3994
0f65dd70
AK		 3995static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3996 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3997 struct x86_exception *exception)
1871c602 3998{
0f65dd70 3999 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4000 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4001}
4002
6a4d7550 4003int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4004 gva_t addr, void *val,
2dafc6c2 4005 unsigned int bytes,
bcc55cba 4006 struct x86_exception *exception)
77c2002e 4007{
0f65dd70 4008 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4009 void *data = val;
4010 int r = X86EMUL_CONTINUE;
4011
4012 while (bytes) {
14dfe855
JR		 4013 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4014 PFERR_WRITE_MASK,
ab9ae313 4015 exception);
77c2002e
IE		 4016 unsigned offset = addr & (PAGE_SIZE-1);
4017 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4018 int ret;
4019
bcc55cba 4020 if (gpa == UNMAPPED_GVA)
ab9ae313 4021 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4022 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4023 if (ret < 0) {
c3cd7ffa 4024 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4025 goto out;
4026 }
4027
4028 bytes -= towrite;
4029 data += towrite;
4030 addr += towrite;
4031 }
4032out:
4033 return r;
4034}
6a4d7550 4035EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4036
af7cc7d1
XG		 4037static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4038 gpa_t *gpa, struct x86_exception *exception,
4039 bool write)
4040{
97d64b78
AK		 4041 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4042 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4043
97d64b78
AK		 4044 if (vcpu_match_mmio_gva(vcpu, gva)
4045 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4046 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4047 (gva & (PAGE_SIZE - 1));
4f022648 4048 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4049 return 1;
4050 }
4051
af7cc7d1
XG		 4052 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4053
4054 if (*gpa == UNMAPPED_GVA)
4055 return -1;
4056
4057 /* For APIC access vmexit */
4058 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4059 return 1;
4060
4f022648
XG		 4061 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4062 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4063 return 1;
4f022648 4064 }
bebb106a 4065
af7cc7d1
XG		 4066 return 0;
4067}
4068
3200f405 4069int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4070 const void *val, int bytes)
bbd9b64e
CO		 4071{
4072 int ret;
4073
4074 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4075 if (ret < 0)
bbd9b64e 4076 return 0;
f57f2ef5 4077 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4078 return 1;
4079}
4080
77d197b2
XG		 4081struct read_write_emulator_ops {
4082 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4083 int bytes);
4084 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4085 void *val, int bytes);
4086 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4087 int bytes, void *val);
4088 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4089 void *val, int bytes);
4090 bool write;
4091};
4092
4093static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4094{
4095 if (vcpu->mmio_read_completed) {
77d197b2 4096 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4097 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4098 vcpu->mmio_read_completed = 0;
4099 return 1;
4100 }
4101
4102 return 0;
4103}
4104
4105static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4106 void *val, int bytes)
4107{
4108 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4109}
4110
4111static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4112 void *val, int bytes)
4113{
4114 return emulator_write_phys(vcpu, gpa, val, bytes);
4115}
4116
4117static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4118{
4119 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4120 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4121}
4122
4123static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4124 void *val, int bytes)
4125{
4126 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4127 return X86EMUL_IO_NEEDED;
4128}
4129
4130static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4131 void *val, int bytes)
4132{
f78146b0
AK		 4133 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4134
87da7e66 4135 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4136 return X86EMUL_CONTINUE;
4137}
4138
0fbe9b0b 4139static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4140 .read_write_prepare = read_prepare,
4141 .read_write_emulate = read_emulate,
4142 .read_write_mmio = vcpu_mmio_read,
4143 .read_write_exit_mmio = read_exit_mmio,
4144};
4145
0fbe9b0b 4146static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4147 .read_write_emulate = write_emulate,
4148 .read_write_mmio = write_mmio,
4149 .read_write_exit_mmio = write_exit_mmio,
4150 .write = true,
4151};
4152
22388a3c
XG		 4153static int emulator_read_write_onepage(unsigned long addr, void *val,
4154 unsigned int bytes,
4155 struct x86_exception *exception,
4156 struct kvm_vcpu *vcpu,
0fbe9b0b 4157 const struct read_write_emulator_ops *ops)
bbd9b64e 4158{
af7cc7d1
XG		 4159 gpa_t gpa;
4160 int handled, ret;
22388a3c 4161 bool write = ops->write;
f78146b0 4162 struct kvm_mmio_fragment *frag;
10589a46 4163
22388a3c 4164 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4165
af7cc7d1 4166 if (ret < 0)
bbd9b64e 4167 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4168
4169 /* For APIC access vmexit */
af7cc7d1 4170 if (ret)
bbd9b64e
CO		 4171 goto mmio;
4172
22388a3c 4173 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4174 return X86EMUL_CONTINUE;
4175
4176mmio:
4177 /*
4178 * Is this MMIO handled locally?
4179 */
22388a3c 4180 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4181 if (handled == bytes)
bbd9b64e 4182 return X86EMUL_CONTINUE;
bbd9b64e 4183
70252a10
AK		 4184 gpa += handled;
4185 bytes -= handled;
4186 val += handled;
4187
87da7e66
XG		 4188 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4189 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4190 frag->gpa = gpa;
4191 frag->data = val;
4192 frag->len = bytes;
f78146b0 4193 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4194}
4195
22388a3c
XG		 4196int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4197 void *val, unsigned int bytes,
4198 struct x86_exception *exception,
0fbe9b0b 4199 const struct read_write_emulator_ops *ops)
bbd9b64e 4200{
0f65dd70 4201 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4202 gpa_t gpa;
4203 int rc;
4204
4205 if (ops->read_write_prepare &&
4206 ops->read_write_prepare(vcpu, val, bytes))
4207 return X86EMUL_CONTINUE;
4208
4209 vcpu->mmio_nr_fragments = 0;
0f65dd70 4210
bbd9b64e
CO		 4211 /* Crossing a page boundary? */
4212 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4213 int now;
bbd9b64e
CO		 4214
4215 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4216 rc = emulator_read_write_onepage(addr, val, now, exception,
4217 vcpu, ops);
4218
bbd9b64e
CO		 4219 if (rc != X86EMUL_CONTINUE)
4220 return rc;
4221 addr += now;
4222 val += now;
4223 bytes -= now;
4224 }
22388a3c 4225
f78146b0
AK		 4226 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4227 vcpu, ops);
4228 if (rc != X86EMUL_CONTINUE)
4229 return rc;
4230
4231 if (!vcpu->mmio_nr_fragments)
4232 return rc;
4233
4234 gpa = vcpu->mmio_fragments[0].gpa;
4235
4236 vcpu->mmio_needed = 1;
4237 vcpu->mmio_cur_fragment = 0;
4238
87da7e66 4239 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4240 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4241 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4242 vcpu->run->mmio.phys_addr = gpa;
4243
4244 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4245}
4246
4247static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4248 unsigned long addr,
4249 void *val,
4250 unsigned int bytes,
4251 struct x86_exception *exception)
4252{
4253 return emulator_read_write(ctxt, addr, val, bytes,
4254 exception, &read_emultor);
4255}
4256
4257int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4258 unsigned long addr,
4259 const void *val,
4260 unsigned int bytes,
4261 struct x86_exception *exception)
4262{
4263 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4264 exception, &write_emultor);
bbd9b64e 4265}
bbd9b64e 4266
daea3e73
AK		 4267#define CMPXCHG_TYPE(t, ptr, old, new) \
4268 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4269
4270#ifdef CONFIG_X86_64
4271# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4272#else
4273# define CMPXCHG64(ptr, old, new) \
9749a6c0 4274 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4275#endif
4276
0f65dd70
AK		 4277static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4278 unsigned long addr,
bbd9b64e
CO		 4279 const void *old,
4280 const void *new,
4281 unsigned int bytes,
0f65dd70 4282 struct x86_exception *exception)
bbd9b64e 4283{
0f65dd70 4284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4285 gpa_t gpa;
4286 struct page *page;
4287 char *kaddr;
4288 bool exchanged;
2bacc55c 4289
daea3e73
AK		 4290 /* guests cmpxchg8b have to be emulated atomically */
4291 if (bytes > 8 || (bytes & (bytes - 1)))
4292 goto emul_write;
10589a46 4293
daea3e73 4294 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4295
daea3e73
AK		 4296 if (gpa == UNMAPPED_GVA ||
4297 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4298 goto emul_write;
2bacc55c 4299
daea3e73
AK		 4300 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4301 goto emul_write;
72dc67a6 4302
daea3e73 4303 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4304 if (is_error_page(page))
c19b8bd6 4305 goto emul_write;
72dc67a6 4306
8fd75e12 4307 kaddr = kmap_atomic(page);
daea3e73
AK		 4308 kaddr += offset_in_page(gpa);
4309 switch (bytes) {
4310 case 1:
4311 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4312 break;
4313 case 2:
4314 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4315 break;
4316 case 4:
4317 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4318 break;
4319 case 8:
4320 exchanged = CMPXCHG64(kaddr, old, new);
4321 break;
4322 default:
4323 BUG();
2bacc55c 4324 }
8fd75e12 4325 kunmap_atomic(kaddr);
daea3e73
AK		 4326 kvm_release_page_dirty(page);
4327
4328 if (!exchanged)
4329 return X86EMUL_CMPXCHG_FAILED;
4330
f57f2ef5 4331 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4332
4333 return X86EMUL_CONTINUE;
4a5f48f6 4334
3200f405 4335emul_write:
daea3e73 4336 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4337
0f65dd70 4338 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4339}
4340
cf8f70bf
GN		 4341static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4342{
4343 /* TODO: String I/O for in kernel device */
4344 int r;
4345
4346 if (vcpu->arch.pio.in)
4347 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4348 vcpu->arch.pio.size, pd);
4349 else
4350 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4351 vcpu->arch.pio.port, vcpu->arch.pio.size,
4352 pd);
4353 return r;
4354}
4355
6f6fbe98
XG		 4356static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4357 unsigned short port, void *val,
4358 unsigned int count, bool in)
cf8f70bf 4359{
6f6fbe98 4360 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4361
4362 vcpu->arch.pio.port = port;
6f6fbe98 4363 vcpu->arch.pio.in = in;
7972995b 4364 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4365 vcpu->arch.pio.size = size;
4366
4367 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4368 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4369 return 1;
4370 }
4371
4372 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4373 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4374 vcpu->run->io.size = size;
4375 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4376 vcpu->run->io.count = count;
4377 vcpu->run->io.port = port;
4378
4379 return 0;
4380}
4381
6f6fbe98
XG		 4382static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4383 int size, unsigned short port, void *val,
4384 unsigned int count)
cf8f70bf 4385{
ca1d4a9e 4386 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4387 int ret;
ca1d4a9e 4388
6f6fbe98
XG		 4389 if (vcpu->arch.pio.count)
4390 goto data_avail;
cf8f70bf 4391
6f6fbe98
XG		 4392 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4393 if (ret) {
4394data_avail:
4395 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4396 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4397 return 1;
4398 }
4399
cf8f70bf
GN		 4400 return 0;
4401}
4402
6f6fbe98
XG		 4403static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4404 int size, unsigned short port,
4405 const void *val, unsigned int count)
4406{
4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4408
4409 memcpy(vcpu->arch.pio_data, val, size * count);
4410 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4411}
4412
bbd9b64e
CO		 4413static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4414{
4415 return kvm_x86_ops->get_segment_base(vcpu, seg);
4416}
4417
3cb16fe7 4418static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4419{
3cb16fe7 4420 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4421}
4422
f5f48ee1
SY		 4423int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4424{
4425 if (!need_emulate_wbinvd(vcpu))
4426 return X86EMUL_CONTINUE;
4427
4428 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4429 int cpu = get_cpu();
4430
4431 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4432 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4433 wbinvd_ipi, NULL, 1);
2eec7343 4434 put_cpu();
f5f48ee1 4435 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4436 } else
4437 wbinvd();
f5f48ee1
SY		 4438 return X86EMUL_CONTINUE;
4439}
4440EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4441
bcaf5cc5
AK		 4442static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4443{
4444 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4445}
4446
717746e3 4447int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4448{
717746e3 4449 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4450}
4451
717746e3 4452int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4453{
338dbc97 4454
717746e3 4455 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4456}
4457
52a46617 4458static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4459{
52a46617 4460 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4461}
4462
717746e3 4463static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4464{
717746e3 4465 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4466 unsigned long value;
4467
4468 switch (cr) {
4469 case 0:
4470 value = kvm_read_cr0(vcpu);
4471 break;
4472 case 2:
4473 value = vcpu->arch.cr2;
4474 break;
4475 case 3:
9f8fe504 4476 value = kvm_read_cr3(vcpu);
52a46617
GN		 4477 break;
4478 case 4:
4479 value = kvm_read_cr4(vcpu);
4480 break;
4481 case 8:
4482 value = kvm_get_cr8(vcpu);
4483 break;
4484 default:
a737f256 4485 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4486 return 0;
4487 }
4488
4489 return value;
4490}
4491
717746e3 4492static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4493{
717746e3 4494 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4495 int res = 0;
4496
52a46617
GN		 4497 switch (cr) {
4498 case 0:
49a9b07e 4499 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4500 break;
4501 case 2:
4502 vcpu->arch.cr2 = val;
4503 break;
4504 case 3:
2390218b 4505 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4506 break;
4507 case 4:
a83b29c6 4508 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4509 break;
4510 case 8:
eea1cff9 4511 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4512 break;
4513 default:
a737f256 4514 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4515 res = -1;
52a46617 4516 }
0f12244f
GN		 4517
4518 return res;
52a46617
GN		 4519}
4520
4cee4798
KW		 4521static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4522{
4523 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4524}
4525
717746e3 4526static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4527{
717746e3 4528 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4529}
4530
4bff1e86 4531static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4532{
4bff1e86 4533 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4534}
4535
4bff1e86 4536static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4537{
4bff1e86 4538 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4539}
4540
1ac9d0cf
AK		 4541static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4542{
4543 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4544}
4545
4546static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4547{
4548 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4549}
4550
4bff1e86
AK		 4551static unsigned long emulator_get_cached_segment_base(
4552 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4553{
4bff1e86 4554 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4555}
4556
1aa36616
AK		 4557static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4558 struct desc_struct *desc, u32 *base3,
4559 int seg)
2dafc6c2
GN		 4560{
4561 struct kvm_segment var;
4562
4bff1e86 4563 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4564 *selector = var.selector;
2dafc6c2 4565
378a8b09
GN		 4566 if (var.unusable) {
4567 memset(desc, 0, sizeof(*desc));
2dafc6c2 4568 return false;
378a8b09 4569 }
2dafc6c2
GN		 4570
4571 if (var.g)
4572 var.limit >>= 12;
4573 set_desc_limit(desc, var.limit);
4574 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4575#ifdef CONFIG_X86_64
4576 if (base3)
4577 *base3 = var.base >> 32;
4578#endif
2dafc6c2
GN		 4579 desc->type = var.type;
4580 desc->s = var.s;
4581 desc->dpl = var.dpl;
4582 desc->p = var.present;
4583 desc->avl = var.avl;
4584 desc->l = var.l;
4585 desc->d = var.db;
4586 desc->g = var.g;
4587
4588 return true;
4589}
4590
1aa36616
AK		 4591static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4592 struct desc_struct *desc, u32 base3,
4593 int seg)
2dafc6c2 4594{
4bff1e86 4595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4596 struct kvm_segment var;
4597
1aa36616 4598 var.selector = selector;
2dafc6c2 4599 var.base = get_desc_base(desc);
5601d05b
GN		 4600#ifdef CONFIG_X86_64
4601 var.base |= ((u64)base3) << 32;
4602#endif
2dafc6c2
GN		 4603 var.limit = get_desc_limit(desc);
4604 if (desc->g)
4605 var.limit = (var.limit << 12) | 0xfff;
4606 var.type = desc->type;
4607 var.present = desc->p;
4608 var.dpl = desc->dpl;
4609 var.db = desc->d;
4610 var.s = desc->s;
4611 var.l = desc->l;
4612 var.g = desc->g;
4613 var.avl = desc->avl;
4614 var.present = desc->p;
4615 var.unusable = !var.present;
4616 var.padding = 0;
4617
4618 kvm_set_segment(vcpu, &var, seg);
4619 return;
4620}
4621
717746e3
AK		 4622static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4623 u32 msr_index, u64 *pdata)
4624{
4625 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4626}
4627
4628static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4629 u32 msr_index, u64 data)
4630{
8fe8ab46
WA		 4631 struct msr_data msr;
4632
4633 msr.data = data;
4634 msr.index = msr_index;
4635 msr.host_initiated = false;
4636 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4637}
4638
222d21aa
AK		 4639static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4640 u32 pmc, u64 *pdata)
4641{
4642 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4643}
4644
6c3287f7
AK		 4645static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4646{
4647 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4648}
4649
5037f6f3
AK		 4650static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4651{
4652 preempt_disable();
5197b808 4653 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4654 /*
4655 * CR0.TS may reference the host fpu state, not the guest fpu state,
4656 * so it may be clear at this point.
4657 */
4658 clts();
4659}
4660
4661static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4662{
4663 preempt_enable();
4664}
4665
2953538e 4666static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4667 struct x86_instruction_info *info,
c4f035c6
AK		 4668 enum x86_intercept_stage stage)
4669{
2953538e 4670 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4671}
4672
0017f93a 4673static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4674 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4675{
0017f93a 4676 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4677}
4678
dd856efa
AK		 4679static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4680{
4681 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4682}
4683
4684static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4685{
4686 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4687}
4688
0225fb50 4689static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4690 .read_gpr = emulator_read_gpr,
4691 .write_gpr = emulator_write_gpr,
1871c602 4692 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4693 .write_std = kvm_write_guest_virt_system,
1871c602 4694 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4695 .read_emulated = emulator_read_emulated,
4696 .write_emulated = emulator_write_emulated,
4697 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4698 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4699 .pio_in_emulated = emulator_pio_in_emulated,
4700 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4701 .get_segment = emulator_get_segment,
4702 .set_segment = emulator_set_segment,
5951c442 4703 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4704 .get_gdt = emulator_get_gdt,
160ce1f1 4705 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4706 .set_gdt = emulator_set_gdt,
4707 .set_idt = emulator_set_idt,
52a46617
GN		 4708 .get_cr = emulator_get_cr,
4709 .set_cr = emulator_set_cr,
4cee4798 4710 .set_rflags = emulator_set_rflags,
9c537244 4711 .cpl = emulator_get_cpl,
35aa5375
GN		 4712 .get_dr = emulator_get_dr,
4713 .set_dr = emulator_set_dr,
717746e3
AK		 4714 .set_msr = emulator_set_msr,
4715 .get_msr = emulator_get_msr,
222d21aa 4716 .read_pmc = emulator_read_pmc,
6c3287f7 4717 .halt = emulator_halt,
bcaf5cc5 4718 .wbinvd = emulator_wbinvd,
d6aa1000 4719 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4720 .get_fpu = emulator_get_fpu,
4721 .put_fpu = emulator_put_fpu,
c4f035c6 4722 .intercept = emulator_intercept,
bdb42f5a 4723 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4724};
4725
95cb2295
GN		 4726static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4727{
4728 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4729 /*
4730 * an sti; sti; sequence only disable interrupts for the first
4731 * instruction. So, if the last instruction, be it emulated or
4732 * not, left the system with the INT_STI flag enabled, it
4733 * means that the last instruction is an sti. We should not
4734 * leave the flag on in this case. The same goes for mov ss
4735 */
4736 if (!(int_shadow & mask))
4737 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4738}
4739
54b8486f
GN		 4740static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4741{
4742 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4743 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4744 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4745 else if (ctxt->exception.error_code_valid)
4746 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4747 ctxt->exception.error_code);
54b8486f 4748 else
da9cb575 4749 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4750}
4751
dd856efa 4752static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4753{
9dac77fa 4754 memset(&ctxt->twobyte, 0,
dd856efa 4755 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4756
9dac77fa
AK		 4757 ctxt->fetch.start = 0;
4758 ctxt->fetch.end = 0;
4759 ctxt->io_read.pos = 0;
4760 ctxt->io_read.end = 0;
4761 ctxt->mem_read.pos = 0;
4762 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4763}
4764
8ec4722d
MG		 4765static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4766{
adf52235 4767 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4768 int cs_db, cs_l;
4769
8ec4722d
MG		 4770 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4771
adf52235
TY		 4772 ctxt->eflags = kvm_get_rflags(vcpu);
4773 ctxt->eip = kvm_rip_read(vcpu);
4774 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4775 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4776 cs_l ? X86EMUL_MODE_PROT64 :
4777 cs_db ? X86EMUL_MODE_PROT32 :
4778 X86EMUL_MODE_PROT16;
4779 ctxt->guest_mode = is_guest_mode(vcpu);
4780
dd856efa 4781 init_decode_cache(ctxt);
7ae441ea 4782 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4783}
4784
71f9833b 4785int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4786{
9d74191a 4787 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4788 int ret;
4789
4790 init_emulate_ctxt(vcpu);
4791
9dac77fa
AK		 4792 ctxt->op_bytes = 2;
4793 ctxt->ad_bytes = 2;
4794 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4795 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4796
4797 if (ret != X86EMUL_CONTINUE)
4798 return EMULATE_FAIL;
4799
9dac77fa 4800 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4801 kvm_rip_write(vcpu, ctxt->eip);
4802 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4803
4804 if (irq == NMI_VECTOR)
7460fb4a 4805 vcpu->arch.nmi_pending = 0;
63995653
MG		 4806 else
4807 vcpu->arch.interrupt.pending = false;
4808
4809 return EMULATE_DONE;
4810}
4811EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4812
6d77dbfc
GN		 4813static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4814{
fc3a9157
JR		 4815 int r = EMULATE_DONE;
4816
6d77dbfc
GN		 4817 ++vcpu->stat.insn_emulation_fail;
4818 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4819 if (!is_guest_mode(vcpu)) {
4820 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4821 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4822 vcpu->run->internal.ndata = 0;
4823 r = EMULATE_FAIL;
4824 }
6d77dbfc 4825 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4826
4827 return r;
6d77dbfc
GN		 4828}
4829
93c05d3e 4830static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4831 bool write_fault_to_shadow_pgtable,
4832 int emulation_type)
a6f177ef 4833{
95b3cf69 4834 gpa_t gpa = cr2;
8e3d9d06 4835 pfn_t pfn;
a6f177ef 4836
991eebf9
GN		 4837 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4838 return false;
4839
95b3cf69
XG		 4840 if (!vcpu->arch.mmu.direct_map) {
4841 /*
4842 * Write permission should be allowed since only
4843 * write access need to be emulated.
4844 */
4845 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4846
95b3cf69
XG		 4847 /*
4848 * If the mapping is invalid in guest, let cpu retry
4849 * it to generate fault.
4850 */
4851 if (gpa == UNMAPPED_GVA)
4852 return true;
4853 }
a6f177ef 4854
8e3d9d06
XG		 4855 /*
4856 * Do not retry the unhandleable instruction if it faults on the
4857 * readonly host memory, otherwise it will goto a infinite loop:
4858 * retry instruction -> write #PF -> emulation fail -> retry
4859 * instruction -> ...
4860 */
4861 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4862
4863 /*
4864 * If the instruction failed on the error pfn, it can not be fixed,
4865 * report the error to userspace.
4866 */
4867 if (is_error_noslot_pfn(pfn))
4868 return false;
4869
4870 kvm_release_pfn_clean(pfn);
4871
4872 /* The instructions are well-emulated on direct mmu. */
4873 if (vcpu->arch.mmu.direct_map) {
4874 unsigned int indirect_shadow_pages;
4875
4876 spin_lock(&vcpu->kvm->mmu_lock);
4877 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4878 spin_unlock(&vcpu->kvm->mmu_lock);
4879
4880 if (indirect_shadow_pages)
4881 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4882
a6f177ef 4883 return true;
8e3d9d06 4884 }
a6f177ef 4885
95b3cf69
XG		 4886 /*
4887 * if emulation was due to access to shadowed page table
4888 * and it failed try to unshadow page and re-enter the
4889 * guest to let CPU execute the instruction.
4890 */
4891 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4892
4893 /*
4894 * If the access faults on its page table, it can not
4895 * be fixed by unprotecting shadow page and it should
4896 * be reported to userspace.
4897 */
4898 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4899}
4900
1cb3f3ae
XG		 4901static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4902 unsigned long cr2, int emulation_type)
4903{
4904 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4905 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4906
4907 last_retry_eip = vcpu->arch.last_retry_eip;
4908 last_retry_addr = vcpu->arch.last_retry_addr;
4909
4910 /*
4911 * If the emulation is caused by #PF and it is non-page_table
4912 * writing instruction, it means the VM-EXIT is caused by shadow
4913 * page protected, we can zap the shadow page and retry this
4914 * instruction directly.
4915 *
4916 * Note: if the guest uses a non-page-table modifying instruction
4917 * on the PDE that points to the instruction, then we will unmap
4918 * the instruction and go to an infinite loop. So, we cache the
4919 * last retried eip and the last fault address, if we meet the eip
4920 * and the address again, we can break out of the potential infinite
4921 * loop.
4922 */
4923 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4924
4925 if (!(emulation_type & EMULTYPE_RETRY))
4926 return false;
4927
4928 if (x86_page_table_writing_insn(ctxt))
4929 return false;
4930
4931 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4932 return false;
4933
4934 vcpu->arch.last_retry_eip = ctxt->eip;
4935 vcpu->arch.last_retry_addr = cr2;
4936
4937 if (!vcpu->arch.mmu.direct_map)
4938 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4939
22368028 4940 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4941
4942 return true;
4943}
4944
716d51ab
GN		 4945static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4946static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4947
4a1e10d5
PB		 4948static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4949 unsigned long *db)
4950{
4951 u32 dr6 = 0;
4952 int i;
4953 u32 enable, rwlen;
4954
4955 enable = dr7;
4956 rwlen = dr7 >> 16;
4957 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4958 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4959 dr6 |= (1 << i);
4960 return dr6;
4961}
4962
663f4c61
PB		 4963static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4964{
4965 struct kvm_run *kvm_run = vcpu->run;
4966
4967 /*
4968 * Use the "raw" value to see if TF was passed to the processor.
4969 * Note that the new value of the flags has not been saved yet.
4970 *
4971 * This is correct even for TF set by the guest, because "the
4972 * processor will not generate this exception after the instruction
4973 * that sets the TF flag".
4974 */
4975 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
4976
4977 if (unlikely(rflags & X86_EFLAGS_TF)) {
4978 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4979 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
4980 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
4981 kvm_run->debug.arch.exception = DB_VECTOR;
4982 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4983 *r = EMULATE_USER_EXIT;
4984 } else {
4985 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
4986 /*
4987 * "Certain debug exceptions may clear bit 0-3. The
4988 * remaining contents of the DR6 register are never
4989 * cleared by the processor".
4990 */
4991 vcpu->arch.dr6 &= ~15;
4992 vcpu->arch.dr6 |= DR6_BS;
4993 kvm_queue_exception(vcpu, DB_VECTOR);
4994 }
4995 }
4996}
4997
4a1e10d5
PB		 4998static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
4999{
5000 struct kvm_run *kvm_run = vcpu->run;
5001 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5002 u32 dr6 = 0;
5003
5004 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5005 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5006 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5007 vcpu->arch.guest_debug_dr7,
5008 vcpu->arch.eff_db);
5009
5010 if (dr6 != 0) {
5011 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5012 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5013 get_segment_base(vcpu, VCPU_SREG_CS);
5014
5015 kvm_run->debug.arch.exception = DB_VECTOR;
5016 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5017 *r = EMULATE_USER_EXIT;
5018 return true;
5019 }
5020 }
5021
5022 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5023 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5024 vcpu->arch.dr7,
5025 vcpu->arch.db);
5026
5027 if (dr6 != 0) {
5028 vcpu->arch.dr6 &= ~15;
5029 vcpu->arch.dr6 |= dr6;
5030 kvm_queue_exception(vcpu, DB_VECTOR);
5031 *r = EMULATE_DONE;
5032 return true;
5033 }
5034 }
5035
5036 return false;
5037}
5038
51d8b661
AP		 5039int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5040 unsigned long cr2,
dc25e89e
AP		 5041 int emulation_type,
5042 void *insn,
5043 int insn_len)
bbd9b64e 5044{
95cb2295 5045 int r;
9d74191a 5046 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5047 bool writeback = true;
93c05d3e 5048 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5049
93c05d3e
XG		 5050 /*
5051 * Clear write_fault_to_shadow_pgtable here to ensure it is
5052 * never reused.
5053 */
5054 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5055 kvm_clear_exception_queue(vcpu);
8d7d8102 5056
571008da 5057 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5058 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5059
5060 /*
5061 * We will reenter on the same instruction since
5062 * we do not set complete_userspace_io. This does not
5063 * handle watchpoints yet, those would be handled in
5064 * the emulate_ops.
5065 */
5066 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5067 return r;
5068
9d74191a
TY		 5069 ctxt->interruptibility = 0;
5070 ctxt->have_exception = false;
5071 ctxt->perm_ok = false;
bbd9b64e 5072
9d74191a 5073 ctxt->only_vendor_specific_insn
4005996e
AK		 5074 = emulation_type & EMULTYPE_TRAP_UD;
5075
9d74191a 5076 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5077
e46479f8 5078 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5079 ++vcpu->stat.insn_emulation;
1d2887e2 5080 if (r != EMULATION_OK) {
4005996e
AK		 5081 if (emulation_type & EMULTYPE_TRAP_UD)
5082 return EMULATE_FAIL;
991eebf9
GN		 5083 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5084 emulation_type))
bbd9b64e 5085 return EMULATE_DONE;
6d77dbfc
GN		 5086 if (emulation_type & EMULTYPE_SKIP)
5087 return EMULATE_FAIL;
5088 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5089 }
5090 }
5091
ba8afb6b 5092 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5093 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5094 return EMULATE_DONE;
5095 }
5096
1cb3f3ae
XG		 5097 if (retry_instruction(ctxt, cr2, emulation_type))
5098 return EMULATE_DONE;
5099
7ae441ea 5100 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5101 changes registers values during IO operation */
7ae441ea
GN		 5102 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5103 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5104 emulator_invalidate_register_cache(ctxt);
7ae441ea 5105 }
4d2179e1 5106
5cd21917 5107restart:
9d74191a 5108 r = x86_emulate_insn(ctxt);
bbd9b64e 5109
775fde86
JR		 5110 if (r == EMULATION_INTERCEPTED)
5111 return EMULATE_DONE;
5112
d2ddd1c4 5113 if (r == EMULATION_FAILED) {
991eebf9
GN		 5114 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5115 emulation_type))
c3cd7ffa
GN		 5116 return EMULATE_DONE;
5117
6d77dbfc 5118 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5119 }
5120
9d74191a 5121 if (ctxt->have_exception) {
54b8486f 5122 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5123 r = EMULATE_DONE;
5124 } else if (vcpu->arch.pio.count) {
3457e419
GN		 5125 if (!vcpu->arch.pio.in)
5126 vcpu->arch.pio.count = 0;
716d51ab 5127 else {
7ae441ea 5128 writeback = false;
716d51ab
GN		 5129 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5130 }
ac0a48c3 5131 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5132 } else if (vcpu->mmio_needed) {
5133 if (!vcpu->mmio_is_write)
5134 writeback = false;
ac0a48c3 5135 r = EMULATE_USER_EXIT;
716d51ab 5136 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5137 } else if (r == EMULATION_RESTART)
5cd21917 5138 goto restart;
d2ddd1c4
GN		 5139 else
5140 r = EMULATE_DONE;
f850e2e6 5141
7ae441ea 5142 if (writeback) {
9d74191a 5143 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5144 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5145 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5146 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5147 if (r == EMULATE_DONE)
5148 kvm_vcpu_check_singlestep(vcpu, &r);
5149 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5150 } else
5151 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5152
5153 return r;
de7d789a 5154}
51d8b661 5155EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5156
cf8f70bf 5157int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5158{
cf8f70bf 5159 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5160 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5161 size, port, &val, 1);
cf8f70bf 5162 /* do not return to emulator after return from userspace */
7972995b 5163 vcpu->arch.pio.count = 0;
de7d789a
CO		 5164 return ret;
5165}
cf8f70bf 5166EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5167
8cfdc000
ZA		 5168static void tsc_bad(void *info)
5169{
0a3aee0d 5170 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5171}
5172
5173static void tsc_khz_changed(void *data)
c8076604 5174{
8cfdc000
ZA		 5175 struct cpufreq_freqs *freq = data;
5176 unsigned long khz = 0;
5177
5178 if (data)
5179 khz = freq->new;
5180 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5181 khz = cpufreq_quick_get(raw_smp_processor_id());
5182 if (!khz)
5183 khz = tsc_khz;
0a3aee0d 5184 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5185}
5186
c8076604
GH		 5187static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5188 void *data)
5189{
5190 struct cpufreq_freqs *freq = data;
5191 struct kvm *kvm;
5192 struct kvm_vcpu *vcpu;
5193 int i, send_ipi = 0;
5194
8cfdc000
ZA		 5195 /*
5196 * We allow guests to temporarily run on slowing clocks,
5197 * provided we notify them after, or to run on accelerating
5198 * clocks, provided we notify them before. Thus time never
5199 * goes backwards.
5200 *
5201 * However, we have a problem. We can't atomically update
5202 * the frequency of a given CPU from this function; it is
5203 * merely a notifier, which can be called from any CPU.
5204 * Changing the TSC frequency at arbitrary points in time
5205 * requires a recomputation of local variables related to
5206 * the TSC for each VCPU. We must flag these local variables
5207 * to be updated and be sure the update takes place with the
5208 * new frequency before any guests proceed.
5209 *
5210 * Unfortunately, the combination of hotplug CPU and frequency
5211 * change creates an intractable locking scenario; the order
5212 * of when these callouts happen is undefined with respect to
5213 * CPU hotplug, and they can race with each other. As such,
5214 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5215 * undefined; you can actually have a CPU frequency change take
5216 * place in between the computation of X and the setting of the
5217 * variable. To protect against this problem, all updates of
5218 * the per_cpu tsc_khz variable are done in an interrupt
5219 * protected IPI, and all callers wishing to update the value
5220 * must wait for a synchronous IPI to complete (which is trivial
5221 * if the caller is on the CPU already). This establishes the
5222 * necessary total order on variable updates.
5223 *
5224 * Note that because a guest time update may take place
5225 * anytime after the setting of the VCPU's request bit, the
5226 * correct TSC value must be set before the request. However,
5227 * to ensure the update actually makes it to any guest which
5228 * starts running in hardware virtualization between the set
5229 * and the acquisition of the spinlock, we must also ping the
5230 * CPU after setting the request bit.
5231 *
5232 */
5233
c8076604
GH		 5234 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5235 return 0;
5236 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5237 return 0;
8cfdc000
ZA		 5238
5239 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5240
e935b837 5241 raw_spin_lock(&kvm_lock);
c8076604 5242 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5243 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5244 if (vcpu->cpu != freq->cpu)
5245 continue;
c285545f 5246 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5247 if (vcpu->cpu != smp_processor_id())
8cfdc000 5248 send_ipi = 1;
c8076604
GH		 5249 }
5250 }
e935b837 5251 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5252
5253 if (freq->old < freq->new && send_ipi) {
5254 /*
5255 * We upscale the frequency. Must make the guest
5256 * doesn't see old kvmclock values while running with
5257 * the new frequency, otherwise we risk the guest sees
5258 * time go backwards.
5259 *
5260 * In case we update the frequency for another cpu
5261 * (which might be in guest context) send an interrupt
5262 * to kick the cpu out of guest context. Next time
5263 * guest context is entered kvmclock will be updated,
5264 * so the guest will not see stale values.
5265 */
8cfdc000 5266 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5267 }
5268 return 0;
5269}
5270
5271static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5272 .notifier_call = kvmclock_cpufreq_notifier
5273};
5274
5275static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5276 unsigned long action, void *hcpu)
5277{
5278 unsigned int cpu = (unsigned long)hcpu;
5279
5280 switch (action) {
5281 case CPU_ONLINE:
5282 case CPU_DOWN_FAILED:
5283 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5284 break;
5285 case CPU_DOWN_PREPARE:
5286 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5287 break;
5288 }
5289 return NOTIFY_OK;
5290}
5291
5292static struct notifier_block kvmclock_cpu_notifier_block = {
5293 .notifier_call = kvmclock_cpu_notifier,
5294 .priority = -INT_MAX
c8076604
GH		 5295};
5296
b820cc0c
ZA		 5297static void kvm_timer_init(void)
5298{
5299 int cpu;
5300
c285545f 5301 max_tsc_khz = tsc_khz;
8cfdc000 5302 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5303 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5304#ifdef CONFIG_CPU_FREQ
5305 struct cpufreq_policy policy;
5306 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5307 cpu = get_cpu();
5308 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5309 if (policy.cpuinfo.max_freq)
5310 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5311 put_cpu();
c285545f 5312#endif
b820cc0c
ZA		 5313 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5314 CPUFREQ_TRANSITION_NOTIFIER);
5315 }
c285545f 5316 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5317 for_each_online_cpu(cpu)
5318 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5319}
5320
ff9d07a0
ZY		 5321static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5322
f5132b01 5323int kvm_is_in_guest(void)
ff9d07a0 5324{
086c9855 5325 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5326}
5327
5328static int kvm_is_user_mode(void)
5329{
5330 int user_mode = 3;
dcf46b94 5331
086c9855
AS		 5332 if (__this_cpu_read(current_vcpu))
5333 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5334
ff9d07a0
ZY		 5335 return user_mode != 0;
5336}
5337
5338static unsigned long kvm_get_guest_ip(void)
5339{
5340 unsigned long ip = 0;
dcf46b94 5341
086c9855
AS		 5342 if (__this_cpu_read(current_vcpu))
5343 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5344
ff9d07a0
ZY		 5345 return ip;
5346}
5347
5348static struct perf_guest_info_callbacks kvm_guest_cbs = {
5349 .is_in_guest = kvm_is_in_guest,
5350 .is_user_mode = kvm_is_user_mode,
5351 .get_guest_ip = kvm_get_guest_ip,
5352};
5353
5354void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5355{
086c9855 5356 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5357}
5358EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5359
5360void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5361{
086c9855 5362 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5363}
5364EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5365
ce88decf
XG		 5366static void kvm_set_mmio_spte_mask(void)
5367{
5368 u64 mask;
5369 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5370
5371 /*
5372 * Set the reserved bits and the present bit of an paging-structure
5373 * entry to generate page fault with PFER.RSV = 1.
5374 */
885032b9
XG		 5375 /* Mask the reserved physical address bits. */
5376 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5377
5378 /* Bit 62 is always reserved for 32bit host. */
5379 mask |= 0x3ull << 62;
5380
5381 /* Set the present bit. */
ce88decf
XG		 5382 mask |= 1ull;
5383
5384#ifdef CONFIG_X86_64
5385 /*
5386 * If reserved bit is not supported, clear the present bit to disable
5387 * mmio page fault.
5388 */
5389 if (maxphyaddr == 52)
5390 mask &= ~1ull;
5391#endif
5392
5393 kvm_mmu_set_mmio_spte_mask(mask);
5394}
5395
16e8d74d
MT		 5396#ifdef CONFIG_X86_64
5397static void pvclock_gtod_update_fn(struct work_struct *work)
5398{
d828199e
MT		 5399 struct kvm *kvm;
5400
5401 struct kvm_vcpu *vcpu;
5402 int i;
5403
5404 raw_spin_lock(&kvm_lock);
5405 list_for_each_entry(kvm, &vm_list, vm_list)
5406 kvm_for_each_vcpu(i, vcpu, kvm)
5407 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5408 atomic_set(&kvm_guest_has_master_clock, 0);
5409 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5410}
5411
5412static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5413
5414/*
5415 * Notification about pvclock gtod data update.
5416 */
5417static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5418 void *priv)
5419{
5420 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5421 struct timekeeper *tk = priv;
5422
5423 update_pvclock_gtod(tk);
5424
5425 /* disable master clock if host does not trust, or does not
5426 * use, TSC clocksource
5427 */
5428 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5429 atomic_read(&kvm_guest_has_master_clock) != 0)
5430 queue_work(system_long_wq, &pvclock_gtod_work);
5431
5432 return 0;
5433}
5434
5435static struct notifier_block pvclock_gtod_notifier = {
5436 .notifier_call = pvclock_gtod_notify,
5437};
5438#endif
5439
f8c16bba 5440int kvm_arch_init(void *opaque)
043405e1 5441{
b820cc0c 5442 int r;
6b61edf7 5443 struct kvm_x86_ops *ops = opaque;
f8c16bba 5444
f8c16bba
ZX		 5445 if (kvm_x86_ops) {
5446 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5447 r = -EEXIST;
5448 goto out;
f8c16bba
ZX		 5449 }
5450
5451 if (!ops->cpu_has_kvm_support()) {
5452 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5453 r = -EOPNOTSUPP;
5454 goto out;
f8c16bba
ZX		 5455 }
5456 if (ops->disabled_by_bios()) {
5457 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5458 r = -EOPNOTSUPP;
5459 goto out;
f8c16bba
ZX		 5460 }
5461
013f6a5d
MT		 5462 r = -ENOMEM;
5463 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5464 if (!shared_msrs) {
5465 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5466 goto out;
5467 }
5468
97db56ce
AK		 5469 r = kvm_mmu_module_init();
5470 if (r)
013f6a5d 5471 goto out_free_percpu;
97db56ce 5472
ce88decf 5473 kvm_set_mmio_spte_mask();
97db56ce
AK		 5474 kvm_init_msr_list();
5475
f8c16bba 5476 kvm_x86_ops = ops;
7b52345e 5477 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5478 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5479
b820cc0c 5480 kvm_timer_init();
c8076604 5481
ff9d07a0
ZY		 5482 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5483
2acf923e
DC		 5484 if (cpu_has_xsave)
5485 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5486
c5cc421b 5487 kvm_lapic_init();
16e8d74d
MT		 5488#ifdef CONFIG_X86_64
5489 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5490#endif
5491
f8c16bba 5492 return 0;
56c6d28a 5493
013f6a5d
MT		 5494out_free_percpu:
5495 free_percpu(shared_msrs);
56c6d28a 5496out:
56c6d28a 5497 return r;
043405e1 5498}
8776e519 5499
f8c16bba
ZX		 5500void kvm_arch_exit(void)
5501{
ff9d07a0
ZY		 5502 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5503
888d256e
JK		 5504 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5505 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5506 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5507 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5508#ifdef CONFIG_X86_64
5509 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5510#endif
f8c16bba 5511 kvm_x86_ops = NULL;
56c6d28a 5512 kvm_mmu_module_exit();
013f6a5d 5513 free_percpu(shared_msrs);
56c6d28a 5514}
f8c16bba 5515
8776e519
HB		 5516int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5517{
5518 ++vcpu->stat.halt_exits;
5519 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5520 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5521 return 1;
5522 } else {
5523 vcpu->run->exit_reason = KVM_EXIT_HLT;
5524 return 0;
5525 }
5526}
5527EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5528
55cd8e5a
GN		 5529int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5530{
5531 u64 param, ingpa, outgpa, ret;
5532 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5533 bool fast, longmode;
5534 int cs_db, cs_l;
5535
5536 /*
5537 * hypercall generates UD from non zero cpl and real mode
5538 * per HYPER-V spec
5539 */
3eeb3288 5540 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5541 kvm_queue_exception(vcpu, UD_VECTOR);
5542 return 0;
5543 }
5544
5545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5546 longmode = is_long_mode(vcpu) && cs_l == 1;
5547
5548 if (!longmode) {
ccd46936
GN		 5549 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5550 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5551 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5552 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5553 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5554 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5555 }
5556#ifdef CONFIG_X86_64
5557 else {
5558 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5559 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5560 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5561 }
5562#endif
5563
5564 code = param & 0xffff;
5565 fast = (param >> 16) & 0x1;
5566 rep_cnt = (param >> 32) & 0xfff;
5567 rep_idx = (param >> 48) & 0xfff;
5568
5569 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5570
c25bc163
GN		 5571 switch (code) {
5572 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5573 kvm_vcpu_on_spin(vcpu);
5574 break;
5575 default:
5576 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5577 break;
5578 }
55cd8e5a
GN		 5579
5580 ret = res | (((u64)rep_done & 0xfff) << 32);
5581 if (longmode) {
5582 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5583 } else {
5584 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5585 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5586 }
5587
5588 return 1;
5589}
5590
8776e519
HB		 5591int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5592{
5593 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5594 int r = 1;
8776e519 5595
55cd8e5a
GN		 5596 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5597 return kvm_hv_hypercall(vcpu);
5598
5fdbf976
MT		 5599 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5600 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5601 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5602 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5603 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5604
229456fc 5605 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5606
8776e519
HB		 5607 if (!is_long_mode(vcpu)) {
5608 nr &= 0xFFFFFFFF;
5609 a0 &= 0xFFFFFFFF;
5610 a1 &= 0xFFFFFFFF;
5611 a2 &= 0xFFFFFFFF;
5612 a3 &= 0xFFFFFFFF;
5613 }
5614
07708c4a
JK		 5615 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5616 ret = -KVM_EPERM;
5617 goto out;
5618 }
5619
8776e519 5620 switch (nr) {
b93463aa
AK		 5621 case KVM_HC_VAPIC_POLL_IRQ:
5622 ret = 0;
5623 break;
8776e519
HB		 5624 default:
5625 ret = -KVM_ENOSYS;
5626 break;
5627 }
07708c4a 5628out:
5fdbf976 5629 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5630 ++vcpu->stat.hypercalls;
2f333bcb 5631 return r;
8776e519
HB		 5632}
5633EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5634
b6785def 5635static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5636{
d6aa1000 5637 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5638 char instruction[3];
5fdbf976 5639 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5640
8776e519 5641 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5642
9d74191a 5643 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5644}
5645
b6c7a5dc
HB		 5646/*
5647 * Check if userspace requested an interrupt window, and that the
5648 * interrupt window is open.
5649 *
5650 * No need to exit to userspace if we already have an interrupt queued.
5651 */
851ba692 5652static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5653{
8061823a 5654 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5655 vcpu->run->request_interrupt_window &&
5df56646 5656 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5657}
5658
851ba692 5659static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5660{
851ba692
AK		 5661 struct kvm_run *kvm_run = vcpu->run;
5662
91586a3b 5663 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5664 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5665 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5666 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5667 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5668 else
b6c7a5dc 5669 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5670 kvm_arch_interrupt_allowed(vcpu) &&
5671 !kvm_cpu_has_interrupt(vcpu) &&
5672 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5673}
5674
4484141a 5675static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5676{
5677 struct kvm_lapic *apic = vcpu->arch.apic;
5678 struct page *page;
5679
5680 if (!apic || !apic->vapic_addr)
4484141a 5681 return 0;
b93463aa
AK		 5682
5683 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5684 if (is_error_page(page))
5685 return -EFAULT;
72dc67a6
IE		 5686
5687 vcpu->arch.apic->vapic_page = page;
4484141a 5688 return 0;
b93463aa
AK		 5689}
5690
5691static void vapic_exit(struct kvm_vcpu *vcpu)
5692{
5693 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5694 int idx;
b93463aa
AK		 5695
5696 if (!apic || !apic->vapic_addr)
5697 return;
5698
f656ce01 5699 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5700 kvm_release_page_dirty(apic->vapic_page);
5701 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5702 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5703}
5704
95ba8273
GN		 5705static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5706{
5707 int max_irr, tpr;
5708
5709 if (!kvm_x86_ops->update_cr8_intercept)
5710 return;
5711
88c808fd
AK		 5712 if (!vcpu->arch.apic)
5713 return;
5714
8db3baa2
GN		 5715 if (!vcpu->arch.apic->vapic_addr)
5716 max_irr = kvm_lapic_find_highest_irr(vcpu);
5717 else
5718 max_irr = -1;
95ba8273
GN		 5719
5720 if (max_irr != -1)
5721 max_irr >>= 4;
5722
5723 tpr = kvm_lapic_get_cr8(vcpu);
5724
5725 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5726}
5727
851ba692 5728static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5729{
5730 /* try to reinject previous events if any */
b59bb7bd 5731 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5732 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5733 vcpu->arch.exception.has_error_code,
5734 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5735 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5736 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5737 vcpu->arch.exception.error_code,
5738 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5739 return;
5740 }
5741
95ba8273
GN		 5742 if (vcpu->arch.nmi_injected) {
5743 kvm_x86_ops->set_nmi(vcpu);
5744 return;
5745 }
5746
5747 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5748 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5749 return;
5750 }
5751
5752 /* try to inject new event if pending */
5753 if (vcpu->arch.nmi_pending) {
5754 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5755 --vcpu->arch.nmi_pending;
95ba8273
GN		 5756 vcpu->arch.nmi_injected = true;
5757 kvm_x86_ops->set_nmi(vcpu);
5758 }
c7c9c56c 5759 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5760 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5761 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5762 false);
5763 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5764 }
5765 }
5766}
5767
7460fb4a
AK		 5768static void process_nmi(struct kvm_vcpu *vcpu)
5769{
5770 unsigned limit = 2;
5771
5772 /*
5773 * x86 is limited to one NMI running, and one NMI pending after it.
5774 * If an NMI is already in progress, limit further NMIs to just one.
5775 * Otherwise, allow two (and we'll inject the first one immediately).
5776 */
5777 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5778 limit = 1;
5779
5780 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5781 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5782 kvm_make_request(KVM_REQ_EVENT, vcpu);
5783}
5784
d828199e
MT		 5785static void kvm_gen_update_masterclock(struct kvm *kvm)
5786{
5787#ifdef CONFIG_X86_64
5788 int i;
5789 struct kvm_vcpu *vcpu;
5790 struct kvm_arch *ka = &kvm->arch;
5791
5792 spin_lock(&ka->pvclock_gtod_sync_lock);
5793 kvm_make_mclock_inprogress_request(kvm);
5794 /* no guest entries from this point */
5795 pvclock_update_vm_gtod_copy(kvm);
5796
5797 kvm_for_each_vcpu(i, vcpu, kvm)
5798 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5799
5800 /* guest entries allowed */
5801 kvm_for_each_vcpu(i, vcpu, kvm)
5802 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5803
5804 spin_unlock(&ka->pvclock_gtod_sync_lock);
5805#endif
5806}
5807
3d81bc7e 5808static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5809{
5810 u64 eoi_exit_bitmap[4];
cf9e65b7 5811 u32 tmr[8];
c7c9c56c 5812
3d81bc7e
YZ		 5813 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5814 return;
c7c9c56c
YZ		 5815
5816 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5817 memset(tmr, 0, 32);
c7c9c56c 5818
cf9e65b7 5819 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5820 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5821 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5822}
5823
851ba692 5824static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5825{
5826 int r;
6a8b1d13 5827 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5828 vcpu->run->request_interrupt_window;
730dca42 5829 bool req_immediate_exit = false;
b6c7a5dc 5830
3e007509 5831 if (vcpu->requests) {
a8eeb04a 5832 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5833 kvm_mmu_unload(vcpu);
a8eeb04a 5834 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5835 __kvm_migrate_timers(vcpu);
d828199e
MT		 5836 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5837 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5838 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5839 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5840 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5841 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5842 if (unlikely(r))
5843 goto out;
5844 }
a8eeb04a 5845 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5846 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5847 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5848 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5849 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5850 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5851 r = 0;
5852 goto out;
5853 }
a8eeb04a 5854 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5855 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5856 r = 0;
5857 goto out;
5858 }
a8eeb04a 5859 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5860 vcpu->fpu_active = 0;
5861 kvm_x86_ops->fpu_deactivate(vcpu);
5862 }
af585b92
GN		 5863 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5864 /* Page is swapped out. Do synthetic halt */
5865 vcpu->arch.apf.halted = true;
5866 r = 1;
5867 goto out;
5868 }
c9aaa895
GC		 5869 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5870 record_steal_time(vcpu);
7460fb4a
AK		 5871 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5872 process_nmi(vcpu);
f5132b01
GN		 5873 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5874 kvm_handle_pmu_event(vcpu);
5875 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5876 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5877 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5878 vcpu_scan_ioapic(vcpu);
2f52d58c 5879 }
b93463aa 5880
b463a6f7 5881 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5882 kvm_apic_accept_events(vcpu);
5883 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5884 r = 1;
5885 goto out;
5886 }
5887
b463a6f7
AK		 5888 inject_pending_event(vcpu);
5889
5890 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5891 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5892 req_immediate_exit =
5893 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5894 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5895 req_immediate_exit =
5896 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5897
5898 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5899 /*
5900 * Update architecture specific hints for APIC
5901 * virtual interrupt delivery.
5902 */
5903 if (kvm_x86_ops->hwapic_irr_update)
5904 kvm_x86_ops->hwapic_irr_update(vcpu,
5905 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5906 update_cr8_intercept(vcpu);
5907 kvm_lapic_sync_to_vapic(vcpu);
5908 }
5909 }
5910
d8368af8
AK		 5911 r = kvm_mmu_reload(vcpu);
5912 if (unlikely(r)) {
d905c069 5913 goto cancel_injection;
d8368af8
AK		 5914 }
5915
b6c7a5dc
HB		 5916 preempt_disable();
5917
5918 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5919 if (vcpu->fpu_active)
5920 kvm_load_guest_fpu(vcpu);
2acf923e 5921 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5922
6b7e2d09
XG		 5923 vcpu->mode = IN_GUEST_MODE;
5924
5925 /* We should set ->mode before check ->requests,
5926 * see the comment in make_all_cpus_request.
5927 */
5928 smp_mb();
b6c7a5dc 5929
d94e1dc9 5930 local_irq_disable();
32f88400 5931
6b7e2d09 5932 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5933 || need_resched() || signal_pending(current)) {
6b7e2d09 5934 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5935 smp_wmb();
6c142801
AK		 5936 local_irq_enable();
5937 preempt_enable();
5938 r = 1;
d905c069 5939 goto cancel_injection;
6c142801
AK		 5940 }
5941
f656ce01 5942 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5943
d6185f20
NHE		 5944 if (req_immediate_exit)
5945 smp_send_reschedule(vcpu->cpu);
5946
b6c7a5dc
HB		 5947 kvm_guest_enter();
5948
42dbaa5a 5949 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5950 set_debugreg(0, 7);
5951 set_debugreg(vcpu->arch.eff_db[0], 0);
5952 set_debugreg(vcpu->arch.eff_db[1], 1);
5953 set_debugreg(vcpu->arch.eff_db[2], 2);
5954 set_debugreg(vcpu->arch.eff_db[3], 3);
5955 }
b6c7a5dc 5956
229456fc 5957 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5958 kvm_x86_ops->run(vcpu);
b6c7a5dc 5959
24f1e32c
FW		 5960 /*
5961 * If the guest has used debug registers, at least dr7
5962 * will be disabled while returning to the host.
5963 * If we don't have active breakpoints in the host, we don't
5964 * care about the messed up debug address registers. But if
5965 * we have some of them active, restore the old state.
5966 */
59d8eb53 5967 if (hw_breakpoint_active())
24f1e32c 5968 hw_breakpoint_restore();
42dbaa5a 5969
886b470c
MT		 5970 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5971 native_read_tsc());
1d5f066e 5972
6b7e2d09 5973 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5974 smp_wmb();
a547c6db
YZ		 5975
5976 /* Interrupt is enabled by handle_external_intr() */
5977 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5978
5979 ++vcpu->stat.exits;
5980
5981 /*
5982 * We must have an instruction between local_irq_enable() and
5983 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5984 * the interrupt shadow. The stat.exits increment will do nicely.
5985 * But we need to prevent reordering, hence this barrier():
5986 */
5987 barrier();
5988
5989 kvm_guest_exit();
5990
5991 preempt_enable();
5992
f656ce01 5993 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5994
b6c7a5dc
HB		 5995 /*
5996 * Profile KVM exit RIPs:
5997 */
5998 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5999 unsigned long rip = kvm_rip_read(vcpu);
6000 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6001 }
6002
cc578287
ZA		 6003 if (unlikely(vcpu->arch.tsc_always_catchup))
6004 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6005
5cfb1d5a
MT		 6006 if (vcpu->arch.apic_attention)
6007 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6008
851ba692 6009 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6010 return r;
6011
6012cancel_injection:
6013 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6014 if (unlikely(vcpu->arch.apic_attention))
6015 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6016out:
6017 return r;
6018}
b6c7a5dc 6019
09cec754 6020
851ba692 6021static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6022{
6023 int r;
f656ce01 6024 struct kvm *kvm = vcpu->kvm;
d7690175 6025
f656ce01 6026 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6027 r = vapic_enter(vcpu);
6028 if (r) {
6029 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6030 return r;
6031 }
d7690175
MT		 6032
6033 r = 1;
6034 while (r > 0) {
af585b92
GN		 6035 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6036 !vcpu->arch.apf.halted)
851ba692 6037 r = vcpu_enter_guest(vcpu);
d7690175 6038 else {
f656ce01 6039 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6040 kvm_vcpu_block(vcpu);
f656ce01 6041 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6042 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6043 kvm_apic_accept_events(vcpu);
09cec754
GN		 6044 switch(vcpu->arch.mp_state) {
6045 case KVM_MP_STATE_HALTED:
d7690175 6046 vcpu->arch.mp_state =
09cec754
GN		 6047 KVM_MP_STATE_RUNNABLE;
6048 case KVM_MP_STATE_RUNNABLE:
af585b92 6049 vcpu->arch.apf.halted = false;
09cec754 6050 break;
66450a21
JK		 6051 case KVM_MP_STATE_INIT_RECEIVED:
6052 break;
09cec754
GN		 6053 default:
6054 r = -EINTR;
6055 break;
6056 }
6057 }
d7690175
MT		 6058 }
6059
09cec754
GN		 6060 if (r <= 0)
6061 break;
6062
6063 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6064 if (kvm_cpu_has_pending_timer(vcpu))
6065 kvm_inject_pending_timer_irqs(vcpu);
6066
851ba692 6067 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6068 r = -EINTR;
851ba692 6069 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6070 ++vcpu->stat.request_irq_exits;
6071 }
af585b92
GN		 6072
6073 kvm_check_async_pf_completion(vcpu);
6074
09cec754
GN		 6075 if (signal_pending(current)) {
6076 r = -EINTR;
851ba692 6077 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6078 ++vcpu->stat.signal_exits;
6079 }
6080 if (need_resched()) {
f656ce01 6081 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 6082 kvm_resched(vcpu);
f656ce01 6083 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6084 }
b6c7a5dc
HB		 6085 }
6086
f656ce01 6087 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6088
b93463aa
AK		 6089 vapic_exit(vcpu);
6090
b6c7a5dc
HB		 6091 return r;
6092}
6093
716d51ab
GN		 6094static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6095{
6096 int r;
6097 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6098 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6099 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6100 if (r != EMULATE_DONE)
6101 return 0;
6102 return 1;
6103}
6104
6105static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6106{
6107 BUG_ON(!vcpu->arch.pio.count);
6108
6109 return complete_emulated_io(vcpu);
6110}
6111
f78146b0
AK		 6112/*
6113 * Implements the following, as a state machine:
6114 *
6115 * read:
6116 * for each fragment
87da7e66
XG		 6117 * for each mmio piece in the fragment
6118 * write gpa, len
6119 * exit
6120 * copy data
f78146b0
AK		 6121 * execute insn
6122 *
6123 * write:
6124 * for each fragment
87da7e66
XG		 6125 * for each mmio piece in the fragment
6126 * write gpa, len
6127 * copy data
6128 * exit
f78146b0 6129 */
716d51ab 6130static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6131{
6132 struct kvm_run *run = vcpu->run;
f78146b0 6133 struct kvm_mmio_fragment *frag;
87da7e66 6134 unsigned len;
5287f194 6135
716d51ab 6136 BUG_ON(!vcpu->mmio_needed);
5287f194 6137
716d51ab 6138 /* Complete previous fragment */
87da7e66
XG		 6139 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6140 len = min(8u, frag->len);
716d51ab 6141 if (!vcpu->mmio_is_write)
87da7e66
XG		 6142 memcpy(frag->data, run->mmio.data, len);
6143
6144 if (frag->len <= 8) {
6145 /* Switch to the next fragment. */
6146 frag++;
6147 vcpu->mmio_cur_fragment++;
6148 } else {
6149 /* Go forward to the next mmio piece. */
6150 frag->data += len;
6151 frag->gpa += len;
6152 frag->len -= len;
6153 }
6154
716d51ab
GN		 6155 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6156 vcpu->mmio_needed = 0;
cef4dea0 6157 if (vcpu->mmio_is_write)
716d51ab
GN		 6158 return 1;
6159 vcpu->mmio_read_completed = 1;
6160 return complete_emulated_io(vcpu);
6161 }
87da7e66 6162
716d51ab
GN		 6163 run->exit_reason = KVM_EXIT_MMIO;
6164 run->mmio.phys_addr = frag->gpa;
6165 if (vcpu->mmio_is_write)
87da7e66
XG		 6166 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6167 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6168 run->mmio.is_write = vcpu->mmio_is_write;
6169 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6170 return 0;
5287f194
AK		 6171}
6172
716d51ab 6173
b6c7a5dc
HB		 6174int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6175{
6176 int r;
6177 sigset_t sigsaved;
6178
e5c30142
AK		 6179 if (!tsk_used_math(current) && init_fpu(current))
6180 return -ENOMEM;
6181
ac9f6dc0
AK		 6182 if (vcpu->sigset_active)
6183 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6184
a4535290 6185 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6186 kvm_vcpu_block(vcpu);
66450a21 6187 kvm_apic_accept_events(vcpu);
d7690175 6188 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6189 r = -EAGAIN;
6190 goto out;
b6c7a5dc
HB		 6191 }
6192
b6c7a5dc 6193 /* re-sync apic's tpr */
eea1cff9
AP		 6194 if (!irqchip_in_kernel(vcpu->kvm)) {
6195 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6196 r = -EINVAL;
6197 goto out;
6198 }
6199 }
b6c7a5dc 6200
716d51ab
GN		 6201 if (unlikely(vcpu->arch.complete_userspace_io)) {
6202 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6203 vcpu->arch.complete_userspace_io = NULL;
6204 r = cui(vcpu);
6205 if (r <= 0)
6206 goto out;
6207 } else
6208 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6209
851ba692 6210 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6211
6212out:
f1d86e46 6213 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6214 if (vcpu->sigset_active)
6215 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6216
b6c7a5dc
HB		 6217 return r;
6218}
6219
6220int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6221{
7ae441ea
GN		 6222 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6223 /*
6224 * We are here if userspace calls get_regs() in the middle of
6225 * instruction emulation. Registers state needs to be copied
4a969980 6226 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6227 * that usually, but some bad designed PV devices (vmware
6228 * backdoor interface) need this to work
6229 */
dd856efa 6230 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6231 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6232 }
5fdbf976
MT		 6233 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6234 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6235 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6236 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6237 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6238 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6239 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6240 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6241#ifdef CONFIG_X86_64
5fdbf976
MT		 6242 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6243 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6244 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6245 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6246 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6247 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6248 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6249 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6250#endif
6251
5fdbf976 6252 regs->rip = kvm_rip_read(vcpu);
91586a3b 6253 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6254
b6c7a5dc
HB		 6255 return 0;
6256}
6257
6258int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6259{
7ae441ea
GN		 6260 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6261 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6262
5fdbf976
MT		 6263 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6264 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6265 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6266 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6267 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6268 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6269 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6270 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6271#ifdef CONFIG_X86_64
5fdbf976
MT		 6272 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6273 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6274 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6275 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6276 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6277 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6278 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6279 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6280#endif
6281
5fdbf976 6282 kvm_rip_write(vcpu, regs->rip);
91586a3b 6283 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6284
b4f14abd
JK		 6285 vcpu->arch.exception.pending = false;
6286
3842d135
AK		 6287 kvm_make_request(KVM_REQ_EVENT, vcpu);
6288
b6c7a5dc
HB		 6289 return 0;
6290}
6291
b6c7a5dc
HB		 6292void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6293{
6294 struct kvm_segment cs;
6295
3e6e0aab 6296 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6297 *db = cs.db;
6298 *l = cs.l;
6299}
6300EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6301
6302int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6303 struct kvm_sregs *sregs)
6304{
89a27f4d 6305 struct desc_ptr dt;
b6c7a5dc 6306
3e6e0aab
GT		 6307 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6308 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6309 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6310 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6311 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6312 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6313
3e6e0aab
GT		 6314 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6315 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6316
6317 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6318 sregs->idt.limit = dt.size;
6319 sregs->idt.base = dt.address;
b6c7a5dc 6320 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6321 sregs->gdt.limit = dt.size;
6322 sregs->gdt.base = dt.address;
b6c7a5dc 6323
4d4ec087 6324 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6325 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6326 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6327 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6328 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6329 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6330 sregs->apic_base = kvm_get_apic_base(vcpu);
6331
923c61bb 6332 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6333
36752c9b 6334 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6335 set_bit(vcpu->arch.interrupt.nr,
6336 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6337
b6c7a5dc
HB		 6338 return 0;
6339}
6340
62d9f0db
MT		 6341int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6342 struct kvm_mp_state *mp_state)
6343{
66450a21 6344 kvm_apic_accept_events(vcpu);
62d9f0db 6345 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6346 return 0;
6347}
6348
6349int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6350 struct kvm_mp_state *mp_state)
6351{
66450a21
JK		 6352 if (!kvm_vcpu_has_lapic(vcpu) &&
6353 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6354 return -EINVAL;
6355
6356 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6357 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6358 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6359 } else
6360 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6361 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6362 return 0;
6363}
6364
7f3d35fd
KW		 6365int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6366 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6367{
9d74191a 6368 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6369 int ret;
e01c2426 6370
8ec4722d 6371 init_emulate_ctxt(vcpu);
c697518a 6372
7f3d35fd 6373 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6374 has_error_code, error_code);
c697518a 6375
c697518a 6376 if (ret)
19d04437 6377 return EMULATE_FAIL;
37817f29 6378
9d74191a
TY		 6379 kvm_rip_write(vcpu, ctxt->eip);
6380 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6381 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6382 return EMULATE_DONE;
37817f29
IE		 6383}
6384EXPORT_SYMBOL_GPL(kvm_task_switch);
6385
b6c7a5dc
HB		 6386int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6387 struct kvm_sregs *sregs)
6388{
6389 int mmu_reset_needed = 0;
63f42e02 6390 int pending_vec, max_bits, idx;
89a27f4d 6391 struct desc_ptr dt;
b6c7a5dc 6392
6d1068b3
PM		 6393 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6394 return -EINVAL;
6395
89a27f4d
GN		 6396 dt.size = sregs->idt.limit;
6397 dt.address = sregs->idt.base;
b6c7a5dc 6398 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6399 dt.size = sregs->gdt.limit;
6400 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6401 kvm_x86_ops->set_gdt(vcpu, &dt);
6402
ad312c7c 6403 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6404 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6405 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6406 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6407
2d3ad1f4 6408 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6409
f6801dff 6410 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6411 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6412 kvm_set_apic_base(vcpu, sregs->apic_base);
6413
4d4ec087 6414 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6415 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6416 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6417
fc78f519 6418 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6419 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6420 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6421 kvm_update_cpuid(vcpu);
63f42e02
XG		 6422
6423 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6424 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6425 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6426 mmu_reset_needed = 1;
6427 }
63f42e02 6428 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6429
6430 if (mmu_reset_needed)
6431 kvm_mmu_reset_context(vcpu);
6432
a50abc3b 6433 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6434 pending_vec = find_first_bit(
6435 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6436 if (pending_vec < max_bits) {
66fd3f7f 6437 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6438 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6439 }
6440
3e6e0aab
GT		 6441 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6442 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6443 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6444 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6445 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6446 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6447
3e6e0aab
GT		 6448 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6449 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6450
5f0269f5
ME		 6451 update_cr8_intercept(vcpu);
6452
9c3e4aab 6453 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6454 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6455 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6456 !is_protmode(vcpu))
9c3e4aab
MT		 6457 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6458
3842d135
AK		 6459 kvm_make_request(KVM_REQ_EVENT, vcpu);
6460
b6c7a5dc
HB		 6461 return 0;
6462}
6463
d0bfb940
JK		 6464int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6465 struct kvm_guest_debug *dbg)
b6c7a5dc 6466{
355be0b9 6467 unsigned long rflags;
ae675ef0 6468 int i, r;
b6c7a5dc 6469
4f926bf2
JK		 6470 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6471 r = -EBUSY;
6472 if (vcpu->arch.exception.pending)
2122ff5e 6473 goto out;
4f926bf2
JK		 6474 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6475 kvm_queue_exception(vcpu, DB_VECTOR);
6476 else
6477 kvm_queue_exception(vcpu, BP_VECTOR);
6478 }
6479
91586a3b
JK		 6480 /*
6481 * Read rflags as long as potentially injected trace flags are still
6482 * filtered out.
6483 */
6484 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6485
6486 vcpu->guest_debug = dbg->control;
6487 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6488 vcpu->guest_debug = 0;
6489
6490 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6491 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6492 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6493 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6494 } else {
6495 for (i = 0; i < KVM_NR_DB_REGS; i++)
6496 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6497 }
c8639010 6498 kvm_update_dr7(vcpu);
ae675ef0 6499
f92653ee
JK		 6500 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6501 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6502 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6503
91586a3b
JK		 6504 /*
6505 * Trigger an rflags update that will inject or remove the trace
6506 * flags.
6507 */
6508 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6509
c8639010 6510 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6511
4f926bf2 6512 r = 0;
d0bfb940 6513
2122ff5e 6514out:
b6c7a5dc
HB		 6515
6516 return r;
6517}
6518
8b006791
ZX		 6519/*
6520 * Translate a guest virtual address to a guest physical address.
6521 */
6522int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6523 struct kvm_translation *tr)
6524{
6525 unsigned long vaddr = tr->linear_address;
6526 gpa_t gpa;
f656ce01 6527 int idx;
8b006791 6528
f656ce01 6529 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6530 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6531 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6532 tr->physical_address = gpa;
6533 tr->valid = gpa != UNMAPPED_GVA;
6534 tr->writeable = 1;
6535 tr->usermode = 0;
8b006791
ZX		 6536
6537 return 0;
6538}
6539
d0752060
HB		 6540int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6541{
98918833
SY		 6542 struct i387_fxsave_struct *fxsave =
6543 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6544
d0752060
HB		 6545 memcpy(fpu->fpr, fxsave->st_space, 128);
6546 fpu->fcw = fxsave->cwd;
6547 fpu->fsw = fxsave->swd;
6548 fpu->ftwx = fxsave->twd;
6549 fpu->last_opcode = fxsave->fop;
6550 fpu->last_ip = fxsave->rip;
6551 fpu->last_dp = fxsave->rdp;
6552 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6553
d0752060
HB		 6554 return 0;
6555}
6556
6557int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6558{
98918833
SY		 6559 struct i387_fxsave_struct *fxsave =
6560 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6561
d0752060
HB		 6562 memcpy(fxsave->st_space, fpu->fpr, 128);
6563 fxsave->cwd = fpu->fcw;
6564 fxsave->swd = fpu->fsw;
6565 fxsave->twd = fpu->ftwx;
6566 fxsave->fop = fpu->last_opcode;
6567 fxsave->rip = fpu->last_ip;
6568 fxsave->rdp = fpu->last_dp;
6569 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6570
d0752060
HB		 6571 return 0;
6572}
6573
10ab25cd 6574int fx_init(struct kvm_vcpu *vcpu)
d0752060 6575{
10ab25cd
JK		 6576 int err;
6577
6578 err = fpu_alloc(&vcpu->arch.guest_fpu);
6579 if (err)
6580 return err;
6581
98918833 6582 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6583
2acf923e
DC		 6584 /*
6585 * Ensure guest xcr0 is valid for loading
6586 */
6587 vcpu->arch.xcr0 = XSTATE_FP;
6588
ad312c7c 6589 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6590
6591 return 0;
d0752060
HB		 6592}
6593EXPORT_SYMBOL_GPL(fx_init);
6594
98918833
SY		 6595static void fx_free(struct kvm_vcpu *vcpu)
6596{
6597 fpu_free(&vcpu->arch.guest_fpu);
6598}
6599
d0752060
HB		 6600void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6601{
2608d7a1 6602 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6603 return;
6604
2acf923e
DC		 6605 /*
6606 * Restore all possible states in the guest,
6607 * and assume host would use all available bits.
6608 * Guest xcr0 would be loaded later.
6609 */
6610 kvm_put_guest_xcr0(vcpu);
d0752060 6611 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6612 __kernel_fpu_begin();
98918833 6613 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6614 trace_kvm_fpu(1);
d0752060 6615}
d0752060
HB		 6616
6617void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6618{
2acf923e
DC		 6619 kvm_put_guest_xcr0(vcpu);
6620
d0752060
HB		 6621 if (!vcpu->guest_fpu_loaded)
6622 return;
6623
6624 vcpu->guest_fpu_loaded = 0;
98918833 6625 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6626 __kernel_fpu_end();
f096ed85 6627 ++vcpu->stat.fpu_reload;
a8eeb04a 6628 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6629 trace_kvm_fpu(0);
d0752060 6630}
e9b11c17
ZX		 6631
6632void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6633{
12f9a48f 6634 kvmclock_reset(vcpu);
7f1ea208 6635
f5f48ee1 6636 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6637 fx_free(vcpu);
e9b11c17
ZX		 6638 kvm_x86_ops->vcpu_free(vcpu);
6639}
6640
6641struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6642 unsigned int id)
6643{
6755bae8
ZA		 6644 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6645 printk_once(KERN_WARNING
6646 "kvm: SMP vm created on host with unstable TSC; "
6647 "guest TSC will not be reliable\n");
26e5215f
AK		 6648 return kvm_x86_ops->vcpu_create(kvm, id);
6649}
e9b11c17 6650
26e5215f
AK		 6651int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6652{
6653 int r;
e9b11c17 6654
0bed3b56 6655 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6656 r = vcpu_load(vcpu);
6657 if (r)
6658 return r;
57f252f2
JK		 6659 kvm_vcpu_reset(vcpu);
6660 r = kvm_mmu_setup(vcpu);
e9b11c17 6661 vcpu_put(vcpu);
e9b11c17 6662
26e5215f 6663 return r;
e9b11c17
ZX		 6664}
6665
42897d86
MT		 6666int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6667{
6668 int r;
8fe8ab46 6669 struct msr_data msr;
42897d86
MT		 6670
6671 r = vcpu_load(vcpu);
6672 if (r)
6673 return r;
8fe8ab46
WA		 6674 msr.data = 0x0;
6675 msr.index = MSR_IA32_TSC;
6676 msr.host_initiated = true;
6677 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6678 vcpu_put(vcpu);
6679
6680 return r;
6681}
6682
d40ccc62 6683void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6684{
9fc77441 6685 int r;
344d9588
GN		 6686 vcpu->arch.apf.msr_val = 0;
6687
9fc77441
MT		 6688 r = vcpu_load(vcpu);
6689 BUG_ON(r);
e9b11c17
ZX		 6690 kvm_mmu_unload(vcpu);
6691 vcpu_put(vcpu);
6692
98918833 6693 fx_free(vcpu);
e9b11c17
ZX		 6694 kvm_x86_ops->vcpu_free(vcpu);
6695}
6696
66450a21 6697void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6698{
7460fb4a
AK		 6699 atomic_set(&vcpu->arch.nmi_queued, 0);
6700 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6701 vcpu->arch.nmi_injected = false;
6702
42dbaa5a
JK		 6703 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6704 vcpu->arch.dr6 = DR6_FIXED_1;
6705 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6706 kvm_update_dr7(vcpu);
42dbaa5a 6707
3842d135 6708 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6709 vcpu->arch.apf.msr_val = 0;
c9aaa895 6710 vcpu->arch.st.msr_val = 0;
3842d135 6711
12f9a48f
GC		 6712 kvmclock_reset(vcpu);
6713
af585b92
GN		 6714 kvm_clear_async_pf_completion_queue(vcpu);
6715 kvm_async_pf_hash_reset(vcpu);
6716 vcpu->arch.apf.halted = false;
3842d135 6717
f5132b01
GN		 6718 kvm_pmu_reset(vcpu);
6719
66f7b72e
JS		 6720 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6721 vcpu->arch.regs_avail = ~0;
6722 vcpu->arch.regs_dirty = ~0;
6723
57f252f2 6724 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6725}
6726
66450a21
JK		 6727void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6728{
6729 struct kvm_segment cs;
6730
6731 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6732 cs.selector = vector << 8;
6733 cs.base = vector << 12;
6734 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6735 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6736}
6737
10474ae8 6738int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6739{
ca84d1a2
ZA		 6740 struct kvm *kvm;
6741 struct kvm_vcpu *vcpu;
6742 int i;
0dd6a6ed
ZA		 6743 int ret;
6744 u64 local_tsc;
6745 u64 max_tsc = 0;
6746 bool stable, backwards_tsc = false;
18863bdd
AK		 6747
6748 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6749 ret = kvm_x86_ops->hardware_enable(garbage);
6750 if (ret != 0)
6751 return ret;
6752
6753 local_tsc = native_read_tsc();
6754 stable = !check_tsc_unstable();
6755 list_for_each_entry(kvm, &vm_list, vm_list) {
6756 kvm_for_each_vcpu(i, vcpu, kvm) {
6757 if (!stable && vcpu->cpu == smp_processor_id())
6758 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6759 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6760 backwards_tsc = true;
6761 if (vcpu->arch.last_host_tsc > max_tsc)
6762 max_tsc = vcpu->arch.last_host_tsc;
6763 }
6764 }
6765 }
6766
6767 /*
6768 * Sometimes, even reliable TSCs go backwards. This happens on
6769 * platforms that reset TSC during suspend or hibernate actions, but
6770 * maintain synchronization. We must compensate. Fortunately, we can
6771 * detect that condition here, which happens early in CPU bringup,
6772 * before any KVM threads can be running. Unfortunately, we can't
6773 * bring the TSCs fully up to date with real time, as we aren't yet far
6774 * enough into CPU bringup that we know how much real time has actually
6775 * elapsed; our helper function, get_kernel_ns() will be using boot
6776 * variables that haven't been updated yet.
6777 *
6778 * So we simply find the maximum observed TSC above, then record the
6779 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6780 * the adjustment will be applied. Note that we accumulate
6781 * adjustments, in case multiple suspend cycles happen before some VCPU
6782 * gets a chance to run again. In the event that no KVM threads get a
6783 * chance to run, we will miss the entire elapsed period, as we'll have
6784 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6785 * loose cycle time. This isn't too big a deal, since the loss will be
6786 * uniform across all VCPUs (not to mention the scenario is extremely
6787 * unlikely). It is possible that a second hibernate recovery happens
6788 * much faster than a first, causing the observed TSC here to be
6789 * smaller; this would require additional padding adjustment, which is
6790 * why we set last_host_tsc to the local tsc observed here.
6791 *
6792 * N.B. - this code below runs only on platforms with reliable TSC,
6793 * as that is the only way backwards_tsc is set above. Also note
6794 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6795 * have the same delta_cyc adjustment applied if backwards_tsc
6796 * is detected. Note further, this adjustment is only done once,
6797 * as we reset last_host_tsc on all VCPUs to stop this from being
6798 * called multiple times (one for each physical CPU bringup).
6799 *
4a969980 6800 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6801 * will be compensated by the logic in vcpu_load, which sets the TSC to
6802 * catchup mode. This will catchup all VCPUs to real time, but cannot
6803 * guarantee that they stay in perfect synchronization.
6804 */
6805 if (backwards_tsc) {
6806 u64 delta_cyc = max_tsc - local_tsc;
6807 list_for_each_entry(kvm, &vm_list, vm_list) {
6808 kvm_for_each_vcpu(i, vcpu, kvm) {
6809 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6810 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6811 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6812 &vcpu->requests);
0dd6a6ed
ZA		 6813 }
6814
6815 /*
6816 * We have to disable TSC offset matching.. if you were
6817 * booting a VM while issuing an S4 host suspend....
6818 * you may have some problem. Solving this issue is
6819 * left as an exercise to the reader.
6820 */
6821 kvm->arch.last_tsc_nsec = 0;
6822 kvm->arch.last_tsc_write = 0;
6823 }
6824
6825 }
6826 return 0;
e9b11c17
ZX		 6827}
6828
6829void kvm_arch_hardware_disable(void *garbage)
6830{
6831 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6832 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6833}
6834
6835int kvm_arch_hardware_setup(void)
6836{
6837 return kvm_x86_ops->hardware_setup();
6838}
6839
6840void kvm_arch_hardware_unsetup(void)
6841{
6842 kvm_x86_ops->hardware_unsetup();
6843}
6844
6845void kvm_arch_check_processor_compat(void *rtn)
6846{
6847 kvm_x86_ops->check_processor_compatibility(rtn);
6848}
6849
3e515705
AK		 6850bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6851{
6852 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6853}
6854
54e9818f
GN		 6855struct static_key kvm_no_apic_vcpu __read_mostly;
6856
e9b11c17
ZX		 6857int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6858{
6859 struct page *page;
6860 struct kvm *kvm;
6861 int r;
6862
6863 BUG_ON(vcpu->kvm == NULL);
6864 kvm = vcpu->kvm;
6865
9aabc88f 6866 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6867 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6868 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6869 else
a4535290 6870 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6871
6872 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6873 if (!page) {
6874 r = -ENOMEM;
6875 goto fail;
6876 }
ad312c7c 6877 vcpu->arch.pio_data = page_address(page);
e9b11c17 6878
cc578287 6879 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6880
e9b11c17
ZX		 6881 r = kvm_mmu_create(vcpu);
6882 if (r < 0)
6883 goto fail_free_pio_data;
6884
6885 if (irqchip_in_kernel(kvm)) {
6886 r = kvm_create_lapic(vcpu);
6887 if (r < 0)
6888 goto fail_mmu_destroy;
54e9818f
GN		 6889 } else
6890 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6891
890ca9ae
HY		 6892 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6893 GFP_KERNEL);
6894 if (!vcpu->arch.mce_banks) {
6895 r = -ENOMEM;
443c39bc 6896 goto fail_free_lapic;
890ca9ae
HY		 6897 }
6898 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6899
f1797359
WY		 6900 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6901 r = -ENOMEM;
f5f48ee1 6902 goto fail_free_mce_banks;
f1797359 6903 }
f5f48ee1 6904
66f7b72e
JS		 6905 r = fx_init(vcpu);
6906 if (r)
6907 goto fail_free_wbinvd_dirty_mask;
6908
ba904635 6909 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6910 vcpu->arch.pv_time_enabled = false;
af585b92 6911 kvm_async_pf_hash_reset(vcpu);
f5132b01 6912 kvm_pmu_init(vcpu);
af585b92 6913
e9b11c17 6914 return 0;
66f7b72e
JS		 6915fail_free_wbinvd_dirty_mask:
6916 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6917fail_free_mce_banks:
6918 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6919fail_free_lapic:
6920 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6921fail_mmu_destroy:
6922 kvm_mmu_destroy(vcpu);
6923fail_free_pio_data:
ad312c7c 6924 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6925fail:
6926 return r;
6927}
6928
6929void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6930{
f656ce01
MT		 6931 int idx;
6932
f5132b01 6933 kvm_pmu_destroy(vcpu);
36cb93fd 6934 kfree(vcpu->arch.mce_banks);
e9b11c17 6935 kvm_free_lapic(vcpu);
f656ce01 6936 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6937 kvm_mmu_destroy(vcpu);
f656ce01 6938 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6939 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6940 if (!irqchip_in_kernel(vcpu->kvm))
6941 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6942}
d19a9cd2 6943
e08b9637 6944int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6945{
e08b9637
CO		 6946 if (type)
6947 return -EINVAL;
6948
f05e70ac 6949 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6950 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 6951 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6952
5550af4d
SY		 6953 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6954 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6955 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6956 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6957 &kvm->arch.irq_sources_bitmap);
5550af4d 6958
038f8c11 6959 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6960 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6961 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6962
6963 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6964
d89f5eff 6965 return 0;
d19a9cd2
ZX		 6966}
6967
6968static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6969{
9fc77441
MT		 6970 int r;
6971 r = vcpu_load(vcpu);
6972 BUG_ON(r);
d19a9cd2
ZX		 6973 kvm_mmu_unload(vcpu);
6974 vcpu_put(vcpu);
6975}
6976
6977static void kvm_free_vcpus(struct kvm *kvm)
6978{
6979 unsigned int i;
988a2cae 6980 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6981
6982 /*
6983 * Unpin any mmu pages first.
6984 */
af585b92
GN		 6985 kvm_for_each_vcpu(i, vcpu, kvm) {
6986 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6987 kvm_unload_vcpu_mmu(vcpu);
af585b92 6988 }
988a2cae
GN		 6989 kvm_for_each_vcpu(i, vcpu, kvm)
6990 kvm_arch_vcpu_free(vcpu);
6991
6992 mutex_lock(&kvm->lock);
6993 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6994 kvm->vcpus[i] = NULL;
d19a9cd2 6995
988a2cae
GN		 6996 atomic_set(&kvm->online_vcpus, 0);
6997 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6998}
6999
ad8ba2cd
SY		 7000void kvm_arch_sync_events(struct kvm *kvm)
7001{
ba4cef31 7002 kvm_free_all_assigned_devices(kvm);
aea924f6 7003 kvm_free_pit(kvm);
ad8ba2cd
SY		 7004}
7005
d19a9cd2
ZX		 7006void kvm_arch_destroy_vm(struct kvm *kvm)
7007{
27469d29
AH		 7008 if (current->mm == kvm->mm) {
7009 /*
7010 * Free memory regions allocated on behalf of userspace,
7011 * unless the the memory map has changed due to process exit
7012 * or fd copying.
7013 */
7014 struct kvm_userspace_memory_region mem;
7015 memset(&mem, 0, sizeof(mem));
7016 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7017 kvm_set_memory_region(kvm, &mem);
7018
7019 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7020 kvm_set_memory_region(kvm, &mem);
7021
7022 mem.slot = TSS_PRIVATE_MEMSLOT;
7023 kvm_set_memory_region(kvm, &mem);
7024 }
6eb55818 7025 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7026 kfree(kvm->arch.vpic);
7027 kfree(kvm->arch.vioapic);
d19a9cd2 7028 kvm_free_vcpus(kvm);
3d45830c
AK		 7029 if (kvm->arch.apic_access_page)
7030 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7031 if (kvm->arch.ept_identity_pagetable)
7032 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7033 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7034}
0de10343 7035
db3fe4eb
TY		 7036void kvm_arch_free_memslot(struct kvm_memory_slot *free,
7037 struct kvm_memory_slot *dont)
7038{
7039 int i;
7040
d89cc617
TY		 7041 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7042 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7043 kvm_kvfree(free->arch.rmap[i]);
7044 free->arch.rmap[i] = NULL;
77d11309 7045 }
d89cc617
TY		 7046 if (i == 0)
7047 continue;
7048
7049 if (!dont || free->arch.lpage_info[i - 1] !=
7050 dont->arch.lpage_info[i - 1]) {
7051 kvm_kvfree(free->arch.lpage_info[i - 1]);
7052 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7053 }
7054 }
7055}
7056
7057int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
7058{
7059 int i;
7060
d89cc617 7061 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7062 unsigned long ugfn;
7063 int lpages;
d89cc617 7064 int level = i + 1;
db3fe4eb
TY		 7065
7066 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7067 slot->base_gfn, level) + 1;
7068
d89cc617
TY		 7069 slot->arch.rmap[i] =
7070 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7071 if (!slot->arch.rmap[i])
77d11309 7072 goto out_free;
d89cc617
TY		 7073 if (i == 0)
7074 continue;
77d11309 7075
d89cc617
TY		 7076 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7077 sizeof(*slot->arch.lpage_info[i - 1]));
7078 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7079 goto out_free;
7080
7081 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7082 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7083 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7084 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7085 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7086 /*
7087 * If the gfn and userspace address are not aligned wrt each
7088 * other, or if explicitly asked to, disable large page
7089 * support for this slot
7090 */
7091 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7092 !kvm_largepages_enabled()) {
7093 unsigned long j;
7094
7095 for (j = 0; j < lpages; ++j)
d89cc617 7096 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7097 }
7098 }
7099
7100 return 0;
7101
7102out_free:
d89cc617
TY		 7103 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7104 kvm_kvfree(slot->arch.rmap[i]);
7105 slot->arch.rmap[i] = NULL;
7106 if (i == 0)
7107 continue;
7108
7109 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7110 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7111 }
7112 return -ENOMEM;
7113}
7114
e59dbe09
TY		 7115void kvm_arch_memslots_updated(struct kvm *kvm)
7116{
e6dff7d1
TY		 7117 /*
7118 * memslots->generation has been incremented.
7119 * mmio generation may have reached its maximum value.
7120 */
7121 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7122}
7123
f7784b8e
MT		 7124int kvm_arch_prepare_memory_region(struct kvm *kvm,
7125 struct kvm_memory_slot *memslot,
f7784b8e 7126 struct kvm_userspace_memory_region *mem,
7b6195a9 7127 enum kvm_mr_change change)
0de10343 7128{
7a905b14
TY		 7129 /*
7130 * Only private memory slots need to be mapped here since
7131 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7132 */
7b6195a9 7133 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7134 unsigned long userspace_addr;
604b38ac 7135
7a905b14
TY		 7136 /*
7137 * MAP_SHARED to prevent internal slot pages from being moved
7138 * by fork()/COW.
7139 */
7b6195a9 7140 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7141 PROT_READ | PROT_WRITE,
7142 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7143
7a905b14
TY		 7144 if (IS_ERR((void *)userspace_addr))
7145 return PTR_ERR((void *)userspace_addr);
604b38ac 7146
7a905b14 7147 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7148 }
7149
f7784b8e
MT		 7150 return 0;
7151}
7152
7153void kvm_arch_commit_memory_region(struct kvm *kvm,
7154 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7155 const struct kvm_memory_slot *old,
7156 enum kvm_mr_change change)
f7784b8e
MT		 7157{
7158
8482644a 7159 int nr_mmu_pages = 0;
f7784b8e 7160
8482644a 7161 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7162 int ret;
7163
8482644a
TY		 7164 ret = vm_munmap(old->userspace_addr,
7165 old->npages * PAGE_SIZE);
f7784b8e
MT		 7166 if (ret < 0)
7167 printk(KERN_WARNING
7168 "kvm_vm_ioctl_set_memory_region: "
7169 "failed to munmap memory\n");
7170 }
7171
48c0e4e9
XG		 7172 if (!kvm->arch.n_requested_mmu_pages)
7173 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7174
48c0e4e9 7175 if (nr_mmu_pages)
0de10343 7176 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7177 /*
7178 * Write protect all pages for dirty logging.
7179 * Existing largepage mappings are destroyed here and new ones will
7180 * not be created until the end of the logging.
7181 */
8482644a 7182 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7183 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7184}
1d737c8a 7185
2df72e9b 7186void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7187{
6ca18b69 7188 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7189}
7190
2df72e9b
MT		 7191void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7192 struct kvm_memory_slot *slot)
7193{
6ca18b69 7194 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7195}
7196
1d737c8a
ZX		 7197int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7198{
af585b92
GN		 7199 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7200 !vcpu->arch.apf.halted)
7201 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7202 || kvm_apic_has_events(vcpu)
7460fb4a 7203 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7204 (kvm_arch_interrupt_allowed(vcpu) &&
7205 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7206}
5736199a 7207
b6d33834 7208int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7209{
b6d33834 7210 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7211}
78646121
GN		 7212
7213int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7214{
7215 return kvm_x86_ops->interrupt_allowed(vcpu);
7216}
229456fc 7217
f92653ee
JK		 7218bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7219{
7220 unsigned long current_rip = kvm_rip_read(vcpu) +
7221 get_segment_base(vcpu, VCPU_SREG_CS);
7222
7223 return current_rip == linear_rip;
7224}
7225EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7226
94fe45da
JK		 7227unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7228{
7229 unsigned long rflags;
7230
7231 rflags = kvm_x86_ops->get_rflags(vcpu);
7232 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7233 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7234 return rflags;
7235}
7236EXPORT_SYMBOL_GPL(kvm_get_rflags);
7237
7238void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7239{
7240 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7241 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7242 rflags |= X86_EFLAGS_TF;
94fe45da 7243 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7244 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7245}
7246EXPORT_SYMBOL_GPL(kvm_set_rflags);
7247
56028d08
GN		 7248void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7249{
7250 int r;
7251
fb67e14f 7252 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7253 is_error_page(work->page))
56028d08
GN		 7254 return;
7255
7256 r = kvm_mmu_reload(vcpu);
7257 if (unlikely(r))
7258 return;
7259
fb67e14f
XG		 7260 if (!vcpu->arch.mmu.direct_map &&
7261 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7262 return;
7263
56028d08
GN		 7264 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7265}
7266
af585b92
GN		 7267static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7268{
7269 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7270}
7271
7272static inline u32 kvm_async_pf_next_probe(u32 key)
7273{
7274 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7275}
7276
7277static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7278{
7279 u32 key = kvm_async_pf_hash_fn(gfn);
7280
7281 while (vcpu->arch.apf.gfns[key] != ~0)
7282 key = kvm_async_pf_next_probe(key);
7283
7284 vcpu->arch.apf.gfns[key] = gfn;
7285}
7286
7287static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7288{
7289 int i;
7290 u32 key = kvm_async_pf_hash_fn(gfn);
7291
7292 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7293 (vcpu->arch.apf.gfns[key] != gfn &&
7294 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7295 key = kvm_async_pf_next_probe(key);
7296
7297 return key;
7298}
7299
7300bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7301{
7302 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7303}
7304
7305static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7306{
7307 u32 i, j, k;
7308
7309 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7310 while (true) {
7311 vcpu->arch.apf.gfns[i] = ~0;
7312 do {
7313 j = kvm_async_pf_next_probe(j);
7314 if (vcpu->arch.apf.gfns[j] == ~0)
7315 return;
7316 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7317 /*
7318 * k lies cyclically in ]i,j]
7319 * | i.k.j |
7320 * |....j i.k.| or |.k..j i...|
7321 */
7322 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7323 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7324 i = j;
7325 }
7326}
7327
7c90705b
GN		 7328static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7329{
7330
7331 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7332 sizeof(val));
7333}
7334
af585b92
GN		 7335void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7336 struct kvm_async_pf *work)
7337{
6389ee94
AK		 7338 struct x86_exception fault;
7339
7c90705b 7340 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7341 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7342
7343 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7344 (vcpu->arch.apf.send_user_only &&
7345 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7346 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7347 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7348 fault.vector = PF_VECTOR;
7349 fault.error_code_valid = true;
7350 fault.error_code = 0;
7351 fault.nested_page_fault = false;
7352 fault.address = work->arch.token;
7353 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7354 }
af585b92
GN		 7355}
7356
7357void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7358 struct kvm_async_pf *work)
7359{
6389ee94
AK		 7360 struct x86_exception fault;
7361
7c90705b
GN		 7362 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7363 if (is_error_page(work->page))
7364 work->arch.token = ~0; /* broadcast wakeup */
7365 else
7366 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7367
7368 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7369 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7370 fault.vector = PF_VECTOR;
7371 fault.error_code_valid = true;
7372 fault.error_code = 0;
7373 fault.nested_page_fault = false;
7374 fault.address = work->arch.token;
7375 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7376 }
e6d53e3b 7377 vcpu->arch.apf.halted = false;
a4fa1635 7378 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7379}
7380
7381bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7382{
7383 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7384 return true;
7385 else
7386 return !kvm_event_needs_reinjection(vcpu) &&
7387 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7388}
7389
229456fc
MT		 7390EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7391EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7392EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7393EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7394EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7395EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7396EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7397EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7398EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7399EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7400EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7401EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git