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git.ipfire.org Git - thirdparty/openssl.git/blob - crypto/ppccap.c
2 * Copyright 2009-2018 The OpenSSL Project Authors. All Rights Reserved.
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
16 #if defined(__linux) || defined(_AIX)
17 # include <sys/utsname.h>
19 #if defined(_AIX53) /* defined even on post-5.3 */
20 # include <sys/systemcfg.h>
21 # if !defined(__power_set)
22 # define __power_set(a) (_system_configuration.implementation & (a))
25 #if defined(__APPLE__) && defined(__MACH__)
26 # include <sys/types.h>
27 # include <sys/sysctl.h>
29 #include <openssl/crypto.h>
30 #include <openssl/bn.h>
31 #include <internal/cryptlib.h>
32 #include <internal/chacha.h>
33 #include "bn/bn_lcl.h"
37 unsigned int OPENSSL_ppccap_P
= 0;
39 static sigset_t all_masked
;
41 #ifdef OPENSSL_BN_ASM_MONT
42 int bn_mul_mont(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
43 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
)
45 int bn_mul_mont_int(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
46 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
);
47 int bn_mul4x_mont_int(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
48 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
);
54 return bn_mul4x_mont_int(rp
, ap
, bp
, np
, n0
, num
);
57 * There used to be [optional] call to bn_mul_mont_fpu64 here,
58 * but above subroutine is faster on contemporary processors.
59 * Formulation means that there might be old processors where
60 * FPU code path would be faster, POWER6 perhaps, but there was
61 * no opportunity to figure it out...
64 return bn_mul_mont_int(rp
, ap
, bp
, np
, n0
, num
);
68 void sha256_block_p8(void *ctx
, const void *inp
, size_t len
);
69 void sha256_block_ppc(void *ctx
, const void *inp
, size_t len
);
70 void sha256_block_data_order(void *ctx
, const void *inp
, size_t len
);
71 void sha256_block_data_order(void *ctx
, const void *inp
, size_t len
)
73 OPENSSL_ppccap_P
& PPC_CRYPTO207
? sha256_block_p8(ctx
, inp
, len
) :
74 sha256_block_ppc(ctx
, inp
, len
);
77 void sha512_block_p8(void *ctx
, const void *inp
, size_t len
);
78 void sha512_block_ppc(void *ctx
, const void *inp
, size_t len
);
79 void sha512_block_data_order(void *ctx
, const void *inp
, size_t len
);
80 void sha512_block_data_order(void *ctx
, const void *inp
, size_t len
)
82 OPENSSL_ppccap_P
& PPC_CRYPTO207
? sha512_block_p8(ctx
, inp
, len
) :
83 sha512_block_ppc(ctx
, inp
, len
);
86 #ifndef OPENSSL_NO_CHACHA
87 void ChaCha20_ctr32_int(unsigned char *out
, const unsigned char *inp
,
88 size_t len
, const unsigned int key
[8],
89 const unsigned int counter
[4]);
90 void ChaCha20_ctr32_vmx(unsigned char *out
, const unsigned char *inp
,
91 size_t len
, const unsigned int key
[8],
92 const unsigned int counter
[4]);
93 void ChaCha20_ctr32_vsx(unsigned char *out
, const unsigned char *inp
,
94 size_t len
, const unsigned int key
[8],
95 const unsigned int counter
[4]);
96 void ChaCha20_ctr32(unsigned char *out
, const unsigned char *inp
,
97 size_t len
, const unsigned int key
[8],
98 const unsigned int counter
[4])
100 OPENSSL_ppccap_P
& PPC_CRYPTO207
101 ? ChaCha20_ctr32_vsx(out
, inp
, len
, key
, counter
)
102 : OPENSSL_ppccap_P
& PPC_ALTIVEC
103 ? ChaCha20_ctr32_vmx(out
, inp
, len
, key
, counter
)
104 : ChaCha20_ctr32_int(out
, inp
, len
, key
, counter
);
108 #ifndef OPENSSL_NO_POLY1305
109 void poly1305_init_int(void *ctx
, const unsigned char key
[16]);
110 void poly1305_blocks(void *ctx
, const unsigned char *inp
, size_t len
,
111 unsigned int padbit
);
112 void poly1305_emit(void *ctx
, unsigned char mac
[16],
113 const unsigned int nonce
[4]);
114 void poly1305_init_fpu(void *ctx
, const unsigned char key
[16]);
115 void poly1305_blocks_fpu(void *ctx
, const unsigned char *inp
, size_t len
,
116 unsigned int padbit
);
117 void poly1305_emit_fpu(void *ctx
, unsigned char mac
[16],
118 const unsigned int nonce
[4]);
119 void poly1305_init_vsx(void *ctx
, const unsigned char key
[16]);
120 void poly1305_blocks_vsx(void *ctx
, const unsigned char *inp
, size_t len
,
121 unsigned int padbit
);
122 void poly1305_emit_vsx(void *ctx
, unsigned char mac
[16],
123 const unsigned int nonce
[4]);
124 int poly1305_init(void *ctx
, const unsigned char key
[16], void *func
[2]);
125 int poly1305_init(void *ctx
, const unsigned char key
[16], void *func
[2])
127 if (OPENSSL_ppccap_P
& PPC_CRYPTO207
) {
128 poly1305_init_int(ctx
, key
);
129 func
[0] = (void*)(uintptr_t)poly1305_blocks_vsx
;
130 func
[1] = (void*)(uintptr_t)poly1305_emit
;
131 } else if (sizeof(size_t) == 4 && (OPENSSL_ppccap_P
& PPC_FPU
)) {
132 poly1305_init_fpu(ctx
, key
);
133 func
[0] = (void*)(uintptr_t)poly1305_blocks_fpu
;
134 func
[1] = (void*)(uintptr_t)poly1305_emit_fpu
;
136 poly1305_init_int(ctx
, key
);
137 func
[0] = (void*)(uintptr_t)poly1305_blocks
;
138 func
[1] = (void*)(uintptr_t)poly1305_emit
;
144 #ifdef ECP_NISTZ256_ASM
145 void ecp_nistz256_mul_mont(unsigned long res
[4], const unsigned long a
[4],
146 const unsigned long b
[4]);
148 void ecp_nistz256_to_mont(unsigned long res
[4], const unsigned long in
[4]);
149 void ecp_nistz256_to_mont(unsigned long res
[4], const unsigned long in
[4])
151 static const unsigned long RR
[] = { 0x0000000000000003U
,
154 0x00000004fffffffdU
};
156 ecp_nistz256_mul_mont(res
, in
, RR
);
159 void ecp_nistz256_from_mont(unsigned long res
[4], const unsigned long in
[4]);
160 void ecp_nistz256_from_mont(unsigned long res
[4], const unsigned long in
[4])
162 static const unsigned long one
[] = { 1, 0, 0, 0 };
164 ecp_nistz256_mul_mont(res
, in
, one
);
168 static sigjmp_buf ill_jmp
;
169 static void ill_handler(int sig
)
171 siglongjmp(ill_jmp
, sig
);
174 void OPENSSL_fpu_probe(void);
175 void OPENSSL_ppc64_probe(void);
176 void OPENSSL_altivec_probe(void);
177 void OPENSSL_crypto207_probe(void);
178 void OPENSSL_madd300_probe(void);
180 long OPENSSL_rdtsc_mftb(void);
181 long OPENSSL_rdtsc_mfspr268(void);
183 uint32_t OPENSSL_rdtsc(void)
185 if (OPENSSL_ppccap_P
& PPC_MFTB
)
186 return OPENSSL_rdtsc_mftb();
187 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
188 return OPENSSL_rdtsc_mfspr268();
193 size_t OPENSSL_instrument_bus_mftb(unsigned int *, size_t);
194 size_t OPENSSL_instrument_bus_mfspr268(unsigned int *, size_t);
196 size_t OPENSSL_instrument_bus(unsigned int *out
, size_t cnt
)
198 if (OPENSSL_ppccap_P
& PPC_MFTB
)
199 return OPENSSL_instrument_bus_mftb(out
, cnt
);
200 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
201 return OPENSSL_instrument_bus_mfspr268(out
, cnt
);
206 size_t OPENSSL_instrument_bus2_mftb(unsigned int *, size_t, size_t);
207 size_t OPENSSL_instrument_bus2_mfspr268(unsigned int *, size_t, size_t);
209 size_t OPENSSL_instrument_bus2(unsigned int *out
, size_t cnt
, size_t max
)
211 if (OPENSSL_ppccap_P
& PPC_MFTB
)
212 return OPENSSL_instrument_bus2_mftb(out
, cnt
, max
);
213 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
214 return OPENSSL_instrument_bus2_mfspr268(out
, cnt
, max
);
219 #if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
220 # if __GLIBC_PREREQ(2, 16)
221 # include <sys/auxv.h>
222 # define OSSL_IMPLEMENT_GETAUXVAL
226 /* I wish <sys/auxv.h> was universally available */
227 #define HWCAP 16 /* AT_HWCAP */
228 #define HWCAP_PPC64 (1U << 30)
229 #define HWCAP_ALTIVEC (1U << 28)
230 #define HWCAP_FPU (1U << 27)
231 #define HWCAP_POWER6_EXT (1U << 9)
232 #define HWCAP_VSX (1U << 7)
234 #define HWCAP2 26 /* AT_HWCAP2 */
235 #define HWCAP_VEC_CRYPTO (1U << 25)
236 #define HWCAP_ARCH_3_00 (1U << 23)
238 # if defined(__GNUC__) && __GNUC__>=2
239 __attribute__ ((constructor
))
241 void OPENSSL_cpuid_setup(void)
244 struct sigaction ill_oact
, ill_act
;
246 static int trigger
= 0;
252 if ((e
= getenv("OPENSSL_ppccap"))) {
253 OPENSSL_ppccap_P
= strtoul(e
, NULL
, 0);
257 OPENSSL_ppccap_P
= 0;
260 OPENSSL_ppccap_P
|= PPC_FPU
;
262 if (sizeof(size_t) == 4) {
264 # if defined(_SC_AIX_KERNEL_BITMODE)
265 if (sysconf(_SC_AIX_KERNEL_BITMODE
) != 64)
268 if (uname(&uts
) != 0 || atoi(uts
.version
) < 6)
272 # if defined(__power_set)
274 * Value used in __power_set is a single-bit 1<<n one denoting
275 * specific processor class. Incidentally 0xffffffff<<n can be
276 * used to denote specific processor and its successors.
278 if (sizeof(size_t) == 4) {
279 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
280 if (__power_set(0xffffffffU
<<13)) /* POWER5 and later */
281 OPENSSL_ppccap_P
|= PPC_FPU64
;
283 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
284 if (__power_set(0x1U
<<14)) /* POWER6 */
285 OPENSSL_ppccap_P
|= PPC_FPU64
;
288 if (__power_set(0xffffffffU
<<14)) /* POWER6 and later */
289 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
291 if (__power_set(0xffffffffU
<<16)) /* POWER8 and later */
292 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
294 if (__power_set(0xffffffffU
<<17)) /* POWER9 and later */
295 OPENSSL_ppccap_P
|= PPC_MADD300
;
301 #if defined(__APPLE__) && defined(__MACH__)
302 OPENSSL_ppccap_P
|= PPC_FPU
;
306 size_t len
= sizeof(val
);
308 if (sysctlbyname("hw.optional.64bitops", &val
, &len
, NULL
, 0) == 0) {
310 OPENSSL_ppccap_P
|= PPC_FPU64
;
314 if (sysctlbyname("hw.optional.altivec", &val
, &len
, NULL
, 0) == 0) {
316 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
323 #ifdef OSSL_IMPLEMENT_GETAUXVAL
325 unsigned long hwcap
= getauxval(HWCAP
);
327 if (hwcap
& HWCAP_FPU
) {
328 OPENSSL_ppccap_P
|= PPC_FPU
;
330 if (sizeof(size_t) == 4) {
331 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
332 if (hwcap
& HWCAP_PPC64
)
333 OPENSSL_ppccap_P
|= PPC_FPU64
;
335 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
336 if (hwcap
& HWCAP_POWER6_EXT
)
337 OPENSSL_ppccap_P
|= PPC_FPU64
;
341 if (hwcap
& HWCAP_ALTIVEC
) {
342 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
344 if ((hwcap
& HWCAP_VSX
) && (getauxval(HWCAP2
) & HWCAP_VEC_CRYPTO
))
345 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
348 if (hwcap
& HWCAP_ARCH_3_00
) {
349 OPENSSL_ppccap_P
|= PPC_MADD300
;
354 sigfillset(&all_masked
);
355 sigdelset(&all_masked
, SIGILL
);
356 sigdelset(&all_masked
, SIGTRAP
);
358 sigdelset(&all_masked
, SIGEMT
);
360 sigdelset(&all_masked
, SIGFPE
);
361 sigdelset(&all_masked
, SIGBUS
);
362 sigdelset(&all_masked
, SIGSEGV
);
364 memset(&ill_act
, 0, sizeof(ill_act
));
365 ill_act
.sa_handler
= ill_handler
;
366 ill_act
.sa_mask
= all_masked
;
368 sigprocmask(SIG_SETMASK
, &ill_act
.sa_mask
, &oset
);
369 sigaction(SIGILL
, &ill_act
, &ill_oact
);
371 #ifndef OSSL_IMPLEMENT_GETAUXVAL
372 if (sigsetjmp(ill_jmp
,1) == 0) {
374 OPENSSL_ppccap_P
|= PPC_FPU
;
376 if (sizeof(size_t) == 4) {
379 if (uname(&uts
) == 0 && strcmp(uts
.machine
, "ppc64") == 0)
381 if (sigsetjmp(ill_jmp
, 1) == 0) {
382 OPENSSL_ppc64_probe();
383 OPENSSL_ppccap_P
|= PPC_FPU64
;
387 * Wanted code detecting POWER6 CPU and setting PPC_FPU64
392 if (sigsetjmp(ill_jmp
, 1) == 0) {
393 OPENSSL_altivec_probe();
394 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
395 if (sigsetjmp(ill_jmp
, 1) == 0) {
396 OPENSSL_crypto207_probe();
397 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
401 if (sigsetjmp(ill_jmp
, 1) == 0) {
402 OPENSSL_madd300_probe();
403 OPENSSL_ppccap_P
|= PPC_MADD300
;
407 if (sigsetjmp(ill_jmp
, 1) == 0) {
408 OPENSSL_rdtsc_mftb();
409 OPENSSL_ppccap_P
|= PPC_MFTB
;
410 } else if (sigsetjmp(ill_jmp
, 1) == 0) {
411 OPENSSL_rdtsc_mfspr268();
412 OPENSSL_ppccap_P
|= PPC_MFSPR268
;
415 sigaction(SIGILL
, &ill_oact
, NULL
);
416 sigprocmask(SIG_SETMASK
, &oset
, NULL
);