crypto/rc4/asm/rc4-x86_64.pl

   1 #!/usr/bin/env perl
   2 #
   3 # ====================================================================
   4 # Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
   5 # project. The module is, however, dual licensed under OpenSSL and
   6 # CRYPTOGAMS licenses depending on where you obtain it. For further
   7 # details see http://www.openssl.org/~appro/cryptogams/.
   8 # ====================================================================
   9 #
  10 # July 2004
  11 #
  12 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
  13 # "hand-coded assembler"] doesn't stand for the whole improvement
  14 # coefficient. It turned out that eliminating RC4_CHAR from config
  15 # line results in ~40% improvement (yes, even for C implementation).
  16 # Presumably it has everything to do with AMD cache architecture and
  17 # RAW or whatever penalties. Once again! The module *requires* config
  18 # line *without* RC4_CHAR! As for coding "secret," I bet on partial
  19 # register arithmetics. For example instead of 'inc %r8; and $255,%r8'
  20 # I simply 'inc %r8b'. Even though optimization manual discourages
  21 # to operate on partial registers, it turned out to be the best bet.
  22 # At least for AMD... How IA32E would perform remains to be seen...
  23
  24 # November 2004
  25 #
  26 # As was shown by Marc Bevand reordering of couple of load operations
  27 # results in even higher performance gain of 3.3x:-) At least on
  28 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
  29 # compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
  30 # Latter means that if you want to *estimate* what to expect from
  31 # *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
  32
  33 # November 2004
  34 #
  35 # Intel P4 EM64T core was found to run the AMD64 code really slow...
  36 # The only way to achieve comparable performance on P4 was to keep
  37 # RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
  38 # compose blended code, which would perform even within 30% marginal
  39 # on either AMD and Intel platforms, I implement both cases. See
  40 # rc4_skey.c for further details...
  41
  42 # April 2005
  43 #
  44 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
  45 # those with add/sub results in 50% performance improvement of folded
  46 # loop...
  47
  48 # May 2005
  49 #
  50 # As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
  51 # performance by >30% [unlike P4 32-bit case that is]. But this is
  52 # provided that loads are reordered even more aggressively! Both code
  53 # pathes, AMD64 and EM64T, reorder loads in essentially same manner
  54 # as my IA-64 implementation. On Opteron this resulted in modest 5%
  55 # improvement [I had to test it], while final Intel P4 performance
  56 # achieves respectful 432MBps on 2.8GHz processor now. For reference.
  57 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
  58 # RC4_INT code-path. While if executed on Opteron, it's only 25%
  59 # slower than the RC4_INT one [meaning that if CPU µ-arch detection
  60 # is not implemented, then this final RC4_CHAR code-path should be
  61 # preferred, as it provides better *all-round* performance].
  62
  63 # March 2007
  64 #
  65 # Intel Core2 was observed to perform poorly on both code paths:-( It
  66 # apparently suffers from some kind of partial register stall, which
  67 # occurs in 64-bit mode only [as virtually identical 32-bit loop was
  68 # observed to outperform 64-bit one by almost 50%]. Adding two movzb to
  69 # cloop1 boosts its performance by 80%! This loop appears to be optimal
  70 # fit for Core2 and therefore the code was modified to skip cloop8 on
  71 # this CPU.
  72
  73 # May 2010
  74 #
  75 # Intel Westmere was observed to perform suboptimally. Adding yet
  76 # another movzb to cloop1 improved performance by almost 50%! Core2
  77 # performance is improved too, but nominally...
  78
  79 # May 2011
  80 #
  81 # The only code path that was not modified is P4-specific one. Non-P4
  82 # Intel code path optimization is heavily based on submission by Maxim
  83 # Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used
  84 # some of the ideas even in attempt to optmize the original RC4_INT
  85 # code path... Current performance in cycles per processed byte (less
  86 # is better) and improvement coefficients relative to previous
  87 # version of this module are:
  88 #
  89 # Opteron       5.3/+0%(*)
  90 # P4            6.5
  91 # Core2         6.2/+15%(**)
  92 # Westmere      4.2/+60%
  93 # Sandy Bridge  4.2/+120%
  94 # Atom          9.3/+80%
  95 # VIA Nano      6.4/+4%
  96 # Ivy Bridge    4.1/+30%
  97 # Bulldozer     4.5/+30%(*)
  98 #
  99 # (*)   But corresponding loop has less instructions, which should have
 100 #       positive effect on upcoming Bulldozer, which has one less ALU.
 101 #       For reference, Intel code runs at 6.8 cpb rate on Opteron.
 102 # (**)  Note that Core2 result is ~15% lower than corresponding result
 103 #       for 32-bit code, meaning that it's possible to improve it,
 104 #       but more than likely at the cost of the others (see rc4-586.pl
 105 #       to get the idea)...
 106
 107 $flavour = shift;
 108 $output  = shift;
 109 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
 110
 111 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
 112
 113 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
 114 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
 115 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
 116 die "can't locate x86_64-xlate.pl";
 117
 118 open OUT,"| \"$^X\" $xlate $flavour $output";
 119 *STDOUT=*OUT;
 120
 121 $dat="%rdi";        # arg1
 122 $len="%rsi";        # arg2
 123 $inp="%rdx";        # arg3
 124 $out="%rcx";        # arg4
 125
 126 {
 127 $code=<<___;
 128 .text
 129 .extern OPENSSL_ia32cap_P
 130
 131 .globl  RC4
 132 .type   RC4,\@function,4
 133 .align  16
 134 RC4:    or      $len,$len
 135         jne     .Lentry
 136         ret
 137 .Lentry:
 138         push    %rbx
 139         push    %r12
 140         push    %r13
 141 .Lprologue:
 142         mov     $len,%r11
 143         mov     $inp,%r12
 144         mov     $out,%r13
 145 ___
 146 my $len="%r11";         # reassign input arguments
 147 my $inp="%r12";
 148 my $out="%r13";
 149
 150 my @XX=("%r10","%rsi");
 151 my @TX=("%rax","%rbx");
 152 my $YY="%rcx";
 153 my $TY="%rdx";
 154
 155 $code.=<<___;
 156         xor     $XX[0],$XX[0]
 157         xor     $YY,$YY
 158
 159         lea     8($dat),$dat
 160         mov     -8($dat),$XX[0]#b
 161         mov     -4($dat),$YY#b
 162         cmpl    \$-1,256($dat)
 163         je      .LRC4_CHAR
 164         mov     OPENSSL_ia32cap_P(%rip),%r8d
 165         xor     $TX[1],$TX[1]
 166         inc     $XX[0]#b
 167         sub     $XX[0],$TX[1]
 168         sub     $inp,$out
 169         movl    ($dat,$XX[0],4),$TX[0]#d
 170         test    \$-16,$len
 171         jz      .Lloop1
 172         bt      \$30,%r8d       # Intel CPU?
 173         jc      .Lintel
 174         and     \$7,$TX[1]
 175         lea     1($XX[0]),$XX[1]
 176         jz      .Loop8
 177         sub     $TX[1],$len
 178 .Loop8_warmup:
 179         add     $TX[0]#b,$YY#b
 180         movl    ($dat,$YY,4),$TY#d
 181         movl    $TX[0]#d,($dat,$YY,4)
 182         movl    $TY#d,($dat,$XX[0],4)
 183         add     $TY#b,$TX[0]#b
 184         inc     $XX[0]#b
 185         movl    ($dat,$TX[0],4),$TY#d
 186         movl    ($dat,$XX[0],4),$TX[0]#d
 187         xorb    ($inp),$TY#b
 188         movb    $TY#b,($out,$inp)
 189         lea     1($inp),$inp
 190         dec     $TX[1]
 191         jnz     .Loop8_warmup
 192
 193         lea     1($XX[0]),$XX[1]
 194         jmp     .Loop8
 195 .align  16
 196 .Loop8:
 197 ___
 198 for ($i=0;$i<8;$i++) {
 199 $code.=<<___ if ($i==7);
 200         add     \$8,$XX[1]#b
 201 ___
 202 $code.=<<___;
 203         add     $TX[0]#b,$YY#b
 204         movl    ($dat,$YY,4),$TY#d
 205         movl    $TX[0]#d,($dat,$YY,4)
 206         movl    `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d
 207         ror     \$8,%r8                         # ror is redundant when $i=0
 208         movl    $TY#d,4*$i($dat,$XX[0],4)
 209         add     $TX[0]#b,$TY#b
 210         movb    ($dat,$TY,4),%r8b
 211 ___
 212 push(@TX,shift(@TX)); #push(@XX,shift(@XX));    # "rotate" registers
 213 }
 214 $code.=<<___;
 215         add     \$8,$XX[0]#b
 216         ror     \$8,%r8
 217         sub     \$8,$len
 218
 219         xor     ($inp),%r8
 220         mov     %r8,($out,$inp)
 221         lea     8($inp),$inp
 222
 223         test    \$-8,$len
 224         jnz     .Loop8
 225         cmp     \$0,$len
 226         jne     .Lloop1
 227         jmp     .Lexit
 228
 229 .align  16
 230 .Lintel:
 231         test    \$-32,$len
 232         jz      .Lloop1
 233         and     \$15,$TX[1]
 234         jz      .Loop16_is_hot
 235         sub     $TX[1],$len
 236 .Loop16_warmup:
 237         add     $TX[0]#b,$YY#b
 238         movl    ($dat,$YY,4),$TY#d
 239         movl    $TX[0]#d,($dat,$YY,4)
 240         movl    $TY#d,($dat,$XX[0],4)
 241         add     $TY#b,$TX[0]#b
 242         inc     $XX[0]#b
 243         movl    ($dat,$TX[0],4),$TY#d
 244         movl    ($dat,$XX[0],4),$TX[0]#d
 245         xorb    ($inp),$TY#b
 246         movb    $TY#b,($out,$inp)
 247         lea     1($inp),$inp
 248         dec     $TX[1]
 249         jnz     .Loop16_warmup
 250
 251         mov     $YY,$TX[1]
 252         xor     $YY,$YY
 253         mov     $TX[1]#b,$YY#b
 254
 255 .Loop16_is_hot:
 256         lea     ($dat,$XX[0],4),$XX[1]
 257 ___
 258 sub RC4_loop {
 259   my $i=shift;
 260   my $j=$i<0?0:$i;
 261   my $xmm="%xmm".($j&1);
 262
 263     $code.="    add     \$16,$XX[0]#b\n"                if ($i==15);
 264     $code.="    movdqu  ($inp),%xmm2\n"                 if ($i==15);
 265     $code.="    add     $TX[0]#b,$YY#b\n"               if ($i<=0);
 266     $code.="    movl    ($dat,$YY,4),$TY#d\n";
 267     $code.="    pxor    %xmm0,%xmm2\n"                  if ($i==0);
 268     $code.="    psllq   \$8,%xmm1\n"                    if ($i==0);
 269     $code.="    pxor    $xmm,$xmm\n"                    if ($i<=1);
 270     $code.="    movl    $TX[0]#d,($dat,$YY,4)\n";
 271     $code.="    add     $TY#b,$TX[0]#b\n";
 272     $code.="    movl    `4*($j+1)`($XX[1]),$TX[1]#d\n"  if ($i<15);
 273     $code.="    movz    $TX[0]#b,$TX[0]#d\n";
 274     $code.="    movl    $TY#d,4*$j($XX[1])\n";
 275     $code.="    pxor    %xmm1,%xmm2\n"                  if ($i==0);
 276     $code.="    lea     ($dat,$XX[0],4),$XX[1]\n"       if ($i==15);
 277     $code.="    add     $TX[1]#b,$YY#b\n"               if ($i<15);
 278     $code.="    pinsrw  \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n";
 279     $code.="    movdqu  %xmm2,($out,$inp)\n"            if ($i==0);
 280     $code.="    lea     16($inp),$inp\n"                if ($i==0);
 281     $code.="    movl    ($XX[1]),$TX[1]#d\n"            if ($i==15);
 282 }
 283         RC4_loop(-1);
 284 $code.=<<___;
 285         jmp     .Loop16_enter
 286 .align  16
 287 .Loop16:
 288 ___
 289
 290 for ($i=0;$i<16;$i++) {
 291     $code.=".Loop16_enter:\n"           if ($i==1);
 292         RC4_loop($i);
 293         push(@TX,shift(@TX));           # "rotate" registers
 294 }
 295 $code.=<<___;
 296         mov     $YY,$TX[1]
 297         xor     $YY,$YY                 # keyword to partial register
 298         sub     \$16,$len
 299         mov     $TX[1]#b,$YY#b
 300         test    \$-16,$len
 301         jnz     .Loop16
 302
 303         psllq   \$8,%xmm1
 304         pxor    %xmm0,%xmm2
 305         pxor    %xmm1,%xmm2
 306         movdqu  %xmm2,($out,$inp)
 307         lea     16($inp),$inp
 308
 309         cmp     \$0,$len
 310         jne     .Lloop1
 311         jmp     .Lexit
 312
 313 .align  16
 314 .Lloop1:
 315         add     $TX[0]#b,$YY#b
 316         movl    ($dat,$YY,4),$TY#d
 317         movl    $TX[0]#d,($dat,$YY,4)
 318         movl    $TY#d,($dat,$XX[0],4)
 319         add     $TY#b,$TX[0]#b
 320         inc     $XX[0]#b
 321         movl    ($dat,$TX[0],4),$TY#d
 322         movl    ($dat,$XX[0],4),$TX[0]#d
 323         xorb    ($inp),$TY#b
 324         movb    $TY#b,($out,$inp)
 325         lea     1($inp),$inp
 326         dec     $len
 327         jnz     .Lloop1
 328         jmp     .Lexit
 329
 330 .align  16
 331 .LRC4_CHAR:
 332         add     \$1,$XX[0]#b
 333         movzb   ($dat,$XX[0]),$TX[0]#d
 334         test    \$-8,$len
 335         jz      .Lcloop1
 336         jmp     .Lcloop8
 337 .align  16
 338 .Lcloop8:
 339         mov     ($inp),%r8d
 340         mov     4($inp),%r9d
 341 ___
 342 # unroll 2x4-wise, because 64-bit rotates kill Intel P4...
 343 for ($i=0;$i<4;$i++) {
 344 $code.=<<___;
 345         add     $TX[0]#b,$YY#b
 346         lea     1($XX[0]),$XX[1]
 347         movzb   ($dat,$YY),$TY#d
 348         movzb   $XX[1]#b,$XX[1]#d
 349         movzb   ($dat,$XX[1]),$TX[1]#d
 350         movb    $TX[0]#b,($dat,$YY)
 351         cmp     $XX[1],$YY
 352         movb    $TY#b,($dat,$XX[0])
 353         jne     .Lcmov$i                        # Intel cmov is sloooow...
 354         mov     $TX[0],$TX[1]
 355 .Lcmov$i:
 356         add     $TX[0]#b,$TY#b
 357         xor     ($dat,$TY),%r8b
 358         ror     \$8,%r8d
 359 ___
 360 push(@TX,shift(@TX)); push(@XX,shift(@XX));     # "rotate" registers
 361 }
 362 for ($i=4;$i<8;$i++) {
 363 $code.=<<___;
 364         add     $TX[0]#b,$YY#b
 365         lea     1($XX[0]),$XX[1]
 366         movzb   ($dat,$YY),$TY#d
 367         movzb   $XX[1]#b,$XX[1]#d
 368         movzb   ($dat,$XX[1]),$TX[1]#d
 369         movb    $TX[0]#b,($dat,$YY)
 370         cmp     $XX[1],$YY
 371         movb    $TY#b,($dat,$XX[0])
 372         jne     .Lcmov$i                        # Intel cmov is sloooow...
 373         mov     $TX[0],$TX[1]
 374 .Lcmov$i:
 375         add     $TX[0]#b,$TY#b
 376         xor     ($dat,$TY),%r9b
 377         ror     \$8,%r9d
 378 ___
 379 push(@TX,shift(@TX)); push(@XX,shift(@XX));     # "rotate" registers
 380 }
 381 $code.=<<___;
 382         lea     -8($len),$len
 383         mov     %r8d,($out)
 384         lea     8($inp),$inp
 385         mov     %r9d,4($out)
 386         lea     8($out),$out
 387
 388         test    \$-8,$len
 389         jnz     .Lcloop8
 390         cmp     \$0,$len
 391         jne     .Lcloop1
 392         jmp     .Lexit
 393 ___
 394 $code.=<<___;
 395 .align  16
 396 .Lcloop1:
 397         add     $TX[0]#b,$YY#b
 398         movzb   $YY#b,$YY#d
 399         movzb   ($dat,$YY),$TY#d
 400         movb    $TX[0]#b,($dat,$YY)
 401         movb    $TY#b,($dat,$XX[0])
 402         add     $TX[0]#b,$TY#b
 403         add     \$1,$XX[0]#b
 404         movzb   $TY#b,$TY#d
 405         movzb   $XX[0]#b,$XX[0]#d
 406         movzb   ($dat,$TY),$TY#d
 407         movzb   ($dat,$XX[0]),$TX[0]#d
 408         xorb    ($inp),$TY#b
 409         lea     1($inp),$inp
 410         movb    $TY#b,($out)
 411         lea     1($out),$out
 412         sub     \$1,$len
 413         jnz     .Lcloop1
 414         jmp     .Lexit
 415
 416 .align  16
 417 .Lexit:
 418         sub     \$1,$XX[0]#b
 419         movl    $XX[0]#d,-8($dat)
 420         movl    $YY#d,-4($dat)
 421
 422         mov     (%rsp),%r13
 423         mov     8(%rsp),%r12
 424         mov     16(%rsp),%rbx
 425         add     \$24,%rsp
 426 .Lepilogue:
 427         ret
 428 .size   RC4,.-RC4
 429 ___
 430 }
 431
 432 $idx="%r8";
 433 $ido="%r9";
 434
 435 $code.=<<___;
 436 .globl  RC4_set_key
 437 .type   RC4_set_key,\@function,3
 438 .align  16
 439 RC4_set_key:
 440         lea     8($dat),$dat
 441         lea     ($inp,$len),$inp
 442         neg     $len
 443         mov     $len,%rcx
 444         xor     %eax,%eax
 445         xor     $ido,$ido
 446         xor     %r10,%r10
 447         xor     %r11,%r11
 448
 449         mov     OPENSSL_ia32cap_P(%rip),$idx#d
 450         bt      \$20,$idx#d     # RC4_CHAR?
 451         jc      .Lc1stloop
 452         jmp     .Lw1stloop
 453
 454 .align  16
 455 .Lw1stloop:
 456         mov     %eax,($dat,%rax,4)
 457         add     \$1,%al
 458         jnc     .Lw1stloop
 459
 460         xor     $ido,$ido
 461         xor     $idx,$idx
 462 .align  16
 463 .Lw2ndloop:
 464         mov     ($dat,$ido,4),%r10d
 465         add     ($inp,$len,1),$idx#b
 466         add     %r10b,$idx#b
 467         add     \$1,$len
 468         mov     ($dat,$idx,4),%r11d
 469         cmovz   %rcx,$len
 470         mov     %r10d,($dat,$idx,4)
 471         mov     %r11d,($dat,$ido,4)
 472         add     \$1,$ido#b
 473         jnc     .Lw2ndloop
 474         jmp     .Lexit_key
 475
 476 .align  16
 477 .Lc1stloop:
 478         mov     %al,($dat,%rax)
 479         add     \$1,%al
 480         jnc     .Lc1stloop
 481
 482         xor     $ido,$ido
 483         xor     $idx,$idx
 484 .align  16
 485 .Lc2ndloop:
 486         mov     ($dat,$ido),%r10b
 487         add     ($inp,$len),$idx#b
 488         add     %r10b,$idx#b
 489         add     \$1,$len
 490         mov     ($dat,$idx),%r11b
 491         jnz     .Lcnowrap
 492         mov     %rcx,$len
 493 .Lcnowrap:
 494         mov     %r10b,($dat,$idx)
 495         mov     %r11b,($dat,$ido)
 496         add     \$1,$ido#b
 497         jnc     .Lc2ndloop
 498         movl    \$-1,256($dat)
 499
 500 .align  16
 501 .Lexit_key:
 502         xor     %eax,%eax
 503         mov     %eax,-8($dat)
 504         mov     %eax,-4($dat)
 505         ret
 506 .size   RC4_set_key,.-RC4_set_key
 507
 508 .globl  RC4_options
 509 .type   RC4_options,\@abi-omnipotent
 510 .align  16
 511 RC4_options:
 512         lea     .Lopts(%rip),%rax
 513         mov     OPENSSL_ia32cap_P(%rip),%edx
 514         bt      \$20,%edx
 515         jc      .L8xchar
 516         bt      \$30,%edx
 517         jnc     .Ldone
 518         add     \$25,%rax
 519         ret
 520 .L8xchar:
 521         add     \$12,%rax
 522 .Ldone:
 523         ret
 524 .align  64
 525 .Lopts:
 526 .asciz  "rc4(8x,int)"
 527 .asciz  "rc4(8x,char)"
 528 .asciz  "rc4(16x,int)"
 529 .asciz  "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>"
 530 .align  64
 531 .size   RC4_options,.-RC4_options
 532 ___
 533
 534 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame,
 535 #               CONTEXT *context,DISPATCHER_CONTEXT *disp)
 536 if ($win64) {
 537 $rec="%rcx";
 538 $frame="%rdx";
 539 $context="%r8";
 540 $disp="%r9";
 541
 542 $code.=<<___;
 543 .extern __imp_RtlVirtualUnwind
 544 .type   stream_se_handler,\@abi-omnipotent
 545 .align  16
 546 stream_se_handler:
 547         push    %rsi
 548         push    %rdi
 549         push    %rbx
 550         push    %rbp
 551         push    %r12
 552         push    %r13
 553         push    %r14
 554         push    %r15
 555         pushfq
 556         sub     \$64,%rsp
 557
 558         mov     120($context),%rax      # pull context->Rax
 559         mov     248($context),%rbx      # pull context->Rip
 560
 561         lea     .Lprologue(%rip),%r10
 562         cmp     %r10,%rbx               # context->Rip<prologue label
 563         jb      .Lin_prologue
 564
 565         mov     152($context),%rax      # pull context->Rsp
 566
 567         lea     .Lepilogue(%rip),%r10
 568         cmp     %r10,%rbx               # context->Rip>=epilogue label
 569         jae     .Lin_prologue
 570
 571         lea     24(%rax),%rax
 572
 573         mov     -8(%rax),%rbx
 574         mov     -16(%rax),%r12
 575         mov     -24(%rax),%r13
 576         mov     %rbx,144($context)      # restore context->Rbx
 577         mov     %r12,216($context)      # restore context->R12
 578         mov     %r13,224($context)      # restore context->R13
 579
 580 .Lin_prologue:
 581         mov     8(%rax),%rdi
 582         mov     16(%rax),%rsi
 583         mov     %rax,152($context)      # restore context->Rsp
 584         mov     %rsi,168($context)      # restore context->Rsi
 585         mov     %rdi,176($context)      # restore context->Rdi
 586
 587         jmp     .Lcommon_seh_exit
 588 .size   stream_se_handler,.-stream_se_handler
 589
 590 .type   key_se_handler,\@abi-omnipotent
 591 .align  16
 592 key_se_handler:
 593         push    %rsi
 594         push    %rdi
 595         push    %rbx
 596         push    %rbp
 597         push    %r12
 598         push    %r13
 599         push    %r14
 600         push    %r15
 601         pushfq
 602         sub     \$64,%rsp
 603
 604         mov     152($context),%rax      # pull context->Rsp
 605         mov     8(%rax),%rdi
 606         mov     16(%rax),%rsi
 607         mov     %rsi,168($context)      # restore context->Rsi
 608         mov     %rdi,176($context)      # restore context->Rdi
 609
 610 .Lcommon_seh_exit:
 611
 612         mov     40($disp),%rdi          # disp->ContextRecord
 613         mov     $context,%rsi           # context
 614         mov     \$154,%ecx              # sizeof(CONTEXT)
 615         .long   0xa548f3fc              # cld; rep movsq
 616
 617         mov     $disp,%rsi
 618         xor     %rcx,%rcx               # arg1, UNW_FLAG_NHANDLER
 619         mov     8(%rsi),%rdx            # arg2, disp->ImageBase
 620         mov     0(%rsi),%r8             # arg3, disp->ControlPc
 621         mov     16(%rsi),%r9            # arg4, disp->FunctionEntry
 622         mov     40(%rsi),%r10           # disp->ContextRecord
 623         lea     56(%rsi),%r11           # &disp->HandlerData
 624         lea     24(%rsi),%r12           # &disp->EstablisherFrame
 625         mov     %r10,32(%rsp)           # arg5
 626         mov     %r11,40(%rsp)           # arg6
 627         mov     %r12,48(%rsp)           # arg7
 628         mov     %rcx,56(%rsp)           # arg8, (NULL)
 629         call    *__imp_RtlVirtualUnwind(%rip)
 630
 631         mov     \$1,%eax                # ExceptionContinueSearch
 632         add     \$64,%rsp
 633         popfq
 634         pop     %r15
 635         pop     %r14
 636         pop     %r13
 637         pop     %r12
 638         pop     %rbp
 639         pop     %rbx
 640         pop     %rdi
 641         pop     %rsi
 642         ret
 643 .size   key_se_handler,.-key_se_handler
 644
 645 .section        .pdata
 646 .align  4
 647         .rva    .LSEH_begin_RC4
 648         .rva    .LSEH_end_RC4
 649         .rva    .LSEH_info_RC4
 650
 651         .rva    .LSEH_begin_RC4_set_key
 652         .rva    .LSEH_end_RC4_set_key
 653         .rva    .LSEH_info_RC4_set_key
 654
 655 .section        .xdata
 656 .align  8
 657 .LSEH_info_RC4:
 658         .byte   9,0,0,0
 659         .rva    stream_se_handler
 660 .LSEH_info_RC4_set_key:
 661         .byte   9,0,0,0
 662         .rva    key_se_handler
 663 ___
 664 }
 665
 666 sub reg_part {
 667 my ($reg,$conv)=@_;
 668     if ($reg =~ /%r[0-9]+/)     { $reg .= $conv; }
 669     elsif ($conv eq "b")        { $reg =~ s/%[er]([^x]+)x?/%$1l/;       }
 670     elsif ($conv eq "w")        { $reg =~ s/%[er](.+)/%$1/;             }
 671     elsif ($conv eq "d")        { $reg =~ s/%[er](.+)/%e$1/;            }
 672     return $reg;
 673 }
 674
 675 $code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem;
 676 $code =~ s/\`([^\`]*)\`/eval $1/gem;
 677
 678 print $code;
 679
 680 close STDOUT;