lib/i386-ports.c

   1 /*
   2  *      The PCI Library -- Direct Configuration access via i386 Ports
   3  *
   4  *      Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL v2+.
   7  *
   8  *      SPDX-License-Identifier: GPL-2.0-or-later
   9  */
  10
  11 #define _GNU_SOURCE
  12
  13 #include "internal.h"
  14
  15 #include <string.h>
  16
  17 #if defined(PCI_OS_LINUX)
  18 #include "i386-io-linux.h"
  19 #elif defined(PCI_OS_GNU)
  20 #include "i386-io-hurd.h"
  21 #elif defined(PCI_OS_SUNOS)
  22 #include "i386-io-sunos.h"
  23 #elif defined(PCI_OS_WINDOWS)
  24 #include "i386-io-windows.h"
  25 #elif defined(PCI_OS_CYGWIN)
  26 #include "i386-io-cygwin.h"
  27 #elif defined(PCI_OS_HAIKU)
  28 #include "i386-io-haiku.h"
  29 #elif defined(PCI_OS_BEOS)
  30 #include "i386-io-beos.h"
  31 #elif defined(PCI_OS_DJGPP)
  32 #include "i386-io-djgpp.h"
  33 #elif defined(PCI_OS_OPENBSD)
  34 #include "i386-io-openbsd.h"
  35 #else
  36 #error Do not know how to access I/O ports on this OS.
  37 #endif
  38
  39 static int conf12_io_enabled = -1;              /* -1=haven't tried, 0=failed, 1=succeeded */
  40
  41 static int
  42 conf12_setup_io(struct pci_access *a)
  43 {
  44   if (conf12_io_enabled < 0)
  45     conf12_io_enabled = intel_setup_io(a);
  46   return conf12_io_enabled;
  47 }
  48
  49 static void
  50 conf12_init(struct pci_access *a)
  51 {
  52   if (!conf12_setup_io(a))
  53     a->error("No permission to access I/O ports (you probably have to be root).");
  54 }
  55
  56 static void
  57 conf12_cleanup(struct pci_access *a)
  58 {
  59   if (conf12_io_enabled > 0)
  60     {
  61       intel_cleanup_io(a);
  62       conf12_io_enabled = -1;
  63     }
  64 }
  65
  66 /*
  67  * Before we decide to use direct hardware access mechanisms, we try to do some
  68  * trivial checks to ensure it at least _seems_ to be working -- we just test
  69  * whether bus 00 contains a host bridge (this is similar to checking
  70  * techniques used in XFree86, but ours should be more reliable since we
  71  * attempt to make use of direct access hints provided by the PCI BIOS).
  72  *
  73  * This should be close to trivial, but it isn't, because there are buggy
  74  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  75  */
  76
  77 static int
  78 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
  79 {
  80   struct pci_dev d;
  81
  82   memset(&d, 0, sizeof(d));
  83   a->debug("...sanity check");
  84   d.bus = 0;
  85   d.func = 0;
  86   for (d.dev = 0; d.dev < 32; d.dev++)
  87     {
  88       u16 class, vendor;
  89       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
  90           (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
  91           m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
  92           (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
  93         {
  94           a->debug("...outside the Asylum at 0/%02x/0", d.dev);
  95           return 1;
  96         }
  97     }
  98   a->debug("...insane");
  99   return 0;
 100 }
 101
 102 /*
 103  *      Configuration type 1
 104  */
 105
 106 #define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
 107
 108 static int
 109 conf1_detect(struct pci_access *a)
 110 {
 111   unsigned int tmp;
 112   int res = 0;
 113
 114   if (!conf12_setup_io(a))
 115     {
 116       a->debug("...no I/O permission");
 117       return 0;
 118     }
 119
 120   intel_io_lock();
 121   intel_outb (0x01, 0xCFB);
 122   tmp = intel_inl (0xCF8);
 123   intel_outl (0x80000000, 0xCF8);
 124   if (intel_inl (0xCF8) == 0x80000000)
 125     res = 1;
 126   intel_outl (tmp, 0xCF8);
 127   intel_io_unlock();
 128
 129   if (res)
 130     res = intel_sanity_check(a, &pm_intel_conf1);
 131   return res;
 132 }
 133
 134 static int
 135 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 136 {
 137   int addr = 0xcfc + (pos&3);
 138   int res = 1;
 139
 140   if (d->domain || pos >= 256)
 141     return 0;
 142
 143   if (len != 1 && len != 2 && len != 4)
 144     return pci_generic_block_read(d, pos, buf, len);
 145
 146   intel_io_lock();
 147   intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 148
 149   switch (len)
 150     {
 151     case 1:
 152       buf[0] = intel_inb(addr);
 153       break;
 154     case 2:
 155       ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr));
 156       break;
 157     case 4:
 158       ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr));
 159       break;
 160     }
 161
 162   intel_io_unlock();
 163   return res;
 164 }
 165
 166 static int
 167 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 168 {
 169   int addr = 0xcfc + (pos&3);
 170   int res = 1;
 171
 172   if (d->domain || pos >= 256)
 173     return 0;
 174
 175   if (len != 1 && len != 2 && len != 4)
 176     return pci_generic_block_write(d, pos, buf, len);
 177
 178   intel_io_lock();
 179   intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 180
 181   switch (len)
 182     {
 183     case 1:
 184       intel_outb(buf[0], addr);
 185       break;
 186     case 2:
 187       intel_outw(le16_to_cpu(((u16 *) buf)[0]), addr);
 188       break;
 189     case 4:
 190       intel_outl(le32_to_cpu(((u32 *) buf)[0]), addr);
 191       break;
 192     }
 193   intel_io_unlock();
 194   return res;
 195 }
 196
 197 /*
 198  *      Configuration type 2. Obsolete and brain-damaged, but existing.
 199  */
 200
 201 static int
 202 conf2_detect(struct pci_access *a)
 203 {
 204   int res = 0;
 205
 206   if (!conf12_setup_io(a))
 207     {
 208       a->debug("...no I/O permission");
 209       return 0;
 210     }
 211
 212   /* This is ugly and tends to produce false positives. Beware. */
 213
 214   intel_io_lock();
 215   intel_outb(0x00, 0xCFB);
 216   intel_outb(0x00, 0xCF8);
 217   intel_outb(0x00, 0xCFA);
 218   if (intel_inb(0xCF8) == 0x00 && intel_inb(0xCFA) == 0x00)
 219     res = intel_sanity_check(a, &pm_intel_conf2);
 220   intel_io_unlock();
 221   return res;
 222 }
 223
 224 static int
 225 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 226 {
 227   int res = 1;
 228   int addr = 0xc000 | (d->dev << 8) | pos;
 229
 230   if (d->domain || pos >= 256)
 231     return 0;
 232
 233   if (d->dev >= 16)
 234     /* conf2 supports only 16 devices per bus */
 235     return 0;
 236
 237   if (len != 1 && len != 2 && len != 4)
 238     return pci_generic_block_read(d, pos, buf, len);
 239
 240   intel_io_lock();
 241   intel_outb((d->func << 1) | 0xf0, 0xcf8);
 242   intel_outb(d->bus, 0xcfa);
 243   switch (len)
 244     {
 245     case 1:
 246       buf[0] = intel_inb(addr);
 247       break;
 248     case 2:
 249       ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr));
 250       break;
 251     case 4:
 252       ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr));
 253       break;
 254     }
 255   intel_outb(0, 0xcf8);
 256   intel_io_unlock();
 257   return res;
 258 }
 259
 260 static int
 261 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 262 {
 263   int res = 1;
 264   int addr = 0xc000 | (d->dev << 8) | pos;
 265
 266   if (d->domain || pos >= 256)
 267     return 0;
 268
 269   if (d->dev >= 16)
 270     /* conf2 supports only 16 devices per bus */
 271     return 0;
 272
 273   if (len != 1 && len != 2 && len != 4)
 274     return pci_generic_block_write(d, pos, buf, len);
 275
 276   intel_io_lock();
 277   intel_outb((d->func << 1) | 0xf0, 0xcf8);
 278   intel_outb(d->bus, 0xcfa);
 279   switch (len)
 280     {
 281     case 1:
 282       intel_outb(buf[0], addr);
 283       break;
 284     case 2:
 285       intel_outw(le16_to_cpu(* (u16 *) buf), addr);
 286       break;
 287     case 4:
 288       intel_outl(le32_to_cpu(* (u32 *) buf), addr);
 289       break;
 290     }
 291
 292   intel_outb(0, 0xcf8);
 293   intel_io_unlock();
 294   return res;
 295 }
 296
 297 struct pci_methods pm_intel_conf1 = {
 298   .name = "intel-conf1",
 299   .help = "Raw I/O port access using Intel conf1 interface",
 300   .detect = conf1_detect,
 301   .init = conf12_init,
 302   .cleanup = conf12_cleanup,
 303   .scan = pci_generic_scan,
 304   .fill_info = pci_generic_fill_info,
 305   .read = conf1_read,
 306   .write = conf1_write,
 307 };
 308
 309 struct pci_methods pm_intel_conf2 = {
 310   .name = "intel-conf2",
 311   .help = "Raw I/O port access using Intel conf2 interface",
 312   .detect = conf2_detect,
 313   .init = conf12_init,
 314   .cleanup = conf12_cleanup,
 315   .scan = pci_generic_scan,
 316   .fill_info = pci_generic_fill_info,
 317   .read = conf2_read,
 318   .write = conf2_write,
 319 };