ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
  40          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  41          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  42          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  43          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  44   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  45   if (b)
  46     printf("\t\tBridge: PM%c B3%c\n",
  47            FLAG(t, PCI_PM_BPCC_ENABLE),
  48            FLAG(~t, PCI_PM_PPB_B2_B3));
  49 }
  50
  51 static void
  52 format_agp_rate(int rate, char *buf, int agp3)
  53 {
  54   char *c = buf;
  55   int i;
  56
  57   for (i=0; i<=2; i++)
  58     if (rate & (1 << i))
  59       {
  60         if (c != buf)
  61           *c++ = ',';
  62         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  63       }
  64   if (c != buf)
  65     *c = 0;
  66   else
  67     strcpy(buf, "<none>");
  68 }
  69
  70 static void
  71 cap_agp(struct device *d, int where, int cap)
  72 {
  73   u32 t;
  74   char rate[16];
  75   int ver, rev;
  76   int agp3 = 0;
  77
  78   ver = (cap >> 4) & 0x0f;
  79   rev = cap & 0x0f;
  80   printf("AGP version %x.%x\n", ver, rev);
  81   if (verbose < 2)
  82     return;
  83   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  84     return;
  85   t = get_conf_long(d, where + PCI_AGP_STATUS);
  86   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  87     agp3 = 1;
  88   format_agp_rate(t & 7, rate, agp3);
  89   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  90          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  91          FLAG(t, PCI_AGP_STATUS_ISOCH),
  92          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  93          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  94          FLAG(t, PCI_AGP_STATUS_SBA),
  95          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  96          FLAG(t, PCI_AGP_STATUS_GART64),
  97          FLAG(t, PCI_AGP_STATUS_HTRANS),
  98          FLAG(t, PCI_AGP_STATUS_64BIT),
  99          FLAG(t, PCI_AGP_STATUS_FW),
 100          FLAG(t, PCI_AGP_STATUS_AGP3),
 101          rate);
 102   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 103   format_agp_rate(t & 7, rate, agp3);
 104   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 105          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 106          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 107          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 108          FLAG(t, PCI_AGP_COMMAND_SBA),
 109          FLAG(t, PCI_AGP_COMMAND_AGP),
 110          FLAG(t, PCI_AGP_COMMAND_GART64),
 111          FLAG(t, PCI_AGP_COMMAND_64BIT),
 112          FLAG(t, PCI_AGP_COMMAND_FW),
 113          rate);
 114 }
 115
 116 static void
 117 cap_pcix_nobridge(struct device *d, int where)
 118 {
 119   u16 command;
 120   u32 status;
 121   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 122
 123   printf("PCI-X non-bridge device\n");
 124
 125   if (verbose < 2)
 126     return;
 127
 128   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 129     return;
 130
 131   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 132   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 133   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 134          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 135          FLAG(command, PCI_PCIX_COMMAND_ERO),
 136          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 137          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 138   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 139          (status & PCI_PCIX_STATUS_BUS) >> 8,
 140          (status & PCI_PCIX_STATUS_DEVICE) >> 3,
 141          (status & PCI_PCIX_STATUS_FUNCTION),
 142          FLAG(status, PCI_PCIX_STATUS_64BIT),
 143          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 144          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 145          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 146          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 147          1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
 148          max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
 149          1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
 150          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 151          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 152          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 153 }
 154
 155 static void
 156 cap_pcix_bridge(struct device *d, int where)
 157 {
 158   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 159   u16 secstatus;
 160   u32 status, upstcr, downstcr;
 161
 162   printf("PCI-X bridge device\n");
 163
 164   if (verbose < 2)
 165     return;
 166
 167   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 168     return;
 169
 170   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 171   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 177          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 178          sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
 179   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 180   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 181          (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
 182          (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
 183          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 189          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 190   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 191   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 192          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 193          (upstcr >> 16) & 0xffff);
 194   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 195   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 196          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 197          (downstcr >> 16) & 0xffff);
 198 }
 199
 200 static void
 201 cap_pcix(struct device *d, int where)
 202 {
 203   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 204     {
 205     case PCI_HEADER_TYPE_NORMAL:
 206       cap_pcix_nobridge(d, where);
 207       break;
 208     case PCI_HEADER_TYPE_BRIDGE:
 209       cap_pcix_bridge(d, where);
 210       break;
 211     }
 212 }
 213
 214 static inline char *
 215 ht_link_width(unsigned width)
 216 {
 217   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 218   return widths[width];
 219 }
 220
 221 static inline char *
 222 ht_link_freq(unsigned freq)
 223 {
 224   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 225                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 226   return freqs[freq];
 227 }
 228
 229 static void
 230 cap_ht_pri(struct device *d, int where, int cmd)
 231 {
 232   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 233   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 234   char *fmt;
 235
 236   printf("HyperTransport: Slave or Primary Interface\n");
 237   if (verbose < 2)
 238     return;
 239
 240   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 241     return;
 242   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 243   if (rid < 0x22 && rid > 0x11)
 244     printf("\t\t!!! Possibly incomplete decoding\n");
 245
 246   if (rid >= 0x22)
 247     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
 248   else
 249     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
 250   printf(fmt,
 251          (cmd & PCI_HT_PRI_CMD_BUID),
 252          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 253          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 254          FLAG(cmd, PCI_HT_PRI_CMD_DD),
 255          FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 256   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 257   if (rid >= 0x22)
 258     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 259   else
 260     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 261   printf(fmt,
 262          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 263          FLAG(lctr0, PCI_HT_LCTR_CST),
 264          FLAG(lctr0, PCI_HT_LCTR_CFE),
 265          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 266          FLAG(lctr0, PCI_HT_LCTR_INIT),
 267          FLAG(lctr0, PCI_HT_LCTR_EOC),
 268          FLAG(lctr0, PCI_HT_LCTR_TXO),
 269          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
 270          FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 271          FLAG(lctr0, PCI_HT_LCTR_LSEN),
 272          FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 273          FLAG(lctr0, PCI_HT_LCTR_64B));
 274   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 275   if (rid >= 0x22)
 276     fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 277   else
 278     fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 279   printf(fmt,
 280          ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 281          ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 282          ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 283          ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 284          FLAG(lcnf0, PCI_HT_LCNF_DFI),
 285          FLAG(lcnf0, PCI_HT_LCNF_DFO),
 286          FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 287          FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 288   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 289   if (rid >= 0x22)
 290     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 291   else
 292     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 293   printf(fmt,
 294          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 295          FLAG(lctr1, PCI_HT_LCTR_CST),
 296          FLAG(lctr1, PCI_HT_LCTR_CFE),
 297          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 298          FLAG(lctr1, PCI_HT_LCTR_INIT),
 299          FLAG(lctr1, PCI_HT_LCTR_EOC),
 300          FLAG(lctr1, PCI_HT_LCTR_TXO),
 301          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
 302          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 303          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 304          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 305          FLAG(lctr1, PCI_HT_LCTR_64B));
 306   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 307   if (rid >= 0x22)
 308     fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 309   else
 310     fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 311   printf(fmt,
 312          ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 313          ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 314          ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 315          ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 316          FLAG(lcnf1, PCI_HT_LCNF_DFI),
 317          FLAG(lcnf1, PCI_HT_LCNF_DFO),
 318          FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 319          FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 320   printf("\t\tRevision ID: %u.%02u\n",
 321          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 322   if (rid < 0x22)
 323     return;
 324   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 325   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 326   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 327          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 328          FLAG(lfrer0, PCI_HT_LFRER_OV),
 329          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 330          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 331   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 332   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 333          FLAG(lfcap0, PCI_HT_LFCAP_200),
 334          FLAG(lfcap0, PCI_HT_LFCAP_300),
 335          FLAG(lfcap0, PCI_HT_LFCAP_400),
 336          FLAG(lfcap0, PCI_HT_LFCAP_500),
 337          FLAG(lfcap0, PCI_HT_LFCAP_600),
 338          FLAG(lfcap0, PCI_HT_LFCAP_800),
 339          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 340          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 341          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 342          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 343          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 344   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 345   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 346          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 347          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 348          FLAG(ftr, PCI_HT_FTR_CRCTM),
 349          FLAG(ftr, PCI_HT_FTR_ECTLT),
 350          FLAG(ftr, PCI_HT_FTR_64BA),
 351          FLAG(ftr, PCI_HT_FTR_UIDRD));
 352   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 353   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 354   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 355          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 356          FLAG(lfrer1, PCI_HT_LFRER_OV),
 357          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 358          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 359   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 360   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 361          FLAG(lfcap1, PCI_HT_LFCAP_200),
 362          FLAG(lfcap1, PCI_HT_LFCAP_300),
 363          FLAG(lfcap1, PCI_HT_LFCAP_400),
 364          FLAG(lfcap1, PCI_HT_LFCAP_500),
 365          FLAG(lfcap1, PCI_HT_LFCAP_600),
 366          FLAG(lfcap1, PCI_HT_LFCAP_800),
 367          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 368          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 369          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 370          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 371          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 372   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 373   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 374          FLAG(eh, PCI_HT_EH_PFLE),
 375          FLAG(eh, PCI_HT_EH_OFLE),
 376          FLAG(eh, PCI_HT_EH_PFE),
 377          FLAG(eh, PCI_HT_EH_OFE),
 378          FLAG(eh, PCI_HT_EH_EOCFE),
 379          FLAG(eh, PCI_HT_EH_RFE),
 380          FLAG(eh, PCI_HT_EH_CRCFE),
 381          FLAG(eh, PCI_HT_EH_SERRFE),
 382          FLAG(eh, PCI_HT_EH_CF),
 383          FLAG(eh, PCI_HT_EH_RE),
 384          FLAG(eh, PCI_HT_EH_PNFE),
 385          FLAG(eh, PCI_HT_EH_ONFE),
 386          FLAG(eh, PCI_HT_EH_EOCNFE),
 387          FLAG(eh, PCI_HT_EH_RNFE),
 388          FLAG(eh, PCI_HT_EH_CRCNFE),
 389          FLAG(eh, PCI_HT_EH_SERRNFE));
 390   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 391   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 392   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 393   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 394   printf("\t\tBus Number: %02x\n", bn);
 395 }
 396
 397 static void
 398 cap_ht_sec(struct device *d, int where, int cmd)
 399 {
 400   u16 lctr, lcnf, ftr, eh;
 401   u8 rid, lfrer, lfcap, mbu, mlu;
 402   char *fmt;
 403
 404   printf("HyperTransport: Host or Secondary Interface\n");
 405   if (verbose < 2)
 406     return;
 407
 408   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 409     return;
 410   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 411   if (rid < 0x22 && rid > 0x11)
 412     printf("\t\t!!! Possibly incomplete decoding\n");
 413
 414   if (rid >= 0x22)
 415     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 416   else
 417     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 418   printf(fmt,
 419          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 420          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 421          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 422          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 423          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 424          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 425          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 426          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 427   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 428   if (rid >= 0x22)
 429     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 430   else
 431     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 432   printf(fmt,
 433          FLAG(lctr, PCI_HT_LCTR_CFLE),
 434          FLAG(lctr, PCI_HT_LCTR_CST),
 435          FLAG(lctr, PCI_HT_LCTR_CFE),
 436          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 437          FLAG(lctr, PCI_HT_LCTR_INIT),
 438          FLAG(lctr, PCI_HT_LCTR_EOC),
 439          FLAG(lctr, PCI_HT_LCTR_TXO),
 440          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 441          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 442          FLAG(lctr, PCI_HT_LCTR_LSEN),
 443          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 444          FLAG(lctr, PCI_HT_LCTR_64B));
 445   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 446   if (rid >= 0x22)
 447     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 448   else
 449     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 450   printf(fmt,
 451          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 452          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 453          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 454          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 455          FLAG(lcnf, PCI_HT_LCNF_DFI),
 456          FLAG(lcnf, PCI_HT_LCNF_DFO),
 457          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 458          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 459   printf("\t\tRevision ID: %u.%02u\n",
 460          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 461   if (rid < 0x22)
 462     return;
 463   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 464   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 465   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 466          FLAG(lfrer, PCI_HT_LFRER_PROT),
 467          FLAG(lfrer, PCI_HT_LFRER_OV),
 468          FLAG(lfrer, PCI_HT_LFRER_EOC),
 469          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 470   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 471   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 472          FLAG(lfcap, PCI_HT_LFCAP_200),
 473          FLAG(lfcap, PCI_HT_LFCAP_300),
 474          FLAG(lfcap, PCI_HT_LFCAP_400),
 475          FLAG(lfcap, PCI_HT_LFCAP_500),
 476          FLAG(lfcap, PCI_HT_LFCAP_600),
 477          FLAG(lfcap, PCI_HT_LFCAP_800),
 478          FLAG(lfcap, PCI_HT_LFCAP_1000),
 479          FLAG(lfcap, PCI_HT_LFCAP_1200),
 480          FLAG(lfcap, PCI_HT_LFCAP_1400),
 481          FLAG(lfcap, PCI_HT_LFCAP_1600),
 482          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 483   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 484   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 485          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 486          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 487          FLAG(ftr, PCI_HT_FTR_CRCTM),
 488          FLAG(ftr, PCI_HT_FTR_ECTLT),
 489          FLAG(ftr, PCI_HT_FTR_64BA),
 490          FLAG(ftr, PCI_HT_FTR_UIDRD),
 491          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 492          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 493   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 494     {
 495       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 496       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 497              FLAG(eh, PCI_HT_EH_PFLE),
 498              FLAG(eh, PCI_HT_EH_OFLE),
 499              FLAG(eh, PCI_HT_EH_PFE),
 500              FLAG(eh, PCI_HT_EH_OFE),
 501              FLAG(eh, PCI_HT_EH_EOCFE),
 502              FLAG(eh, PCI_HT_EH_RFE),
 503              FLAG(eh, PCI_HT_EH_CRCFE),
 504              FLAG(eh, PCI_HT_EH_SERRFE),
 505              FLAG(eh, PCI_HT_EH_CF),
 506              FLAG(eh, PCI_HT_EH_RE),
 507              FLAG(eh, PCI_HT_EH_PNFE),
 508              FLAG(eh, PCI_HT_EH_ONFE),
 509              FLAG(eh, PCI_HT_EH_EOCNFE),
 510              FLAG(eh, PCI_HT_EH_RNFE),
 511              FLAG(eh, PCI_HT_EH_CRCNFE),
 512              FLAG(eh, PCI_HT_EH_SERRNFE));
 513       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 514       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 515       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 516     }
 517 }
 518
 519 static void
 520 cap_ht(struct device *d, int where, int cmd)
 521 {
 522   int type;
 523
 524   switch (cmd & PCI_HT_CMD_TYP_HI)
 525     {
 526     case PCI_HT_CMD_TYP_HI_PRI:
 527       cap_ht_pri(d, where, cmd);
 528       return;
 529     case PCI_HT_CMD_TYP_HI_SEC:
 530       cap_ht_sec(d, where, cmd);
 531       return;
 532     }
 533
 534   type = cmd & PCI_HT_CMD_TYP;
 535   switch (type)
 536     {
 537     case PCI_HT_CMD_TYP_SW:
 538       printf("HyperTransport: Switch\n");
 539       break;
 540     case PCI_HT_CMD_TYP_IDC:
 541       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 542       break;
 543     case PCI_HT_CMD_TYP_RID:
 544       printf("HyperTransport: Revision ID: %u.%02u\n",
 545              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 546       break;
 547     case PCI_HT_CMD_TYP_UIDC:
 548       printf("HyperTransport: UnitID Clumping\n");
 549       break;
 550     case PCI_HT_CMD_TYP_ECSA:
 551       printf("HyperTransport: Extended Configuration Space Access\n");
 552       break;
 553     case PCI_HT_CMD_TYP_AM:
 554       printf("HyperTransport: Address Mapping\n");
 555       break;
 556     case PCI_HT_CMD_TYP_MSIM:
 557       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 558              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 559              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 560       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 561         {
 562           u32 offl, offh;
 563           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 564             break;
 565           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 566           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 567           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 568         }
 569       break;
 570     case PCI_HT_CMD_TYP_DR:
 571       printf("HyperTransport: DirectRoute\n");
 572       break;
 573     case PCI_HT_CMD_TYP_VCS:
 574       printf("HyperTransport: VCSet\n");
 575       break;
 576     case PCI_HT_CMD_TYP_RM:
 577       printf("HyperTransport: Retry Mode\n");
 578       break;
 579     case PCI_HT_CMD_TYP_X86:
 580       printf("HyperTransport: X86 (reserved)\n");
 581       break;
 582     default:
 583       printf("HyperTransport: #%02x\n", type >> 11);
 584     }
 585 }
 586
 587 static void
 588 cap_msi(struct device *d, int where, int cap)
 589 {
 590   int is64;
 591   u32 t;
 592   u16 w;
 593
 594   printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
 595          FLAG(cap, PCI_MSI_FLAGS_ENABLE),
 596          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 597          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 598          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 599          FLAG(cap, PCI_MSI_FLAGS_64BIT));
 600   if (verbose < 2)
 601     return;
 602   is64 = cap & PCI_MSI_FLAGS_64BIT;
 603   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 604     return;
 605   printf("\t\tAddress: ");
 606   if (is64)
 607     {
 608       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 609       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 610       printf("%08x", t);
 611     }
 612   else
 613     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 614   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 615   printf("%08x  Data: %04x\n", t, w);
 616   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 617     {
 618       u32 mask, pending;
 619
 620       if (is64)
 621         {
 622           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 623             return;
 624           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 625           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 626         }
 627       else
 628         {
 629           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 630             return;
 631           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 632           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 633         }
 634       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 635     }
 636 }
 637
 638 static float power_limit(int value, int scale)
 639 {
 640   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 641   return value * scales[scale];
 642 }
 643
 644 static const char *latency_l0s(int value)
 645 {
 646   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 647   return latencies[value];
 648 }
 649
 650 static const char *latency_l1(int value)
 651 {
 652   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 653   return latencies[value];
 654 }
 655
 656 static void cap_express_dev(struct device *d, int where, int type)
 657 {
 658   u32 t;
 659   u16 w;
 660
 661   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 662   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 663         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 664         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
 665   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 666     printf(", Latency L0s %s, L1 %s",
 667         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 668         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 669   printf("\n");
 670   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 671   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 672       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 673     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 674         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 675         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 676   printf(" RBE%c",
 677         FLAG(t, PCI_EXP_DEVCAP_RBE));
 678   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 679     printf(" FLReset%c",
 680         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 681   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
 682       (type == PCI_EXP_TYPE_PCI_BRIDGE))
 683     printf(" SlotPowerLimit %.3fW",
 684         power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 685                     (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
 686   printf("\n");
 687
 688   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 689   printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
 690         FLAG(w, PCI_EXP_DEVCTL_CERE),
 691         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 692         FLAG(w, PCI_EXP_DEVCTL_FERE),
 693         FLAG(w, PCI_EXP_DEVCTL_URRE));
 694   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 695         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 696         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 697         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 698         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 699         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 700   if (type == PCI_EXP_TYPE_PCI_BRIDGE)
 701     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 702   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
 703       (t & PCI_EXP_DEVCAP_FLRESET))
 704     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 705   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 706         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 707         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 708
 709   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 710   printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
 711         FLAG(w, PCI_EXP_DEVSTA_CED),
 712         FLAG(w, PCI_EXP_DEVSTA_NFED),
 713         FLAG(w, PCI_EXP_DEVSTA_FED),
 714         FLAG(w, PCI_EXP_DEVSTA_URD),
 715         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 716         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 717 }
 718
 719 static char *link_speed(int speed)
 720 {
 721   switch (speed)
 722     {
 723       case 1:
 724         return "2.5GT/s";
 725       case 2:
 726         return "5GT/s";
 727       case 3:
 728         return "8GT/s";
 729       case 4:
 730         return "16GT/s";
 731       default:
 732         return "unknown";
 733     }
 734 }
 735
 736 static char *link_compare(int sta, int cap)
 737 {
 738   if (sta < cap)
 739     return "downgraded";
 740   if (sta > cap)
 741     return "strange";
 742   return "ok";
 743 }
 744
 745 static char *aspm_support(int code)
 746 {
 747   switch (code)
 748     {
 749       case 0:
 750         return "not supported";
 751       case 1:
 752         return "L0s";
 753       case 2:
 754         return "L1";
 755       case 3:
 756         return "L0s L1";
 757       default:
 758         return "unknown";
 759     }
 760 }
 761
 762 static const char *aspm_enabled(int code)
 763 {
 764   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 765   return desc[code];
 766 }
 767
 768 static void cap_express_link(struct device *d, int where, int type)
 769 {
 770   u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
 771   u16 w;
 772
 773   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 774   aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
 775   cap_speed = t & PCI_EXP_LNKCAP_SPEED;
 776   cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
 777   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
 778         t >> 24,
 779         link_speed(cap_speed), cap_width,
 780         aspm_support(aspm));
 781   if (aspm)
 782     {
 783       printf(", Exit Latency ");
 784       if (aspm & 1)
 785         printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
 786       if (aspm & 2)
 787         printf("%sL1 %s", (aspm & 1) ? ", " : "",
 788             latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 789     }
 790   printf("\n");
 791   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
 792         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 793         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 794         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 795         FLAG(t, PCI_EXP_LNKCAP_LBNC),
 796         FLAG(t, PCI_EXP_LNKCAP_AOC));
 797
 798   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 799   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 800   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 801       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 802     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 803   printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 804         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 805         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 806         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 807         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 808         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 809         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 810         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 811
 812   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 813   sta_speed = w & PCI_EXP_LNKSTA_SPEED;
 814   sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
 815   printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
 816         link_speed(sta_speed),
 817         link_compare(sta_speed, cap_speed),
 818         sta_width,
 819         link_compare(sta_width, cap_width));
 820   printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 821         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 822         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 823         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 824         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 825         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 826         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 827 }
 828
 829 static const char *indicator(int code)
 830 {
 831   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 832   return names[code];
 833 }
 834
 835 static void cap_express_slot(struct device *d, int where)
 836 {
 837   u32 t;
 838   u16 w;
 839
 840   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 841   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 842         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 843         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 844         FLAG(t, PCI_EXP_SLTCAP_MRL),
 845         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 846         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 847         FLAG(t, PCI_EXP_SLTCAP_HPC),
 848         FLAG(t, PCI_EXP_SLTCAP_HPS));
 849   printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
 850         (t & PCI_EXP_SLTCAP_PSN) >> 19,
 851         power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
 852         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 853         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 854
 855   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 856   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 857         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 858         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 859         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 860         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 861         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 862         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 863         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 864   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 865         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 866         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 867         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 868         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 869
 870   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 871   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 872         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 873         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 874         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 875         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 876         FLAG(w, PCI_EXP_SLTSTA_PRES),
 877         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 878   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 879         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 880         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 881         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 882 }
 883
 884 static void cap_express_root(struct device *d, int where)
 885 {
 886   u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
 887   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 888         FLAG(w, PCI_EXP_RTCTL_SECEE),
 889         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 890         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 891         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 892         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 893
 894   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 895   printf("\t\tRootCap: CRSVisible%c\n",
 896         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 897
 898   w = get_conf_long(d, where + PCI_EXP_RTSTA);
 899   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 900         w & PCI_EXP_RTSTA_PME_REQID,
 901         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 902         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 903 }
 904
 905 static const char *cap_express_dev2_timeout_range(int type)
 906 {
 907   /* Decode Completion Timeout Ranges. */
 908   switch (type)
 909     {
 910       case 0:
 911         return "Not Supported";
 912       case 1:
 913         return "Range A";
 914       case 2:
 915         return "Range B";
 916       case 3:
 917         return "Range AB";
 918       case 6:
 919         return "Range BC";
 920       case 7:
 921         return "Range ABC";
 922       case 14:
 923         return "Range BCD";
 924       case 15:
 925         return "Range ABCD";
 926       default:
 927         return "Unknown";
 928     }
 929 }
 930
 931 static const char *cap_express_dev2_timeout_value(int type)
 932 {
 933   /* Decode Completion Timeout Value. */
 934   switch (type)
 935     {
 936       case 0:
 937         return "50us to 50ms";
 938       case 1:
 939         return "50us to 100us";
 940       case 2:
 941         return "1ms to 10ms";
 942       case 5:
 943         return "16ms to 55ms";
 944       case 6:
 945         return "65ms to 210ms";
 946       case 9:
 947         return "260ms to 900ms";
 948       case 10:
 949         return "1s to 3.5s";
 950       case 13:
 951         return "4s to 13s";
 952       case 14:
 953         return "17s to 64s";
 954       default:
 955         return "Unknown";
 956     }
 957 }
 958
 959 static const char *cap_express_devcap2_obff(int obff)
 960 {
 961   switch (obff)
 962     {
 963       case 1:
 964         return "Via message";
 965       case 2:
 966         return "Via WAKE#";
 967       case 3:
 968         return "Via message/WAKE#";
 969       default:
 970         return "Not Supported";
 971     }
 972 }
 973
 974 static const char *cap_express_devctl2_obff(int obff)
 975 {
 976   switch (obff)
 977     {
 978       case 0:
 979         return "Disabled";
 980       case 1:
 981         return "Via message A";
 982       case 2:
 983         return "Via message B";
 984       case 3:
 985         return "Via WAKE#";
 986       default:
 987         return "Unknown";
 988     }
 989 }
 990
 991 static int
 992 device_has_memory_space_bar(struct device *d)
 993 {
 994   struct pci_dev *p = d->dev;
 995   int i, found = 0;
 996
 997   for (i=0; i<6; i++)
 998     if (p->base_addr[i] && p->size[i])
 999       {
1000         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1001           {
1002             found = 1;
1003             break;
1004           }
1005       }
1006   return found;
1007 }
1008
1009 static void cap_express_dev2(struct device *d, int where, int type)
1010 {
1011   u32 l;
1012   u16 w;
1013   int has_mem_bar = device_has_memory_space_bar(d);
1014
1015   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1016   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1017         cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1018         FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
1019         FLAG(l, PCI_EXP_DEVCAP2_LTR),
1020         cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)));
1021   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1022     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1023   else
1024     printf("\n");
1025   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1026       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1027     {
1028        printf("\t\t\t AtomicOpsCap:");
1029        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1030            type == PCI_EXP_TYPE_DOWNSTREAM)
1031          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1032        if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1033          printf(" 32bit%c 64bit%c 128bitCAS%c",
1034                 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1035                 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1036                 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1037        printf("\n");
1038     }
1039
1040   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1041   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1042         cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1043         FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
1044         FLAG(w, PCI_EXP_DEV2_LTR),
1045         cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
1046   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1047     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1048   else
1049     printf("\n");
1050   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1051       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1052       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1053     {
1054       printf("\t\t\t AtomicOpsCtl:");
1055       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1056           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1057         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
1058       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1059           type == PCI_EXP_TYPE_DOWNSTREAM)
1060         printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
1061       printf("\n");
1062     }
1063 }
1064
1065 static const char *cap_express_link2_speed(int type)
1066 {
1067   switch (type)
1068     {
1069       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1070       case 1:
1071         return "2.5GT/s";
1072       case 2:
1073         return "5GT/s";
1074       case 3:
1075         return "8GT/s";
1076       case 4:
1077         return "16GT/s";
1078       default:
1079         return "Unknown";
1080     }
1081 }
1082
1083 static const char *cap_express_link2_deemphasis(int type)
1084 {
1085   switch (type)
1086     {
1087       case 0:
1088         return "-6dB";
1089       case 1:
1090         return "-3.5dB";
1091       default:
1092         return "Unknown";
1093     }
1094 }
1095
1096 static const char *cap_express_link2_transmargin(int type)
1097 {
1098   switch (type)
1099     {
1100       case 0:
1101         return "Normal Operating Range";
1102       case 1:
1103         return "800-1200mV(full-swing)/400-700mV(half-swing)";
1104       case 2:
1105       case 3:
1106       case 4:
1107       case 5:
1108         return "200-400mV(full-swing)/100-200mV(half-swing)";
1109       default:
1110         return "Unknown";
1111     }
1112 }
1113
1114 static void cap_express_link2(struct device *d, int where, int type)
1115 {
1116   u16 w;
1117
1118   if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1119         (d->dev->dev != 0 || d->dev->func != 0))) {
1120     w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1121     printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1122         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1123         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1124         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1125     if (type == PCI_EXP_TYPE_DOWNSTREAM)
1126       printf(", Selectable De-emphasis: %s",
1127         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1128     printf("\n"
1129         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1130         "\t\t\t Compliance De-emphasis: %s\n",
1131         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1132         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1133         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1134         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1135   }
1136
1137   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1138   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
1139         "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
1140         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1141         FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1142         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1143         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1144         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1145         FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
1146 }
1147
1148 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1149 {
1150   /* No capabilities that require this field in PCIe rev2.0 spec. */
1151 }
1152
1153 static int
1154 cap_express(struct device *d, int where, int cap)
1155 {
1156   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1157   int size;
1158   int slot = 0;
1159   int link = 1;
1160
1161   printf("Express ");
1162   if (verbose >= 2)
1163     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1164   switch (type)
1165     {
1166     case PCI_EXP_TYPE_ENDPOINT:
1167       printf("Endpoint");
1168       break;
1169     case PCI_EXP_TYPE_LEG_END:
1170       printf("Legacy Endpoint");
1171       break;
1172     case PCI_EXP_TYPE_ROOT_PORT:
1173       slot = cap & PCI_EXP_FLAGS_SLOT;
1174       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1175       break;
1176     case PCI_EXP_TYPE_UPSTREAM:
1177       printf("Upstream Port");
1178       break;
1179     case PCI_EXP_TYPE_DOWNSTREAM:
1180       slot = cap & PCI_EXP_FLAGS_SLOT;
1181       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1182       break;
1183     case PCI_EXP_TYPE_PCI_BRIDGE:
1184       printf("PCI-Express to PCI/PCI-X Bridge");
1185       break;
1186     case PCI_EXP_TYPE_PCIE_BRIDGE:
1187       slot = cap & PCI_EXP_FLAGS_SLOT;
1188       printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1189              FLAG(cap, PCI_EXP_FLAGS_SLOT));
1190       break;
1191     case PCI_EXP_TYPE_ROOT_INT_EP:
1192       link = 0;
1193       printf("Root Complex Integrated Endpoint");
1194       break;
1195     case PCI_EXP_TYPE_ROOT_EC:
1196       link = 0;
1197       printf("Root Complex Event Collector");
1198       break;
1199     default:
1200       printf("Unknown type %d", type);
1201   }
1202   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1203   if (verbose < 2)
1204     return type;
1205
1206   size = 16;
1207   if (slot)
1208     size = 24;
1209   if (type == PCI_EXP_TYPE_ROOT_PORT)
1210     size = 32;
1211   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1212     return type;
1213
1214   cap_express_dev(d, where, type);
1215   if (link)
1216     cap_express_link(d, where, type);
1217   if (slot)
1218     cap_express_slot(d, where);
1219   if (type == PCI_EXP_TYPE_ROOT_PORT)
1220     cap_express_root(d, where);
1221
1222   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1223     return type;
1224
1225   size = 16;
1226   if (slot)
1227     size = 24;
1228   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1229     return type;
1230
1231   cap_express_dev2(d, where, type);
1232   if (link)
1233     cap_express_link2(d, where, type);
1234   if (slot)
1235     cap_express_slot2(d, where);
1236   return type;
1237 }
1238
1239 static void
1240 cap_msix(struct device *d, int where, int cap)
1241 {
1242   u32 off;
1243
1244   printf("MSI-X: Enable%c Count=%d Masked%c\n",
1245          FLAG(cap, PCI_MSIX_ENABLE),
1246          (cap & PCI_MSIX_TABSIZE) + 1,
1247          FLAG(cap, PCI_MSIX_MASK));
1248   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1249     return;
1250
1251   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1252   printf("\t\tVector table: BAR=%d offset=%08x\n",
1253          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1254   off = get_conf_long(d, where + PCI_MSIX_PBA);
1255   printf("\t\tPBA: BAR=%d offset=%08x\n",
1256          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1257 }
1258
1259 static void
1260 cap_slotid(int cap)
1261 {
1262   int esr = cap & 0xff;
1263   int chs = cap >> 8;
1264
1265   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1266          esr & PCI_SID_ESR_NSLOTS,
1267          FLAG(esr, PCI_SID_ESR_FIC),
1268          chs);
1269 }
1270
1271 static void
1272 cap_ssvid(struct device *d, int where)
1273 {
1274   u16 subsys_v, subsys_d;
1275   char ssnamebuf[256];
1276
1277   if (!config_fetch(d, where, 8))
1278     return;
1279   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1280   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1281   printf("Subsystem: %s\n",
1282            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1283                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1284                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1285 }
1286
1287 static void
1288 cap_debug_port(int cap)
1289 {
1290   int bar = cap >> 13;
1291   int pos = cap & 0x1fff;
1292   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1293 }
1294
1295 static void
1296 cap_af(struct device *d, int where)
1297 {
1298   u8 reg;
1299
1300   printf("PCI Advanced Features\n");
1301   if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1302     return;
1303
1304   reg = get_conf_byte(d, where + PCI_AF_CAP);
1305   printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1306          FLAG(reg, PCI_AF_CAP_FLR));
1307   reg = get_conf_byte(d, where + PCI_AF_CTRL);
1308   printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1309   reg = get_conf_byte(d, where + PCI_AF_STATUS);
1310   printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1311 }
1312
1313 static void
1314 cap_sata_hba(struct device *d, int where, int cap)
1315 {
1316   u32 bars;
1317   int bar;
1318
1319   printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1320   if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1321     {
1322       printf("\n");
1323       return;
1324     }
1325
1326   bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1327   bar = BITS(bars, 0, 4);
1328   if (bar >= 4 && bar <= 9)
1329     printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1330   else if (bar == 15)
1331     printf(" InCfgSpace\n");
1332   else
1333     printf(" BAR??%d\n", bar);
1334 }
1335
1336 static const char *cap_ea_property(int p, int is_secondary)
1337 {
1338   switch (p) {
1339   case 0x00:
1340     return "memory space, non-prefetchable";
1341   case 0x01:
1342     return "memory space, prefetchable";
1343   case 0x02:
1344     return "I/O space";
1345   case 0x03:
1346     return "VF memory space, prefetchable";
1347   case 0x04:
1348     return "VF memory space, non-prefetchable";
1349   case 0x05:
1350     return "allocation behind bridge, non-prefetchable memory";
1351   case 0x06:
1352     return "allocation behind bridge, prefetchable memory";
1353   case 0x07:
1354     return "allocation behind bridge, I/O space";
1355   case 0xfd:
1356     return "memory space resource unavailable for use";
1357   case 0xfe:
1358     return "I/O space resource unavailable for use";
1359   case 0xff:
1360     if (is_secondary)
1361       return "entry unavailable for use, PrimaryProperties should be used";
1362     else
1363       return "entry unavailable for use";
1364   default:
1365     return NULL;
1366   }
1367 }
1368
1369 static void cap_ea(struct device *d, int where, int cap)
1370 {
1371   int entry;
1372   int entry_base = where + 4;
1373   int num_entries = BITS(cap, 0, 6);
1374   u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1375
1376   printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1377   if (htype == PCI_HEADER_TYPE_BRIDGE) {
1378     byte fixed_sub, fixed_sec;
1379
1380     entry_base += 4;
1381     if (!config_fetch(d, where + 4, 2)) {
1382       printf("\n");
1383       return;
1384     }
1385     fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1386     fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1387     printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1388   }
1389   printf("\n");
1390   if (verbose < 2)
1391     return;
1392
1393   for (entry = 0; entry < num_entries; entry++) {
1394     int max_offset_high_pos, has_base_high, has_max_offset_high;
1395     u32 entry_header;
1396     u32 base, max_offset;
1397     int es, bei, pp, sp;
1398     const char *prop_text;
1399
1400     if (!config_fetch(d, entry_base, 4))
1401       return;
1402     entry_header = get_conf_long(d, entry_base);
1403     es = BITS(entry_header, 0, 3);
1404     bei = BITS(entry_header, 4, 4);
1405     pp = BITS(entry_header, 8, 8);
1406     sp = BITS(entry_header, 16, 8);
1407     if (!config_fetch(d, entry_base + 4, es * 4))
1408       return;
1409     printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1410            FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1411            FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1412     printf("\t\t\t BAR Equivalent Indicator: ");
1413     switch (bei) {
1414     case 0:
1415     case 1:
1416     case 2:
1417     case 3:
1418     case 4:
1419     case 5:
1420       printf("BAR %u", bei);
1421       break;
1422     case 6:
1423       printf("resource behind function");
1424       break;
1425     case 7:
1426       printf("not indicated");
1427       break;
1428     case 8:
1429       printf("expansion ROM");
1430       break;
1431     case 9:
1432     case 10:
1433     case 11:
1434     case 12:
1435     case 13:
1436     case 14:
1437       printf("VF-BAR %u", bei - 9);
1438       break;
1439     default:
1440       printf("reserved");
1441       break;
1442     }
1443     printf("\n");
1444
1445     prop_text = cap_ea_property(pp, 0);
1446     printf("\t\t\t PrimaryProperties: ");
1447     if (prop_text)
1448       printf("%s\n", prop_text);
1449     else
1450       printf("[%02x]\n", pp);
1451
1452     prop_text = cap_ea_property(sp, 1);
1453     printf("\t\t\t SecondaryProperties: ");
1454     if (prop_text)
1455       printf("%s\n", prop_text);
1456     else
1457       printf("[%02x]\n", sp);
1458
1459     base = get_conf_long(d, entry_base + 4);
1460     has_base_high = ((base & 2) != 0);
1461     base &= ~3;
1462
1463     max_offset = get_conf_long(d, entry_base + 8);
1464     has_max_offset_high = ((max_offset & 2) != 0);
1465     max_offset |= 3;
1466     max_offset_high_pos = entry_base + 12;
1467
1468     printf("\t\t\t Base: ");
1469     if (has_base_high) {
1470       u32 base_high = get_conf_long(d, entry_base + 12);
1471
1472       printf("%x", base_high);
1473       max_offset_high_pos += 4;
1474     }
1475     printf("%08x\n", base);
1476
1477     printf("\t\t\t MaxOffset: ");
1478     if (has_max_offset_high) {
1479       u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1480
1481       printf("%x", max_offset_high);
1482     }
1483     printf("%08x\n", max_offset);
1484
1485     entry_base += 4 + 4 * es;
1486   }
1487 }
1488
1489 void
1490 show_caps(struct device *d, int where)
1491 {
1492   int can_have_ext_caps = 0;
1493   int type = -1;
1494
1495   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1496     {
1497       byte been_there[256];
1498       where = get_conf_byte(d, where) & ~3;
1499       memset(been_there, 0, 256);
1500       while (where)
1501         {
1502           int id, next, cap;
1503           printf("\tCapabilities: ");
1504           if (!config_fetch(d, where, 4))
1505             {
1506               puts("<access denied>");
1507               break;
1508             }
1509           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1510           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1511           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1512           printf("[%02x] ", where);
1513           if (been_there[where]++)
1514             {
1515               printf("<chain looped>\n");
1516               break;
1517             }
1518           if (id == 0xff)
1519             {
1520               printf("<chain broken>\n");
1521               break;
1522             }
1523           switch (id)
1524             {
1525             case PCI_CAP_ID_PM:
1526               cap_pm(d, where, cap);
1527               break;
1528             case PCI_CAP_ID_AGP:
1529               cap_agp(d, where, cap);
1530               break;
1531             case PCI_CAP_ID_VPD:
1532               cap_vpd(d);
1533               break;
1534             case PCI_CAP_ID_SLOTID:
1535               cap_slotid(cap);
1536               break;
1537             case PCI_CAP_ID_MSI:
1538               cap_msi(d, where, cap);
1539               break;
1540             case PCI_CAP_ID_CHSWP:
1541               printf("CompactPCI hot-swap <?>\n");
1542               break;
1543             case PCI_CAP_ID_PCIX:
1544               cap_pcix(d, where);
1545               can_have_ext_caps = 1;
1546               break;
1547             case PCI_CAP_ID_HT:
1548               cap_ht(d, where, cap);
1549               break;
1550             case PCI_CAP_ID_VNDR:
1551               show_vendor_caps(d, where, cap);
1552               break;
1553             case PCI_CAP_ID_DBG:
1554               cap_debug_port(cap);
1555               break;
1556             case PCI_CAP_ID_CCRC:
1557               printf("CompactPCI central resource control <?>\n");
1558               break;
1559             case PCI_CAP_ID_HOTPLUG:
1560               printf("Hot-plug capable\n");
1561               break;
1562             case PCI_CAP_ID_SSVID:
1563               cap_ssvid(d, where);
1564               break;
1565             case PCI_CAP_ID_AGP3:
1566               printf("AGP3 <?>\n");
1567               break;
1568             case PCI_CAP_ID_SECURE:
1569               printf("Secure device <?>\n");
1570               break;
1571             case PCI_CAP_ID_EXP:
1572               type = cap_express(d, where, cap);
1573               can_have_ext_caps = 1;
1574               break;
1575             case PCI_CAP_ID_MSIX:
1576               cap_msix(d, where, cap);
1577               break;
1578             case PCI_CAP_ID_SATA:
1579               cap_sata_hba(d, where, cap);
1580               break;
1581             case PCI_CAP_ID_AF:
1582               cap_af(d, where);
1583               break;
1584             case PCI_CAP_ID_EA:
1585               cap_ea(d, where, cap);
1586               break;
1587             default:
1588               printf("#%02x [%04x]\n", id, cap);
1589             }
1590           where = next;
1591         }
1592     }
1593   if (can_have_ext_caps)
1594     show_ext_caps(d, type);
1595 }