2 * The PCI Utilities -- Show Capabilities
4 * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_pm(struct device
*d
, int where
, int cap
)
18 static int pm_aux_current
[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
20 printf("Power Management version %d\n", cap
& PCI_PM_CAP_VER_MASK
);
23 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
24 FLAG(cap
, PCI_PM_CAP_PME_CLOCK
),
25 FLAG(cap
, PCI_PM_CAP_DSI
),
26 FLAG(cap
, PCI_PM_CAP_D1
),
27 FLAG(cap
, PCI_PM_CAP_D2
),
28 pm_aux_current
[(cap
& PCI_PM_CAP_AUX_C_MASK
) >> 6],
29 FLAG(cap
, PCI_PM_CAP_PME_D0
),
30 FLAG(cap
, PCI_PM_CAP_PME_D1
),
31 FLAG(cap
, PCI_PM_CAP_PME_D2
),
32 FLAG(cap
, PCI_PM_CAP_PME_D3_HOT
),
33 FLAG(cap
, PCI_PM_CAP_PME_D3_COLD
));
34 if (!config_fetch(d
, where
+ PCI_PM_CTRL
, PCI_PM_SIZEOF
- PCI_PM_CTRL
))
36 t
= get_conf_word(d
, where
+ PCI_PM_CTRL
);
37 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
38 t
& PCI_PM_CTRL_STATE_MASK
,
39 FLAG(t
, PCI_PM_CTRL_NO_SOFT_RST
),
40 FLAG(t
, PCI_PM_CTRL_PME_ENABLE
),
41 (t
& PCI_PM_CTRL_DATA_SEL_MASK
) >> 9,
42 (t
& PCI_PM_CTRL_DATA_SCALE_MASK
) >> 13,
43 FLAG(t
, PCI_PM_CTRL_PME_STATUS
));
44 b
= get_conf_byte(d
, where
+ PCI_PM_PPB_EXTENSIONS
);
46 printf("\t\tBridge: PM%c B3%c\n",
47 FLAG(t
, PCI_PM_BPCC_ENABLE
),
48 FLAG(~t
, PCI_PM_PPB_B2_B3
));
52 format_agp_rate(int rate
, char *buf
, int agp3
)
62 c
+= sprintf(c
, "x%d", 1 << (i
+ 2*agp3
));
67 strcpy(buf
, "<none>");
71 cap_agp(struct device
*d
, int where
, int cap
)
78 ver
= (cap
>> 4) & 0x0f;
80 printf("AGP version %x.%x\n", ver
, rev
);
83 if (!config_fetch(d
, where
+ PCI_AGP_STATUS
, PCI_AGP_SIZEOF
- PCI_AGP_STATUS
))
85 t
= get_conf_long(d
, where
+ PCI_AGP_STATUS
);
86 if (ver
>= 3 && (t
& PCI_AGP_STATUS_AGP3
))
88 format_agp_rate(t
& 7, rate
, agp3
);
89 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
90 ((t
& PCI_AGP_STATUS_RQ_MASK
) >> 24U) + 1,
91 FLAG(t
, PCI_AGP_STATUS_ISOCH
),
92 ((t
& PCI_AGP_STATUS_ARQSZ_MASK
) >> 13),
93 ((t
& PCI_AGP_STATUS_CAL_MASK
) >> 10),
94 FLAG(t
, PCI_AGP_STATUS_SBA
),
95 FLAG(t
, PCI_AGP_STATUS_ITA_COH
),
96 FLAG(t
, PCI_AGP_STATUS_GART64
),
97 FLAG(t
, PCI_AGP_STATUS_HTRANS
),
98 FLAG(t
, PCI_AGP_STATUS_64BIT
),
99 FLAG(t
, PCI_AGP_STATUS_FW
),
100 FLAG(t
, PCI_AGP_STATUS_AGP3
),
102 t
= get_conf_long(d
, where
+ PCI_AGP_COMMAND
);
103 format_agp_rate(t
& 7, rate
, agp3
);
104 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
105 ((t
& PCI_AGP_COMMAND_RQ_MASK
) >> 24U) + 1,
106 ((t
& PCI_AGP_COMMAND_ARQSZ_MASK
) >> 13),
107 ((t
& PCI_AGP_COMMAND_CAL_MASK
) >> 10),
108 FLAG(t
, PCI_AGP_COMMAND_SBA
),
109 FLAG(t
, PCI_AGP_COMMAND_AGP
),
110 FLAG(t
, PCI_AGP_COMMAND_GART64
),
111 FLAG(t
, PCI_AGP_COMMAND_64BIT
),
112 FLAG(t
, PCI_AGP_COMMAND_FW
),
117 cap_pcix_nobridge(struct device
*d
, int where
)
121 static const byte max_outstanding
[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
123 printf("PCI-X non-bridge device\n");
128 if (!config_fetch(d
, where
+ PCI_PCIX_STATUS
, 4))
131 command
= get_conf_word(d
, where
+ PCI_PCIX_COMMAND
);
132 status
= get_conf_long(d
, where
+ PCI_PCIX_STATUS
);
133 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
134 FLAG(command
, PCI_PCIX_COMMAND_DPERE
),
135 FLAG(command
, PCI_PCIX_COMMAND_ERO
),
136 1 << (9 + ((command
& PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT
) >> 2U)),
137 max_outstanding
[(command
& PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS
) >> 4U]);
138 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
139 (status
& PCI_PCIX_STATUS_BUS
) >> 8,
140 (status
& PCI_PCIX_STATUS_DEVICE
) >> 3,
141 (status
& PCI_PCIX_STATUS_FUNCTION
),
142 FLAG(status
, PCI_PCIX_STATUS_64BIT
),
143 FLAG(status
, PCI_PCIX_STATUS_133MHZ
),
144 FLAG(status
, PCI_PCIX_STATUS_SC_DISCARDED
),
145 FLAG(status
, PCI_PCIX_STATUS_UNEXPECTED_SC
),
146 ((status
& PCI_PCIX_STATUS_DEVICE_COMPLEXITY
) ? "bridge" : "simple"),
147 1 << (9 + ((status
& PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT
) >> 21)),
148 max_outstanding
[(status
& PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS
) >> 23],
149 1 << (3 + ((status
& PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE
) >> 26)),
150 FLAG(status
, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS
),
151 FLAG(status
, PCI_PCIX_STATUS_266MHZ
),
152 FLAG(status
, PCI_PCIX_STATUS_533MHZ
));
156 cap_pcix_bridge(struct device
*d
, int where
)
158 static const char * const sec_clock_freq
[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
160 u32 status
, upstcr
, downstcr
;
162 printf("PCI-X bridge device\n");
167 if (!config_fetch(d
, where
+ PCI_PCIX_BRIDGE_STATUS
, 12))
170 secstatus
= get_conf_word(d
, where
+ PCI_PCIX_BRIDGE_SEC_STATUS
);
171 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
172 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT
),
173 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ
),
174 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED
),
175 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC
),
176 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN
),
177 FLAG(secstatus
, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED
),
178 sec_clock_freq
[(secstatus
& PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ
) >> 6]);
179 status
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_STATUS
);
180 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
181 (status
& PCI_PCIX_BRIDGE_STATUS_BUS
) >> 8,
182 (status
& PCI_PCIX_BRIDGE_STATUS_DEVICE
) >> 3,
183 (status
& PCI_PCIX_BRIDGE_STATUS_FUNCTION
),
184 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_64BIT
),
185 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_133MHZ
),
186 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED
),
187 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC
),
188 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN
),
189 FLAG(status
, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED
));
190 upstcr
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL
);
191 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
192 (upstcr
& PCI_PCIX_BRIDGE_STR_CAPACITY
),
193 (upstcr
>> 16) & 0xffff);
194 downstcr
= get_conf_long(d
, where
+ PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL
);
195 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
196 (downstcr
& PCI_PCIX_BRIDGE_STR_CAPACITY
),
197 (downstcr
>> 16) & 0xffff);
201 cap_pcix(struct device
*d
, int where
)
203 switch (get_conf_byte(d
, PCI_HEADER_TYPE
) & 0x7f)
205 case PCI_HEADER_TYPE_NORMAL
:
206 cap_pcix_nobridge(d
, where
);
208 case PCI_HEADER_TYPE_BRIDGE
:
209 cap_pcix_bridge(d
, where
);
215 ht_link_width(unsigned width
)
217 static char * const widths
[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
218 return widths
[width
];
222 ht_link_freq(unsigned freq
)
224 static char * const freqs
[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
225 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
230 cap_ht_pri(struct device
*d
, int where
, int cmd
)
232 u16 lctr0
, lcnf0
, lctr1
, lcnf1
, eh
;
233 u8 rid
, lfrer0
, lfcap0
, ftr
, lfrer1
, lfcap1
, mbu
, mlu
, bn
;
235 printf("HyperTransport: Slave or Primary Interface\n");
239 if (!config_fetch(d
, where
+ PCI_HT_PRI_LCTR0
, PCI_HT_PRI_SIZEOF
- PCI_HT_PRI_LCTR0
))
241 rid
= get_conf_byte(d
, where
+ PCI_HT_PRI_RID
);
242 if (rid
< 0x22 && rid
> 0x11)
243 printf("\t\t!!! Possibly incomplete decoding\n");
245 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
246 (cmd
& PCI_HT_PRI_CMD_BUID
),
247 (cmd
& PCI_HT_PRI_CMD_UC
) >> 5,
248 FLAG(cmd
, PCI_HT_PRI_CMD_MH
),
249 FLAG(cmd
, PCI_HT_PRI_CMD_DD
));
251 printf(" DUL%c", FLAG(cmd
, PCI_HT_PRI_CMD_DUL
));
254 lctr0
= get_conf_word(d
, where
+ PCI_HT_PRI_LCTR0
);
255 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
256 FLAG(lctr0
, PCI_HT_LCTR_CFLE
),
257 FLAG(lctr0
, PCI_HT_LCTR_CST
),
258 FLAG(lctr0
, PCI_HT_LCTR_CFE
),
259 FLAG(lctr0
, PCI_HT_LCTR_LKFAIL
),
260 FLAG(lctr0
, PCI_HT_LCTR_INIT
),
261 FLAG(lctr0
, PCI_HT_LCTR_EOC
),
262 FLAG(lctr0
, PCI_HT_LCTR_TXO
),
263 (lctr0
& PCI_HT_LCTR_CRCERR
) >> 8);
265 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
266 FLAG(lctr0
, PCI_HT_LCTR_ISOCEN
),
267 FLAG(lctr0
, PCI_HT_LCTR_LSEN
),
268 FLAG(lctr0
, PCI_HT_LCTR_EXTCTL
),
269 FLAG(lctr0
, PCI_HT_LCTR_64B
));
272 lcnf0
= get_conf_word(d
, where
+ PCI_HT_PRI_LCNF0
);
274 printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
275 ht_link_width(lcnf0
& PCI_HT_LCNF_MLWI
),
276 ht_link_width((lcnf0
& PCI_HT_LCNF_MLWO
) >> 4),
277 ht_link_width((lcnf0
& PCI_HT_LCNF_LWI
) >> 8),
278 ht_link_width((lcnf0
& PCI_HT_LCNF_LWO
) >> 12));
280 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
281 ht_link_width(lcnf0
& PCI_HT_LCNF_MLWI
),
282 FLAG(lcnf0
, PCI_HT_LCNF_DFI
),
283 ht_link_width((lcnf0
& PCI_HT_LCNF_MLWO
) >> 4),
284 FLAG(lcnf0
, PCI_HT_LCNF_DFO
),
285 ht_link_width((lcnf0
& PCI_HT_LCNF_LWI
) >> 8),
286 FLAG(lcnf0
, PCI_HT_LCNF_DFIE
),
287 ht_link_width((lcnf0
& PCI_HT_LCNF_LWO
) >> 12),
288 FLAG(lcnf0
, PCI_HT_LCNF_DFOE
));
290 lctr1
= get_conf_word(d
, where
+ PCI_HT_PRI_LCTR1
);
291 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
292 FLAG(lctr1
, PCI_HT_LCTR_CFLE
),
293 FLAG(lctr1
, PCI_HT_LCTR_CST
),
294 FLAG(lctr1
, PCI_HT_LCTR_CFE
),
295 FLAG(lctr1
, PCI_HT_LCTR_LKFAIL
),
296 FLAG(lctr1
, PCI_HT_LCTR_INIT
),
297 FLAG(lctr1
, PCI_HT_LCTR_EOC
),
298 FLAG(lctr1
, PCI_HT_LCTR_TXO
),
299 (lctr1
& PCI_HT_LCTR_CRCERR
) >> 8);
301 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
302 FLAG(lctr1
, PCI_HT_LCTR_ISOCEN
),
303 FLAG(lctr1
, PCI_HT_LCTR_LSEN
),
304 FLAG(lctr1
, PCI_HT_LCTR_EXTCTL
),
305 FLAG(lctr1
, PCI_HT_LCTR_64B
));
308 lcnf1
= get_conf_word(d
, where
+ PCI_HT_PRI_LCNF1
);
310 printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
311 ht_link_width(lcnf1
& PCI_HT_LCNF_MLWI
),
312 ht_link_width((lcnf1
& PCI_HT_LCNF_MLWO
) >> 4),
313 ht_link_width((lcnf1
& PCI_HT_LCNF_LWI
) >> 8),
314 ht_link_width((lcnf1
& PCI_HT_LCNF_LWO
) >> 12));
316 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
317 ht_link_width(lcnf1
& PCI_HT_LCNF_MLWI
),
318 FLAG(lcnf1
, PCI_HT_LCNF_DFI
),
319 ht_link_width((lcnf1
& PCI_HT_LCNF_MLWO
) >> 4),
320 FLAG(lcnf1
, PCI_HT_LCNF_DFO
),
321 ht_link_width((lcnf1
& PCI_HT_LCNF_LWI
) >> 8),
322 FLAG(lcnf1
, PCI_HT_LCNF_DFIE
),
323 ht_link_width((lcnf1
& PCI_HT_LCNF_LWO
) >> 12),
324 FLAG(lcnf1
, PCI_HT_LCNF_DFOE
));
326 printf("\t\tRevision ID: %u.%02u\n",
327 (rid
& PCI_HT_RID_MAJ
) >> 5, (rid
& PCI_HT_RID_MIN
));
331 lfrer0
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFRER0
);
332 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0
& PCI_HT_LFRER_FREQ
));
333 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
334 FLAG(lfrer0
, PCI_HT_LFRER_PROT
),
335 FLAG(lfrer0
, PCI_HT_LFRER_OV
),
336 FLAG(lfrer0
, PCI_HT_LFRER_EOC
),
337 FLAG(lfrer0
, PCI_HT_LFRER_CTLT
));
339 lfcap0
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFCAP0
);
340 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
341 FLAG(lfcap0
, PCI_HT_LFCAP_200
),
342 FLAG(lfcap0
, PCI_HT_LFCAP_300
),
343 FLAG(lfcap0
, PCI_HT_LFCAP_400
),
344 FLAG(lfcap0
, PCI_HT_LFCAP_500
),
345 FLAG(lfcap0
, PCI_HT_LFCAP_600
),
346 FLAG(lfcap0
, PCI_HT_LFCAP_800
),
347 FLAG(lfcap0
, PCI_HT_LFCAP_1000
),
348 FLAG(lfcap0
, PCI_HT_LFCAP_1200
),
349 FLAG(lfcap0
, PCI_HT_LFCAP_1400
),
350 FLAG(lfcap0
, PCI_HT_LFCAP_1600
),
351 FLAG(lfcap0
, PCI_HT_LFCAP_VEND
));
353 ftr
= get_conf_byte(d
, where
+ PCI_HT_PRI_FTR
);
354 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
355 FLAG(ftr
, PCI_HT_FTR_ISOCFC
),
356 FLAG(ftr
, PCI_HT_FTR_LDTSTOP
),
357 FLAG(ftr
, PCI_HT_FTR_CRCTM
),
358 FLAG(ftr
, PCI_HT_FTR_ECTLT
),
359 FLAG(ftr
, PCI_HT_FTR_64BA
),
360 FLAG(ftr
, PCI_HT_FTR_UIDRD
));
362 lfrer1
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFRER1
);
363 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1
& PCI_HT_LFRER_FREQ
));
364 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
365 FLAG(lfrer1
, PCI_HT_LFRER_PROT
),
366 FLAG(lfrer1
, PCI_HT_LFRER_OV
),
367 FLAG(lfrer1
, PCI_HT_LFRER_EOC
),
368 FLAG(lfrer1
, PCI_HT_LFRER_CTLT
));
370 lfcap1
= get_conf_byte(d
, where
+ PCI_HT_PRI_LFCAP1
);
371 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
372 FLAG(lfcap1
, PCI_HT_LFCAP_200
),
373 FLAG(lfcap1
, PCI_HT_LFCAP_300
),
374 FLAG(lfcap1
, PCI_HT_LFCAP_400
),
375 FLAG(lfcap1
, PCI_HT_LFCAP_500
),
376 FLAG(lfcap1
, PCI_HT_LFCAP_600
),
377 FLAG(lfcap1
, PCI_HT_LFCAP_800
),
378 FLAG(lfcap1
, PCI_HT_LFCAP_1000
),
379 FLAG(lfcap1
, PCI_HT_LFCAP_1200
),
380 FLAG(lfcap1
, PCI_HT_LFCAP_1400
),
381 FLAG(lfcap1
, PCI_HT_LFCAP_1600
),
382 FLAG(lfcap1
, PCI_HT_LFCAP_VEND
));
384 eh
= get_conf_word(d
, where
+ PCI_HT_PRI_EH
);
385 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
386 FLAG(eh
, PCI_HT_EH_PFLE
),
387 FLAG(eh
, PCI_HT_EH_OFLE
),
388 FLAG(eh
, PCI_HT_EH_PFE
),
389 FLAG(eh
, PCI_HT_EH_OFE
),
390 FLAG(eh
, PCI_HT_EH_EOCFE
),
391 FLAG(eh
, PCI_HT_EH_RFE
),
392 FLAG(eh
, PCI_HT_EH_CRCFE
),
393 FLAG(eh
, PCI_HT_EH_SERRFE
),
394 FLAG(eh
, PCI_HT_EH_CF
),
395 FLAG(eh
, PCI_HT_EH_RE
),
396 FLAG(eh
, PCI_HT_EH_PNFE
),
397 FLAG(eh
, PCI_HT_EH_ONFE
),
398 FLAG(eh
, PCI_HT_EH_EOCNFE
),
399 FLAG(eh
, PCI_HT_EH_RNFE
),
400 FLAG(eh
, PCI_HT_EH_CRCNFE
),
401 FLAG(eh
, PCI_HT_EH_SERRNFE
));
403 mbu
= get_conf_byte(d
, where
+ PCI_HT_PRI_MBU
);
404 mlu
= get_conf_byte(d
, where
+ PCI_HT_PRI_MLU
);
405 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu
, mlu
);
407 bn
= get_conf_byte(d
, where
+ PCI_HT_PRI_BN
);
408 printf("\t\tBus Number: %02x\n", bn
);
412 cap_ht_sec(struct device
*d
, int where
, int cmd
)
414 u16 lctr
, lcnf
, ftr
, eh
;
415 u8 rid
, lfrer
, lfcap
, mbu
, mlu
;
418 printf("HyperTransport: Host or Secondary Interface\n");
422 if (!config_fetch(d
, where
+ PCI_HT_SEC_LCTR
, PCI_HT_SEC_SIZEOF
- PCI_HT_SEC_LCTR
))
424 rid
= get_conf_byte(d
, where
+ PCI_HT_SEC_RID
);
425 if (rid
< 0x22 && rid
> 0x11)
426 printf("\t\t!!! Possibly incomplete decoding\n");
429 fmt
= "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
431 fmt
= "\t\tCommand: WarmRst%c DblEnd%c\n";
433 FLAG(cmd
, PCI_HT_SEC_CMD_WR
),
434 FLAG(cmd
, PCI_HT_SEC_CMD_DE
),
435 (cmd
& PCI_HT_SEC_CMD_DN
) >> 2,
436 FLAG(cmd
, PCI_HT_SEC_CMD_CS
),
437 FLAG(cmd
, PCI_HT_SEC_CMD_HH
),
438 FLAG(cmd
, PCI_HT_SEC_CMD_AS
),
439 FLAG(cmd
, PCI_HT_SEC_CMD_HIECE
),
440 FLAG(cmd
, PCI_HT_SEC_CMD_DUL
));
441 lctr
= get_conf_word(d
, where
+ PCI_HT_SEC_LCTR
);
443 fmt
= "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
445 fmt
= "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
447 FLAG(lctr
, PCI_HT_LCTR_CFLE
),
448 FLAG(lctr
, PCI_HT_LCTR_CST
),
449 FLAG(lctr
, PCI_HT_LCTR_CFE
),
450 FLAG(lctr
, PCI_HT_LCTR_LKFAIL
),
451 FLAG(lctr
, PCI_HT_LCTR_INIT
),
452 FLAG(lctr
, PCI_HT_LCTR_EOC
),
453 FLAG(lctr
, PCI_HT_LCTR_TXO
),
454 (lctr
& PCI_HT_LCTR_CRCERR
) >> 8,
455 FLAG(lctr
, PCI_HT_LCTR_ISOCEN
),
456 FLAG(lctr
, PCI_HT_LCTR_LSEN
),
457 FLAG(lctr
, PCI_HT_LCTR_EXTCTL
),
458 FLAG(lctr
, PCI_HT_LCTR_64B
));
459 lcnf
= get_conf_word(d
, where
+ PCI_HT_SEC_LCNF
);
461 fmt
= "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
463 fmt
= "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
465 ht_link_width(lcnf
& PCI_HT_LCNF_MLWI
),
466 ht_link_width((lcnf
& PCI_HT_LCNF_MLWO
) >> 4),
467 ht_link_width((lcnf
& PCI_HT_LCNF_LWI
) >> 8),
468 ht_link_width((lcnf
& PCI_HT_LCNF_LWO
) >> 12),
469 FLAG(lcnf
, PCI_HT_LCNF_DFI
),
470 FLAG(lcnf
, PCI_HT_LCNF_DFO
),
471 FLAG(lcnf
, PCI_HT_LCNF_DFIE
),
472 FLAG(lcnf
, PCI_HT_LCNF_DFOE
));
473 printf("\t\tRevision ID: %u.%02u\n",
474 (rid
& PCI_HT_RID_MAJ
) >> 5, (rid
& PCI_HT_RID_MIN
));
477 lfrer
= get_conf_byte(d
, where
+ PCI_HT_SEC_LFRER
);
478 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer
& PCI_HT_LFRER_FREQ
));
479 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
480 FLAG(lfrer
, PCI_HT_LFRER_PROT
),
481 FLAG(lfrer
, PCI_HT_LFRER_OV
),
482 FLAG(lfrer
, PCI_HT_LFRER_EOC
),
483 FLAG(lfrer
, PCI_HT_LFRER_CTLT
));
484 lfcap
= get_conf_byte(d
, where
+ PCI_HT_SEC_LFCAP
);
485 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
486 FLAG(lfcap
, PCI_HT_LFCAP_200
),
487 FLAG(lfcap
, PCI_HT_LFCAP_300
),
488 FLAG(lfcap
, PCI_HT_LFCAP_400
),
489 FLAG(lfcap
, PCI_HT_LFCAP_500
),
490 FLAG(lfcap
, PCI_HT_LFCAP_600
),
491 FLAG(lfcap
, PCI_HT_LFCAP_800
),
492 FLAG(lfcap
, PCI_HT_LFCAP_1000
),
493 FLAG(lfcap
, PCI_HT_LFCAP_1200
),
494 FLAG(lfcap
, PCI_HT_LFCAP_1400
),
495 FLAG(lfcap
, PCI_HT_LFCAP_1600
),
496 FLAG(lfcap
, PCI_HT_LFCAP_VEND
));
497 ftr
= get_conf_word(d
, where
+ PCI_HT_SEC_FTR
);
498 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
499 FLAG(ftr
, PCI_HT_FTR_ISOCFC
),
500 FLAG(ftr
, PCI_HT_FTR_LDTSTOP
),
501 FLAG(ftr
, PCI_HT_FTR_CRCTM
),
502 FLAG(ftr
, PCI_HT_FTR_ECTLT
),
503 FLAG(ftr
, PCI_HT_FTR_64BA
),
504 FLAG(ftr
, PCI_HT_FTR_UIDRD
),
505 FLAG(ftr
, PCI_HT_SEC_FTR_EXTRS
),
506 FLAG(ftr
, PCI_HT_SEC_FTR_UCNFE
));
507 if (ftr
& PCI_HT_SEC_FTR_EXTRS
)
509 eh
= get_conf_word(d
, where
+ PCI_HT_SEC_EH
);
510 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
511 FLAG(eh
, PCI_HT_EH_PFLE
),
512 FLAG(eh
, PCI_HT_EH_OFLE
),
513 FLAG(eh
, PCI_HT_EH_PFE
),
514 FLAG(eh
, PCI_HT_EH_OFE
),
515 FLAG(eh
, PCI_HT_EH_EOCFE
),
516 FLAG(eh
, PCI_HT_EH_RFE
),
517 FLAG(eh
, PCI_HT_EH_CRCFE
),
518 FLAG(eh
, PCI_HT_EH_SERRFE
),
519 FLAG(eh
, PCI_HT_EH_CF
),
520 FLAG(eh
, PCI_HT_EH_RE
),
521 FLAG(eh
, PCI_HT_EH_PNFE
),
522 FLAG(eh
, PCI_HT_EH_ONFE
),
523 FLAG(eh
, PCI_HT_EH_EOCNFE
),
524 FLAG(eh
, PCI_HT_EH_RNFE
),
525 FLAG(eh
, PCI_HT_EH_CRCNFE
),
526 FLAG(eh
, PCI_HT_EH_SERRNFE
));
527 mbu
= get_conf_byte(d
, where
+ PCI_HT_SEC_MBU
);
528 mlu
= get_conf_byte(d
, where
+ PCI_HT_SEC_MLU
);
529 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu
, mlu
);
534 cap_ht(struct device
*d
, int where
, int cmd
)
538 switch (cmd
& PCI_HT_CMD_TYP_HI
)
540 case PCI_HT_CMD_TYP_HI_PRI
:
541 cap_ht_pri(d
, where
, cmd
);
543 case PCI_HT_CMD_TYP_HI_SEC
:
544 cap_ht_sec(d
, where
, cmd
);
548 type
= cmd
& PCI_HT_CMD_TYP
;
551 case PCI_HT_CMD_TYP_SW
:
552 printf("HyperTransport: Switch\n");
554 case PCI_HT_CMD_TYP_IDC
:
555 printf("HyperTransport: Interrupt Discovery and Configuration\n");
557 case PCI_HT_CMD_TYP_RID
:
558 printf("HyperTransport: Revision ID: %u.%02u\n",
559 (cmd
& PCI_HT_RID_MAJ
) >> 5, (cmd
& PCI_HT_RID_MIN
));
561 case PCI_HT_CMD_TYP_UIDC
:
562 printf("HyperTransport: UnitID Clumping\n");
564 case PCI_HT_CMD_TYP_ECSA
:
565 printf("HyperTransport: Extended Configuration Space Access\n");
567 case PCI_HT_CMD_TYP_AM
:
568 printf("HyperTransport: Address Mapping\n");
570 case PCI_HT_CMD_TYP_MSIM
:
571 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
572 FLAG(cmd
, PCI_HT_MSIM_CMD_EN
),
573 FLAG(cmd
, PCI_HT_MSIM_CMD_FIXD
));
574 if (verbose
>= 2 && !(cmd
& PCI_HT_MSIM_CMD_FIXD
))
577 if (!config_fetch(d
, where
+ PCI_HT_MSIM_ADDR_LO
, 8))
579 offl
= get_conf_long(d
, where
+ PCI_HT_MSIM_ADDR_LO
);
580 offh
= get_conf_long(d
, where
+ PCI_HT_MSIM_ADDR_HI
);
581 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh
<< 32) | (offl
& ~0xfffff));
584 case PCI_HT_CMD_TYP_DR
:
585 printf("HyperTransport: DirectRoute\n");
587 case PCI_HT_CMD_TYP_VCS
:
588 printf("HyperTransport: VCSet\n");
590 case PCI_HT_CMD_TYP_RM
:
591 printf("HyperTransport: Retry Mode\n");
593 case PCI_HT_CMD_TYP_X86
:
594 printf("HyperTransport: X86 (reserved)\n");
597 printf("HyperTransport: #%02x\n", type
>> 11);
602 cap_msi(struct device
*d
, int where
, int cap
)
608 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
609 FLAG(cap
, PCI_MSI_FLAGS_ENABLE
),
610 1 << ((cap
& PCI_MSI_FLAGS_QSIZE
) >> 4),
611 1 << ((cap
& PCI_MSI_FLAGS_QMASK
) >> 1),
612 FLAG(cap
, PCI_MSI_FLAGS_MASK_BIT
),
613 FLAG(cap
, PCI_MSI_FLAGS_64BIT
));
616 is64
= cap
& PCI_MSI_FLAGS_64BIT
;
617 if (!config_fetch(d
, where
+ PCI_MSI_ADDRESS_LO
, (is64
? PCI_MSI_DATA_64
: PCI_MSI_DATA_32
) + 2 - PCI_MSI_ADDRESS_LO
))
619 printf("\t\tAddress: ");
622 t
= get_conf_long(d
, where
+ PCI_MSI_ADDRESS_HI
);
623 w
= get_conf_word(d
, where
+ PCI_MSI_DATA_64
);
627 w
= get_conf_word(d
, where
+ PCI_MSI_DATA_32
);
628 t
= get_conf_long(d
, where
+ PCI_MSI_ADDRESS_LO
);
629 printf("%08x Data: %04x\n", t
, w
);
630 if (cap
& PCI_MSI_FLAGS_MASK_BIT
)
636 if (!config_fetch(d
, where
+ PCI_MSI_MASK_BIT_64
, 8))
638 mask
= get_conf_long(d
, where
+ PCI_MSI_MASK_BIT_64
);
639 pending
= get_conf_long(d
, where
+ PCI_MSI_PENDING_64
);
643 if (!config_fetch(d
, where
+ PCI_MSI_MASK_BIT_32
, 8))
645 mask
= get_conf_long(d
, where
+ PCI_MSI_MASK_BIT_32
);
646 pending
= get_conf_long(d
, where
+ PCI_MSI_PENDING_32
);
648 printf("\t\tMasking: %08x Pending: %08x\n", mask
, pending
);
652 static int exp_downstream_port(int type
)
654 return type
== PCI_EXP_TYPE_ROOT_PORT
||
655 type
== PCI_EXP_TYPE_DOWNSTREAM
||
656 type
== PCI_EXP_TYPE_PCIE_BRIDGE
; /* PCI/PCI-X to PCIe Bridge */
659 static float power_limit(int value
, int scale
)
661 static const float scales
[4] = { 1.0, 0.1, 0.01, 0.001 };
662 return value
* scales
[scale
];
665 static const char *latency_l0s(int value
)
667 static const char *latencies
[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
668 return latencies
[value
];
671 static const char *latency_l1(int value
)
673 static const char *latencies
[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
674 return latencies
[value
];
677 static void cap_express_dev(struct device
*d
, int where
, int type
)
682 t
= get_conf_long(d
, where
+ PCI_EXP_DEVCAP
);
683 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
684 128 << (t
& PCI_EXP_DEVCAP_PAYLOAD
),
685 (1 << ((t
& PCI_EXP_DEVCAP_PHANTOM
) >> 3)) - 1);
686 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
))
687 printf(", Latency L0s %s, L1 %s",
688 latency_l0s((t
& PCI_EXP_DEVCAP_L0S
) >> 6),
689 latency_l1((t
& PCI_EXP_DEVCAP_L1
) >> 9));
691 printf("\t\t\tExtTag%c", FLAG(t
, PCI_EXP_DEVCAP_EXT_TAG
));
692 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
) ||
693 (type
== PCI_EXP_TYPE_UPSTREAM
) || (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
694 printf(" AttnBtn%c AttnInd%c PwrInd%c",
695 FLAG(t
, PCI_EXP_DEVCAP_ATN_BUT
),
696 FLAG(t
, PCI_EXP_DEVCAP_ATN_IND
), FLAG(t
, PCI_EXP_DEVCAP_PWR_IND
));
698 FLAG(t
, PCI_EXP_DEVCAP_RBE
));
699 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
) || (type
== PCI_EXP_TYPE_ROOT_INT_EP
))
701 FLAG(t
, PCI_EXP_DEVCAP_FLRESET
));
702 if ((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_UPSTREAM
) ||
703 (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
704 printf(" SlotPowerLimit %.3fW",
705 power_limit((t
& PCI_EXP_DEVCAP_PWR_VAL
) >> 18,
706 (t
& PCI_EXP_DEVCAP_PWR_SCL
) >> 26));
709 w
= get_conf_word(d
, where
+ PCI_EXP_DEVCTL
);
710 printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
711 FLAG(w
, PCI_EXP_DEVCTL_CERE
),
712 FLAG(w
, PCI_EXP_DEVCTL_NFERE
),
713 FLAG(w
, PCI_EXP_DEVCTL_FERE
),
714 FLAG(w
, PCI_EXP_DEVCTL_URRE
));
715 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
716 FLAG(w
, PCI_EXP_DEVCTL_RELAXED
),
717 FLAG(w
, PCI_EXP_DEVCTL_EXT_TAG
),
718 FLAG(w
, PCI_EXP_DEVCTL_PHANTOM
),
719 FLAG(w
, PCI_EXP_DEVCTL_AUX_PME
),
720 FLAG(w
, PCI_EXP_DEVCTL_NOSNOOP
));
721 if (type
== PCI_EXP_TYPE_PCI_BRIDGE
)
722 printf(" BrConfRtry%c", FLAG(w
, PCI_EXP_DEVCTL_BCRE
));
723 if (((type
== PCI_EXP_TYPE_ENDPOINT
) || (type
== PCI_EXP_TYPE_LEG_END
) || (type
== PCI_EXP_TYPE_ROOT_INT_EP
)) &&
724 (t
& PCI_EXP_DEVCAP_FLRESET
))
725 printf(" FLReset%c", FLAG(w
, PCI_EXP_DEVCTL_FLRESET
));
726 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
727 128 << ((w
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5),
728 128 << ((w
& PCI_EXP_DEVCTL_READRQ
) >> 12));
730 w
= get_conf_word(d
, where
+ PCI_EXP_DEVSTA
);
731 printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
732 FLAG(w
, PCI_EXP_DEVSTA_CED
),
733 FLAG(w
, PCI_EXP_DEVSTA_NFED
),
734 FLAG(w
, PCI_EXP_DEVSTA_FED
),
735 FLAG(w
, PCI_EXP_DEVSTA_URD
),
736 FLAG(w
, PCI_EXP_DEVSTA_AUXPD
),
737 FLAG(w
, PCI_EXP_DEVSTA_TRPND
));
740 static char *link_speed(int speed
)
759 static char *link_compare(int sta
, int cap
)
768 static char *aspm_support(int code
)
773 return "not supported";
785 static const char *aspm_enabled(int code
)
787 static const char *desc
[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
791 static void cap_express_link(struct device
*d
, int where
, int type
)
793 u32 t
, aspm
, cap_speed
, cap_width
, sta_speed
, sta_width
;
796 t
= get_conf_long(d
, where
+ PCI_EXP_LNKCAP
);
797 aspm
= (t
& PCI_EXP_LNKCAP_ASPM
) >> 10;
798 cap_speed
= t
& PCI_EXP_LNKCAP_SPEED
;
799 cap_width
= (t
& PCI_EXP_LNKCAP_WIDTH
) >> 4;
800 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
802 link_speed(cap_speed
), cap_width
,
806 printf(", Exit Latency ");
808 printf("L0s %s", latency_l0s((t
& PCI_EXP_LNKCAP_L0S
) >> 12));
810 printf("%sL1 %s", (aspm
& 1) ? ", " : "",
811 latency_l1((t
& PCI_EXP_LNKCAP_L1
) >> 15));
814 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
815 FLAG(t
, PCI_EXP_LNKCAP_CLOCKPM
),
816 FLAG(t
, PCI_EXP_LNKCAP_SURPRISE
),
817 FLAG(t
, PCI_EXP_LNKCAP_DLLA
),
818 FLAG(t
, PCI_EXP_LNKCAP_LBNC
),
819 FLAG(t
, PCI_EXP_LNKCAP_AOC
));
821 w
= get_conf_word(d
, where
+ PCI_EXP_LNKCTL
);
822 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w
& PCI_EXP_LNKCTL_ASPM
));
823 if ((type
== PCI_EXP_TYPE_ROOT_PORT
) || (type
== PCI_EXP_TYPE_ENDPOINT
) ||
824 (type
== PCI_EXP_TYPE_LEG_END
) || (type
== PCI_EXP_TYPE_PCI_BRIDGE
))
825 printf(" RCB %d bytes,", w
& PCI_EXP_LNKCTL_RCB
? 128 : 64);
826 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
827 FLAG(w
, PCI_EXP_LNKCTL_DISABLE
),
828 FLAG(w
, PCI_EXP_LNKCTL_CLOCK
),
829 FLAG(w
, PCI_EXP_LNKCTL_XSYNCH
),
830 FLAG(w
, PCI_EXP_LNKCTL_CLOCKPM
),
831 FLAG(w
, PCI_EXP_LNKCTL_HWAUTWD
),
832 FLAG(w
, PCI_EXP_LNKCTL_BWMIE
),
833 FLAG(w
, PCI_EXP_LNKCTL_AUTBWIE
));
835 w
= get_conf_word(d
, where
+ PCI_EXP_LNKSTA
);
836 sta_speed
= w
& PCI_EXP_LNKSTA_SPEED
;
837 sta_width
= (w
& PCI_EXP_LNKSTA_WIDTH
) >> 4;
838 printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
839 link_speed(sta_speed
),
840 link_compare(sta_speed
, cap_speed
),
842 link_compare(sta_width
, cap_width
));
843 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
844 FLAG(w
, PCI_EXP_LNKSTA_TR_ERR
),
845 FLAG(w
, PCI_EXP_LNKSTA_TRAIN
),
846 FLAG(w
, PCI_EXP_LNKSTA_SL_CLK
),
847 FLAG(w
, PCI_EXP_LNKSTA_DL_ACT
),
848 FLAG(w
, PCI_EXP_LNKSTA_BWMGMT
),
849 FLAG(w
, PCI_EXP_LNKSTA_AUTBW
));
852 static const char *indicator(int code
)
854 static const char *names
[] = { "Unknown", "On", "Blink", "Off" };
858 static void cap_express_slot(struct device
*d
, int where
)
863 t
= get_conf_long(d
, where
+ PCI_EXP_SLTCAP
);
864 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
865 FLAG(t
, PCI_EXP_SLTCAP_ATNB
),
866 FLAG(t
, PCI_EXP_SLTCAP_PWRC
),
867 FLAG(t
, PCI_EXP_SLTCAP_MRL
),
868 FLAG(t
, PCI_EXP_SLTCAP_ATNI
),
869 FLAG(t
, PCI_EXP_SLTCAP_PWRI
),
870 FLAG(t
, PCI_EXP_SLTCAP_HPC
),
871 FLAG(t
, PCI_EXP_SLTCAP_HPS
));
872 printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
873 (t
& PCI_EXP_SLTCAP_PSN
) >> 19,
874 power_limit((t
& PCI_EXP_SLTCAP_PWR_VAL
) >> 7, (t
& PCI_EXP_SLTCAP_PWR_SCL
) >> 15),
875 FLAG(t
, PCI_EXP_SLTCAP_INTERLOCK
),
876 FLAG(t
, PCI_EXP_SLTCAP_NOCMDCOMP
));
878 w
= get_conf_word(d
, where
+ PCI_EXP_SLTCTL
);
879 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
880 FLAG(w
, PCI_EXP_SLTCTL_ATNB
),
881 FLAG(w
, PCI_EXP_SLTCTL_PWRF
),
882 FLAG(w
, PCI_EXP_SLTCTL_MRLS
),
883 FLAG(w
, PCI_EXP_SLTCTL_PRSD
),
884 FLAG(w
, PCI_EXP_SLTCTL_CMDC
),
885 FLAG(w
, PCI_EXP_SLTCTL_HPIE
),
886 FLAG(w
, PCI_EXP_SLTCTL_LLCHG
));
887 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
888 indicator((w
& PCI_EXP_SLTCTL_ATNI
) >> 6),
889 indicator((w
& PCI_EXP_SLTCTL_PWRI
) >> 8),
890 FLAG(w
, PCI_EXP_SLTCTL_PWRC
),
891 FLAG(w
, PCI_EXP_SLTCTL_INTERLOCK
));
893 w
= get_conf_word(d
, where
+ PCI_EXP_SLTSTA
);
894 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
895 FLAG(w
, PCI_EXP_SLTSTA_ATNB
),
896 FLAG(w
, PCI_EXP_SLTSTA_PWRF
),
897 FLAG(w
, PCI_EXP_SLTSTA_MRL_ST
),
898 FLAG(w
, PCI_EXP_SLTSTA_CMDC
),
899 FLAG(w
, PCI_EXP_SLTSTA_PRES
),
900 FLAG(w
, PCI_EXP_SLTSTA_INTERLOCK
));
901 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
902 FLAG(w
, PCI_EXP_SLTSTA_MRLS
),
903 FLAG(w
, PCI_EXP_SLTSTA_PRSD
),
904 FLAG(w
, PCI_EXP_SLTSTA_LLCHG
));
907 static void cap_express_root(struct device
*d
, int where
)
911 w
= get_conf_word(d
, where
+ PCI_EXP_RTCAP
);
912 printf("\t\tRootCap: CRSVisible%c\n",
913 FLAG(w
, PCI_EXP_RTCAP_CRSVIS
));
915 w
= get_conf_word(d
, where
+ PCI_EXP_RTCTL
);
916 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
917 FLAG(w
, PCI_EXP_RTCTL_SECEE
),
918 FLAG(w
, PCI_EXP_RTCTL_SENFEE
),
919 FLAG(w
, PCI_EXP_RTCTL_SEFEE
),
920 FLAG(w
, PCI_EXP_RTCTL_PMEIE
),
921 FLAG(w
, PCI_EXP_RTCTL_CRSVIS
));
923 w
= get_conf_long(d
, where
+ PCI_EXP_RTSTA
);
924 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
925 w
& PCI_EXP_RTSTA_PME_REQID
,
926 FLAG(w
, PCI_EXP_RTSTA_PME_STATUS
),
927 FLAG(w
, PCI_EXP_RTSTA_PME_PENDING
));
930 static const char *cap_express_dev2_timeout_range(int type
)
932 /* Decode Completion Timeout Ranges. */
936 return "Not Supported";
956 static const char *cap_express_dev2_timeout_value(int type
)
958 /* Decode Completion Timeout Value. */
962 return "50us to 50ms";
964 return "50us to 100us";
966 return "1ms to 10ms";
968 return "16ms to 55ms";
970 return "65ms to 210ms";
972 return "260ms to 900ms";
984 static const char *cap_express_devcap2_obff(int obff
)
989 return "Via message";
993 return "Via message/WAKE#";
995 return "Not Supported";
999 static const char *cap_express_devcap2_epr(int epr
)
1004 return "Dev Specific";
1006 return "Form Factor Dev Specific";
1010 return "Not Supported";
1014 static const char *cap_express_devcap2_lncls(int lncls
)
1019 return "64byte cachelines";
1021 return "128byte cachelines";
1025 return "Not Supported";
1029 static const char *cap_express_devcap2_tphcomp(int tph
)
1034 return "TPHComp+ ExtTPHComp-";
1036 /* Reserved; intentionally left blank */
1039 return "TPHComp+ ExtTPHComp+";
1041 return "TPHComp- ExtTPHComp-";
1045 static const char *cap_express_devctl2_obff(int obff
)
1052 return "Via message A";
1054 return "Via message B";
1063 device_has_memory_space_bar(struct device
*d
)
1065 struct pci_dev
*p
= d
->dev
;
1069 if (p
->base_addr
[i
] && p
->size
[i
])
1071 if (!(p
->base_addr
[i
] & PCI_BASE_ADDRESS_SPACE_IO
))
1080 static void cap_express_dev2(struct device
*d
, int where
, int type
)
1084 int has_mem_bar
= device_has_memory_space_bar(d
);
1086 l
= get_conf_long(d
, where
+ PCI_EXP_DEVCAP2
);
1087 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1088 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l
)),
1089 FLAG(l
, PCI_EXP_DEV2_TIMEOUT_DIS
),
1090 FLAG(l
, PCI_EXP_DEVCAP2_NROPRPRP
),
1091 FLAG(l
, PCI_EXP_DEVCAP2_LTR
));
1092 printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1093 FLAG(l
, PCI_EXP_DEVCAP2_10BIT_TAG_COMP
),
1094 FLAG(l
, PCI_EXP_DEVCAP2_10BIT_TAG_REQ
),
1095 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l
)),
1096 FLAG(l
, PCI_EXP_DEVCAP2_EXTFMT
),
1097 FLAG(l
, PCI_EXP_DEVCAP2_EE_TLP
));
1099 if (PCI_EXP_DEVCAP2_EE_TLP
== (l
& PCI_EXP_DEVCAP2_EE_TLP
))
1101 printf(", MaxEETLPPrefixes %d",
1102 PCI_EXP_DEVCAP2_MEE_TLP(l
) ? PCI_EXP_DEVCAP2_MEE_TLP(l
) : 4);
1105 printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1106 cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l
)),
1107 FLAG(l
, PCI_EXP_DEVCAP2_EPR_INIT
));
1108 printf("\n\t\t\t FRS%c", FLAG(l
, PCI_EXP_DEVCAP2_FRS
));
1110 if (type
== PCI_EXP_TYPE_ROOT_PORT
)
1111 printf(" LN System CLS %s,",
1112 cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l
)));
1114 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ENDPOINT
)
1115 printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l
)));
1117 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
1118 printf(" ARIFwd%c\n", FLAG(l
, PCI_EXP_DEV2_ARI
));
1121 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_UPSTREAM
||
1122 type
== PCI_EXP_TYPE_DOWNSTREAM
|| has_mem_bar
)
1124 printf("\t\t\t AtomicOpsCap:");
1125 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_UPSTREAM
||
1126 type
== PCI_EXP_TYPE_DOWNSTREAM
)
1127 printf(" Routing%c", FLAG(l
, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING
));
1128 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| has_mem_bar
)
1129 printf(" 32bit%c 64bit%c 128bitCAS%c",
1130 FLAG(l
, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP
),
1131 FLAG(l
, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP
),
1132 FLAG(l
, PCI_EXP_DEVCAP2_128BIT_CAS_COMP
));
1136 w
= get_conf_word(d
, where
+ PCI_EXP_DEVCTL2
);
1137 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,",
1138 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w
)),
1139 FLAG(w
, PCI_EXP_DEV2_TIMEOUT_DIS
),
1140 FLAG(w
, PCI_EXP_DEV2_LTR
),
1141 cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w
)));
1142 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_DOWNSTREAM
)
1143 printf(" ARIFwd%c\n", FLAG(w
, PCI_EXP_DEV2_ARI
));
1146 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_UPSTREAM
||
1147 type
== PCI_EXP_TYPE_DOWNSTREAM
|| type
== PCI_EXP_TYPE_ENDPOINT
||
1148 type
== PCI_EXP_TYPE_ROOT_INT_EP
|| type
== PCI_EXP_TYPE_LEG_END
)
1150 printf("\t\t\t AtomicOpsCtl:");
1151 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ENDPOINT
||
1152 type
== PCI_EXP_TYPE_ROOT_INT_EP
|| type
== PCI_EXP_TYPE_LEG_END
)
1153 printf(" ReqEn%c", FLAG(w
, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN
));
1154 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_UPSTREAM
||
1155 type
== PCI_EXP_TYPE_DOWNSTREAM
)
1156 printf(" EgressBlck%c", FLAG(w
, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK
));
1161 static const char *cap_express_link2_speed_cap(int vector
)
1164 * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1165 * permitted to skip support for any data rates between 2.5GT/s and the
1166 * highest supported rate.
1171 return "2.5-32GT/s";
1173 return "2.5-16GT/s";
1184 static const char *cap_express_link2_speed(int type
)
1188 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1204 static const char *cap_express_link2_deemphasis(int type
)
1217 static const char *cap_express_link2_transmargin(int type
)
1222 return "Normal Operating Range";
1224 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1229 return "200-400mV(full-swing)/100-200mV(half-swing)";
1235 static const char *cap_express_link2_crosslink_res(int crosslink
)
1240 return "unsupported";
1242 return "Upstream Port";
1244 return "Downstream Port";
1246 return "incomplete";
1250 static const char *cap_express_link2_component(int presence
)
1255 return "Link Down - Not Determined";
1257 return "Link Down - Not Present";
1259 return "Link Down - Present";
1261 return "Link Up - Present";
1263 return "Link Up - Present and DRS Received";
1269 static void cap_express_link2(struct device
*d
, int where
, int type
)
1274 if (!((type
== PCI_EXP_TYPE_ENDPOINT
|| type
== PCI_EXP_TYPE_LEG_END
) &&
1275 (d
->dev
->dev
!= 0 || d
->dev
->func
!= 0))) {
1276 /* Link Capabilities 2 was reserved before PCIe r3.0 */
1277 l
= get_conf_long(d
, where
+ PCI_EXP_LNKCAP2
);
1279 printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1280 "Retimer%c 2Retimers%c DRS%c\n",
1281 cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l
)),
1282 FLAG(l
, PCI_EXP_LNKCAP2_CROSSLINK
),
1283 FLAG(l
, PCI_EXP_LNKCAP2_RETIMER
),
1284 FLAG(l
, PCI_EXP_LNKCAP2_2RETIMERS
),
1285 FLAG(l
, PCI_EXP_LNKCAP2_DRS
));
1288 w
= get_conf_word(d
, where
+ PCI_EXP_LNKCTL2
);
1289 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1290 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w
)),
1291 FLAG(w
, PCI_EXP_LNKCTL2_CMPLNC
),
1292 FLAG(w
, PCI_EXP_LNKCTL2_SPEED_DIS
));
1293 if (type
== PCI_EXP_TYPE_DOWNSTREAM
)
1294 printf(", Selectable De-emphasis: %s",
1295 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w
)));
1297 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1298 "\t\t\t Compliance De-emphasis: %s\n",
1299 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w
)),
1300 FLAG(w
, PCI_EXP_LNKCTL2_MOD_CMPLNC
),
1301 FLAG(w
, PCI_EXP_LNKCTL2_CMPLNC_SOS
),
1302 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w
)));
1305 w
= get_conf_word(d
, where
+ PCI_EXP_LNKSTA2
);
1306 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1307 "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1308 "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
1309 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w
)),
1310 FLAG(w
, PCI_EXP_LINKSTA2_EQU_COMP
),
1311 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE1
),
1312 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE2
),
1313 FLAG(w
, PCI_EXP_LINKSTA2_EQU_PHASE3
),
1314 FLAG(w
, PCI_EXP_LINKSTA2_EQU_REQ
),
1315 FLAG(w
, PCI_EXP_LINKSTA2_RETIMER
),
1316 FLAG(w
, PCI_EXP_LINKSTA2_2RETIMERS
),
1317 cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w
)));
1319 if (exp_downstream_port(type
) && (l
& PCI_EXP_LNKCAP2_DRS
)) {
1321 "\t\t\t DownstreamComp: %s\n",
1322 FLAG(w
, PCI_EXP_LINKSTA2_DRS_RCVD
),
1323 cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w
)));
1328 static void cap_express_slot2(struct device
*d UNUSED
, int where UNUSED
)
1330 /* No capabilities that require this field in PCIe rev2.0 spec. */
1334 cap_express(struct device
*d
, int where
, int cap
)
1336 int type
= (cap
& PCI_EXP_FLAGS_TYPE
) >> 4;
1343 printf("(v%d) ", cap
& PCI_EXP_FLAGS_VERS
);
1346 case PCI_EXP_TYPE_ENDPOINT
:
1349 case PCI_EXP_TYPE_LEG_END
:
1350 printf("Legacy Endpoint");
1352 case PCI_EXP_TYPE_ROOT_PORT
:
1353 slot
= cap
& PCI_EXP_FLAGS_SLOT
;
1354 printf("Root Port (Slot%c)", FLAG(cap
, PCI_EXP_FLAGS_SLOT
));
1356 case PCI_EXP_TYPE_UPSTREAM
:
1357 printf("Upstream Port");
1359 case PCI_EXP_TYPE_DOWNSTREAM
:
1360 slot
= cap
& PCI_EXP_FLAGS_SLOT
;
1361 printf("Downstream Port (Slot%c)", FLAG(cap
, PCI_EXP_FLAGS_SLOT
));
1363 case PCI_EXP_TYPE_PCI_BRIDGE
:
1364 printf("PCI-Express to PCI/PCI-X Bridge");
1366 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1367 slot
= cap
& PCI_EXP_FLAGS_SLOT
;
1368 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1369 FLAG(cap
, PCI_EXP_FLAGS_SLOT
));
1371 case PCI_EXP_TYPE_ROOT_INT_EP
:
1373 printf("Root Complex Integrated Endpoint");
1375 case PCI_EXP_TYPE_ROOT_EC
:
1377 printf("Root Complex Event Collector");
1380 printf("Unknown type %d", type
);
1382 printf(", MSI %02x\n", (cap
& PCI_EXP_FLAGS_IRQ
) >> 9);
1389 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ROOT_EC
)
1391 if (!config_fetch(d
, where
+ PCI_EXP_DEVCAP
, size
))
1394 cap_express_dev(d
, where
, type
);
1396 cap_express_link(d
, where
, type
);
1398 cap_express_slot(d
, where
);
1399 if (type
== PCI_EXP_TYPE_ROOT_PORT
|| type
== PCI_EXP_TYPE_ROOT_EC
)
1400 cap_express_root(d
, where
);
1402 if ((cap
& PCI_EXP_FLAGS_VERS
) < 2)
1408 if (!config_fetch(d
, where
+ PCI_EXP_DEVCAP2
, size
))
1411 cap_express_dev2(d
, where
, type
);
1413 cap_express_link2(d
, where
, type
);
1415 cap_express_slot2(d
, where
);
1420 cap_msix(struct device
*d
, int where
, int cap
)
1424 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1425 FLAG(cap
, PCI_MSIX_ENABLE
),
1426 (cap
& PCI_MSIX_TABSIZE
) + 1,
1427 FLAG(cap
, PCI_MSIX_MASK
));
1428 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_MSIX_TABLE
, 8))
1431 off
= get_conf_long(d
, where
+ PCI_MSIX_TABLE
);
1432 printf("\t\tVector table: BAR=%d offset=%08x\n",
1433 off
& PCI_MSIX_BIR
, off
& ~PCI_MSIX_BIR
);
1434 off
= get_conf_long(d
, where
+ PCI_MSIX_PBA
);
1435 printf("\t\tPBA: BAR=%d offset=%08x\n",
1436 off
& PCI_MSIX_BIR
, off
& ~PCI_MSIX_BIR
);
1442 int esr
= cap
& 0xff;
1445 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1446 esr
& PCI_SID_ESR_NSLOTS
,
1447 FLAG(esr
, PCI_SID_ESR_FIC
),
1452 cap_ssvid(struct device
*d
, int where
)
1454 u16 subsys_v
, subsys_d
;
1455 char ssnamebuf
[256];
1457 if (!config_fetch(d
, where
, 8))
1459 subsys_v
= get_conf_word(d
, where
+ PCI_SSVID_VENDOR
);
1460 subsys_d
= get_conf_word(d
, where
+ PCI_SSVID_DEVICE
);
1461 printf("Subsystem: %s\n",
1462 pci_lookup_name(pacc
, ssnamebuf
, sizeof(ssnamebuf
),
1463 PCI_LOOKUP_SUBSYSTEM
| PCI_LOOKUP_VENDOR
| PCI_LOOKUP_DEVICE
,
1464 d
->dev
->vendor_id
, d
->dev
->device_id
, subsys_v
, subsys_d
));
1468 cap_debug_port(int cap
)
1470 int bar
= cap
>> 13;
1471 int pos
= cap
& 0x1fff;
1472 printf("Debug port: BAR=%d offset=%04x\n", bar
, pos
);
1476 cap_af(struct device
*d
, int where
)
1480 printf("PCI Advanced Features\n");
1481 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_AF_CAP
, 3))
1484 reg
= get_conf_byte(d
, where
+ PCI_AF_CAP
);
1485 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg
, PCI_AF_CAP_TP
),
1486 FLAG(reg
, PCI_AF_CAP_FLR
));
1487 reg
= get_conf_byte(d
, where
+ PCI_AF_CTRL
);
1488 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg
, PCI_AF_CTRL_FLR
));
1489 reg
= get_conf_byte(d
, where
+ PCI_AF_STATUS
);
1490 printf("\t\tAFStatus: TP%c\n", FLAG(reg
, PCI_AF_STATUS_TP
));
1494 cap_sata_hba(struct device
*d
, int where
, int cap
)
1499 printf("SATA HBA v%d.%d", BITS(cap
, 4, 4), BITS(cap
, 0, 4));
1500 if (verbose
< 2 || !config_fetch(d
, where
+ PCI_SATA_HBA_BARS
, 4))
1506 bars
= get_conf_long(d
, where
+ PCI_SATA_HBA_BARS
);
1507 bar
= BITS(bars
, 0, 4);
1508 if (bar
>= 4 && bar
<= 9)
1509 printf(" BAR%d Offset=%08x\n", bar
- 4, BITS(bars
, 4, 20));
1511 printf(" InCfgSpace\n");
1513 printf(" BAR??%d\n", bar
);
1516 static const char *cap_ea_property(int p
, int is_secondary
)
1520 return "memory space, non-prefetchable";
1522 return "memory space, prefetchable";
1526 return "VF memory space, prefetchable";
1528 return "VF memory space, non-prefetchable";
1530 return "allocation behind bridge, non-prefetchable memory";
1532 return "allocation behind bridge, prefetchable memory";
1534 return "allocation behind bridge, I/O space";
1536 return "memory space resource unavailable for use";
1538 return "I/O space resource unavailable for use";
1541 return "entry unavailable for use, PrimaryProperties should be used";
1543 return "entry unavailable for use";
1549 static void cap_ea(struct device
*d
, int where
, int cap
)
1552 int entry_base
= where
+ 4;
1553 int num_entries
= BITS(cap
, 0, 6);
1554 u8 htype
= get_conf_byte(d
, PCI_HEADER_TYPE
) & 0x7f;
1556 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries
);
1557 if (htype
== PCI_HEADER_TYPE_BRIDGE
) {
1558 byte fixed_sub
, fixed_sec
;
1561 if (!config_fetch(d
, where
+ 4, 2)) {
1565 fixed_sec
= get_conf_byte(d
, where
+ PCI_EA_CAP_TYPE1_SECONDARY
);
1566 fixed_sub
= get_conf_byte(d
, where
+ PCI_EA_CAP_TYPE1_SUBORDINATE
);
1567 printf(", secondary=%d, subordinate=%d", fixed_sec
, fixed_sub
);
1573 for (entry
= 0; entry
< num_entries
; entry
++) {
1574 int max_offset_high_pos
, has_base_high
, has_max_offset_high
;
1576 u32 base
, max_offset
;
1577 int es
, bei
, pp
, sp
;
1578 const char *prop_text
;
1580 if (!config_fetch(d
, entry_base
, 4))
1582 entry_header
= get_conf_long(d
, entry_base
);
1583 es
= BITS(entry_header
, 0, 3);
1584 bei
= BITS(entry_header
, 4, 4);
1585 pp
= BITS(entry_header
, 8, 8);
1586 sp
= BITS(entry_header
, 16, 8);
1587 if (!config_fetch(d
, entry_base
+ 4, es
* 4))
1589 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry
,
1590 FLAG(entry_header
, PCI_EA_CAP_ENT_ENABLE
),
1591 FLAG(entry_header
, PCI_EA_CAP_ENT_WRITABLE
), es
);
1592 printf("\t\t\t BAR Equivalent Indicator: ");
1600 printf("BAR %u", bei
);
1603 printf("resource behind function");
1606 printf("not indicated");
1609 printf("expansion ROM");
1617 printf("VF-BAR %u", bei
- 9);
1625 prop_text
= cap_ea_property(pp
, 0);
1626 printf("\t\t\t PrimaryProperties: ");
1628 printf("%s\n", prop_text
);
1630 printf("[%02x]\n", pp
);
1632 prop_text
= cap_ea_property(sp
, 1);
1633 printf("\t\t\t SecondaryProperties: ");
1635 printf("%s\n", prop_text
);
1637 printf("[%02x]\n", sp
);
1639 base
= get_conf_long(d
, entry_base
+ 4);
1640 has_base_high
= ((base
& 2) != 0);
1643 max_offset
= get_conf_long(d
, entry_base
+ 8);
1644 has_max_offset_high
= ((max_offset
& 2) != 0);
1646 max_offset_high_pos
= entry_base
+ 12;
1648 printf("\t\t\t Base: ");
1649 if (has_base_high
) {
1650 u32 base_high
= get_conf_long(d
, entry_base
+ 12);
1652 printf("%x", base_high
);
1653 max_offset_high_pos
+= 4;
1655 printf("%08x\n", base
);
1657 printf("\t\t\t MaxOffset: ");
1658 if (has_max_offset_high
) {
1659 u32 max_offset_high
= get_conf_long(d
, max_offset_high_pos
);
1661 printf("%x", max_offset_high
);
1663 printf("%08x\n", max_offset
);
1665 entry_base
+= 4 + 4 * es
;
1670 show_caps(struct device
*d
, int where
)
1672 int can_have_ext_caps
= 0;
1675 if (get_conf_word(d
, PCI_STATUS
) & PCI_STATUS_CAP_LIST
)
1677 byte been_there
[256];
1678 where
= get_conf_byte(d
, where
) & ~3;
1679 memset(been_there
, 0, 256);
1683 printf("\tCapabilities: ");
1684 if (!config_fetch(d
, where
, 4))
1686 puts("<access denied>");
1689 id
= get_conf_byte(d
, where
+ PCI_CAP_LIST_ID
);
1690 next
= get_conf_byte(d
, where
+ PCI_CAP_LIST_NEXT
) & ~3;
1691 cap
= get_conf_word(d
, where
+ PCI_CAP_FLAGS
);
1692 printf("[%02x] ", where
);
1693 if (been_there
[where
]++)
1695 printf("<chain looped>\n");
1700 printf("<chain broken>\n");
1705 case PCI_CAP_ID_NULL
:
1709 cap_pm(d
, where
, cap
);
1711 case PCI_CAP_ID_AGP
:
1712 cap_agp(d
, where
, cap
);
1714 case PCI_CAP_ID_VPD
:
1717 case PCI_CAP_ID_SLOTID
:
1720 case PCI_CAP_ID_MSI
:
1721 cap_msi(d
, where
, cap
);
1723 case PCI_CAP_ID_CHSWP
:
1724 printf("CompactPCI hot-swap <?>\n");
1726 case PCI_CAP_ID_PCIX
:
1728 can_have_ext_caps
= 1;
1731 cap_ht(d
, where
, cap
);
1733 case PCI_CAP_ID_VNDR
:
1734 show_vendor_caps(d
, where
, cap
);
1736 case PCI_CAP_ID_DBG
:
1737 cap_debug_port(cap
);
1739 case PCI_CAP_ID_CCRC
:
1740 printf("CompactPCI central resource control <?>\n");
1742 case PCI_CAP_ID_HOTPLUG
:
1743 printf("Hot-plug capable\n");
1745 case PCI_CAP_ID_SSVID
:
1746 cap_ssvid(d
, where
);
1748 case PCI_CAP_ID_AGP3
:
1749 printf("AGP3 <?>\n");
1751 case PCI_CAP_ID_SECURE
:
1752 printf("Secure device <?>\n");
1754 case PCI_CAP_ID_EXP
:
1755 type
= cap_express(d
, where
, cap
);
1756 can_have_ext_caps
= 1;
1758 case PCI_CAP_ID_MSIX
:
1759 cap_msix(d
, where
, cap
);
1761 case PCI_CAP_ID_SATA
:
1762 cap_sata_hba(d
, where
, cap
);
1768 cap_ea(d
, where
, cap
);
1771 printf("Capability ID %#02x [%04x]\n", id
, cap
);
1776 if (can_have_ext_caps
)
1777 show_ext_caps(d
, type
);