ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap >> 6) & 7],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
  40          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  41          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  42          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  43          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  44   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  45   if (b)
  46     printf("\t\tBridge: PM%c B3%c\n",
  47            FLAG(t, PCI_PM_BPCC_ENABLE),
  48            FLAG(~t, PCI_PM_PPB_B2_B3));
  49 }
  50
  51 static void
  52 format_agp_rate(int rate, char *buf, int agp3)
  53 {
  54   char *c = buf;
  55   int i;
  56
  57   for (i=0; i<=2; i++)
  58     if (rate & (1 << i))
  59       {
  60         if (c != buf)
  61           *c++ = ',';
  62         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  63       }
  64   if (c != buf)
  65     *c = 0;
  66   else
  67     strcpy(buf, "<none>");
  68 }
  69
  70 static void
  71 cap_agp(struct device *d, int where, int cap)
  72 {
  73   u32 t;
  74   char rate[16];
  75   int ver, rev;
  76   int agp3 = 0;
  77
  78   ver = (cap >> 4) & 0x0f;
  79   rev = cap & 0x0f;
  80   printf("AGP version %x.%x\n", ver, rev);
  81   if (verbose < 2)
  82     return;
  83   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  84     return;
  85   t = get_conf_long(d, where + PCI_AGP_STATUS);
  86   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  87     agp3 = 1;
  88   format_agp_rate(t & 7, rate, agp3);
  89   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  90          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  91          FLAG(t, PCI_AGP_STATUS_ISOCH),
  92          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  93          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  94          FLAG(t, PCI_AGP_STATUS_SBA),
  95          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  96          FLAG(t, PCI_AGP_STATUS_GART64),
  97          FLAG(t, PCI_AGP_STATUS_HTRANS),
  98          FLAG(t, PCI_AGP_STATUS_64BIT),
  99          FLAG(t, PCI_AGP_STATUS_FW),
 100          FLAG(t, PCI_AGP_STATUS_AGP3),
 101          rate);
 102   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 103   format_agp_rate(t & 7, rate, agp3);
 104   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 105          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 106          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 107          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 108          FLAG(t, PCI_AGP_COMMAND_SBA),
 109          FLAG(t, PCI_AGP_COMMAND_AGP),
 110          FLAG(t, PCI_AGP_COMMAND_GART64),
 111          FLAG(t, PCI_AGP_COMMAND_64BIT),
 112          FLAG(t, PCI_AGP_COMMAND_FW),
 113          rate);
 114 }
 115
 116 static void
 117 cap_pcix_nobridge(struct device *d, int where)
 118 {
 119   u16 command;
 120   u32 status;
 121   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 122
 123   printf("PCI-X non-bridge device\n");
 124
 125   if (verbose < 2)
 126     return;
 127
 128   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 129     return;
 130
 131   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 132   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 133   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 134          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 135          FLAG(command, PCI_PCIX_COMMAND_ERO),
 136          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 137          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 138   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 139          ((status >> 8) & 0xff),
 140          ((status >> 3) & 0x1f),
 141          (status & PCI_PCIX_STATUS_FUNCTION),
 142          FLAG(status, PCI_PCIX_STATUS_64BIT),
 143          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 144          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 145          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 146          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 147          1 << (9 + ((status >> 21) & 3U)),
 148          max_outstanding[(status >> 23) & 7U],
 149          1 << (3 + ((status >> 26) & 7U)),
 150          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 151          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 152          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 153 }
 154
 155 static void
 156 cap_pcix_bridge(struct device *d, int where)
 157 {
 158   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 159   u16 secstatus;
 160   u32 status, upstcr, downstcr;
 161
 162   printf("PCI-X bridge device\n");
 163
 164   if (verbose < 2)
 165     return;
 166
 167   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 168     return;
 169
 170   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 171   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 177          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 178          sec_clock_freq[(secstatus >> 6) & 7]);
 179   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 180   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 181          ((status >> 8) & 0xff),
 182          ((status >> 3) & 0x1f),
 183          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 189          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 190   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 191   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 192          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 193          (upstcr >> 16) & 0xffff);
 194   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 195   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 196          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 197          (downstcr >> 16) & 0xffff);
 198 }
 199
 200 static void
 201 cap_pcix(struct device *d, int where)
 202 {
 203   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 204     {
 205     case PCI_HEADER_TYPE_NORMAL:
 206       cap_pcix_nobridge(d, where);
 207       break;
 208     case PCI_HEADER_TYPE_BRIDGE:
 209       cap_pcix_bridge(d, where);
 210       break;
 211     }
 212 }
 213
 214 static inline char *
 215 ht_link_width(unsigned width)
 216 {
 217   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 218   return widths[width];
 219 }
 220
 221 static inline char *
 222 ht_link_freq(unsigned freq)
 223 {
 224   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 225                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 226   return freqs[freq];
 227 }
 228
 229 static void
 230 cap_ht_pri(struct device *d, int where, int cmd)
 231 {
 232   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 233   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 234   char *fmt;
 235
 236   printf("HyperTransport: Slave or Primary Interface\n");
 237   if (verbose < 2)
 238     return;
 239
 240   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 241     return;
 242   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 243   if (rid < 0x22 && rid > 0x11)
 244     printf("\t\t!!! Possibly incomplete decoding\n");
 245
 246   if (rid >= 0x22)
 247     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
 248   else
 249     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
 250   printf(fmt,
 251          (cmd & PCI_HT_PRI_CMD_BUID),
 252          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 253          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 254          FLAG(cmd, PCI_HT_PRI_CMD_DD),
 255          FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 256   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 257   if (rid >= 0x22)
 258     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 259   else
 260     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 261   printf(fmt,
 262          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 263          FLAG(lctr0, PCI_HT_LCTR_CST),
 264          FLAG(lctr0, PCI_HT_LCTR_CFE),
 265          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 266          FLAG(lctr0, PCI_HT_LCTR_INIT),
 267          FLAG(lctr0, PCI_HT_LCTR_EOC),
 268          FLAG(lctr0, PCI_HT_LCTR_TXO),
 269          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
 270          FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 271          FLAG(lctr0, PCI_HT_LCTR_LSEN),
 272          FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 273          FLAG(lctr0, PCI_HT_LCTR_64B));
 274   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 275   if (rid >= 0x22)
 276     fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 277   else
 278     fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 279   printf(fmt,
 280          ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 281          ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 282          ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 283          ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 284          FLAG(lcnf0, PCI_HT_LCNF_DFI),
 285          FLAG(lcnf0, PCI_HT_LCNF_DFO),
 286          FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 287          FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 288   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 289   if (rid >= 0x22)
 290     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 291   else
 292     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 293   printf(fmt,
 294          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 295          FLAG(lctr1, PCI_HT_LCTR_CST),
 296          FLAG(lctr1, PCI_HT_LCTR_CFE),
 297          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 298          FLAG(lctr1, PCI_HT_LCTR_INIT),
 299          FLAG(lctr1, PCI_HT_LCTR_EOC),
 300          FLAG(lctr1, PCI_HT_LCTR_TXO),
 301          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
 302          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 303          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 304          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 305          FLAG(lctr1, PCI_HT_LCTR_64B));
 306   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 307   if (rid >= 0x22)
 308     fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 309   else
 310     fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 311   printf(fmt,
 312          ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 313          ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 314          ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 315          ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 316          FLAG(lcnf1, PCI_HT_LCNF_DFI),
 317          FLAG(lcnf1, PCI_HT_LCNF_DFO),
 318          FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 319          FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 320   printf("\t\tRevision ID: %u.%02u\n",
 321          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 322   if (rid < 0x22)
 323     return;
 324   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 325   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 326   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 327          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 328          FLAG(lfrer0, PCI_HT_LFRER_OV),
 329          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 330          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 331   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 332   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 333          FLAG(lfcap0, PCI_HT_LFCAP_200),
 334          FLAG(lfcap0, PCI_HT_LFCAP_300),
 335          FLAG(lfcap0, PCI_HT_LFCAP_400),
 336          FLAG(lfcap0, PCI_HT_LFCAP_500),
 337          FLAG(lfcap0, PCI_HT_LFCAP_600),
 338          FLAG(lfcap0, PCI_HT_LFCAP_800),
 339          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 340          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 341          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 342          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 343          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 344   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 345   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 346          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 347          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 348          FLAG(ftr, PCI_HT_FTR_CRCTM),
 349          FLAG(ftr, PCI_HT_FTR_ECTLT),
 350          FLAG(ftr, PCI_HT_FTR_64BA),
 351          FLAG(ftr, PCI_HT_FTR_UIDRD));
 352   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 353   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 354   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 355          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 356          FLAG(lfrer1, PCI_HT_LFRER_OV),
 357          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 358          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 359   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 360   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 361          FLAG(lfcap1, PCI_HT_LFCAP_200),
 362          FLAG(lfcap1, PCI_HT_LFCAP_300),
 363          FLAG(lfcap1, PCI_HT_LFCAP_400),
 364          FLAG(lfcap1, PCI_HT_LFCAP_500),
 365          FLAG(lfcap1, PCI_HT_LFCAP_600),
 366          FLAG(lfcap1, PCI_HT_LFCAP_800),
 367          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 368          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 369          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 370          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 371          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 372   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 373   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 374          FLAG(eh, PCI_HT_EH_PFLE),
 375          FLAG(eh, PCI_HT_EH_OFLE),
 376          FLAG(eh, PCI_HT_EH_PFE),
 377          FLAG(eh, PCI_HT_EH_OFE),
 378          FLAG(eh, PCI_HT_EH_EOCFE),
 379          FLAG(eh, PCI_HT_EH_RFE),
 380          FLAG(eh, PCI_HT_EH_CRCFE),
 381          FLAG(eh, PCI_HT_EH_SERRFE),
 382          FLAG(eh, PCI_HT_EH_CF),
 383          FLAG(eh, PCI_HT_EH_RE),
 384          FLAG(eh, PCI_HT_EH_PNFE),
 385          FLAG(eh, PCI_HT_EH_ONFE),
 386          FLAG(eh, PCI_HT_EH_EOCNFE),
 387          FLAG(eh, PCI_HT_EH_RNFE),
 388          FLAG(eh, PCI_HT_EH_CRCNFE),
 389          FLAG(eh, PCI_HT_EH_SERRNFE));
 390   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 391   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 392   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 393   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 394   printf("\t\tBus Number: %02x\n", bn);
 395 }
 396
 397 static void
 398 cap_ht_sec(struct device *d, int where, int cmd)
 399 {
 400   u16 lctr, lcnf, ftr, eh;
 401   u8 rid, lfrer, lfcap, mbu, mlu;
 402   char *fmt;
 403
 404   printf("HyperTransport: Host or Secondary Interface\n");
 405   if (verbose < 2)
 406     return;
 407
 408   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 409     return;
 410   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 411   if (rid < 0x22 && rid > 0x11)
 412     printf("\t\t!!! Possibly incomplete decoding\n");
 413
 414   if (rid >= 0x22)
 415     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 416   else
 417     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 418   printf(fmt,
 419          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 420          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 421          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 422          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 423          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 424          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 425          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 426          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 427   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 428   if (rid >= 0x22)
 429     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 430   else
 431     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 432   printf(fmt,
 433          FLAG(lctr, PCI_HT_LCTR_CFLE),
 434          FLAG(lctr, PCI_HT_LCTR_CST),
 435          FLAG(lctr, PCI_HT_LCTR_CFE),
 436          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 437          FLAG(lctr, PCI_HT_LCTR_INIT),
 438          FLAG(lctr, PCI_HT_LCTR_EOC),
 439          FLAG(lctr, PCI_HT_LCTR_TXO),
 440          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 441          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 442          FLAG(lctr, PCI_HT_LCTR_LSEN),
 443          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 444          FLAG(lctr, PCI_HT_LCTR_64B));
 445   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 446   if (rid >= 0x22)
 447     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 448   else
 449     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 450   printf(fmt,
 451          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 452          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 453          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 454          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 455          FLAG(lcnf, PCI_HT_LCNF_DFI),
 456          FLAG(lcnf, PCI_HT_LCNF_DFO),
 457          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 458          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 459   printf("\t\tRevision ID: %u.%02u\n",
 460          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 461   if (rid < 0x22)
 462     return;
 463   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 464   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 465   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 466          FLAG(lfrer, PCI_HT_LFRER_PROT),
 467          FLAG(lfrer, PCI_HT_LFRER_OV),
 468          FLAG(lfrer, PCI_HT_LFRER_EOC),
 469          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 470   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 471   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 472          FLAG(lfcap, PCI_HT_LFCAP_200),
 473          FLAG(lfcap, PCI_HT_LFCAP_300),
 474          FLAG(lfcap, PCI_HT_LFCAP_400),
 475          FLAG(lfcap, PCI_HT_LFCAP_500),
 476          FLAG(lfcap, PCI_HT_LFCAP_600),
 477          FLAG(lfcap, PCI_HT_LFCAP_800),
 478          FLAG(lfcap, PCI_HT_LFCAP_1000),
 479          FLAG(lfcap, PCI_HT_LFCAP_1200),
 480          FLAG(lfcap, PCI_HT_LFCAP_1400),
 481          FLAG(lfcap, PCI_HT_LFCAP_1600),
 482          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 483   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 484   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 485          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 486          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 487          FLAG(ftr, PCI_HT_FTR_CRCTM),
 488          FLAG(ftr, PCI_HT_FTR_ECTLT),
 489          FLAG(ftr, PCI_HT_FTR_64BA),
 490          FLAG(ftr, PCI_HT_FTR_UIDRD),
 491          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 492          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 493   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 494     {
 495       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 496       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 497              FLAG(eh, PCI_HT_EH_PFLE),
 498              FLAG(eh, PCI_HT_EH_OFLE),
 499              FLAG(eh, PCI_HT_EH_PFE),
 500              FLAG(eh, PCI_HT_EH_OFE),
 501              FLAG(eh, PCI_HT_EH_EOCFE),
 502              FLAG(eh, PCI_HT_EH_RFE),
 503              FLAG(eh, PCI_HT_EH_CRCFE),
 504              FLAG(eh, PCI_HT_EH_SERRFE),
 505              FLAG(eh, PCI_HT_EH_CF),
 506              FLAG(eh, PCI_HT_EH_RE),
 507              FLAG(eh, PCI_HT_EH_PNFE),
 508              FLAG(eh, PCI_HT_EH_ONFE),
 509              FLAG(eh, PCI_HT_EH_EOCNFE),
 510              FLAG(eh, PCI_HT_EH_RNFE),
 511              FLAG(eh, PCI_HT_EH_CRCNFE),
 512              FLAG(eh, PCI_HT_EH_SERRNFE));
 513       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 514       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 515       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 516     }
 517 }
 518
 519 static void
 520 cap_ht(struct device *d, int where, int cmd)
 521 {
 522   int type;
 523
 524   switch (cmd & PCI_HT_CMD_TYP_HI)
 525     {
 526     case PCI_HT_CMD_TYP_HI_PRI:
 527       cap_ht_pri(d, where, cmd);
 528       return;
 529     case PCI_HT_CMD_TYP_HI_SEC:
 530       cap_ht_sec(d, where, cmd);
 531       return;
 532     }
 533
 534   type = cmd & PCI_HT_CMD_TYP;
 535   switch (type)
 536     {
 537     case PCI_HT_CMD_TYP_SW:
 538       printf("HyperTransport: Switch\n");
 539       break;
 540     case PCI_HT_CMD_TYP_IDC:
 541       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 542       break;
 543     case PCI_HT_CMD_TYP_RID:
 544       printf("HyperTransport: Revision ID: %u.%02u\n",
 545              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 546       break;
 547     case PCI_HT_CMD_TYP_UIDC:
 548       printf("HyperTransport: UnitID Clumping\n");
 549       break;
 550     case PCI_HT_CMD_TYP_ECSA:
 551       printf("HyperTransport: Extended Configuration Space Access\n");
 552       break;
 553     case PCI_HT_CMD_TYP_AM:
 554       printf("HyperTransport: Address Mapping\n");
 555       break;
 556     case PCI_HT_CMD_TYP_MSIM:
 557       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 558              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 559              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 560       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 561         {
 562           u32 offl, offh;
 563           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 564             break;
 565           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 566           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 567           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 568         }
 569       break;
 570     case PCI_HT_CMD_TYP_DR:
 571       printf("HyperTransport: DirectRoute\n");
 572       break;
 573     case PCI_HT_CMD_TYP_VCS:
 574       printf("HyperTransport: VCSet\n");
 575       break;
 576     case PCI_HT_CMD_TYP_RM:
 577       printf("HyperTransport: Retry Mode\n");
 578       break;
 579     case PCI_HT_CMD_TYP_X86:
 580       printf("HyperTransport: X86 (reserved)\n");
 581       break;
 582     default:
 583       printf("HyperTransport: #%02x\n", type >> 11);
 584     }
 585 }
 586
 587 static void
 588 cap_msi(struct device *d, int where, int cap)
 589 {
 590   int is64;
 591   u32 t;
 592   u16 w;
 593
 594   printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
 595          FLAG(cap, PCI_MSI_FLAGS_ENABLE),
 596          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 597          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 598          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 599          FLAG(cap, PCI_MSI_FLAGS_64BIT));
 600   if (verbose < 2)
 601     return;
 602   is64 = cap & PCI_MSI_FLAGS_64BIT;
 603   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 604     return;
 605   printf("\t\tAddress: ");
 606   if (is64)
 607     {
 608       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 609       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 610       printf("%08x", t);
 611     }
 612   else
 613     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 614   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 615   printf("%08x  Data: %04x\n", t, w);
 616   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 617     {
 618       u32 mask, pending;
 619
 620       if (is64)
 621         {
 622           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 623             return;
 624           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 625           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 626         }
 627       else
 628         {
 629           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 630             return;
 631           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 632           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 633         }
 634       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 635     }
 636 }
 637
 638 static float power_limit(int value, int scale)
 639 {
 640   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 641   return value * scales[scale];
 642 }
 643
 644 static const char *latency_l0s(int value)
 645 {
 646   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 647   return latencies[value];
 648 }
 649
 650 static const char *latency_l1(int value)
 651 {
 652   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 653   return latencies[value];
 654 }
 655
 656 static void cap_express_dev(struct device *d, int where, int type)
 657 {
 658   u32 t;
 659   u16 w;
 660
 661   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 662   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 663         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 664         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
 665   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 666     printf(", Latency L0s %s, L1 %s",
 667         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 668         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 669   printf("\n");
 670   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 671   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 672       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 673     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 674         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 675         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 676   printf(" RBE%c",
 677         FLAG(t, PCI_EXP_DEVCAP_RBE));
 678   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 679     printf(" FLReset%c",
 680         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 681   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
 682       (type == PCI_EXP_TYPE_PCI_BRIDGE))
 683     printf(" SlotPowerLimit %.3fW",
 684         power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 685                     (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
 686   printf("\n");
 687
 688   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 689   printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
 690         FLAG(w, PCI_EXP_DEVCTL_CERE),
 691         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 692         FLAG(w, PCI_EXP_DEVCTL_FERE),
 693         FLAG(w, PCI_EXP_DEVCTL_URRE));
 694   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 695         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 696         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 697         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 698         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 699         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 700   if (type == PCI_EXP_TYPE_PCI_BRIDGE)
 701     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 702   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
 703       (t & PCI_EXP_DEVCAP_FLRESET))
 704     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 705   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 706         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 707         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 708
 709   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 710   printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
 711         FLAG(w, PCI_EXP_DEVSTA_CED),
 712         FLAG(w, PCI_EXP_DEVSTA_NFED),
 713         FLAG(w, PCI_EXP_DEVSTA_FED),
 714         FLAG(w, PCI_EXP_DEVSTA_URD),
 715         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 716         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 717 }
 718
 719 static char *link_speed(int speed)
 720 {
 721   switch (speed)
 722     {
 723       case 1:
 724         return "2.5GT/s";
 725       case 2:
 726         return "5GT/s";
 727       case 3:
 728         return "8GT/s";
 729       case 4:
 730         return "16GT/s";
 731       default:
 732         return "unknown";
 733     }
 734 }
 735
 736 static char *aspm_support(int code)
 737 {
 738   switch (code)
 739     {
 740       case 0:
 741         return "not supported";
 742       case 1:
 743         return "L0s";
 744       case 2:
 745         return "L1";
 746       case 3:
 747         return "L0s L1";
 748       default:
 749         return "unknown";
 750     }
 751 }
 752
 753 static const char *aspm_enabled(int code)
 754 {
 755   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 756   return desc[code];
 757 }
 758
 759 static void cap_express_link(struct device *d, int where, int type)
 760 {
 761   u32 t;
 762   u16 w;
 763
 764   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 765   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n",
 766         t >> 24,
 767         link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
 768         aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
 769         latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
 770         latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 771   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
 772         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 773         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 774         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 775         FLAG(t, PCI_EXP_LNKCAP_LBNC),
 776         FLAG(t, PCI_EXP_LNKCAP_AOC));
 777
 778   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 779   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 780   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 781       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 782     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 783   printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 784         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 785         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 786         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 787         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 788         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 789         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 790         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 791
 792   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 793   printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 794         link_speed(w & PCI_EXP_LNKSTA_SPEED),
 795         (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
 796         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 797         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 798         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 799         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 800         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 801         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 802 }
 803
 804 static const char *indicator(int code)
 805 {
 806   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 807   return names[code];
 808 }
 809
 810 static void cap_express_slot(struct device *d, int where)
 811 {
 812   u32 t;
 813   u16 w;
 814
 815   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 816   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 817         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 818         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 819         FLAG(t, PCI_EXP_SLTCAP_MRL),
 820         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 821         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 822         FLAG(t, PCI_EXP_SLTCAP_HPC),
 823         FLAG(t, PCI_EXP_SLTCAP_HPS));
 824   printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
 825         t >> 19,
 826         power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
 827         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 828         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 829
 830   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 831   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 832         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 833         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 834         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 835         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 836         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 837         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 838         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 839   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 840         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 841         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 842         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 843         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 844
 845   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 846   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 847         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 848         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 849         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 850         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 851         FLAG(w, PCI_EXP_SLTSTA_PRES),
 852         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 853   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 854         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 855         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 856         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 857 }
 858
 859 static void cap_express_root(struct device *d, int where)
 860 {
 861   u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
 862   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 863         FLAG(w, PCI_EXP_RTCTL_SECEE),
 864         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 865         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 866         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 867         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 868
 869   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 870   printf("\t\tRootCap: CRSVisible%c\n",
 871         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 872
 873   w = get_conf_word(d, where + PCI_EXP_RTSTA);
 874   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 875         w & PCI_EXP_RTSTA_PME_REQID,
 876         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 877         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 878 }
 879
 880 static const char *cap_express_dev2_timeout_range(int type)
 881 {
 882   /* Decode Completion Timeout Ranges. */
 883   switch (type)
 884     {
 885       case 0:
 886         return "Not Supported";
 887       case 1:
 888         return "Range A";
 889       case 2:
 890         return "Range B";
 891       case 3:
 892         return "Range AB";
 893       case 6:
 894         return "Range BC";
 895       case 7:
 896         return "Range ABC";
 897       case 14:
 898         return "Range BCD";
 899       case 15:
 900         return "Range ABCD";
 901       default:
 902         return "Unknown";
 903     }
 904 }
 905
 906 static const char *cap_express_dev2_timeout_value(int type)
 907 {
 908   /* Decode Completion Timeout Value. */
 909   switch (type)
 910     {
 911       case 0:
 912         return "50us to 50ms";
 913       case 1:
 914         return "50us to 100us";
 915       case 2:
 916         return "1ms to 10ms";
 917       case 5:
 918         return "16ms to 55ms";
 919       case 6:
 920         return "65ms to 210ms";
 921       case 9:
 922         return "260ms to 900ms";
 923       case 10:
 924         return "1s to 3.5s";
 925       case 13:
 926         return "4s to 13s";
 927       case 14:
 928         return "17s to 64s";
 929       default:
 930         return "Unknown";
 931     }
 932 }
 933
 934 static const char *cap_express_devcap2_obff(int obff)
 935 {
 936   switch (obff)
 937     {
 938       case 1:
 939         return "Via message";
 940       case 2:
 941         return "Via WAKE#";
 942       case 3:
 943         return "Via message/WAKE#";
 944       default:
 945         return "Not Supported";
 946     }
 947 }
 948
 949 static const char *cap_express_devctl2_obff(int obff)
 950 {
 951   switch (obff)
 952     {
 953       case 0:
 954         return "Disabled";
 955       case 1:
 956         return "Via message A";
 957       case 2:
 958         return "Via message B";
 959       case 3:
 960         return "Via WAKE#";
 961       default:
 962         return "Unknown";
 963     }
 964 }
 965
 966 static int
 967 device_has_memory_space_bar(struct device *d)
 968 {
 969   struct pci_dev *p = d->dev;
 970   int i, found = 0;
 971
 972   for (i=0; i<6; i++)
 973     if (p->base_addr[i] && p->size[i])
 974       {
 975         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
 976           {
 977             found = 1;
 978             break;
 979           }
 980       }
 981   return found;
 982 }
 983
 984 static void cap_express_dev2(struct device *d, int where, int type)
 985 {
 986   u32 l;
 987   u16 w;
 988   int has_mem_bar = device_has_memory_space_bar(d);
 989
 990   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
 991   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
 992         cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
 993         FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
 994         FLAG(l, PCI_EXP_DEVCAP2_LTR),
 995         cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)));
 996   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
 997     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
 998   else
 999     printf("\n");
1000   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1001       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1002     {
1003        printf("\t\tAtomicOpsCap:");
1004        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1005            type == PCI_EXP_TYPE_DOWNSTREAM)
1006          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1007        if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1008          printf(" 32bit%c 64bit%c 128bitCAS%c",
1009                 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1010                 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1011                 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1012        printf("\n");
1013     }
1014
1015   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1016   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1017         cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1018         FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
1019         FLAG(w, PCI_EXP_DEV2_LTR),
1020         cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
1021   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1022     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1023   else
1024     printf("\n");
1025   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1026       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1027       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1028     {
1029       printf("\t\tAtomicOpsCtl:");
1030       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1031           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1032         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
1033       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1034           type == PCI_EXP_TYPE_DOWNSTREAM)
1035         printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
1036       printf("\n");
1037     }
1038 }
1039
1040 static const char *cap_express_link2_speed(int type)
1041 {
1042   switch (type)
1043     {
1044       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1045       case 1:
1046         return "2.5GT/s";
1047       case 2:
1048         return "5GT/s";
1049       case 3:
1050         return "8GT/s";
1051       case 4:
1052         return "16GT/s";
1053       default:
1054         return "Unknown";
1055     }
1056 }
1057
1058 static const char *cap_express_link2_deemphasis(int type)
1059 {
1060   switch (type)
1061     {
1062       case 0:
1063         return "-6dB";
1064       case 1:
1065         return "-3.5dB";
1066       default:
1067         return "Unknown";
1068     }
1069 }
1070
1071 static const char *cap_express_link2_transmargin(int type)
1072 {
1073   switch (type)
1074     {
1075       case 0:
1076         return "Normal Operating Range";
1077       case 1:
1078         return "800-1200mV(full-swing)/400-700mV(half-swing)";
1079       case 2:
1080       case 3:
1081       case 4:
1082       case 5:
1083         return "200-400mV(full-swing)/100-200mV(half-swing)";
1084       default:
1085         return "Unknown";
1086     }
1087 }
1088
1089 static void cap_express_link2(struct device *d, int where, int type)
1090 {
1091   u16 w;
1092
1093   if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1094         (d->dev->dev != 0 || d->dev->func != 0))) {
1095     w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1096     printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1097         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1098         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1099         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1100     if (type == PCI_EXP_TYPE_DOWNSTREAM)
1101       printf(", Selectable De-emphasis: %s",
1102         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1103     printf("\n"
1104         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1105         "\t\t\t Compliance De-emphasis: %s\n",
1106         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1107         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1108         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1109         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1110   }
1111
1112   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1113   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
1114         "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
1115         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1116         FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1117         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1118         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1119         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1120         FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
1121 }
1122
1123 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1124 {
1125   /* No capabilities that require this field in PCIe rev2.0 spec. */
1126 }
1127
1128 static void
1129 cap_express(struct device *d, int where, int cap)
1130 {
1131   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1132   int size;
1133   int slot = 0;
1134   int link = 1;
1135
1136   printf("Express ");
1137   if (verbose >= 2)
1138     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1139   switch (type)
1140     {
1141     case PCI_EXP_TYPE_ENDPOINT:
1142       printf("Endpoint");
1143       break;
1144     case PCI_EXP_TYPE_LEG_END:
1145       printf("Legacy Endpoint");
1146       break;
1147     case PCI_EXP_TYPE_ROOT_PORT:
1148       slot = cap & PCI_EXP_FLAGS_SLOT;
1149       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1150       break;
1151     case PCI_EXP_TYPE_UPSTREAM:
1152       printf("Upstream Port");
1153       break;
1154     case PCI_EXP_TYPE_DOWNSTREAM:
1155       slot = cap & PCI_EXP_FLAGS_SLOT;
1156       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1157       break;
1158     case PCI_EXP_TYPE_PCI_BRIDGE:
1159       printf("PCI-Express to PCI/PCI-X Bridge");
1160       break;
1161     case PCI_EXP_TYPE_PCIE_BRIDGE:
1162       printf("PCI/PCI-X to PCI-Express Bridge");
1163       break;
1164     case PCI_EXP_TYPE_ROOT_INT_EP:
1165       link = 0;
1166       printf("Root Complex Integrated Endpoint");
1167       break;
1168     case PCI_EXP_TYPE_ROOT_EC:
1169       link = 0;
1170       printf("Root Complex Event Collector");
1171       break;
1172     default:
1173       printf("Unknown type %d", type);
1174   }
1175   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1176   if (verbose < 2)
1177     return;
1178
1179   size = 16;
1180   if (slot)
1181     size = 24;
1182   if (type == PCI_EXP_TYPE_ROOT_PORT)
1183     size = 32;
1184   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1185     return;
1186
1187   cap_express_dev(d, where, type);
1188   if (link)
1189     cap_express_link(d, where, type);
1190   if (slot)
1191     cap_express_slot(d, where);
1192   if (type == PCI_EXP_TYPE_ROOT_PORT)
1193     cap_express_root(d, where);
1194
1195   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1196     return;
1197
1198   size = 16;
1199   if (slot)
1200     size = 24;
1201   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1202     return;
1203
1204   cap_express_dev2(d, where, type);
1205   if (link)
1206     cap_express_link2(d, where, type);
1207   if (slot)
1208     cap_express_slot2(d, where);
1209 }
1210
1211 static void
1212 cap_msix(struct device *d, int where, int cap)
1213 {
1214   u32 off;
1215
1216   printf("MSI-X: Enable%c Count=%d Masked%c\n",
1217          FLAG(cap, PCI_MSIX_ENABLE),
1218          (cap & PCI_MSIX_TABSIZE) + 1,
1219          FLAG(cap, PCI_MSIX_MASK));
1220   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1221     return;
1222
1223   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1224   printf("\t\tVector table: BAR=%d offset=%08x\n",
1225          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1226   off = get_conf_long(d, where + PCI_MSIX_PBA);
1227   printf("\t\tPBA: BAR=%d offset=%08x\n",
1228          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1229 }
1230
1231 static void
1232 cap_slotid(int cap)
1233 {
1234   int esr = cap & 0xff;
1235   int chs = cap >> 8;
1236
1237   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1238          esr & PCI_SID_ESR_NSLOTS,
1239          FLAG(esr, PCI_SID_ESR_FIC),
1240          chs);
1241 }
1242
1243 static void
1244 cap_ssvid(struct device *d, int where)
1245 {
1246   u16 subsys_v, subsys_d;
1247   char ssnamebuf[256];
1248
1249   if (!config_fetch(d, where, 8))
1250     return;
1251   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1252   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1253   printf("Subsystem: %s\n",
1254            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1255                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1256                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1257 }
1258
1259 static void
1260 cap_debug_port(int cap)
1261 {
1262   int bar = cap >> 13;
1263   int pos = cap & 0x1fff;
1264   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1265 }
1266
1267 static void
1268 cap_af(struct device *d, int where)
1269 {
1270   u8 reg;
1271
1272   printf("PCI Advanced Features\n");
1273   if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1274     return;
1275
1276   reg = get_conf_byte(d, where + PCI_AF_CAP);
1277   printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1278          FLAG(reg, PCI_AF_CAP_FLR));
1279   reg = get_conf_byte(d, where + PCI_AF_CTRL);
1280   printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1281   reg = get_conf_byte(d, where + PCI_AF_STATUS);
1282   printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1283 }
1284
1285 static void
1286 cap_sata_hba(struct device *d, int where, int cap)
1287 {
1288   u32 bars;
1289   int bar;
1290
1291   printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1292   if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1293     {
1294       printf("\n");
1295       return;
1296     }
1297
1298   bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1299   bar = BITS(bars, 0, 4);
1300   if (bar >= 4 && bar <= 9)
1301     printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1302   else if (bar == 15)
1303     printf(" InCfgSpace\n");
1304   else
1305     printf(" BAR??%d\n", bar);
1306 }
1307
1308 static const char *cap_ea_property(int p, int is_secondary)
1309 {
1310   switch (p) {
1311   case 0x00:
1312     return "memory space, non-prefetchable";
1313   case 0x01:
1314     return "memory space, prefetchable";
1315   case 0x02:
1316     return "I/O space";
1317   case 0x03:
1318     return "VF memory space, prefetchable";
1319   case 0x04:
1320     return "VF memory space, non-prefetchable";
1321   case 0x05:
1322     return "allocation behind bridge, non-prefetchable memory";
1323   case 0x06:
1324     return "allocation behind bridge, prefetchable memory";
1325   case 0x07:
1326     return "allocation behind bridge, I/O space";
1327   case 0xfd:
1328     return "memory space resource unavailable for use";
1329   case 0xfe:
1330     return "I/O space resource unavailable for use";
1331   case 0xff:
1332     if (is_secondary)
1333       return "entry unavailable for use, PrimaryProperties should be used";
1334     else
1335       return "entry unavailable for use";
1336   default:
1337     return NULL;
1338   }
1339 }
1340
1341 static void cap_ea(struct device *d, int where, int cap)
1342 {
1343   int entry;
1344   int entry_base = where + 4;
1345   int num_entries = BITS(cap, 0, 6);
1346   u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1347
1348   printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1349   if (htype == PCI_HEADER_TYPE_BRIDGE) {
1350     byte fixed_sub, fixed_sec;
1351
1352     entry_base += 4;
1353     if (!config_fetch(d, where + 4, 2)) {
1354       printf("\n");
1355       return;
1356     }
1357     fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1358     fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1359     printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1360   }
1361   printf("\n");
1362   if (verbose < 2)
1363     return;
1364
1365   for (entry = 0; entry < num_entries; entry++) {
1366     int max_offset_high_pos, has_base_high, has_max_offset_high;
1367     u32 entry_header;
1368     u32 base, max_offset;
1369     int es, bei, pp, sp;
1370     const char *prop_text;
1371
1372     if (!config_fetch(d, entry_base, 4))
1373       return;
1374     entry_header = get_conf_long(d, entry_base);
1375     es = BITS(entry_header, 0, 3);
1376     bei = BITS(entry_header, 4, 4);
1377     pp = BITS(entry_header, 8, 8);
1378     sp = BITS(entry_header, 16, 8);
1379     if (!config_fetch(d, entry_base + 4, es * 4))
1380       return;
1381     printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1382            FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1383            FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1384     printf("\t\t\t BAR Equivalent Indicator: ");
1385     switch (bei) {
1386     case 0:
1387     case 1:
1388     case 2:
1389     case 3:
1390     case 4:
1391     case 5:
1392       printf("BAR %u", bei);
1393       break;
1394     case 6:
1395       printf("resource behind function");
1396       break;
1397     case 7:
1398       printf("not indicated");
1399       break;
1400     case 8:
1401       printf("expansion ROM");
1402       break;
1403     case 9:
1404     case 10:
1405     case 11:
1406     case 12:
1407     case 13:
1408     case 14:
1409       printf("VF-BAR %u", bei - 9);
1410       break;
1411     default:
1412       printf("reserved");
1413       break;
1414     }
1415     printf("\n");
1416
1417     prop_text = cap_ea_property(pp, 0);
1418     printf("\t\t\t PrimaryProperties: ");
1419     if (prop_text)
1420       printf("%s\n", prop_text);
1421     else
1422       printf("[%02x]\n", pp);
1423
1424     prop_text = cap_ea_property(sp, 1);
1425     printf("\t\t\t SecondaryProperties: ");
1426     if (prop_text)
1427       printf("%s\n", prop_text);
1428     else
1429       printf("[%02x]\n", sp);
1430
1431     base = get_conf_long(d, entry_base + 4);
1432     has_base_high = ((base & 2) != 0);
1433     base &= ~3;
1434
1435     max_offset = get_conf_long(d, entry_base + 8);
1436     has_max_offset_high = ((max_offset & 2) != 0);
1437     max_offset |= 3;
1438     max_offset_high_pos = entry_base + 12;
1439
1440     printf("\t\t\t Base: ");
1441     if (has_base_high) {
1442       u32 base_high = get_conf_long(d, entry_base + 12);
1443
1444       printf("%x", base_high);
1445       max_offset_high_pos += 4;
1446     }
1447     printf("%08x\n", base);
1448
1449     printf("\t\t\t MaxOffset: ");
1450     if (has_max_offset_high) {
1451       u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1452
1453       printf("%x", max_offset_high);
1454     }
1455     printf("%08x\n", max_offset);
1456
1457     entry_base += 4 + 4 * es;
1458   }
1459 }
1460
1461 void
1462 show_caps(struct device *d, int where)
1463 {
1464   int can_have_ext_caps = 0;
1465
1466   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1467     {
1468       byte been_there[256];
1469       where = get_conf_byte(d, where) & ~3;
1470       memset(been_there, 0, 256);
1471       while (where)
1472         {
1473           int id, next, cap;
1474           printf("\tCapabilities: ");
1475           if (!config_fetch(d, where, 4))
1476             {
1477               puts("<access denied>");
1478               break;
1479             }
1480           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1481           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1482           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1483           printf("[%02x] ", where);
1484           if (been_there[where]++)
1485             {
1486               printf("<chain looped>\n");
1487               break;
1488             }
1489           if (id == 0xff)
1490             {
1491               printf("<chain broken>\n");
1492               break;
1493             }
1494           switch (id)
1495             {
1496             case PCI_CAP_ID_PM:
1497               cap_pm(d, where, cap);
1498               break;
1499             case PCI_CAP_ID_AGP:
1500               cap_agp(d, where, cap);
1501               break;
1502             case PCI_CAP_ID_VPD:
1503               cap_vpd(d);
1504               break;
1505             case PCI_CAP_ID_SLOTID:
1506               cap_slotid(cap);
1507               break;
1508             case PCI_CAP_ID_MSI:
1509               cap_msi(d, where, cap);
1510               break;
1511             case PCI_CAP_ID_CHSWP:
1512               printf("CompactPCI hot-swap <?>\n");
1513               break;
1514             case PCI_CAP_ID_PCIX:
1515               cap_pcix(d, where);
1516               can_have_ext_caps = 1;
1517               break;
1518             case PCI_CAP_ID_HT:
1519               cap_ht(d, where, cap);
1520               break;
1521             case PCI_CAP_ID_VNDR:
1522               show_vendor_caps(d, where, cap);
1523               break;
1524             case PCI_CAP_ID_DBG:
1525               cap_debug_port(cap);
1526               break;
1527             case PCI_CAP_ID_CCRC:
1528               printf("CompactPCI central resource control <?>\n");
1529               break;
1530             case PCI_CAP_ID_HOTPLUG:
1531               printf("Hot-plug capable\n");
1532               break;
1533             case PCI_CAP_ID_SSVID:
1534               cap_ssvid(d, where);
1535               break;
1536             case PCI_CAP_ID_AGP3:
1537               printf("AGP3 <?>\n");
1538               break;
1539             case PCI_CAP_ID_SECURE:
1540               printf("Secure device <?>\n");
1541               break;
1542             case PCI_CAP_ID_EXP:
1543               cap_express(d, where, cap);
1544               can_have_ext_caps = 1;
1545               break;
1546             case PCI_CAP_ID_MSIX:
1547               cap_msix(d, where, cap);
1548               break;
1549             case PCI_CAP_ID_SATA:
1550               cap_sata_hba(d, where, cap);
1551               break;
1552             case PCI_CAP_ID_AF:
1553               cap_af(d, where);
1554               break;
1555             case PCI_CAP_ID_EA:
1556               cap_ea(d, where, cap);
1557               break;
1558             default:
1559               printf("#%02x [%04x]\n", id, cap);
1560             }
1561           where = next;
1562         }
1563     }
1564   if (can_have_ext_caps)
1565     show_ext_caps(d);
1566 }