ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
  40          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  41          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  42          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  43          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  44   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  45   if (b)
  46     printf("\t\tBridge: PM%c B3%c\n",
  47            FLAG(t, PCI_PM_BPCC_ENABLE),
  48            FLAG(~t, PCI_PM_PPB_B2_B3));
  49 }
  50
  51 static void
  52 format_agp_rate(int rate, char *buf, int agp3)
  53 {
  54   char *c = buf;
  55   int i;
  56
  57   for (i=0; i<=2; i++)
  58     if (rate & (1 << i))
  59       {
  60         if (c != buf)
  61           *c++ = ',';
  62         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  63       }
  64   if (c != buf)
  65     *c = 0;
  66   else
  67     strcpy(buf, "<none>");
  68 }
  69
  70 static void
  71 cap_agp(struct device *d, int where, int cap)
  72 {
  73   u32 t;
  74   char rate[16];
  75   int ver, rev;
  76   int agp3 = 0;
  77
  78   ver = (cap >> 4) & 0x0f;
  79   rev = cap & 0x0f;
  80   printf("AGP version %x.%x\n", ver, rev);
  81   if (verbose < 2)
  82     return;
  83   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  84     return;
  85   t = get_conf_long(d, where + PCI_AGP_STATUS);
  86   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  87     agp3 = 1;
  88   format_agp_rate(t & 7, rate, agp3);
  89   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  90          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  91          FLAG(t, PCI_AGP_STATUS_ISOCH),
  92          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  93          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  94          FLAG(t, PCI_AGP_STATUS_SBA),
  95          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  96          FLAG(t, PCI_AGP_STATUS_GART64),
  97          FLAG(t, PCI_AGP_STATUS_HTRANS),
  98          FLAG(t, PCI_AGP_STATUS_64BIT),
  99          FLAG(t, PCI_AGP_STATUS_FW),
 100          FLAG(t, PCI_AGP_STATUS_AGP3),
 101          rate);
 102   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 103   format_agp_rate(t & 7, rate, agp3);
 104   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 105          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 106          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 107          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 108          FLAG(t, PCI_AGP_COMMAND_SBA),
 109          FLAG(t, PCI_AGP_COMMAND_AGP),
 110          FLAG(t, PCI_AGP_COMMAND_GART64),
 111          FLAG(t, PCI_AGP_COMMAND_64BIT),
 112          FLAG(t, PCI_AGP_COMMAND_FW),
 113          rate);
 114 }
 115
 116 static void
 117 cap_pcix_nobridge(struct device *d, int where)
 118 {
 119   u16 command;
 120   u32 status;
 121   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 122
 123   printf("PCI-X non-bridge device\n");
 124
 125   if (verbose < 2)
 126     return;
 127
 128   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 129     return;
 130
 131   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 132   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 133   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 134          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 135          FLAG(command, PCI_PCIX_COMMAND_ERO),
 136          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 137          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 138   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 139          (status & PCI_PCIX_STATUS_BUS) >> 8,
 140          (status & PCI_PCIX_STATUS_DEVICE) >> 3,
 141          (status & PCI_PCIX_STATUS_FUNCTION),
 142          FLAG(status, PCI_PCIX_STATUS_64BIT),
 143          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 144          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 145          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 146          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 147          1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
 148          max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
 149          1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
 150          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 151          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 152          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 153 }
 154
 155 static void
 156 cap_pcix_bridge(struct device *d, int where)
 157 {
 158   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 159   u16 secstatus;
 160   u32 status, upstcr, downstcr;
 161
 162   printf("PCI-X bridge device\n");
 163
 164   if (verbose < 2)
 165     return;
 166
 167   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 168     return;
 169
 170   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 171   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 177          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 178          sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
 179   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 180   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 181          (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
 182          (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
 183          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 189          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 190   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 191   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 192          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 193          (upstcr >> 16) & 0xffff);
 194   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 195   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 196          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 197          (downstcr >> 16) & 0xffff);
 198 }
 199
 200 static void
 201 cap_pcix(struct device *d, int where)
 202 {
 203   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 204     {
 205     case PCI_HEADER_TYPE_NORMAL:
 206       cap_pcix_nobridge(d, where);
 207       break;
 208     case PCI_HEADER_TYPE_BRIDGE:
 209       cap_pcix_bridge(d, where);
 210       break;
 211     }
 212 }
 213
 214 static inline char *
 215 ht_link_width(unsigned width)
 216 {
 217   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 218   return widths[width];
 219 }
 220
 221 static inline char *
 222 ht_link_freq(unsigned freq)
 223 {
 224   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 225                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 226   return freqs[freq];
 227 }
 228
 229 static void
 230 cap_ht_pri(struct device *d, int where, int cmd)
 231 {
 232   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 233   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 234
 235   printf("HyperTransport: Slave or Primary Interface\n");
 236   if (verbose < 2)
 237     return;
 238
 239   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 240     return;
 241   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 242   if (rid < 0x22 && rid > 0x11)
 243     printf("\t\t!!! Possibly incomplete decoding\n");
 244
 245   printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
 246          (cmd & PCI_HT_PRI_CMD_BUID),
 247          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 248          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 249          FLAG(cmd, PCI_HT_PRI_CMD_DD));
 250   if (rid >= 0x22)
 251     printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 252   printf("\n");
 253
 254   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 255   printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 256          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 257          FLAG(lctr0, PCI_HT_LCTR_CST),
 258          FLAG(lctr0, PCI_HT_LCTR_CFE),
 259          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 260          FLAG(lctr0, PCI_HT_LCTR_INIT),
 261          FLAG(lctr0, PCI_HT_LCTR_EOC),
 262          FLAG(lctr0, PCI_HT_LCTR_TXO),
 263          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
 264   if (rid >= 0x22)
 265     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 266            FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 267            FLAG(lctr0, PCI_HT_LCTR_LSEN),
 268            FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 269            FLAG(lctr0, PCI_HT_LCTR_64B));
 270   printf("\n");
 271
 272   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 273   if (rid < 0x22)
 274     printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 275            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 276            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 277            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 278            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
 279   else
 280     printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 281            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 282            FLAG(lcnf0, PCI_HT_LCNF_DFI),
 283            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 284            FLAG(lcnf0, PCI_HT_LCNF_DFO),
 285            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 286            FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 287            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 288            FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 289
 290   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 291   printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 292          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 293          FLAG(lctr1, PCI_HT_LCTR_CST),
 294          FLAG(lctr1, PCI_HT_LCTR_CFE),
 295          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 296          FLAG(lctr1, PCI_HT_LCTR_INIT),
 297          FLAG(lctr1, PCI_HT_LCTR_EOC),
 298          FLAG(lctr1, PCI_HT_LCTR_TXO),
 299          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
 300   if (rid >= 0x22)
 301     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 302          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 303          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 304          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 305          FLAG(lctr1, PCI_HT_LCTR_64B));
 306   printf("\n");
 307
 308   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 309   if (rid < 0x22)
 310     printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 311            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 312            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 313            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 314            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
 315   else
 316     printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 317            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 318            FLAG(lcnf1, PCI_HT_LCNF_DFI),
 319            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 320            FLAG(lcnf1, PCI_HT_LCNF_DFO),
 321            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 322            FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 323            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 324            FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 325
 326   printf("\t\tRevision ID: %u.%02u\n",
 327          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 328   if (rid < 0x22)
 329     return;
 330
 331   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 332   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 333   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 334          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 335          FLAG(lfrer0, PCI_HT_LFRER_OV),
 336          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 337          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 338
 339   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 340   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 341          FLAG(lfcap0, PCI_HT_LFCAP_200),
 342          FLAG(lfcap0, PCI_HT_LFCAP_300),
 343          FLAG(lfcap0, PCI_HT_LFCAP_400),
 344          FLAG(lfcap0, PCI_HT_LFCAP_500),
 345          FLAG(lfcap0, PCI_HT_LFCAP_600),
 346          FLAG(lfcap0, PCI_HT_LFCAP_800),
 347          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 348          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 349          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 350          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 351          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 352
 353   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 354   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 355          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 356          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 357          FLAG(ftr, PCI_HT_FTR_CRCTM),
 358          FLAG(ftr, PCI_HT_FTR_ECTLT),
 359          FLAG(ftr, PCI_HT_FTR_64BA),
 360          FLAG(ftr, PCI_HT_FTR_UIDRD));
 361
 362   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 363   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 364   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 365          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 366          FLAG(lfrer1, PCI_HT_LFRER_OV),
 367          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 368          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 369
 370   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 371   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 372          FLAG(lfcap1, PCI_HT_LFCAP_200),
 373          FLAG(lfcap1, PCI_HT_LFCAP_300),
 374          FLAG(lfcap1, PCI_HT_LFCAP_400),
 375          FLAG(lfcap1, PCI_HT_LFCAP_500),
 376          FLAG(lfcap1, PCI_HT_LFCAP_600),
 377          FLAG(lfcap1, PCI_HT_LFCAP_800),
 378          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 379          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 380          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 381          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 382          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 383
 384   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 385   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 386          FLAG(eh, PCI_HT_EH_PFLE),
 387          FLAG(eh, PCI_HT_EH_OFLE),
 388          FLAG(eh, PCI_HT_EH_PFE),
 389          FLAG(eh, PCI_HT_EH_OFE),
 390          FLAG(eh, PCI_HT_EH_EOCFE),
 391          FLAG(eh, PCI_HT_EH_RFE),
 392          FLAG(eh, PCI_HT_EH_CRCFE),
 393          FLAG(eh, PCI_HT_EH_SERRFE),
 394          FLAG(eh, PCI_HT_EH_CF),
 395          FLAG(eh, PCI_HT_EH_RE),
 396          FLAG(eh, PCI_HT_EH_PNFE),
 397          FLAG(eh, PCI_HT_EH_ONFE),
 398          FLAG(eh, PCI_HT_EH_EOCNFE),
 399          FLAG(eh, PCI_HT_EH_RNFE),
 400          FLAG(eh, PCI_HT_EH_CRCNFE),
 401          FLAG(eh, PCI_HT_EH_SERRNFE));
 402
 403   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 404   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 405   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 406
 407   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 408   printf("\t\tBus Number: %02x\n", bn);
 409 }
 410
 411 static void
 412 cap_ht_sec(struct device *d, int where, int cmd)
 413 {
 414   u16 lctr, lcnf, ftr, eh;
 415   u8 rid, lfrer, lfcap, mbu, mlu;
 416   char *fmt;
 417
 418   printf("HyperTransport: Host or Secondary Interface\n");
 419   if (verbose < 2)
 420     return;
 421
 422   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 423     return;
 424   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 425   if (rid < 0x22 && rid > 0x11)
 426     printf("\t\t!!! Possibly incomplete decoding\n");
 427
 428   if (rid >= 0x22)
 429     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 430   else
 431     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 432   printf(fmt,
 433          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 434          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 435          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 436          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 437          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 438          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 439          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 440          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 441   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 442   if (rid >= 0x22)
 443     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 444   else
 445     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 446   printf(fmt,
 447          FLAG(lctr, PCI_HT_LCTR_CFLE),
 448          FLAG(lctr, PCI_HT_LCTR_CST),
 449          FLAG(lctr, PCI_HT_LCTR_CFE),
 450          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 451          FLAG(lctr, PCI_HT_LCTR_INIT),
 452          FLAG(lctr, PCI_HT_LCTR_EOC),
 453          FLAG(lctr, PCI_HT_LCTR_TXO),
 454          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 455          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 456          FLAG(lctr, PCI_HT_LCTR_LSEN),
 457          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 458          FLAG(lctr, PCI_HT_LCTR_64B));
 459   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 460   if (rid >= 0x22)
 461     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 462   else
 463     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 464   printf(fmt,
 465          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 466          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 467          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 468          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 469          FLAG(lcnf, PCI_HT_LCNF_DFI),
 470          FLAG(lcnf, PCI_HT_LCNF_DFO),
 471          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 472          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 473   printf("\t\tRevision ID: %u.%02u\n",
 474          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 475   if (rid < 0x22)
 476     return;
 477   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 478   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 479   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 480          FLAG(lfrer, PCI_HT_LFRER_PROT),
 481          FLAG(lfrer, PCI_HT_LFRER_OV),
 482          FLAG(lfrer, PCI_HT_LFRER_EOC),
 483          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 484   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 485   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 486          FLAG(lfcap, PCI_HT_LFCAP_200),
 487          FLAG(lfcap, PCI_HT_LFCAP_300),
 488          FLAG(lfcap, PCI_HT_LFCAP_400),
 489          FLAG(lfcap, PCI_HT_LFCAP_500),
 490          FLAG(lfcap, PCI_HT_LFCAP_600),
 491          FLAG(lfcap, PCI_HT_LFCAP_800),
 492          FLAG(lfcap, PCI_HT_LFCAP_1000),
 493          FLAG(lfcap, PCI_HT_LFCAP_1200),
 494          FLAG(lfcap, PCI_HT_LFCAP_1400),
 495          FLAG(lfcap, PCI_HT_LFCAP_1600),
 496          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 497   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 498   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 499          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 500          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 501          FLAG(ftr, PCI_HT_FTR_CRCTM),
 502          FLAG(ftr, PCI_HT_FTR_ECTLT),
 503          FLAG(ftr, PCI_HT_FTR_64BA),
 504          FLAG(ftr, PCI_HT_FTR_UIDRD),
 505          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 506          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 507   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 508     {
 509       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 510       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 511              FLAG(eh, PCI_HT_EH_PFLE),
 512              FLAG(eh, PCI_HT_EH_OFLE),
 513              FLAG(eh, PCI_HT_EH_PFE),
 514              FLAG(eh, PCI_HT_EH_OFE),
 515              FLAG(eh, PCI_HT_EH_EOCFE),
 516              FLAG(eh, PCI_HT_EH_RFE),
 517              FLAG(eh, PCI_HT_EH_CRCFE),
 518              FLAG(eh, PCI_HT_EH_SERRFE),
 519              FLAG(eh, PCI_HT_EH_CF),
 520              FLAG(eh, PCI_HT_EH_RE),
 521              FLAG(eh, PCI_HT_EH_PNFE),
 522              FLAG(eh, PCI_HT_EH_ONFE),
 523              FLAG(eh, PCI_HT_EH_EOCNFE),
 524              FLAG(eh, PCI_HT_EH_RNFE),
 525              FLAG(eh, PCI_HT_EH_CRCNFE),
 526              FLAG(eh, PCI_HT_EH_SERRNFE));
 527       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 528       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 529       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 530     }
 531 }
 532
 533 static void
 534 cap_ht(struct device *d, int where, int cmd)
 535 {
 536   int type;
 537
 538   switch (cmd & PCI_HT_CMD_TYP_HI)
 539     {
 540     case PCI_HT_CMD_TYP_HI_PRI:
 541       cap_ht_pri(d, where, cmd);
 542       return;
 543     case PCI_HT_CMD_TYP_HI_SEC:
 544       cap_ht_sec(d, where, cmd);
 545       return;
 546     }
 547
 548   type = cmd & PCI_HT_CMD_TYP;
 549   switch (type)
 550     {
 551     case PCI_HT_CMD_TYP_SW:
 552       printf("HyperTransport: Switch\n");
 553       break;
 554     case PCI_HT_CMD_TYP_IDC:
 555       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 556       break;
 557     case PCI_HT_CMD_TYP_RID:
 558       printf("HyperTransport: Revision ID: %u.%02u\n",
 559              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 560       break;
 561     case PCI_HT_CMD_TYP_UIDC:
 562       printf("HyperTransport: UnitID Clumping\n");
 563       break;
 564     case PCI_HT_CMD_TYP_ECSA:
 565       printf("HyperTransport: Extended Configuration Space Access\n");
 566       break;
 567     case PCI_HT_CMD_TYP_AM:
 568       printf("HyperTransport: Address Mapping\n");
 569       break;
 570     case PCI_HT_CMD_TYP_MSIM:
 571       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 572              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 573              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 574       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 575         {
 576           u32 offl, offh;
 577           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 578             break;
 579           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 580           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 581           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 582         }
 583       break;
 584     case PCI_HT_CMD_TYP_DR:
 585       printf("HyperTransport: DirectRoute\n");
 586       break;
 587     case PCI_HT_CMD_TYP_VCS:
 588       printf("HyperTransport: VCSet\n");
 589       break;
 590     case PCI_HT_CMD_TYP_RM:
 591       printf("HyperTransport: Retry Mode\n");
 592       break;
 593     case PCI_HT_CMD_TYP_X86:
 594       printf("HyperTransport: X86 (reserved)\n");
 595       break;
 596     default:
 597       printf("HyperTransport: #%02x\n", type >> 11);
 598     }
 599 }
 600
 601 static void
 602 cap_msi(struct device *d, int where, int cap)
 603 {
 604   int is64;
 605   u32 t;
 606   u16 w;
 607
 608   printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
 609          FLAG(cap, PCI_MSI_FLAGS_ENABLE),
 610          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 611          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 612          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 613          FLAG(cap, PCI_MSI_FLAGS_64BIT));
 614   if (verbose < 2)
 615     return;
 616   is64 = cap & PCI_MSI_FLAGS_64BIT;
 617   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 618     return;
 619   printf("\t\tAddress: ");
 620   if (is64)
 621     {
 622       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 623       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 624       printf("%08x", t);
 625     }
 626   else
 627     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 628   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 629   printf("%08x  Data: %04x\n", t, w);
 630   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 631     {
 632       u32 mask, pending;
 633
 634       if (is64)
 635         {
 636           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 637             return;
 638           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 639           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 640         }
 641       else
 642         {
 643           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 644             return;
 645           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 646           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 647         }
 648       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 649     }
 650 }
 651
 652 static int exp_downstream_port(int type)
 653 {
 654   return type == PCI_EXP_TYPE_ROOT_PORT ||
 655          type == PCI_EXP_TYPE_DOWNSTREAM ||
 656          type == PCI_EXP_TYPE_PCIE_BRIDGE;      /* PCI/PCI-X to PCIe Bridge */
 657 }
 658
 659 static float power_limit(int value, int scale)
 660 {
 661   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 662   return value * scales[scale];
 663 }
 664
 665 static const char *latency_l0s(int value)
 666 {
 667   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 668   return latencies[value];
 669 }
 670
 671 static const char *latency_l1(int value)
 672 {
 673   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 674   return latencies[value];
 675 }
 676
 677 static void cap_express_dev(struct device *d, int where, int type)
 678 {
 679   u32 t;
 680   u16 w;
 681
 682   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 683   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 684         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 685         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
 686   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 687     printf(", Latency L0s %s, L1 %s",
 688         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 689         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 690   printf("\n");
 691   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 692   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 693       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 694     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 695         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 696         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 697   printf(" RBE%c",
 698         FLAG(t, PCI_EXP_DEVCAP_RBE));
 699   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
 700     printf(" FLReset%c",
 701         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 702   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
 703       (type == PCI_EXP_TYPE_PCI_BRIDGE))
 704     printf(" SlotPowerLimit %.3fW",
 705         power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 706                     (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
 707   printf("\n");
 708
 709   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 710   printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
 711         FLAG(w, PCI_EXP_DEVCTL_CERE),
 712         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 713         FLAG(w, PCI_EXP_DEVCTL_FERE),
 714         FLAG(w, PCI_EXP_DEVCTL_URRE));
 715   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 716         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 717         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 718         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 719         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 720         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 721   if (type == PCI_EXP_TYPE_PCI_BRIDGE)
 722     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 723   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
 724       (t & PCI_EXP_DEVCAP_FLRESET))
 725     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 726   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 727         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 728         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 729
 730   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 731   printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
 732         FLAG(w, PCI_EXP_DEVSTA_CED),
 733         FLAG(w, PCI_EXP_DEVSTA_NFED),
 734         FLAG(w, PCI_EXP_DEVSTA_FED),
 735         FLAG(w, PCI_EXP_DEVSTA_URD),
 736         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 737         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 738 }
 739
 740 static char *link_speed(int speed)
 741 {
 742   switch (speed)
 743     {
 744       case 1:
 745         return "2.5GT/s";
 746       case 2:
 747         return "5GT/s";
 748       case 3:
 749         return "8GT/s";
 750       case 4:
 751         return "16GT/s";
 752       case 5:
 753         return "32GT/s";
 754       default:
 755         return "unknown";
 756     }
 757 }
 758
 759 static char *link_compare(int sta, int cap)
 760 {
 761   if (sta < cap)
 762     return "downgraded";
 763   if (sta > cap)
 764     return "strange";
 765   return "ok";
 766 }
 767
 768 static char *aspm_support(int code)
 769 {
 770   switch (code)
 771     {
 772       case 0:
 773         return "not supported";
 774       case 1:
 775         return "L0s";
 776       case 2:
 777         return "L1";
 778       case 3:
 779         return "L0s L1";
 780       default:
 781         return "unknown";
 782     }
 783 }
 784
 785 static const char *aspm_enabled(int code)
 786 {
 787   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 788   return desc[code];
 789 }
 790
 791 static void cap_express_link(struct device *d, int where, int type)
 792 {
 793   u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
 794   u16 w;
 795
 796   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 797   aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
 798   cap_speed = t & PCI_EXP_LNKCAP_SPEED;
 799   cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
 800   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
 801         t >> 24,
 802         link_speed(cap_speed), cap_width,
 803         aspm_support(aspm));
 804   if (aspm)
 805     {
 806       printf(", Exit Latency ");
 807       if (aspm & 1)
 808         printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
 809       if (aspm & 2)
 810         printf("%sL1 %s", (aspm & 1) ? ", " : "",
 811             latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 812     }
 813   printf("\n");
 814   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
 815         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 816         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 817         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 818         FLAG(t, PCI_EXP_LNKCAP_LBNC),
 819         FLAG(t, PCI_EXP_LNKCAP_AOC));
 820
 821   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 822   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 823   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 824       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 825     printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 826   printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 827         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 828         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 829         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 830         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 831         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 832         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 833         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 834
 835   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 836   sta_speed = w & PCI_EXP_LNKSTA_SPEED;
 837   sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
 838   printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
 839         link_speed(sta_speed),
 840         link_compare(sta_speed, cap_speed),
 841         sta_width,
 842         link_compare(sta_width, cap_width));
 843   printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 844         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 845         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 846         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 847         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 848         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 849         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 850 }
 851
 852 static const char *indicator(int code)
 853 {
 854   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 855   return names[code];
 856 }
 857
 858 static void cap_express_slot(struct device *d, int where)
 859 {
 860   u32 t;
 861   u16 w;
 862
 863   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 864   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 865         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 866         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 867         FLAG(t, PCI_EXP_SLTCAP_MRL),
 868         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 869         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 870         FLAG(t, PCI_EXP_SLTCAP_HPC),
 871         FLAG(t, PCI_EXP_SLTCAP_HPS));
 872   printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
 873         (t & PCI_EXP_SLTCAP_PSN) >> 19,
 874         power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
 875         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 876         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 877
 878   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 879   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 880         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 881         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 882         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 883         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 884         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 885         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 886         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 887   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 888         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 889         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 890         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 891         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 892
 893   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 894   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 895         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 896         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 897         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 898         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 899         FLAG(w, PCI_EXP_SLTSTA_PRES),
 900         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 901   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 902         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 903         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 904         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 905 }
 906
 907 static void cap_express_root(struct device *d, int where)
 908 {
 909   u32 w;
 910
 911   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 912   printf("\t\tRootCap: CRSVisible%c\n",
 913         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 914
 915   w = get_conf_word(d, where + PCI_EXP_RTCTL);
 916   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 917         FLAG(w, PCI_EXP_RTCTL_SECEE),
 918         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 919         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 920         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 921         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 922
 923   w = get_conf_long(d, where + PCI_EXP_RTSTA);
 924   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 925         w & PCI_EXP_RTSTA_PME_REQID,
 926         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 927         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 928 }
 929
 930 static const char *cap_express_dev2_timeout_range(int type)
 931 {
 932   /* Decode Completion Timeout Ranges. */
 933   switch (type)
 934     {
 935       case 0:
 936         return "Not Supported";
 937       case 1:
 938         return "Range A";
 939       case 2:
 940         return "Range B";
 941       case 3:
 942         return "Range AB";
 943       case 6:
 944         return "Range BC";
 945       case 7:
 946         return "Range ABC";
 947       case 14:
 948         return "Range BCD";
 949       case 15:
 950         return "Range ABCD";
 951       default:
 952         return "Unknown";
 953     }
 954 }
 955
 956 static const char *cap_express_dev2_timeout_value(int type)
 957 {
 958   /* Decode Completion Timeout Value. */
 959   switch (type)
 960     {
 961       case 0:
 962         return "50us to 50ms";
 963       case 1:
 964         return "50us to 100us";
 965       case 2:
 966         return "1ms to 10ms";
 967       case 5:
 968         return "16ms to 55ms";
 969       case 6:
 970         return "65ms to 210ms";
 971       case 9:
 972         return "260ms to 900ms";
 973       case 10:
 974         return "1s to 3.5s";
 975       case 13:
 976         return "4s to 13s";
 977       case 14:
 978         return "17s to 64s";
 979       default:
 980         return "Unknown";
 981     }
 982 }
 983
 984 static const char *cap_express_devcap2_obff(int obff)
 985 {
 986   switch (obff)
 987     {
 988       case 1:
 989         return "Via message";
 990       case 2:
 991         return "Via WAKE#";
 992       case 3:
 993         return "Via message/WAKE#";
 994       default:
 995         return "Not Supported";
 996     }
 997 }
 998
 999 static const char *cap_express_devcap2_epr(int epr)
1000 {
1001   switch (epr)
1002     {
1003       case 1:
1004         return "Dev Specific";
1005       case 2:
1006         return "Form Factor Dev Specific";
1007       case 3:
1008         return "Reserved";
1009       default:
1010         return "Not Supported";
1011     }
1012 }
1013
1014 static const char *cap_express_devcap2_lncls(int lncls)
1015 {
1016   switch (lncls)
1017     {
1018       case 1:
1019         return "64byte cachelines";
1020       case 2:
1021         return "128byte cachelines";
1022       case 3:
1023         return "Reserved";
1024       default:
1025         return "Not Supported";
1026     }
1027 }
1028
1029 static const char *cap_express_devcap2_tphcomp(int tph)
1030 {
1031   switch (tph)
1032     {
1033       case 1:
1034         return "TPHComp+ ExtTPHComp-";
1035       case 2:
1036         /* Reserved; intentionally left blank */
1037         return "";
1038       case 3:
1039         return "TPHComp+ ExtTPHComp+";
1040       default:
1041         return "TPHComp- ExtTPHComp-";
1042     }
1043 }
1044
1045 static const char *cap_express_devctl2_obff(int obff)
1046 {
1047   switch (obff)
1048     {
1049       case 0:
1050         return "Disabled";
1051       case 1:
1052         return "Via message A";
1053       case 2:
1054         return "Via message B";
1055       case 3:
1056         return "Via WAKE#";
1057       default:
1058         return "Unknown";
1059     }
1060 }
1061
1062 static int
1063 device_has_memory_space_bar(struct device *d)
1064 {
1065   struct pci_dev *p = d->dev;
1066   int i, found = 0;
1067
1068   for (i=0; i<6; i++)
1069     if (p->base_addr[i] && p->size[i])
1070       {
1071         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1072           {
1073             found = 1;
1074             break;
1075           }
1076       }
1077   return found;
1078 }
1079
1080 static void cap_express_dev2(struct device *d, int where, int type)
1081 {
1082   u32 l;
1083   u16 w;
1084   int has_mem_bar = device_has_memory_space_bar(d);
1085
1086   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1087   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1088         cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1089         FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
1090         FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1091         FLAG(l, PCI_EXP_DEVCAP2_LTR));
1092   printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1093         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1094         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1095         cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1096         FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1097         FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1098
1099   if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1100     {
1101       printf(", MaxEETLPPrefixes %d",
1102              PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1103     }
1104
1105   printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1106         cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1107         FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1108   printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1109
1110   if (type == PCI_EXP_TYPE_ROOT_PORT)
1111     printf(" LN System CLS %s,",
1112           cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1113
1114   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1115     printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1116
1117   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1118     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
1119   else
1120     printf("\n");
1121   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1122       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1123     {
1124        printf("\t\t\t AtomicOpsCap:");
1125        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1126            type == PCI_EXP_TYPE_DOWNSTREAM)
1127          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1128        if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1129          printf(" 32bit%c 64bit%c 128bitCAS%c",
1130                 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1131                 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1132                 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1133        printf("\n");
1134     }
1135
1136   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1137   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,",
1138         cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
1139         FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
1140         FLAG(w, PCI_EXP_DEVCTL2_LTR),
1141         FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
1142         cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
1143   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1144     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
1145   else
1146     printf("\n");
1147   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1148       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1149       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1150     {
1151       printf("\t\t\t AtomicOpsCtl:");
1152       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1153           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1154         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
1155       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1156           type == PCI_EXP_TYPE_DOWNSTREAM)
1157         printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
1158       printf("\n");
1159     }
1160 }
1161
1162 static const char *cap_express_link2_speed_cap(int vector)
1163 {
1164   /*
1165    * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1166    * permitted to skip support for any data rates between 2.5GT/s and the
1167    * highest supported rate.
1168    */
1169   if (vector & 0x60)
1170     return "RsvdP";
1171   if (vector & 0x10)
1172     return "2.5-32GT/s";
1173   if (vector & 0x08)
1174     return "2.5-16GT/s";
1175   if (vector & 0x04)
1176     return "2.5-8GT/s";
1177   if (vector & 0x02)
1178     return "2.5-5GT/s";
1179   if (vector & 0x01)
1180     return "2.5GT/s";
1181
1182   return "Unknown";
1183 }
1184
1185 static const char *cap_express_link2_speed(int type)
1186 {
1187   switch (type)
1188     {
1189       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1190       case 1:
1191         return "2.5GT/s";
1192       case 2:
1193         return "5GT/s";
1194       case 3:
1195         return "8GT/s";
1196       case 4:
1197         return "16GT/s";
1198       case 5:
1199         return "32GT/s";
1200       default:
1201         return "Unknown";
1202     }
1203 }
1204
1205 static const char *cap_express_link2_deemphasis(int type)
1206 {
1207   switch (type)
1208     {
1209       case 0:
1210         return "-6dB";
1211       case 1:
1212         return "-3.5dB";
1213       default:
1214         return "Unknown";
1215     }
1216 }
1217
1218 static const char *cap_express_link2_transmargin(int type)
1219 {
1220   switch (type)
1221     {
1222       case 0:
1223         return "Normal Operating Range";
1224       case 1:
1225         return "800-1200mV(full-swing)/400-700mV(half-swing)";
1226       case 2:
1227       case 3:
1228       case 4:
1229       case 5:
1230         return "200-400mV(full-swing)/100-200mV(half-swing)";
1231       default:
1232         return "Unknown";
1233     }
1234 }
1235
1236 static const char *cap_express_link2_crosslink_res(int crosslink)
1237 {
1238   switch (crosslink)
1239     {
1240       case 0:
1241         return "unsupported";
1242       case 1:
1243         return "Upstream Port";
1244       case 2:
1245         return "Downstream Port";
1246       default:
1247         return "incomplete";
1248     }
1249 }
1250
1251 static const char *cap_express_link2_component(int presence)
1252 {
1253   switch (presence)
1254     {
1255       case 0:
1256         return "Link Down - Not Determined";
1257       case 1:
1258         return "Link Down - Not Present";
1259       case 2:
1260         return "Link Down - Present";
1261       case 4:
1262         return "Link Up - Present";
1263       case 5:
1264         return "Link Up - Present and DRS Received";
1265       default:
1266         return "Reserved";
1267     }
1268 }
1269
1270 static void cap_express_link2(struct device *d, int where, int type)
1271 {
1272   u32 l = 0;
1273   u16 w;
1274
1275   if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1276         (d->dev->dev != 0 || d->dev->func != 0))) {
1277     /* Link Capabilities 2 was reserved before PCIe r3.0 */
1278     l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1279     if (l) {
1280       printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1281         "Retimer%c 2Retimers%c DRS%c\n",
1282           cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1283           FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1284           FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1285           FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1286           FLAG(l, PCI_EXP_LNKCAP2_DRS));
1287     }
1288
1289     w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1290     printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1291         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1292         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1293         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1294     if (type == PCI_EXP_TYPE_DOWNSTREAM)
1295       printf(", Selectable De-emphasis: %s",
1296         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1297     printf("\n"
1298         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1299         "\t\t\t Compliance De-emphasis: %s\n",
1300         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1301         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1302         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1303         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1304   }
1305
1306   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1307   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1308         "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1309         "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
1310         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1311         FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1312         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1313         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1314         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1315         FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1316         FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1317         FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1318         cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
1319
1320   if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1321     printf(", DRS%c\n"
1322         "\t\t\t DownstreamComp: %s\n",
1323         FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1324         cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1325   } else
1326     printf("\n");
1327 }
1328
1329 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1330 {
1331   /* No capabilities that require this field in PCIe rev2.0 spec. */
1332 }
1333
1334 static int
1335 cap_express(struct device *d, int where, int cap)
1336 {
1337   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1338   int size;
1339   int slot = 0;
1340   int link = 1;
1341
1342   printf("Express ");
1343   if (verbose >= 2)
1344     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1345   switch (type)
1346     {
1347     case PCI_EXP_TYPE_ENDPOINT:
1348       printf("Endpoint");
1349       break;
1350     case PCI_EXP_TYPE_LEG_END:
1351       printf("Legacy Endpoint");
1352       break;
1353     case PCI_EXP_TYPE_ROOT_PORT:
1354       slot = cap & PCI_EXP_FLAGS_SLOT;
1355       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1356       break;
1357     case PCI_EXP_TYPE_UPSTREAM:
1358       printf("Upstream Port");
1359       break;
1360     case PCI_EXP_TYPE_DOWNSTREAM:
1361       slot = cap & PCI_EXP_FLAGS_SLOT;
1362       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1363       break;
1364     case PCI_EXP_TYPE_PCI_BRIDGE:
1365       printf("PCI-Express to PCI/PCI-X Bridge");
1366       break;
1367     case PCI_EXP_TYPE_PCIE_BRIDGE:
1368       slot = cap & PCI_EXP_FLAGS_SLOT;
1369       printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1370              FLAG(cap, PCI_EXP_FLAGS_SLOT));
1371       break;
1372     case PCI_EXP_TYPE_ROOT_INT_EP:
1373       link = 0;
1374       printf("Root Complex Integrated Endpoint");
1375       break;
1376     case PCI_EXP_TYPE_ROOT_EC:
1377       link = 0;
1378       printf("Root Complex Event Collector");
1379       break;
1380     default:
1381       printf("Unknown type %d", type);
1382   }
1383   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1384   if (verbose < 2)
1385     return type;
1386
1387   size = 16;
1388   if (slot)
1389     size = 24;
1390   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1391     size = 32;
1392   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1393     return type;
1394
1395   cap_express_dev(d, where, type);
1396   if (link)
1397     cap_express_link(d, where, type);
1398   if (slot)
1399     cap_express_slot(d, where);
1400   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1401     cap_express_root(d, where);
1402
1403   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1404     return type;
1405
1406   size = 16;
1407   if (slot)
1408     size = 24;
1409   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1410     return type;
1411
1412   cap_express_dev2(d, where, type);
1413   if (link)
1414     cap_express_link2(d, where, type);
1415   if (slot)
1416     cap_express_slot2(d, where);
1417   return type;
1418 }
1419
1420 static void
1421 cap_msix(struct device *d, int where, int cap)
1422 {
1423   u32 off;
1424
1425   printf("MSI-X: Enable%c Count=%d Masked%c\n",
1426          FLAG(cap, PCI_MSIX_ENABLE),
1427          (cap & PCI_MSIX_TABSIZE) + 1,
1428          FLAG(cap, PCI_MSIX_MASK));
1429   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1430     return;
1431
1432   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1433   printf("\t\tVector table: BAR=%d offset=%08x\n",
1434          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1435   off = get_conf_long(d, where + PCI_MSIX_PBA);
1436   printf("\t\tPBA: BAR=%d offset=%08x\n",
1437          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1438 }
1439
1440 static void
1441 cap_slotid(int cap)
1442 {
1443   int esr = cap & 0xff;
1444   int chs = cap >> 8;
1445
1446   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1447          esr & PCI_SID_ESR_NSLOTS,
1448          FLAG(esr, PCI_SID_ESR_FIC),
1449          chs);
1450 }
1451
1452 static void
1453 cap_ssvid(struct device *d, int where)
1454 {
1455   u16 subsys_v, subsys_d;
1456   char ssnamebuf[256];
1457
1458   if (!config_fetch(d, where, 8))
1459     return;
1460   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1461   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1462   printf("Subsystem: %s\n",
1463            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1464                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1465                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1466 }
1467
1468 static void
1469 cap_debug_port(int cap)
1470 {
1471   int bar = cap >> 13;
1472   int pos = cap & 0x1fff;
1473   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1474 }
1475
1476 static void
1477 cap_af(struct device *d, int where)
1478 {
1479   u8 reg;
1480
1481   printf("PCI Advanced Features\n");
1482   if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1483     return;
1484
1485   reg = get_conf_byte(d, where + PCI_AF_CAP);
1486   printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1487          FLAG(reg, PCI_AF_CAP_FLR));
1488   reg = get_conf_byte(d, where + PCI_AF_CTRL);
1489   printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1490   reg = get_conf_byte(d, where + PCI_AF_STATUS);
1491   printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1492 }
1493
1494 static void
1495 cap_sata_hba(struct device *d, int where, int cap)
1496 {
1497   u32 bars;
1498   int bar;
1499
1500   printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1501   if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1502     {
1503       printf("\n");
1504       return;
1505     }
1506
1507   bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1508   bar = BITS(bars, 0, 4);
1509   if (bar >= 4 && bar <= 9)
1510     printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1511   else if (bar == 15)
1512     printf(" InCfgSpace\n");
1513   else
1514     printf(" BAR??%d\n", bar);
1515 }
1516
1517 static const char *cap_ea_property(int p, int is_secondary)
1518 {
1519   switch (p) {
1520   case 0x00:
1521     return "memory space, non-prefetchable";
1522   case 0x01:
1523     return "memory space, prefetchable";
1524   case 0x02:
1525     return "I/O space";
1526   case 0x03:
1527     return "VF memory space, prefetchable";
1528   case 0x04:
1529     return "VF memory space, non-prefetchable";
1530   case 0x05:
1531     return "allocation behind bridge, non-prefetchable memory";
1532   case 0x06:
1533     return "allocation behind bridge, prefetchable memory";
1534   case 0x07:
1535     return "allocation behind bridge, I/O space";
1536   case 0xfd:
1537     return "memory space resource unavailable for use";
1538   case 0xfe:
1539     return "I/O space resource unavailable for use";
1540   case 0xff:
1541     if (is_secondary)
1542       return "entry unavailable for use, PrimaryProperties should be used";
1543     else
1544       return "entry unavailable for use";
1545   default:
1546     return NULL;
1547   }
1548 }
1549
1550 static void cap_ea(struct device *d, int where, int cap)
1551 {
1552   int entry;
1553   int entry_base = where + 4;
1554   int num_entries = BITS(cap, 0, 6);
1555   u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1556
1557   printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1558   if (htype == PCI_HEADER_TYPE_BRIDGE) {
1559     byte fixed_sub, fixed_sec;
1560
1561     entry_base += 4;
1562     if (!config_fetch(d, where + 4, 2)) {
1563       printf("\n");
1564       return;
1565     }
1566     fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1567     fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1568     printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1569   }
1570   printf("\n");
1571   if (verbose < 2)
1572     return;
1573
1574   for (entry = 0; entry < num_entries; entry++) {
1575     int max_offset_high_pos, has_base_high, has_max_offset_high;
1576     u32 entry_header;
1577     u32 base, max_offset;
1578     int es, bei, pp, sp;
1579     const char *prop_text;
1580
1581     if (!config_fetch(d, entry_base, 4))
1582       return;
1583     entry_header = get_conf_long(d, entry_base);
1584     es = BITS(entry_header, 0, 3);
1585     bei = BITS(entry_header, 4, 4);
1586     pp = BITS(entry_header, 8, 8);
1587     sp = BITS(entry_header, 16, 8);
1588     if (!config_fetch(d, entry_base + 4, es * 4))
1589       return;
1590     printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1591            FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1592            FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1593     printf("\t\t\t BAR Equivalent Indicator: ");
1594     switch (bei) {
1595     case 0:
1596     case 1:
1597     case 2:
1598     case 3:
1599     case 4:
1600     case 5:
1601       printf("BAR %u", bei);
1602       break;
1603     case 6:
1604       printf("resource behind function");
1605       break;
1606     case 7:
1607       printf("not indicated");
1608       break;
1609     case 8:
1610       printf("expansion ROM");
1611       break;
1612     case 9:
1613     case 10:
1614     case 11:
1615     case 12:
1616     case 13:
1617     case 14:
1618       printf("VF-BAR %u", bei - 9);
1619       break;
1620     default:
1621       printf("reserved");
1622       break;
1623     }
1624     printf("\n");
1625
1626     prop_text = cap_ea_property(pp, 0);
1627     printf("\t\t\t PrimaryProperties: ");
1628     if (prop_text)
1629       printf("%s\n", prop_text);
1630     else
1631       printf("[%02x]\n", pp);
1632
1633     prop_text = cap_ea_property(sp, 1);
1634     printf("\t\t\t SecondaryProperties: ");
1635     if (prop_text)
1636       printf("%s\n", prop_text);
1637     else
1638       printf("[%02x]\n", sp);
1639
1640     base = get_conf_long(d, entry_base + 4);
1641     has_base_high = ((base & 2) != 0);
1642     base &= ~3;
1643
1644     max_offset = get_conf_long(d, entry_base + 8);
1645     has_max_offset_high = ((max_offset & 2) != 0);
1646     max_offset |= 3;
1647     max_offset_high_pos = entry_base + 12;
1648
1649     printf("\t\t\t Base: ");
1650     if (has_base_high) {
1651       u32 base_high = get_conf_long(d, entry_base + 12);
1652
1653       printf("%x", base_high);
1654       max_offset_high_pos += 4;
1655     }
1656     printf("%08x\n", base);
1657
1658     printf("\t\t\t MaxOffset: ");
1659     if (has_max_offset_high) {
1660       u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1661
1662       printf("%x", max_offset_high);
1663     }
1664     printf("%08x\n", max_offset);
1665
1666     entry_base += 4 + 4 * es;
1667   }
1668 }
1669
1670 void
1671 show_caps(struct device *d, int where)
1672 {
1673   int can_have_ext_caps = 0;
1674   int type = -1;
1675
1676   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1677     {
1678       byte been_there[256];
1679       where = get_conf_byte(d, where) & ~3;
1680       memset(been_there, 0, 256);
1681       while (where)
1682         {
1683           int id, next, cap;
1684           printf("\tCapabilities: ");
1685           if (!config_fetch(d, where, 4))
1686             {
1687               puts("<access denied>");
1688               break;
1689             }
1690           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1691           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1692           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1693           printf("[%02x] ", where);
1694           if (been_there[where]++)
1695             {
1696               printf("<chain looped>\n");
1697               break;
1698             }
1699           if (id == 0xff)
1700             {
1701               printf("<chain broken>\n");
1702               break;
1703             }
1704           switch (id)
1705             {
1706             case PCI_CAP_ID_NULL:
1707               printf("Null\n");
1708               break;
1709             case PCI_CAP_ID_PM:
1710               cap_pm(d, where, cap);
1711               break;
1712             case PCI_CAP_ID_AGP:
1713               cap_agp(d, where, cap);
1714               break;
1715             case PCI_CAP_ID_VPD:
1716               cap_vpd(d);
1717               break;
1718             case PCI_CAP_ID_SLOTID:
1719               cap_slotid(cap);
1720               break;
1721             case PCI_CAP_ID_MSI:
1722               cap_msi(d, where, cap);
1723               break;
1724             case PCI_CAP_ID_CHSWP:
1725               printf("CompactPCI hot-swap <?>\n");
1726               break;
1727             case PCI_CAP_ID_PCIX:
1728               cap_pcix(d, where);
1729               can_have_ext_caps = 1;
1730               break;
1731             case PCI_CAP_ID_HT:
1732               cap_ht(d, where, cap);
1733               break;
1734             case PCI_CAP_ID_VNDR:
1735               show_vendor_caps(d, where, cap);
1736               break;
1737             case PCI_CAP_ID_DBG:
1738               cap_debug_port(cap);
1739               break;
1740             case PCI_CAP_ID_CCRC:
1741               printf("CompactPCI central resource control <?>\n");
1742               break;
1743             case PCI_CAP_ID_HOTPLUG:
1744               printf("Hot-plug capable\n");
1745               break;
1746             case PCI_CAP_ID_SSVID:
1747               cap_ssvid(d, where);
1748               break;
1749             case PCI_CAP_ID_AGP3:
1750               printf("AGP3 <?>\n");
1751               break;
1752             case PCI_CAP_ID_SECURE:
1753               printf("Secure device <?>\n");
1754               break;
1755             case PCI_CAP_ID_EXP:
1756               type = cap_express(d, where, cap);
1757               can_have_ext_caps = 1;
1758               break;
1759             case PCI_CAP_ID_MSIX:
1760               cap_msix(d, where, cap);
1761               break;
1762             case PCI_CAP_ID_SATA:
1763               cap_sata_hba(d, where, cap);
1764               break;
1765             case PCI_CAP_ID_AF:
1766               cap_af(d, where);
1767               break;
1768             case PCI_CAP_ID_EA:
1769               cap_ea(d, where, cap);
1770               break;
1771             default:
1772               printf("Capability ID %#02x [%04x]\n", id, cap);
1773             }
1774           where = next;
1775         }
1776     }
1777   if (can_have_ext_caps)
1778     show_ext_caps(d, type);
1779 }