ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
  40          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  41          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  42          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  43          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  44   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  45   if (b)
  46     printf("\t\tBridge: PM%c B3%c\n",
  47            FLAG(t, PCI_PM_BPCC_ENABLE),
  48            FLAG(~t, PCI_PM_PPB_B2_B3));
  49 }
  50
  51 static void
  52 format_agp_rate(int rate, char *buf, int agp3)
  53 {
  54   char *c = buf;
  55   int i;
  56
  57   for (i=0; i<=2; i++)
  58     if (rate & (1 << i))
  59       {
  60         if (c != buf)
  61           *c++ = ',';
  62         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  63       }
  64   if (c != buf)
  65     *c = 0;
  66   else
  67     strcpy(buf, "<none>");
  68 }
  69
  70 static void
  71 cap_agp(struct device *d, int where, int cap)
  72 {
  73   u32 t;
  74   char rate[16];
  75   int ver, rev;
  76   int agp3 = 0;
  77
  78   ver = (cap >> 4) & 0x0f;
  79   rev = cap & 0x0f;
  80   printf("AGP version %x.%x\n", ver, rev);
  81   if (verbose < 2)
  82     return;
  83   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  84     return;
  85   t = get_conf_long(d, where + PCI_AGP_STATUS);
  86   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  87     agp3 = 1;
  88   format_agp_rate(t & 7, rate, agp3);
  89   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  90          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  91          FLAG(t, PCI_AGP_STATUS_ISOCH),
  92          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  93          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  94          FLAG(t, PCI_AGP_STATUS_SBA),
  95          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  96          FLAG(t, PCI_AGP_STATUS_GART64),
  97          FLAG(t, PCI_AGP_STATUS_HTRANS),
  98          FLAG(t, PCI_AGP_STATUS_64BIT),
  99          FLAG(t, PCI_AGP_STATUS_FW),
 100          FLAG(t, PCI_AGP_STATUS_AGP3),
 101          rate);
 102   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 103   format_agp_rate(t & 7, rate, agp3);
 104   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 105          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 106          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 107          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 108          FLAG(t, PCI_AGP_COMMAND_SBA),
 109          FLAG(t, PCI_AGP_COMMAND_AGP),
 110          FLAG(t, PCI_AGP_COMMAND_GART64),
 111          FLAG(t, PCI_AGP_COMMAND_64BIT),
 112          FLAG(t, PCI_AGP_COMMAND_FW),
 113          rate);
 114 }
 115
 116 static void
 117 cap_pcix_nobridge(struct device *d, int where)
 118 {
 119   u16 command;
 120   u32 status;
 121   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 122
 123   printf("PCI-X non-bridge device\n");
 124
 125   if (verbose < 2)
 126     return;
 127
 128   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 129     return;
 130
 131   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 132   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 133   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 134          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 135          FLAG(command, PCI_PCIX_COMMAND_ERO),
 136          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 137          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 138   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 139          (status & PCI_PCIX_STATUS_BUS) >> 8,
 140          (status & PCI_PCIX_STATUS_DEVICE) >> 3,
 141          (status & PCI_PCIX_STATUS_FUNCTION),
 142          FLAG(status, PCI_PCIX_STATUS_64BIT),
 143          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 144          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 145          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 146          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 147          1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
 148          max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
 149          1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
 150          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 151          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 152          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 153 }
 154
 155 static void
 156 cap_pcix_bridge(struct device *d, int where)
 157 {
 158   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 159   u16 secstatus;
 160   u32 status, upstcr, downstcr;
 161
 162   printf("PCI-X bridge device\n");
 163
 164   if (verbose < 2)
 165     return;
 166
 167   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 168     return;
 169
 170   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 171   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 177          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 178          sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
 179   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 180   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 181          (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
 182          (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
 183          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 189          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 190   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 191   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 192          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 193          (upstcr >> 16) & 0xffff);
 194   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 195   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 196          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 197          (downstcr >> 16) & 0xffff);
 198 }
 199
 200 static void
 201 cap_pcix(struct device *d, int where)
 202 {
 203   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 204     {
 205     case PCI_HEADER_TYPE_NORMAL:
 206       cap_pcix_nobridge(d, where);
 207       break;
 208     case PCI_HEADER_TYPE_BRIDGE:
 209       cap_pcix_bridge(d, where);
 210       break;
 211     }
 212 }
 213
 214 static inline char *
 215 ht_link_width(unsigned width)
 216 {
 217   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 218   return widths[width];
 219 }
 220
 221 static inline char *
 222 ht_link_freq(unsigned freq)
 223 {
 224   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 225                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 226   return freqs[freq];
 227 }
 228
 229 static void
 230 cap_ht_pri(struct device *d, int where, int cmd)
 231 {
 232   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 233   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 234
 235   printf("HyperTransport: Slave or Primary Interface\n");
 236   if (verbose < 2)
 237     return;
 238
 239   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 240     return;
 241   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 242   if (rid < 0x22 && rid > 0x11)
 243     printf("\t\t!!! Possibly incomplete decoding\n");
 244
 245   printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
 246          (cmd & PCI_HT_PRI_CMD_BUID),
 247          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 248          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 249          FLAG(cmd, PCI_HT_PRI_CMD_DD));
 250   if (rid >= 0x22)
 251     printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 252   printf("\n");
 253
 254   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 255   printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 256          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 257          FLAG(lctr0, PCI_HT_LCTR_CST),
 258          FLAG(lctr0, PCI_HT_LCTR_CFE),
 259          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 260          FLAG(lctr0, PCI_HT_LCTR_INIT),
 261          FLAG(lctr0, PCI_HT_LCTR_EOC),
 262          FLAG(lctr0, PCI_HT_LCTR_TXO),
 263          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
 264   if (rid >= 0x22)
 265     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 266            FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 267            FLAG(lctr0, PCI_HT_LCTR_LSEN),
 268            FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 269            FLAG(lctr0, PCI_HT_LCTR_64B));
 270   printf("\n");
 271
 272   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 273   if (rid < 0x22)
 274     printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 275            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 276            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 277            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 278            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
 279   else
 280     printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 281            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 282            FLAG(lcnf0, PCI_HT_LCNF_DFI),
 283            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 284            FLAG(lcnf0, PCI_HT_LCNF_DFO),
 285            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 286            FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 287            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 288            FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 289
 290   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 291   printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 292          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 293          FLAG(lctr1, PCI_HT_LCTR_CST),
 294          FLAG(lctr1, PCI_HT_LCTR_CFE),
 295          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 296          FLAG(lctr1, PCI_HT_LCTR_INIT),
 297          FLAG(lctr1, PCI_HT_LCTR_EOC),
 298          FLAG(lctr1, PCI_HT_LCTR_TXO),
 299          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
 300   if (rid >= 0x22)
 301     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 302          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 303          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 304          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 305          FLAG(lctr1, PCI_HT_LCTR_64B));
 306   printf("\n");
 307
 308   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 309   if (rid < 0x22)
 310     printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 311            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 312            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 313            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 314            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
 315   else
 316     printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 317            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 318            FLAG(lcnf1, PCI_HT_LCNF_DFI),
 319            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 320            FLAG(lcnf1, PCI_HT_LCNF_DFO),
 321            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 322            FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 323            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 324            FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 325
 326   printf("\t\tRevision ID: %u.%02u\n",
 327          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 328   if (rid < 0x22)
 329     return;
 330
 331   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 332   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 333   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 334          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 335          FLAG(lfrer0, PCI_HT_LFRER_OV),
 336          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 337          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 338
 339   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 340   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 341          FLAG(lfcap0, PCI_HT_LFCAP_200),
 342          FLAG(lfcap0, PCI_HT_LFCAP_300),
 343          FLAG(lfcap0, PCI_HT_LFCAP_400),
 344          FLAG(lfcap0, PCI_HT_LFCAP_500),
 345          FLAG(lfcap0, PCI_HT_LFCAP_600),
 346          FLAG(lfcap0, PCI_HT_LFCAP_800),
 347          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 348          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 349          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 350          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 351          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 352
 353   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 354   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 355          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 356          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 357          FLAG(ftr, PCI_HT_FTR_CRCTM),
 358          FLAG(ftr, PCI_HT_FTR_ECTLT),
 359          FLAG(ftr, PCI_HT_FTR_64BA),
 360          FLAG(ftr, PCI_HT_FTR_UIDRD));
 361
 362   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 363   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 364   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 365          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 366          FLAG(lfrer1, PCI_HT_LFRER_OV),
 367          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 368          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 369
 370   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 371   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 372          FLAG(lfcap1, PCI_HT_LFCAP_200),
 373          FLAG(lfcap1, PCI_HT_LFCAP_300),
 374          FLAG(lfcap1, PCI_HT_LFCAP_400),
 375          FLAG(lfcap1, PCI_HT_LFCAP_500),
 376          FLAG(lfcap1, PCI_HT_LFCAP_600),
 377          FLAG(lfcap1, PCI_HT_LFCAP_800),
 378          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 379          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 380          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 381          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 382          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 383
 384   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 385   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 386          FLAG(eh, PCI_HT_EH_PFLE),
 387          FLAG(eh, PCI_HT_EH_OFLE),
 388          FLAG(eh, PCI_HT_EH_PFE),
 389          FLAG(eh, PCI_HT_EH_OFE),
 390          FLAG(eh, PCI_HT_EH_EOCFE),
 391          FLAG(eh, PCI_HT_EH_RFE),
 392          FLAG(eh, PCI_HT_EH_CRCFE),
 393          FLAG(eh, PCI_HT_EH_SERRFE),
 394          FLAG(eh, PCI_HT_EH_CF),
 395          FLAG(eh, PCI_HT_EH_RE),
 396          FLAG(eh, PCI_HT_EH_PNFE),
 397          FLAG(eh, PCI_HT_EH_ONFE),
 398          FLAG(eh, PCI_HT_EH_EOCNFE),
 399          FLAG(eh, PCI_HT_EH_RNFE),
 400          FLAG(eh, PCI_HT_EH_CRCNFE),
 401          FLAG(eh, PCI_HT_EH_SERRNFE));
 402
 403   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 404   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 405   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 406
 407   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 408   printf("\t\tBus Number: %02x\n", bn);
 409 }
 410
 411 static void
 412 cap_ht_sec(struct device *d, int where, int cmd)
 413 {
 414   u16 lctr, lcnf, ftr, eh;
 415   u8 rid, lfrer, lfcap, mbu, mlu;
 416   char *fmt;
 417
 418   printf("HyperTransport: Host or Secondary Interface\n");
 419   if (verbose < 2)
 420     return;
 421
 422   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 423     return;
 424   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 425   if (rid < 0x22 && rid > 0x11)
 426     printf("\t\t!!! Possibly incomplete decoding\n");
 427
 428   if (rid >= 0x22)
 429     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 430   else
 431     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 432   printf(fmt,
 433          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 434          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 435          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 436          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 437          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 438          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 439          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 440          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 441   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 442   if (rid >= 0x22)
 443     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 444   else
 445     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 446   printf(fmt,
 447          FLAG(lctr, PCI_HT_LCTR_CFLE),
 448          FLAG(lctr, PCI_HT_LCTR_CST),
 449          FLAG(lctr, PCI_HT_LCTR_CFE),
 450          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 451          FLAG(lctr, PCI_HT_LCTR_INIT),
 452          FLAG(lctr, PCI_HT_LCTR_EOC),
 453          FLAG(lctr, PCI_HT_LCTR_TXO),
 454          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 455          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 456          FLAG(lctr, PCI_HT_LCTR_LSEN),
 457          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 458          FLAG(lctr, PCI_HT_LCTR_64B));
 459   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 460   if (rid >= 0x22)
 461     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 462   else
 463     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 464   printf(fmt,
 465          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 466          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 467          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 468          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 469          FLAG(lcnf, PCI_HT_LCNF_DFI),
 470          FLAG(lcnf, PCI_HT_LCNF_DFO),
 471          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 472          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 473   printf("\t\tRevision ID: %u.%02u\n",
 474          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 475   if (rid < 0x22)
 476     return;
 477   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 478   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 479   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 480          FLAG(lfrer, PCI_HT_LFRER_PROT),
 481          FLAG(lfrer, PCI_HT_LFRER_OV),
 482          FLAG(lfrer, PCI_HT_LFRER_EOC),
 483          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 484   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 485   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 486          FLAG(lfcap, PCI_HT_LFCAP_200),
 487          FLAG(lfcap, PCI_HT_LFCAP_300),
 488          FLAG(lfcap, PCI_HT_LFCAP_400),
 489          FLAG(lfcap, PCI_HT_LFCAP_500),
 490          FLAG(lfcap, PCI_HT_LFCAP_600),
 491          FLAG(lfcap, PCI_HT_LFCAP_800),
 492          FLAG(lfcap, PCI_HT_LFCAP_1000),
 493          FLAG(lfcap, PCI_HT_LFCAP_1200),
 494          FLAG(lfcap, PCI_HT_LFCAP_1400),
 495          FLAG(lfcap, PCI_HT_LFCAP_1600),
 496          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 497   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 498   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 499          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 500          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 501          FLAG(ftr, PCI_HT_FTR_CRCTM),
 502          FLAG(ftr, PCI_HT_FTR_ECTLT),
 503          FLAG(ftr, PCI_HT_FTR_64BA),
 504          FLAG(ftr, PCI_HT_FTR_UIDRD),
 505          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 506          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 507   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 508     {
 509       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 510       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 511              FLAG(eh, PCI_HT_EH_PFLE),
 512              FLAG(eh, PCI_HT_EH_OFLE),
 513              FLAG(eh, PCI_HT_EH_PFE),
 514              FLAG(eh, PCI_HT_EH_OFE),
 515              FLAG(eh, PCI_HT_EH_EOCFE),
 516              FLAG(eh, PCI_HT_EH_RFE),
 517              FLAG(eh, PCI_HT_EH_CRCFE),
 518              FLAG(eh, PCI_HT_EH_SERRFE),
 519              FLAG(eh, PCI_HT_EH_CF),
 520              FLAG(eh, PCI_HT_EH_RE),
 521              FLAG(eh, PCI_HT_EH_PNFE),
 522              FLAG(eh, PCI_HT_EH_ONFE),
 523              FLAG(eh, PCI_HT_EH_EOCNFE),
 524              FLAG(eh, PCI_HT_EH_RNFE),
 525              FLAG(eh, PCI_HT_EH_CRCNFE),
 526              FLAG(eh, PCI_HT_EH_SERRNFE));
 527       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 528       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 529       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 530     }
 531 }
 532
 533 static void
 534 cap_ht(struct device *d, int where, int cmd)
 535 {
 536   int type;
 537
 538   switch (cmd & PCI_HT_CMD_TYP_HI)
 539     {
 540     case PCI_HT_CMD_TYP_HI_PRI:
 541       cap_ht_pri(d, where, cmd);
 542       return;
 543     case PCI_HT_CMD_TYP_HI_SEC:
 544       cap_ht_sec(d, where, cmd);
 545       return;
 546     }
 547
 548   type = cmd & PCI_HT_CMD_TYP;
 549   switch (type)
 550     {
 551     case PCI_HT_CMD_TYP_SW:
 552       printf("HyperTransport: Switch\n");
 553       break;
 554     case PCI_HT_CMD_TYP_IDC:
 555       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 556       break;
 557     case PCI_HT_CMD_TYP_RID:
 558       printf("HyperTransport: Revision ID: %u.%02u\n",
 559              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 560       break;
 561     case PCI_HT_CMD_TYP_UIDC:
 562       printf("HyperTransport: UnitID Clumping\n");
 563       break;
 564     case PCI_HT_CMD_TYP_ECSA:
 565       printf("HyperTransport: Extended Configuration Space Access\n");
 566       break;
 567     case PCI_HT_CMD_TYP_AM:
 568       printf("HyperTransport: Address Mapping\n");
 569       break;
 570     case PCI_HT_CMD_TYP_MSIM:
 571       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 572              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 573              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 574       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 575         {
 576           u32 offl, offh;
 577           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 578             break;
 579           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 580           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 581           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 582         }
 583       break;
 584     case PCI_HT_CMD_TYP_DR:
 585       printf("HyperTransport: DirectRoute\n");
 586       break;
 587     case PCI_HT_CMD_TYP_VCS:
 588       printf("HyperTransport: VCSet\n");
 589       break;
 590     case PCI_HT_CMD_TYP_RM:
 591       printf("HyperTransport: Retry Mode\n");
 592       break;
 593     case PCI_HT_CMD_TYP_X86:
 594       printf("HyperTransport: X86 (reserved)\n");
 595       break;
 596     default:
 597       printf("HyperTransport: #%02x\n", type >> 11);
 598     }
 599 }
 600
 601 static void
 602 cap_msi(struct device *d, int where, int cap)
 603 {
 604   int is64;
 605   u32 t;
 606   u16 w;
 607
 608   printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
 609          FLAG(cap, PCI_MSI_FLAGS_ENABLE),
 610          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 611          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 612          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 613          FLAG(cap, PCI_MSI_FLAGS_64BIT));
 614   if (verbose < 2)
 615     return;
 616   is64 = cap & PCI_MSI_FLAGS_64BIT;
 617   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 618     return;
 619   printf("\t\tAddress: ");
 620   if (is64)
 621     {
 622       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 623       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 624       printf("%08x", t);
 625     }
 626   else
 627     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 628   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 629   printf("%08x  Data: %04x\n", t, w);
 630   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 631     {
 632       u32 mask, pending;
 633
 634       if (is64)
 635         {
 636           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 637             return;
 638           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 639           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 640         }
 641       else
 642         {
 643           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 644             return;
 645           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 646           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 647         }
 648       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 649     }
 650 }
 651
 652 static int exp_downstream_port(int type)
 653 {
 654   return type == PCI_EXP_TYPE_ROOT_PORT ||
 655          type == PCI_EXP_TYPE_DOWNSTREAM ||
 656          type == PCI_EXP_TYPE_PCIE_BRIDGE;      /* PCI/PCI-X to PCIe Bridge */
 657 }
 658
 659 static void show_power_limit(int value, int scale)
 660 {
 661   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 662   static const int scale0_values[3] = { 250, 275, 300 };
 663
 664   if (scale == 0 && value >= 0xF0)
 665     {
 666       /* F3h to FFh = Reserved for Slot Power Limit values above 300 W */
 667       if (value >= 0xF3)
 668         {
 669           printf(">300W");
 670           return;
 671         }
 672       value = scale0_values[value - 0xF0];
 673     }
 674   printf("%gW", value * scales[scale]);
 675 }
 676
 677 static const char *latency_l0s(int value)
 678 {
 679   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 680   return latencies[value];
 681 }
 682
 683 static const char *latency_l1(int value)
 684 {
 685   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 686   return latencies[value];
 687 }
 688
 689 static void cap_express_dev(struct device *d, int where, int type)
 690 {
 691   u32 t;
 692   u16 w;
 693
 694   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 695   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 696         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 697         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
 698   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 699     printf(", Latency L0s %s, L1 %s",
 700         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 701         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 702   printf("\n");
 703   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 704   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 705       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 706     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 707         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 708         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 709   printf(" RBE%c",
 710         FLAG(t, PCI_EXP_DEVCAP_RBE));
 711   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
 712     printf(" FLReset%c",
 713         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 714   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
 715       (type == PCI_EXP_TYPE_PCI_BRIDGE))
 716     {
 717       printf(" SlotPowerLimit ");
 718       show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
 719     }
 720   printf("\n");
 721
 722   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 723   printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
 724         FLAG(w, PCI_EXP_DEVCTL_CERE),
 725         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 726         FLAG(w, PCI_EXP_DEVCTL_FERE),
 727         FLAG(w, PCI_EXP_DEVCTL_URRE));
 728   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 729         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 730         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 731         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 732         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 733         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 734   if (type == PCI_EXP_TYPE_PCI_BRIDGE)
 735     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 736   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
 737       (t & PCI_EXP_DEVCAP_FLRESET))
 738     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 739   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 740         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 741         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 742
 743   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 744   printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
 745         FLAG(w, PCI_EXP_DEVSTA_CED),
 746         FLAG(w, PCI_EXP_DEVSTA_NFED),
 747         FLAG(w, PCI_EXP_DEVSTA_FED),
 748         FLAG(w, PCI_EXP_DEVSTA_URD),
 749         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 750         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 751 }
 752
 753 static char *link_speed(int speed)
 754 {
 755   switch (speed)
 756     {
 757       case 1:
 758         return "2.5GT/s";
 759       case 2:
 760         return "5GT/s";
 761       case 3:
 762         return "8GT/s";
 763       case 4:
 764         return "16GT/s";
 765       case 5:
 766         return "32GT/s";
 767       case 6:
 768         return "64GT/s";
 769       default:
 770         return "unknown";
 771     }
 772 }
 773
 774 static char *link_compare(int sta, int cap)
 775 {
 776   if (sta < cap)
 777     return "downgraded";
 778   if (sta > cap)
 779     return "strange";
 780   return "ok";
 781 }
 782
 783 static char *aspm_support(int code)
 784 {
 785   switch (code)
 786     {
 787       case 0:
 788         return "not supported";
 789       case 1:
 790         return "L0s";
 791       case 2:
 792         return "L1";
 793       case 3:
 794         return "L0s L1";
 795       default:
 796         return "unknown";
 797     }
 798 }
 799
 800 static const char *aspm_enabled(int code)
 801 {
 802   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 803   return desc[code];
 804 }
 805
 806 static void cap_express_link(struct device *d, int where, int type)
 807 {
 808   u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
 809   u16 w;
 810
 811   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 812   aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
 813   cap_speed = t & PCI_EXP_LNKCAP_SPEED;
 814   cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
 815   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
 816         t >> 24,
 817         link_speed(cap_speed), cap_width,
 818         aspm_support(aspm));
 819   if (aspm)
 820     {
 821       printf(", Exit Latency ");
 822       if (aspm & 1)
 823         printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
 824       if (aspm & 2)
 825         printf("%sL1 %s", (aspm & 1) ? ", " : "",
 826             latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 827     }
 828   printf("\n");
 829   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
 830         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 831         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 832         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 833         FLAG(t, PCI_EXP_LNKCAP_LBNC),
 834         FLAG(t, PCI_EXP_LNKCAP_AOC));
 835
 836   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 837   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 838   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 839       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 840     printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 841   printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 842         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 843         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 844         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 845         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 846         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 847         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 848         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 849
 850   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 851   sta_speed = w & PCI_EXP_LNKSTA_SPEED;
 852   sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
 853   printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
 854         link_speed(sta_speed),
 855         link_compare(sta_speed, cap_speed),
 856         sta_width,
 857         link_compare(sta_width, cap_width));
 858   printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 859         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 860         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 861         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 862         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 863         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 864         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 865 }
 866
 867 static const char *indicator(int code)
 868 {
 869   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 870   return names[code];
 871 }
 872
 873 static void cap_express_slot(struct device *d, int where)
 874 {
 875   u32 t;
 876   u16 w;
 877
 878   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 879   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 880         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 881         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 882         FLAG(t, PCI_EXP_SLTCAP_MRL),
 883         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 884         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 885         FLAG(t, PCI_EXP_SLTCAP_HPC),
 886         FLAG(t, PCI_EXP_SLTCAP_HPS));
 887   printf("\t\t\tSlot #%d, PowerLimit ",
 888         (t & PCI_EXP_SLTCAP_PSN) >> 19);
 889   show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
 890   printf("; Interlock%c NoCompl%c\n",
 891         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 892         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 893
 894   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 895   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 896         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 897         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 898         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 899         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 900         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 901         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 902         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 903   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 904         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 905         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 906         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 907         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 908
 909   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 910   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 911         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 912         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 913         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 914         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 915         FLAG(w, PCI_EXP_SLTSTA_PRES),
 916         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 917   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 918         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 919         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 920         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 921 }
 922
 923 static void cap_express_root(struct device *d, int where)
 924 {
 925   u32 w;
 926
 927   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 928   printf("\t\tRootCap: CRSVisible%c\n",
 929         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 930
 931   w = get_conf_word(d, where + PCI_EXP_RTCTL);
 932   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 933         FLAG(w, PCI_EXP_RTCTL_SECEE),
 934         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 935         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 936         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 937         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 938
 939   w = get_conf_long(d, where + PCI_EXP_RTSTA);
 940   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 941         w & PCI_EXP_RTSTA_PME_REQID,
 942         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 943         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 944 }
 945
 946 static const char *cap_express_dev2_timeout_range(int type)
 947 {
 948   /* Decode Completion Timeout Ranges. */
 949   switch (type)
 950     {
 951       case 0:
 952         return "Not Supported";
 953       case 1:
 954         return "Range A";
 955       case 2:
 956         return "Range B";
 957       case 3:
 958         return "Range AB";
 959       case 6:
 960         return "Range BC";
 961       case 7:
 962         return "Range ABC";
 963       case 14:
 964         return "Range BCD";
 965       case 15:
 966         return "Range ABCD";
 967       default:
 968         return "Unknown";
 969     }
 970 }
 971
 972 static const char *cap_express_dev2_timeout_value(int type)
 973 {
 974   /* Decode Completion Timeout Value. */
 975   switch (type)
 976     {
 977       case 0:
 978         return "50us to 50ms";
 979       case 1:
 980         return "50us to 100us";
 981       case 2:
 982         return "1ms to 10ms";
 983       case 5:
 984         return "16ms to 55ms";
 985       case 6:
 986         return "65ms to 210ms";
 987       case 9:
 988         return "260ms to 900ms";
 989       case 10:
 990         return "1s to 3.5s";
 991       case 13:
 992         return "4s to 13s";
 993       case 14:
 994         return "17s to 64s";
 995       default:
 996         return "Unknown";
 997     }
 998 }
 999
1000 static const char *cap_express_devcap2_obff(int obff)
1001 {
1002   switch (obff)
1003     {
1004       case 1:
1005         return "Via message";
1006       case 2:
1007         return "Via WAKE#";
1008       case 3:
1009         return "Via message/WAKE#";
1010       default:
1011         return "Not Supported";
1012     }
1013 }
1014
1015 static const char *cap_express_devcap2_epr(int epr)
1016 {
1017   switch (epr)
1018     {
1019       case 1:
1020         return "Dev Specific";
1021       case 2:
1022         return "Form Factor Dev Specific";
1023       case 3:
1024         return "Reserved";
1025       default:
1026         return "Not Supported";
1027     }
1028 }
1029
1030 static const char *cap_express_devcap2_lncls(int lncls)
1031 {
1032   switch (lncls)
1033     {
1034       case 1:
1035         return "64byte cachelines";
1036       case 2:
1037         return "128byte cachelines";
1038       case 3:
1039         return "Reserved";
1040       default:
1041         return "Not Supported";
1042     }
1043 }
1044
1045 static const char *cap_express_devcap2_tphcomp(int tph)
1046 {
1047   switch (tph)
1048     {
1049       case 1:
1050         return "TPHComp+ ExtTPHComp-";
1051       case 2:
1052         /* Reserved; intentionally left blank */
1053         return "";
1054       case 3:
1055         return "TPHComp+ ExtTPHComp+";
1056       default:
1057         return "TPHComp- ExtTPHComp-";
1058     }
1059 }
1060
1061 static const char *cap_express_devctl2_obff(int obff)
1062 {
1063   switch (obff)
1064     {
1065       case 0:
1066         return "Disabled";
1067       case 1:
1068         return "Via message A";
1069       case 2:
1070         return "Via message B";
1071       case 3:
1072         return "Via WAKE#";
1073       default:
1074         return "Unknown";
1075     }
1076 }
1077
1078 static int
1079 device_has_memory_space_bar(struct device *d)
1080 {
1081   struct pci_dev *p = d->dev;
1082   int i, found = 0;
1083
1084   for (i=0; i<6; i++)
1085     if (p->base_addr[i] && p->size[i])
1086       {
1087         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1088           {
1089             found = 1;
1090             break;
1091           }
1092       }
1093   return found;
1094 }
1095
1096 static void cap_express_dev2(struct device *d, int where, int type)
1097 {
1098   u32 l;
1099   u16 w;
1100   int has_mem_bar = device_has_memory_space_bar(d);
1101
1102   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1103   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1104         cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1105         FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
1106         FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1107         FLAG(l, PCI_EXP_DEVCAP2_LTR));
1108   printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1109         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1110         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1111         cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1112         FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1113         FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1114
1115   if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1116     {
1117       printf(", MaxEETLPPrefixes %d",
1118              PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1119     }
1120
1121   printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1122         cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1123         FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1124   printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1125
1126   if (type == PCI_EXP_TYPE_ROOT_PORT)
1127     printf(" LN System CLS %s,",
1128           cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1129
1130   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1131     printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1132
1133   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1134     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
1135   else
1136     printf("\n");
1137   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1138       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1139     {
1140        printf("\t\t\t AtomicOpsCap:");
1141        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1142            type == PCI_EXP_TYPE_DOWNSTREAM)
1143          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1144        if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1145          printf(" 32bit%c 64bit%c 128bitCAS%c",
1146                 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1147                 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1148                 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1149        printf("\n");
1150     }
1151
1152   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1153   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,",
1154         cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
1155         FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
1156         FLAG(w, PCI_EXP_DEVCTL2_LTR),
1157         FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
1158         cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
1159   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1160     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
1161   else
1162     printf("\n");
1163   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1164       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1165       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1166     {
1167       printf("\t\t\t AtomicOpsCtl:");
1168       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1169           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1170         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
1171       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1172           type == PCI_EXP_TYPE_DOWNSTREAM)
1173         printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
1174       printf("\n");
1175     }
1176 }
1177
1178 static const char *cap_express_link2_speed_cap(int vector)
1179 {
1180   /*
1181    * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1182    * permitted to skip support for any data rates between 2.5GT/s and the
1183    * highest supported rate.
1184    */
1185   if (vector & 0x60)
1186     return "RsvdP";
1187   if (vector & 0x10)
1188     return "2.5-32GT/s";
1189   if (vector & 0x08)
1190     return "2.5-16GT/s";
1191   if (vector & 0x04)
1192     return "2.5-8GT/s";
1193   if (vector & 0x02)
1194     return "2.5-5GT/s";
1195   if (vector & 0x01)
1196     return "2.5GT/s";
1197
1198   return "Unknown";
1199 }
1200
1201 static const char *cap_express_link2_speed(int type)
1202 {
1203   switch (type)
1204     {
1205       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1206       case 1:
1207         return "2.5GT/s";
1208       case 2:
1209         return "5GT/s";
1210       case 3:
1211         return "8GT/s";
1212       case 4:
1213         return "16GT/s";
1214       case 5:
1215         return "32GT/s";
1216       case 6:
1217         return "64GT/s";
1218       default:
1219         return "Unknown";
1220     }
1221 }
1222
1223 static const char *cap_express_link2_deemphasis(int type)
1224 {
1225   switch (type)
1226     {
1227       case 0:
1228         return "-6dB";
1229       case 1:
1230         return "-3.5dB";
1231       default:
1232         return "Unknown";
1233     }
1234 }
1235
1236 static const char *cap_express_link2_compliance_preset(int type)
1237 {
1238   switch (type)
1239     {
1240       case 0:
1241         return "-6dB de-emphasis, 0dB preshoot";
1242       case 1:
1243         return "-3.5dB de-emphasis, 0dB preshoot";
1244       case 2:
1245         return "-4.4dB de-emphasis, 0dB preshoot";
1246       case 3:
1247         return "-2.5dB de-emphasis, 0dB preshoot";
1248       case 4:
1249         return "0dB de-emphasis, 0dB preshoot";
1250       case 5:
1251         return "0dB de-emphasis, 1.9dB preshoot";
1252       case 6:
1253         return "0dB de-emphasis, 2.5dB preshoot";
1254       case 7:
1255         return "-6.0dB de-emphasis, 3.5dB preshoot";
1256       case 8:
1257         return "-3.5dB de-emphasis, 3.5dB preshoot";
1258       case 9:
1259         return "0dB de-emphasis, 3.5dB preshoot";
1260       default:
1261         return "Unknown";
1262     }
1263 }
1264
1265 static const char *cap_express_link2_transmargin(int type)
1266 {
1267   switch (type)
1268     {
1269       case 0:
1270         return "Normal Operating Range";
1271       case 1:
1272         return "800-1200mV(full-swing)/400-700mV(half-swing)";
1273       case 2:
1274       case 3:
1275       case 4:
1276       case 5:
1277         return "200-400mV(full-swing)/100-200mV(half-swing)";
1278       default:
1279         return "Unknown";
1280     }
1281 }
1282
1283 static const char *cap_express_link2_crosslink_res(int crosslink)
1284 {
1285   switch (crosslink)
1286     {
1287       case 0:
1288         return "unsupported";
1289       case 1:
1290         return "Upstream Port";
1291       case 2:
1292         return "Downstream Port";
1293       default:
1294         return "incomplete";
1295     }
1296 }
1297
1298 static const char *cap_express_link2_component(int presence)
1299 {
1300   switch (presence)
1301     {
1302       case 0:
1303         return "Link Down - Not Determined";
1304       case 1:
1305         return "Link Down - Not Present";
1306       case 2:
1307         return "Link Down - Present";
1308       case 4:
1309         return "Link Up - Present";
1310       case 5:
1311         return "Link Up - Present and DRS Received";
1312       default:
1313         return "Reserved";
1314     }
1315 }
1316
1317 static void cap_express_link2(struct device *d, int where, int type)
1318 {
1319   u32 l = 0;
1320   u16 w;
1321
1322   if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1323         (d->dev->dev != 0 || d->dev->func != 0))) {
1324     /* Link Capabilities 2 was reserved before PCIe r3.0 */
1325     l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1326     if (l) {
1327       printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1328         "Retimer%c 2Retimers%c DRS%c\n",
1329           cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1330           FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1331           FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1332           FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1333           FLAG(l, PCI_EXP_LNKCAP2_DRS));
1334     }
1335
1336     w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1337     printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1338         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1339         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1340         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1341     if (type == PCI_EXP_TYPE_DOWNSTREAM)
1342       printf(", Selectable De-emphasis: %s",
1343         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1344     printf("\n"
1345         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1346         "\t\t\t Compliance Preset/De-emphasis: %s\n",
1347         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1348         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1349         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1350         cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1351   }
1352
1353   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1354   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1355         "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1356         "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
1357         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1358         FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1359         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1360         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1361         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1362         FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1363         FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1364         FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1365         cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
1366
1367   if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1368     printf(", DRS%c\n"
1369         "\t\t\t DownstreamComp: %s\n",
1370         FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1371         cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1372   } else
1373     printf("\n");
1374 }
1375
1376 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1377 {
1378   /* No capabilities that require this field in PCIe rev2.0 spec. */
1379 }
1380
1381 static int
1382 cap_express(struct device *d, int where, int cap)
1383 {
1384   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1385   int size;
1386   int slot = 0;
1387   int link = 1;
1388
1389   printf("Express ");
1390   if (verbose >= 2)
1391     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1392   switch (type)
1393     {
1394     case PCI_EXP_TYPE_ENDPOINT:
1395       printf("Endpoint");
1396       break;
1397     case PCI_EXP_TYPE_LEG_END:
1398       printf("Legacy Endpoint");
1399       break;
1400     case PCI_EXP_TYPE_ROOT_PORT:
1401       slot = cap & PCI_EXP_FLAGS_SLOT;
1402       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1403       break;
1404     case PCI_EXP_TYPE_UPSTREAM:
1405       printf("Upstream Port");
1406       break;
1407     case PCI_EXP_TYPE_DOWNSTREAM:
1408       slot = cap & PCI_EXP_FLAGS_SLOT;
1409       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1410       break;
1411     case PCI_EXP_TYPE_PCI_BRIDGE:
1412       printf("PCI-Express to PCI/PCI-X Bridge");
1413       break;
1414     case PCI_EXP_TYPE_PCIE_BRIDGE:
1415       slot = cap & PCI_EXP_FLAGS_SLOT;
1416       printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1417              FLAG(cap, PCI_EXP_FLAGS_SLOT));
1418       break;
1419     case PCI_EXP_TYPE_ROOT_INT_EP:
1420       link = 0;
1421       printf("Root Complex Integrated Endpoint");
1422       break;
1423     case PCI_EXP_TYPE_ROOT_EC:
1424       link = 0;
1425       printf("Root Complex Event Collector");
1426       break;
1427     default:
1428       printf("Unknown type %d", type);
1429   }
1430   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1431   if (verbose < 2)
1432     return type;
1433
1434   size = 16;
1435   if (slot)
1436     size = 24;
1437   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1438     size = 32;
1439   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1440     return type;
1441
1442   cap_express_dev(d, where, type);
1443   if (link)
1444     cap_express_link(d, where, type);
1445   if (slot)
1446     cap_express_slot(d, where);
1447   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1448     cap_express_root(d, where);
1449
1450   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1451     return type;
1452
1453   size = 16;
1454   if (slot)
1455     size = 24;
1456   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1457     return type;
1458
1459   cap_express_dev2(d, where, type);
1460   if (link)
1461     cap_express_link2(d, where, type);
1462   if (slot)
1463     cap_express_slot2(d, where);
1464   return type;
1465 }
1466
1467 static void
1468 cap_msix(struct device *d, int where, int cap)
1469 {
1470   u32 off;
1471
1472   printf("MSI-X: Enable%c Count=%d Masked%c\n",
1473          FLAG(cap, PCI_MSIX_ENABLE),
1474          (cap & PCI_MSIX_TABSIZE) + 1,
1475          FLAG(cap, PCI_MSIX_MASK));
1476   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1477     return;
1478
1479   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1480   printf("\t\tVector table: BAR=%d offset=%08x\n",
1481          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1482   off = get_conf_long(d, where + PCI_MSIX_PBA);
1483   printf("\t\tPBA: BAR=%d offset=%08x\n",
1484          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1485 }
1486
1487 static void
1488 cap_slotid(int cap)
1489 {
1490   int esr = cap & 0xff;
1491   int chs = cap >> 8;
1492
1493   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1494          esr & PCI_SID_ESR_NSLOTS,
1495          FLAG(esr, PCI_SID_ESR_FIC),
1496          chs);
1497 }
1498
1499 static void
1500 cap_ssvid(struct device *d, int where)
1501 {
1502   u16 subsys_v, subsys_d;
1503   char ssnamebuf[256];
1504
1505   if (!config_fetch(d, where, 8))
1506     return;
1507   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1508   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1509   printf("Subsystem: %s\n",
1510            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1511                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1512                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1513 }
1514
1515 static void
1516 cap_debug_port(int cap)
1517 {
1518   int bar = cap >> 13;
1519   int pos = cap & 0x1fff;
1520   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1521 }
1522
1523 static void
1524 cap_af(struct device *d, int where)
1525 {
1526   u8 reg;
1527
1528   printf("PCI Advanced Features\n");
1529   if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1530     return;
1531
1532   reg = get_conf_byte(d, where + PCI_AF_CAP);
1533   printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1534          FLAG(reg, PCI_AF_CAP_FLR));
1535   reg = get_conf_byte(d, where + PCI_AF_CTRL);
1536   printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1537   reg = get_conf_byte(d, where + PCI_AF_STATUS);
1538   printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1539 }
1540
1541 static void
1542 cap_sata_hba(struct device *d, int where, int cap)
1543 {
1544   u32 bars;
1545   int bar;
1546
1547   printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1548   if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1549     {
1550       printf("\n");
1551       return;
1552     }
1553
1554   bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1555   bar = BITS(bars, 0, 4);
1556   if (bar >= 4 && bar <= 9)
1557     printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1558   else if (bar == 15)
1559     printf(" InCfgSpace\n");
1560   else
1561     printf(" BAR??%d\n", bar);
1562 }
1563
1564 static const char *cap_ea_property(int p, int is_secondary)
1565 {
1566   switch (p) {
1567   case 0x00:
1568     return "memory space, non-prefetchable";
1569   case 0x01:
1570     return "memory space, prefetchable";
1571   case 0x02:
1572     return "I/O space";
1573   case 0x03:
1574     return "VF memory space, prefetchable";
1575   case 0x04:
1576     return "VF memory space, non-prefetchable";
1577   case 0x05:
1578     return "allocation behind bridge, non-prefetchable memory";
1579   case 0x06:
1580     return "allocation behind bridge, prefetchable memory";
1581   case 0x07:
1582     return "allocation behind bridge, I/O space";
1583   case 0xfd:
1584     return "memory space resource unavailable for use";
1585   case 0xfe:
1586     return "I/O space resource unavailable for use";
1587   case 0xff:
1588     if (is_secondary)
1589       return "entry unavailable for use, PrimaryProperties should be used";
1590     else
1591       return "entry unavailable for use";
1592   default:
1593     return NULL;
1594   }
1595 }
1596
1597 static void cap_ea(struct device *d, int where, int cap)
1598 {
1599   int entry;
1600   int entry_base = where + 4;
1601   int num_entries = BITS(cap, 0, 6);
1602   u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1603
1604   printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1605   if (htype == PCI_HEADER_TYPE_BRIDGE) {
1606     byte fixed_sub, fixed_sec;
1607
1608     entry_base += 4;
1609     if (!config_fetch(d, where + 4, 2)) {
1610       printf("\n");
1611       return;
1612     }
1613     fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1614     fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1615     printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1616   }
1617   printf("\n");
1618   if (verbose < 2)
1619     return;
1620
1621   for (entry = 0; entry < num_entries; entry++) {
1622     int max_offset_high_pos, has_base_high, has_max_offset_high;
1623     u32 entry_header;
1624     u32 base, max_offset;
1625     int es, bei, pp, sp;
1626     const char *prop_text;
1627
1628     if (!config_fetch(d, entry_base, 4))
1629       return;
1630     entry_header = get_conf_long(d, entry_base);
1631     es = BITS(entry_header, 0, 3);
1632     bei = BITS(entry_header, 4, 4);
1633     pp = BITS(entry_header, 8, 8);
1634     sp = BITS(entry_header, 16, 8);
1635     if (!config_fetch(d, entry_base + 4, es * 4))
1636       return;
1637     printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1638            FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1639            FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1640     printf("\t\t\t BAR Equivalent Indicator: ");
1641     switch (bei) {
1642     case 0:
1643     case 1:
1644     case 2:
1645     case 3:
1646     case 4:
1647     case 5:
1648       printf("BAR %u", bei);
1649       break;
1650     case 6:
1651       printf("resource behind function");
1652       break;
1653     case 7:
1654       printf("not indicated");
1655       break;
1656     case 8:
1657       printf("expansion ROM");
1658       break;
1659     case 9:
1660     case 10:
1661     case 11:
1662     case 12:
1663     case 13:
1664     case 14:
1665       printf("VF-BAR %u", bei - 9);
1666       break;
1667     default:
1668       printf("reserved");
1669       break;
1670     }
1671     printf("\n");
1672
1673     prop_text = cap_ea_property(pp, 0);
1674     printf("\t\t\t PrimaryProperties: ");
1675     if (prop_text)
1676       printf("%s\n", prop_text);
1677     else
1678       printf("[%02x]\n", pp);
1679
1680     prop_text = cap_ea_property(sp, 1);
1681     printf("\t\t\t SecondaryProperties: ");
1682     if (prop_text)
1683       printf("%s\n", prop_text);
1684     else
1685       printf("[%02x]\n", sp);
1686
1687     base = get_conf_long(d, entry_base + 4);
1688     has_base_high = ((base & 2) != 0);
1689     base &= ~3;
1690
1691     max_offset = get_conf_long(d, entry_base + 8);
1692     has_max_offset_high = ((max_offset & 2) != 0);
1693     max_offset |= 3;
1694     max_offset_high_pos = entry_base + 12;
1695
1696     printf("\t\t\t Base: ");
1697     if (has_base_high) {
1698       u32 base_high = get_conf_long(d, entry_base + 12);
1699
1700       printf("%x", base_high);
1701       max_offset_high_pos += 4;
1702     }
1703     printf("%08x\n", base);
1704
1705     printf("\t\t\t MaxOffset: ");
1706     if (has_max_offset_high) {
1707       u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1708
1709       printf("%x", max_offset_high);
1710     }
1711     printf("%08x\n", max_offset);
1712
1713     entry_base += 4 + 4 * es;
1714   }
1715 }
1716
1717 void
1718 show_caps(struct device *d, int where)
1719 {
1720   int can_have_ext_caps = 0;
1721   int type = -1;
1722
1723   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1724     {
1725       byte been_there[256];
1726       where = get_conf_byte(d, where) & ~3;
1727       memset(been_there, 0, 256);
1728       while (where)
1729         {
1730           int id, next, cap;
1731           printf("\tCapabilities: ");
1732           if (!config_fetch(d, where, 4))
1733             {
1734               puts("<access denied>");
1735               break;
1736             }
1737           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1738           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1739           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1740           printf("[%02x] ", where);
1741           if (been_there[where]++)
1742             {
1743               printf("<chain looped>\n");
1744               break;
1745             }
1746           if (id == 0xff)
1747             {
1748               printf("<chain broken>\n");
1749               break;
1750             }
1751           switch (id)
1752             {
1753             case PCI_CAP_ID_NULL:
1754               printf("Null\n");
1755               break;
1756             case PCI_CAP_ID_PM:
1757               cap_pm(d, where, cap);
1758               break;
1759             case PCI_CAP_ID_AGP:
1760               cap_agp(d, where, cap);
1761               break;
1762             case PCI_CAP_ID_VPD:
1763               cap_vpd(d);
1764               break;
1765             case PCI_CAP_ID_SLOTID:
1766               cap_slotid(cap);
1767               break;
1768             case PCI_CAP_ID_MSI:
1769               cap_msi(d, where, cap);
1770               break;
1771             case PCI_CAP_ID_CHSWP:
1772               printf("CompactPCI hot-swap <?>\n");
1773               break;
1774             case PCI_CAP_ID_PCIX:
1775               cap_pcix(d, where);
1776               can_have_ext_caps = 1;
1777               break;
1778             case PCI_CAP_ID_HT:
1779               cap_ht(d, where, cap);
1780               break;
1781             case PCI_CAP_ID_VNDR:
1782               show_vendor_caps(d, where, cap);
1783               break;
1784             case PCI_CAP_ID_DBG:
1785               cap_debug_port(cap);
1786               break;
1787             case PCI_CAP_ID_CCRC:
1788               printf("CompactPCI central resource control <?>\n");
1789               break;
1790             case PCI_CAP_ID_HOTPLUG:
1791               printf("Hot-plug capable\n");
1792               break;
1793             case PCI_CAP_ID_SSVID:
1794               cap_ssvid(d, where);
1795               break;
1796             case PCI_CAP_ID_AGP3:
1797               printf("AGP3 <?>\n");
1798               break;
1799             case PCI_CAP_ID_SECURE:
1800               printf("Secure device <?>\n");
1801               break;
1802             case PCI_CAP_ID_EXP:
1803               type = cap_express(d, where, cap);
1804               can_have_ext_caps = 1;
1805               break;
1806             case PCI_CAP_ID_MSIX:
1807               cap_msix(d, where, cap);
1808               break;
1809             case PCI_CAP_ID_SATA:
1810               cap_sata_hba(d, where, cap);
1811               break;
1812             case PCI_CAP_ID_AF:
1813               cap_af(d, where);
1814               break;
1815             case PCI_CAP_ID_EA:
1816               cap_ea(d, where, cap);
1817               break;
1818             default:
1819               printf("Capability ID %#02x [%04x]\n", id, cap);
1820             }
1821           where = next;
1822         }
1823     }
1824   if (can_have_ext_caps)
1825     show_ext_caps(d, type);
1826 }