ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap >> 6) & 7],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  40          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  41          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  42          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  43   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  44   if (b)
  45     printf("\t\tBridge: PM%c B3%c\n",
  46            FLAG(t, PCI_PM_BPCC_ENABLE),
  47            FLAG(~t, PCI_PM_PPB_B2_B3));
  48 }
  49
  50 static void
  51 format_agp_rate(int rate, char *buf, int agp3)
  52 {
  53   char *c = buf;
  54   int i;
  55
  56   for (i=0; i<=2; i++)
  57     if (rate & (1 << i))
  58       {
  59         if (c != buf)
  60           *c++ = ',';
  61         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  62       }
  63   if (c != buf)
  64     *c = 0;
  65   else
  66     strcpy(buf, "<none>");
  67 }
  68
  69 static void
  70 cap_agp(struct device *d, int where, int cap)
  71 {
  72   u32 t;
  73   char rate[16];
  74   int ver, rev;
  75   int agp3 = 0;
  76
  77   ver = (cap >> 4) & 0x0f;
  78   rev = cap & 0x0f;
  79   printf("AGP version %x.%x\n", ver, rev);
  80   if (verbose < 2)
  81     return;
  82   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  83     return;
  84   t = get_conf_long(d, where + PCI_AGP_STATUS);
  85   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  86     agp3 = 1;
  87   format_agp_rate(t & 7, rate, agp3);
  88   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  89          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  90          FLAG(t, PCI_AGP_STATUS_ISOCH),
  91          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  92          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  93          FLAG(t, PCI_AGP_STATUS_SBA),
  94          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  95          FLAG(t, PCI_AGP_STATUS_GART64),
  96          FLAG(t, PCI_AGP_STATUS_HTRANS),
  97          FLAG(t, PCI_AGP_STATUS_64BIT),
  98          FLAG(t, PCI_AGP_STATUS_FW),
  99          FLAG(t, PCI_AGP_STATUS_AGP3),
 100          rate);
 101   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 102   format_agp_rate(t & 7, rate, agp3);
 103   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 104          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 105          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 106          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 107          FLAG(t, PCI_AGP_COMMAND_SBA),
 108          FLAG(t, PCI_AGP_COMMAND_AGP),
 109          FLAG(t, PCI_AGP_COMMAND_GART64),
 110          FLAG(t, PCI_AGP_COMMAND_64BIT),
 111          FLAG(t, PCI_AGP_COMMAND_FW),
 112          rate);
 113 }
 114
 115 static void
 116 cap_pcix_nobridge(struct device *d, int where)
 117 {
 118   u16 command;
 119   u32 status;
 120   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 121
 122   printf("PCI-X non-bridge device\n");
 123
 124   if (verbose < 2)
 125     return;
 126
 127   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 128     return;
 129
 130   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 131   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 132   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 133          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 134          FLAG(command, PCI_PCIX_COMMAND_ERO),
 135          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 136          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 137   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 138          ((status >> 8) & 0xff),
 139          ((status >> 3) & 0x1f),
 140          (status & PCI_PCIX_STATUS_FUNCTION),
 141          FLAG(status, PCI_PCIX_STATUS_64BIT),
 142          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 143          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 144          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 145          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 146          1 << (9 + ((status >> 21) & 3U)),
 147          max_outstanding[(status >> 23) & 7U],
 148          1 << (3 + ((status >> 26) & 7U)),
 149          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 150          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 151          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 152 }
 153
 154 static void
 155 cap_pcix_bridge(struct device *d, int where)
 156 {
 157   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 158   u16 secstatus;
 159   u32 status, upstcr, downstcr;
 160
 161   printf("PCI-X bridge device\n");
 162
 163   if (verbose < 2)
 164     return;
 165
 166   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 167     return;
 168
 169   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 170   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 171          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 177          sec_clock_freq[(secstatus >> 6) & 7]);
 178   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 179   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 180          ((status >> 8) & 0xff),
 181          ((status >> 3) & 0x1f),
 182          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 183          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 189   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 190   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 191          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 192          (upstcr >> 16) & 0xffff);
 193   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 194   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 195          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 196          (downstcr >> 16) & 0xffff);
 197 }
 198
 199 static void
 200 cap_pcix(struct device *d, int where)
 201 {
 202   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 203     {
 204     case PCI_HEADER_TYPE_NORMAL:
 205       cap_pcix_nobridge(d, where);
 206       break;
 207     case PCI_HEADER_TYPE_BRIDGE:
 208       cap_pcix_bridge(d, where);
 209       break;
 210     }
 211 }
 212
 213 static inline char *
 214 ht_link_width(unsigned width)
 215 {
 216   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 217   return widths[width];
 218 }
 219
 220 static inline char *
 221 ht_link_freq(unsigned freq)
 222 {
 223   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 224                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 225   return freqs[freq];
 226 }
 227
 228 static void
 229 cap_ht_pri(struct device *d, int where, int cmd)
 230 {
 231   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 232   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 233   char *fmt;
 234
 235   printf("HyperTransport: Slave or Primary Interface\n");
 236   if (verbose < 2)
 237     return;
 238
 239   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 240     return;
 241   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 242   if (rid < 0x22 && rid > 0x11)
 243     printf("\t\t!!! Possibly incomplete decoding\n");
 244
 245   if (rid >= 0x22)
 246     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
 247   else
 248     fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
 249   printf(fmt,
 250          (cmd & PCI_HT_PRI_CMD_BUID),
 251          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 252          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 253          FLAG(cmd, PCI_HT_PRI_CMD_DD),
 254          FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 255   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 256   if (rid >= 0x22)
 257     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 258   else
 259     fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 260   printf(fmt,
 261          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 262          FLAG(lctr0, PCI_HT_LCTR_CST),
 263          FLAG(lctr0, PCI_HT_LCTR_CFE),
 264          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 265          FLAG(lctr0, PCI_HT_LCTR_INIT),
 266          FLAG(lctr0, PCI_HT_LCTR_EOC),
 267          FLAG(lctr0, PCI_HT_LCTR_TXO),
 268          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
 269          FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 270          FLAG(lctr0, PCI_HT_LCTR_LSEN),
 271          FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 272          FLAG(lctr0, PCI_HT_LCTR_64B));
 273   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 274   if (rid >= 0x22)
 275     fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 276   else
 277     fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 278   printf(fmt,
 279          ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 280          ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 281          ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 282          ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 283          FLAG(lcnf0, PCI_HT_LCNF_DFI),
 284          FLAG(lcnf0, PCI_HT_LCNF_DFO),
 285          FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 286          FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 287   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 288   if (rid >= 0x22)
 289     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 290   else
 291     fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 292   printf(fmt,
 293          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 294          FLAG(lctr1, PCI_HT_LCTR_CST),
 295          FLAG(lctr1, PCI_HT_LCTR_CFE),
 296          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 297          FLAG(lctr1, PCI_HT_LCTR_INIT),
 298          FLAG(lctr1, PCI_HT_LCTR_EOC),
 299          FLAG(lctr1, PCI_HT_LCTR_TXO),
 300          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
 301          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 302          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 303          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 304          FLAG(lctr1, PCI_HT_LCTR_64B));
 305   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 306   if (rid >= 0x22)
 307     fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 308   else
 309     fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 310   printf(fmt,
 311          ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 312          ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 313          ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 314          ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 315          FLAG(lcnf1, PCI_HT_LCNF_DFI),
 316          FLAG(lcnf1, PCI_HT_LCNF_DFO),
 317          FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 318          FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 319   printf("\t\tRevision ID: %u.%02u\n",
 320          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 321   if (rid < 0x22)
 322     return;
 323   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 324   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 325   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 326          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 327          FLAG(lfrer0, PCI_HT_LFRER_OV),
 328          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 329          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 330   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 331   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 332          FLAG(lfcap0, PCI_HT_LFCAP_200),
 333          FLAG(lfcap0, PCI_HT_LFCAP_300),
 334          FLAG(lfcap0, PCI_HT_LFCAP_400),
 335          FLAG(lfcap0, PCI_HT_LFCAP_500),
 336          FLAG(lfcap0, PCI_HT_LFCAP_600),
 337          FLAG(lfcap0, PCI_HT_LFCAP_800),
 338          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 339          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 340          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 341          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 342          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 343   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 344   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 345          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 346          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 347          FLAG(ftr, PCI_HT_FTR_CRCTM),
 348          FLAG(ftr, PCI_HT_FTR_ECTLT),
 349          FLAG(ftr, PCI_HT_FTR_64BA),
 350          FLAG(ftr, PCI_HT_FTR_UIDRD));
 351   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 352   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 353   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 354          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 355          FLAG(lfrer1, PCI_HT_LFRER_OV),
 356          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 357          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 358   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 359   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 360          FLAG(lfcap1, PCI_HT_LFCAP_200),
 361          FLAG(lfcap1, PCI_HT_LFCAP_300),
 362          FLAG(lfcap1, PCI_HT_LFCAP_400),
 363          FLAG(lfcap1, PCI_HT_LFCAP_500),
 364          FLAG(lfcap1, PCI_HT_LFCAP_600),
 365          FLAG(lfcap1, PCI_HT_LFCAP_800),
 366          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 367          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 368          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 369          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 370          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 371   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 372   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 373          FLAG(eh, PCI_HT_EH_PFLE),
 374          FLAG(eh, PCI_HT_EH_OFLE),
 375          FLAG(eh, PCI_HT_EH_PFE),
 376          FLAG(eh, PCI_HT_EH_OFE),
 377          FLAG(eh, PCI_HT_EH_EOCFE),
 378          FLAG(eh, PCI_HT_EH_RFE),
 379          FLAG(eh, PCI_HT_EH_CRCFE),
 380          FLAG(eh, PCI_HT_EH_SERRFE),
 381          FLAG(eh, PCI_HT_EH_CF),
 382          FLAG(eh, PCI_HT_EH_RE),
 383          FLAG(eh, PCI_HT_EH_PNFE),
 384          FLAG(eh, PCI_HT_EH_ONFE),
 385          FLAG(eh, PCI_HT_EH_EOCNFE),
 386          FLAG(eh, PCI_HT_EH_RNFE),
 387          FLAG(eh, PCI_HT_EH_CRCNFE),
 388          FLAG(eh, PCI_HT_EH_SERRNFE));
 389   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 390   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 391   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 392   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 393   printf("\t\tBus Number: %02x\n", bn);
 394 }
 395
 396 static void
 397 cap_ht_sec(struct device *d, int where, int cmd)
 398 {
 399   u16 lctr, lcnf, ftr, eh;
 400   u8 rid, lfrer, lfcap, mbu, mlu;
 401   char *fmt;
 402
 403   printf("HyperTransport: Host or Secondary Interface\n");
 404   if (verbose < 2)
 405     return;
 406
 407   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 408     return;
 409   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 410   if (rid < 0x22 && rid > 0x11)
 411     printf("\t\t!!! Possibly incomplete decoding\n");
 412
 413   if (rid >= 0x22)
 414     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 415   else
 416     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 417   printf(fmt,
 418          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 419          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 420          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 421          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 422          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 423          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 424          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 425          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 426   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 427   if (rid >= 0x22)
 428     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 429   else
 430     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 431   printf(fmt,
 432          FLAG(lctr, PCI_HT_LCTR_CFLE),
 433          FLAG(lctr, PCI_HT_LCTR_CST),
 434          FLAG(lctr, PCI_HT_LCTR_CFE),
 435          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 436          FLAG(lctr, PCI_HT_LCTR_INIT),
 437          FLAG(lctr, PCI_HT_LCTR_EOC),
 438          FLAG(lctr, PCI_HT_LCTR_TXO),
 439          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 440          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 441          FLAG(lctr, PCI_HT_LCTR_LSEN),
 442          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 443          FLAG(lctr, PCI_HT_LCTR_64B));
 444   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 445   if (rid >= 0x22)
 446     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 447   else
 448     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 449   printf(fmt,
 450          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 451          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 452          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 453          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 454          FLAG(lcnf, PCI_HT_LCNF_DFI),
 455          FLAG(lcnf, PCI_HT_LCNF_DFO),
 456          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 457          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 458   printf("\t\tRevision ID: %u.%02u\n",
 459          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 460   if (rid < 0x22)
 461     return;
 462   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 463   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 464   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 465          FLAG(lfrer, PCI_HT_LFRER_PROT),
 466          FLAG(lfrer, PCI_HT_LFRER_OV),
 467          FLAG(lfrer, PCI_HT_LFRER_EOC),
 468          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 469   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 470   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 471          FLAG(lfcap, PCI_HT_LFCAP_200),
 472          FLAG(lfcap, PCI_HT_LFCAP_300),
 473          FLAG(lfcap, PCI_HT_LFCAP_400),
 474          FLAG(lfcap, PCI_HT_LFCAP_500),
 475          FLAG(lfcap, PCI_HT_LFCAP_600),
 476          FLAG(lfcap, PCI_HT_LFCAP_800),
 477          FLAG(lfcap, PCI_HT_LFCAP_1000),
 478          FLAG(lfcap, PCI_HT_LFCAP_1200),
 479          FLAG(lfcap, PCI_HT_LFCAP_1400),
 480          FLAG(lfcap, PCI_HT_LFCAP_1600),
 481          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 482   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 483   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 484          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 485          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 486          FLAG(ftr, PCI_HT_FTR_CRCTM),
 487          FLAG(ftr, PCI_HT_FTR_ECTLT),
 488          FLAG(ftr, PCI_HT_FTR_64BA),
 489          FLAG(ftr, PCI_HT_FTR_UIDRD),
 490          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 491          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 492   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 493     {
 494       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 495       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 496              FLAG(eh, PCI_HT_EH_PFLE),
 497              FLAG(eh, PCI_HT_EH_OFLE),
 498              FLAG(eh, PCI_HT_EH_PFE),
 499              FLAG(eh, PCI_HT_EH_OFE),
 500              FLAG(eh, PCI_HT_EH_EOCFE),
 501              FLAG(eh, PCI_HT_EH_RFE),
 502              FLAG(eh, PCI_HT_EH_CRCFE),
 503              FLAG(eh, PCI_HT_EH_SERRFE),
 504              FLAG(eh, PCI_HT_EH_CF),
 505              FLAG(eh, PCI_HT_EH_RE),
 506              FLAG(eh, PCI_HT_EH_PNFE),
 507              FLAG(eh, PCI_HT_EH_ONFE),
 508              FLAG(eh, PCI_HT_EH_EOCNFE),
 509              FLAG(eh, PCI_HT_EH_RNFE),
 510              FLAG(eh, PCI_HT_EH_CRCNFE),
 511              FLAG(eh, PCI_HT_EH_SERRNFE));
 512       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 513       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 514       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 515     }
 516 }
 517
 518 static void
 519 cap_ht(struct device *d, int where, int cmd)
 520 {
 521   int type;
 522
 523   switch (cmd & PCI_HT_CMD_TYP_HI)
 524     {
 525     case PCI_HT_CMD_TYP_HI_PRI:
 526       cap_ht_pri(d, where, cmd);
 527       return;
 528     case PCI_HT_CMD_TYP_HI_SEC:
 529       cap_ht_sec(d, where, cmd);
 530       return;
 531     }
 532
 533   type = cmd & PCI_HT_CMD_TYP;
 534   switch (type)
 535     {
 536     case PCI_HT_CMD_TYP_SW:
 537       printf("HyperTransport: Switch\n");
 538       break;
 539     case PCI_HT_CMD_TYP_IDC:
 540       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 541       break;
 542     case PCI_HT_CMD_TYP_RID:
 543       printf("HyperTransport: Revision ID: %u.%02u\n",
 544              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 545       break;
 546     case PCI_HT_CMD_TYP_UIDC:
 547       printf("HyperTransport: UnitID Clumping\n");
 548       break;
 549     case PCI_HT_CMD_TYP_ECSA:
 550       printf("HyperTransport: Extended Configuration Space Access\n");
 551       break;
 552     case PCI_HT_CMD_TYP_AM:
 553       printf("HyperTransport: Address Mapping\n");
 554       break;
 555     case PCI_HT_CMD_TYP_MSIM:
 556       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 557              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 558              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 559       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 560         {
 561           u32 offl, offh;
 562           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 563             break;
 564           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 565           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 566           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 567         }
 568       break;
 569     case PCI_HT_CMD_TYP_DR:
 570       printf("HyperTransport: DirectRoute\n");
 571       break;
 572     case PCI_HT_CMD_TYP_VCS:
 573       printf("HyperTransport: VCSet\n");
 574       break;
 575     case PCI_HT_CMD_TYP_RM:
 576       printf("HyperTransport: Retry Mode\n");
 577       break;
 578     case PCI_HT_CMD_TYP_X86:
 579       printf("HyperTransport: X86 (reserved)\n");
 580       break;
 581     default:
 582       printf("HyperTransport: #%02x\n", type >> 11);
 583     }
 584 }
 585
 586 static void
 587 cap_msi(struct device *d, int where, int cap)
 588 {
 589   int is64;
 590   u32 t;
 591   u16 w;
 592
 593   printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
 594          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 595          FLAG(cap, PCI_MSI_FLAGS_64BIT),
 596          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 597          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 598          FLAG(cap, PCI_MSI_FLAGS_ENABLE));
 599   if (verbose < 2)
 600     return;
 601   is64 = cap & PCI_MSI_FLAGS_64BIT;
 602   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 603     return;
 604   printf("\t\tAddress: ");
 605   if (is64)
 606     {
 607       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 608       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 609       printf("%08x", t);
 610     }
 611   else
 612     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 613   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 614   printf("%08x  Data: %04x\n", t, w);
 615   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 616     {
 617       u32 mask, pending;
 618
 619       if (is64)
 620         {
 621           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 622             return;
 623           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 624           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 625         }
 626       else
 627         {
 628           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 629             return;
 630           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 631           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 632         }
 633       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 634     }
 635 }
 636
 637 static float power_limit(int value, int scale)
 638 {
 639   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 640   return value * scales[scale];
 641 }
 642
 643 static const char *latency_l0s(int value)
 644 {
 645   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 646   return latencies[value];
 647 }
 648
 649 static const char *latency_l1(int value)
 650 {
 651   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 652   return latencies[value];
 653 }
 654
 655 static void cap_express_dev(struct device *d, int where, int type)
 656 {
 657   u32 t;
 658   u16 w;
 659
 660   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 661   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
 662         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 663         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
 664         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 665         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 666   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 667   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 668       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 669     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 670         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 671         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 672   printf(" RBE%c FLReset%c",
 673         FLAG(t, PCI_EXP_DEVCAP_RBE),
 674         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 675   if (type == PCI_EXP_TYPE_UPSTREAM)
 676     printf("SlotPowerLimit %fW",
 677         power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 678                     (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
 679   printf("\n");
 680
 681   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 682   printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
 683         FLAG(w, PCI_EXP_DEVCTL_CERE),
 684         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 685         FLAG(w, PCI_EXP_DEVCTL_FERE),
 686         FLAG(w, PCI_EXP_DEVCTL_URRE));
 687   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 688         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 689         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 690         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 691         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 692         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 693   if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
 694     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 695   if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
 696     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 697   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 698         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 699         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 700
 701   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 702   printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
 703         FLAG(w, PCI_EXP_DEVSTA_CED),
 704         FLAG(w, PCI_EXP_DEVSTA_NFED),
 705         FLAG(w, PCI_EXP_DEVSTA_FED),
 706         FLAG(w, PCI_EXP_DEVSTA_URD),
 707         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 708         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 709 }
 710
 711 static char *link_speed(int speed)
 712 {
 713   switch (speed)
 714     {
 715       case 1:
 716         return "2.5GT/s";
 717       case 2:
 718         return "5GT/s";
 719       default:
 720         return "unknown";
 721     }
 722 }
 723
 724 static char *aspm_support(int code)
 725 {
 726   switch (code)
 727     {
 728       case 1:
 729         return "L0s";
 730       case 3:
 731         return "L0s L1";
 732       default:
 733         return "unknown";
 734     }
 735 }
 736
 737 static const char *aspm_enabled(int code)
 738 {
 739   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 740   return desc[code];
 741 }
 742
 743 static void cap_express_link(struct device *d, int where, int type)
 744 {
 745   u32 t;
 746   u16 w;
 747
 748   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 749   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
 750         t >> 24,
 751         link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
 752         aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
 753         latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
 754         latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 755   printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
 756         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 757         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 758         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 759         FLAG(t, PCI_EXP_LNKCAP_LBNC));
 760
 761   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 762   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 763   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 764       (type == PCI_EXP_TYPE_LEG_END))
 765     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 766   printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 767         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 768         FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
 769         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 770         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 771         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 772         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 773         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 774         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 775
 776   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 777   printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 778         link_speed(w & PCI_EXP_LNKSTA_SPEED),
 779         (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
 780         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 781         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 782         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 783         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 784         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 785         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 786 }
 787
 788 static const char *indicator(int code)
 789 {
 790   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 791   return names[code];
 792 }
 793
 794 static void cap_express_slot(struct device *d, int where)
 795 {
 796   u32 t;
 797   u16 w;
 798
 799   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 800   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
 801         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 802         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 803         FLAG(t, PCI_EXP_SLTCAP_MRL),
 804         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 805         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 806         FLAG(t, PCI_EXP_SLTCAP_HPC),
 807         FLAG(t, PCI_EXP_SLTCAP_HPS));
 808   printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
 809         t >> 19,
 810         power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
 811         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 812         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 813
 814   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 815   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 816         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 817         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 818         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 819         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 820         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 821         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 822         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 823   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 824         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 825         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 826         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 827         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 828
 829   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 830   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 831         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 832         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 833         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 834         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 835         FLAG(w, PCI_EXP_SLTSTA_PRES),
 836         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 837   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 838         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 839         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 840         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 841 }
 842
 843 static void cap_express_root(struct device *d, int where)
 844 {
 845   u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
 846   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 847         FLAG(w, PCI_EXP_RTCTL_SECEE),
 848         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 849         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 850         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 851         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 852
 853   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 854   printf("\t\tRootCap: CRSVisible%c\n",
 855         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 856
 857   w = get_conf_word(d, where + PCI_EXP_RTSTA);
 858   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 859         w & PCI_EXP_RTSTA_PME_REQID,
 860         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 861         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 862 }
 863
 864 static const char *cap_express_dev2_timeout_range(int type)
 865 {
 866   /* Decode Completion Timeout Ranges. */
 867   switch (type)
 868     {
 869       case 0:
 870         return "Not Supported";
 871       case 1:
 872         return "Range A";
 873       case 2:
 874         return "Range B";
 875       case 3:
 876         return "Range AB";
 877       case 6:
 878         return "Range BC";
 879       case 7:
 880         return "Range ABC";
 881       case 14:
 882         return "Range BCD";
 883       case 15:
 884         return "Range ABCD";
 885       default:
 886         return "Unknown";
 887     }
 888 }
 889
 890 static const char *cap_express_dev2_timeout_value(int type)
 891 {
 892   /* Decode Completion Timeout Value. */
 893   switch (type)
 894     {
 895       case 0:
 896         return "50us to 50ms";
 897       case 1:
 898         return "50us to 100us";
 899       case 2:
 900         return "1ms to 10ms";
 901       case 5:
 902         return "16ms to 55ms";
 903       case 6:
 904         return "65ms to 210ms";
 905       case 9:
 906         return "260ms to 900ms";
 907       case 10:
 908         return "1s to 3.5s";
 909       case 13:
 910         return "4s to 13s";
 911       case 14:
 912         return "17s to 64s";
 913       default:
 914         return "Unknown";
 915     }
 916 }
 917
 918 static void cap_express_dev2(struct device *d, int where, int type)
 919 {
 920   u32 l;
 921   u16 w;
 922
 923   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
 924   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c",
 925         cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
 926         FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS));
 927   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
 928     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
 929   else
 930     printf("\n");
 931
 932   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
 933   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
 934         cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
 935         FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS));
 936   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
 937     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
 938   else
 939     printf("\n");
 940 }
 941
 942 static const char *cap_express_link2_speed(int type)
 943 {
 944   switch (type)
 945     {
 946       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
 947       case 1:
 948         return "2.5GT/s";
 949       case 2:
 950         return "5GT/s";
 951       default:
 952         return "Unknown";
 953     }
 954 }
 955
 956 static const char *cap_express_link2_deemphasis(int type)
 957 {
 958   switch (type)
 959     {
 960       case 0:
 961         return "-6dB";
 962       case 1:
 963         return "-3.5dB";
 964       default:
 965         return "Unknown";
 966     }
 967 }
 968
 969 static const char *cap_express_link2_transmargin(int type)
 970 {
 971   switch (type)
 972     {
 973       case 0:
 974         return "Normal Operating Range";
 975       case 1:
 976         return "800-1200mV(full-swing)/400-700mV(half-swing)";
 977       case 2:
 978       case 3:
 979       case 4:
 980       case 5:
 981         return "200-400mV(full-swing)/100-200mV(half-swing)";
 982       default:
 983         return "Unknown";
 984     }
 985 }
 986
 987 static void cap_express_link2(struct device *d, int where, int type UNUSED)
 988 {
 989   u16 w;
 990
 991   w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
 992   printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
 993         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
 994         "\t\t\t Compliance De-emphasis: %s\n",
 995         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
 996         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
 997         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
 998         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
 999         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1000         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1001         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1002         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1003
1004   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1005   printf("\t\tLnkSta2: Current De-emphasis Level: %s\n",
1006         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)));
1007 }
1008
1009 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1010 {
1011   /* No capabilities that require this field in PCIe rev2.0 spec. */
1012 }
1013
1014 static void
1015 cap_express(struct device *d, int where, int cap)
1016 {
1017   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1018   int size;
1019   int slot = 0;
1020
1021   printf("Express ");
1022   if (verbose >= 2)
1023     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1024   switch (type)
1025     {
1026     case PCI_EXP_TYPE_ENDPOINT:
1027       printf("Endpoint");
1028       break;
1029     case PCI_EXP_TYPE_LEG_END:
1030       printf("Legacy Endpoint");
1031       break;
1032     case PCI_EXP_TYPE_ROOT_PORT:
1033       slot = cap & PCI_EXP_FLAGS_SLOT;
1034       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1035       break;
1036     case PCI_EXP_TYPE_UPSTREAM:
1037       printf("Upstream Port");
1038       break;
1039     case PCI_EXP_TYPE_DOWNSTREAM:
1040       slot = cap & PCI_EXP_FLAGS_SLOT;
1041       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1042       break;
1043     case PCI_EXP_TYPE_PCI_BRIDGE:
1044       printf("PCI/PCI-X Bridge");
1045       break;
1046     case PCI_EXP_TYPE_PCIE_BRIDGE:
1047       printf("PCI/PCI-X to PCI-Express Bridge");
1048       break;
1049     case PCI_EXP_TYPE_ROOT_INT_EP:
1050       printf("Root Complex Integrated Endpoint");
1051       break;
1052     case PCI_EXP_TYPE_ROOT_EC:
1053       printf("Root Complex Event Collector");
1054       break;
1055     default:
1056       printf("Unknown type %d", type);
1057   }
1058   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1059   if (verbose < 2)
1060     return;
1061
1062   size = 16;
1063   if (slot)
1064     size = 24;
1065   if (type == PCI_EXP_TYPE_ROOT_PORT)
1066     size = 32;
1067   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1068     return;
1069
1070   cap_express_dev(d, where, type);
1071   cap_express_link(d, where, type);
1072   if (slot)
1073     cap_express_slot(d, where);
1074   if (type == PCI_EXP_TYPE_ROOT_PORT)
1075     cap_express_root(d, where);
1076
1077   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1078     return;
1079
1080   size = 16;
1081   if (slot)
1082     size = 24;
1083   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1084     return;
1085
1086   cap_express_dev2(d, where, type);
1087   cap_express_link2(d, where, type);
1088   if (slot)
1089     cap_express_slot2(d, where);
1090 }
1091
1092 static void
1093 cap_msix(struct device *d, int where, int cap)
1094 {
1095   u32 off;
1096
1097   printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1098          FLAG(cap, PCI_MSIX_ENABLE),
1099          FLAG(cap, PCI_MSIX_MASK),
1100          (cap & PCI_MSIX_TABSIZE) + 1);
1101   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1102     return;
1103
1104   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1105   printf("\t\tVector table: BAR=%d offset=%08x\n",
1106          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1107   off = get_conf_long(d, where + PCI_MSIX_PBA);
1108   printf("\t\tPBA: BAR=%d offset=%08x\n",
1109          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1110 }
1111
1112 static void
1113 cap_slotid(int cap)
1114 {
1115   int esr = cap & 0xff;
1116   int chs = cap >> 8;
1117
1118   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1119          esr & PCI_SID_ESR_NSLOTS,
1120          FLAG(esr, PCI_SID_ESR_FIC),
1121          chs);
1122 }
1123
1124 static void
1125 cap_ssvid(struct device *d, int where)
1126 {
1127   u16 subsys_v, subsys_d;
1128   char ssnamebuf[256];
1129
1130   if (!config_fetch(d, where, 8))
1131     return;
1132   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1133   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1134   printf("Subsystem: %s\n",
1135            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1136                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1137                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1138 }
1139
1140 static void
1141 cap_debug_port(int cap)
1142 {
1143   int bar = cap >> 13;
1144   int pos = cap & 0x1fff;
1145   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1146 }
1147
1148 void
1149 show_caps(struct device *d)
1150 {
1151   int can_have_ext_caps = 0;
1152
1153   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1154     {
1155       int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1156       byte been_there[256];
1157       memset(been_there, 0, 256);
1158       while (where)
1159         {
1160           int id, next, cap;
1161           printf("\tCapabilities: ");
1162           if (!config_fetch(d, where, 4))
1163             {
1164               puts("<access denied>");
1165               break;
1166             }
1167           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1168           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1169           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1170           printf("[%02x] ", where);
1171           if (been_there[where]++)
1172             {
1173               printf("<chain looped>\n");
1174               break;
1175             }
1176           if (id == 0xff)
1177             {
1178               printf("<chain broken>\n");
1179               break;
1180             }
1181           switch (id)
1182             {
1183             case PCI_CAP_ID_PM:
1184               cap_pm(d, where, cap);
1185               break;
1186             case PCI_CAP_ID_AGP:
1187               cap_agp(d, where, cap);
1188               break;
1189             case PCI_CAP_ID_VPD:
1190               cap_vpd(d);
1191               break;
1192             case PCI_CAP_ID_SLOTID:
1193               cap_slotid(cap);
1194               break;
1195             case PCI_CAP_ID_MSI:
1196               cap_msi(d, where, cap);
1197               break;
1198             case PCI_CAP_ID_CHSWP:
1199               printf("CompactPCI hot-swap <?>\n");
1200               break;
1201             case PCI_CAP_ID_PCIX:
1202               cap_pcix(d, where);
1203               can_have_ext_caps = 1;
1204               break;
1205             case PCI_CAP_ID_HT:
1206               cap_ht(d, where, cap);
1207               break;
1208             case PCI_CAP_ID_VNDR:
1209               printf("Vendor Specific Information <?>\n");
1210               break;
1211             case PCI_CAP_ID_DBG:
1212               cap_debug_port(cap);
1213               break;
1214             case PCI_CAP_ID_CCRC:
1215               printf("CompactPCI central resource control <?>\n");
1216               break;
1217             case PCI_CAP_ID_HOTPLUG:
1218               printf("Hot-plug capable\n");
1219               break;
1220             case PCI_CAP_ID_SSVID:
1221               cap_ssvid(d, where);
1222               break;
1223             case PCI_CAP_ID_AGP3:
1224               printf("AGP3 <?>\n");
1225               break;
1226             case PCI_CAP_ID_SECURE:
1227               printf("Secure device <?>\n");
1228               break;
1229             case PCI_CAP_ID_EXP:
1230               cap_express(d, where, cap);
1231               can_have_ext_caps = 1;
1232               break;
1233             case PCI_CAP_ID_MSIX:
1234               cap_msix(d, where, cap);
1235               break;
1236             case PCI_CAP_ID_SATA:
1237               printf("SATA HBA <?>\n");
1238               break;
1239             case PCI_CAP_ID_AF:
1240               printf("PCIe advanced features <?>\n");
1241               break;
1242             default:
1243               printf("#%02x [%04x]\n", id, cap);
1244             }
1245           where = next;
1246         }
1247     }
1248   if (can_have_ext_caps)
1249     show_ext_caps(d);
1250 }