ls-ecaps.c

   1 /*
   2  *      The PCI Utilities -- Show Extended Capabilities
   3  *
   4  *      Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_tph(struct device *d, int where)
  16 {
  17   u32 tph_cap;
  18   printf("Transaction Processing Hints\n");
  19   if (verbose < 2)
  20     return;
  21
  22   if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
  23     return;
  24
  25   tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
  26
  27   if (tph_cap & PCI_TPH_INTVEC_SUP)
  28     printf("\t\tInterrupt vector mode supported\n");
  29   if (tph_cap & PCI_TPH_DEV_SUP)
  30     printf("\t\tDevice specific mode supported\n");
  31   if (tph_cap & PCI_TPH_EXT_REQ_SUP)
  32     printf("\t\tExtended requester support\n");
  33
  34   switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
  35   case PCI_TPH_ST_NONE:
  36     printf("\t\tNo steering table available\n");
  37     break;
  38   case PCI_TPH_ST_CAP:
  39     printf("\t\tSteering table in TPH capability structure\n");
  40     break;
  41   case PCI_TPH_ST_MSIX:
  42     printf("\t\tSteering table in MSI-X table\n");
  43     break;
  44   default:
  45     printf("\t\tReserved steering table location\n");
  46     break;
  47   }
  48 }
  49
  50 static u32
  51 cap_ltr_scale(u8 scale)
  52 {
  53   return 1 << (scale * 5);
  54 }
  55
  56 static void
  57 cap_ltr(struct device *d, int where)
  58 {
  59   u32 scale;
  60   u16 snoop, nosnoop;
  61   printf("Latency Tolerance Reporting\n");
  62   if (verbose < 2)
  63     return;
  64
  65   if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
  66     return;
  67
  68   snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
  69   scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  70   printf("\t\tMax snoop latency: %lldns\n",
  71          ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
  72
  73   nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
  74   scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
  75   printf("\t\tMax no snoop latency: %lldns\n",
  76          ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
  77 }
  78
  79 static void
  80 cap_sec(struct device *d, int where)
  81 {
  82   u32 ctrl3, lane_err_stat;
  83   u8 lane;
  84   printf("Secondary PCI Express\n");
  85   if (verbose < 2)
  86     return;
  87
  88   if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
  89     return;
  90
  91   ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
  92   printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
  93         FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
  94         FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
  95
  96   lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
  97   printf("\t\tLaneErrStat: ");
  98   if (lane_err_stat)
  99     {
 100       printf("LaneErr at lane:");
 101       for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
 102         if (BITS(lane_err_stat, 0, 1))
 103           printf(" %u", lane);
 104     }
 105   else
 106     printf("0");
 107   printf("\n");
 108 }
 109
 110 static void
 111 cap_dsn(struct device *d, int where)
 112 {
 113   u32 t1, t2;
 114   if (!config_fetch(d, where + 4, 8))
 115     return;
 116   t1 = get_conf_long(d, where + 4);
 117   t2 = get_conf_long(d, where + 8);
 118   printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
 119         t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
 120         t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
 121 }
 122
 123 static void
 124 cap_aer(struct device *d, int where, int type)
 125 {
 126   u32 l, l0, l1, l2, l3;
 127   u16 w;
 128
 129   printf("Advanced Error Reporting\n");
 130   if (verbose < 2)
 131     return;
 132
 133   if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
 134     return;
 135
 136   l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
 137   printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 138         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 139         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 140         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 141         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 142         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 143   l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
 144   printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 145         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 146         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 147         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 148         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 149         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 150   l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
 151   printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
 152         "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
 153         FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
 154         FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
 155         FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 156         FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
 157   l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
 158   printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 159         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 160         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 161   l = get_conf_long(d, where + PCI_ERR_COR_MASK);
 162   printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 163         FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 164         FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
 165   l = get_conf_long(d, where + PCI_ERR_CAP);
 166   printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
 167         "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
 168         PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
 169         FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
 170         FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
 171         FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
 172
 173   l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
 174   l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
 175   l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
 176   l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
 177   printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
 178
 179   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
 180     {
 181       if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
 182         return;
 183
 184       l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
 185       printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
 186             FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
 187             FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
 188             FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
 189
 190       l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
 191       printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
 192             "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
 193             FLAG(l, PCI_ERR_ROOT_COR_RCV),
 194             FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
 195             FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
 196             FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
 197             FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
 198             FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
 199             FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
 200             PCI_ERR_MSG_NUM(l));
 201
 202       w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
 203       printf("\t\tErrorSrc: ERR_COR: %04x ", w);
 204
 205       w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
 206       printf("ERR_FATAL/NONFATAL: %04x\n", w);
 207     }
 208 }
 209
 210 static void cap_dpc(struct device *d, int where)
 211 {
 212   u16 l;
 213
 214   printf("Downstream Port Containment\n");
 215   if (verbose < 2)
 216     return;
 217
 218   if (!config_fetch(d, where + PCI_DPC_CAP, 8))
 219     return;
 220
 221   l = get_conf_word(d, where + PCI_DPC_CAP);
 222   printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
 223     PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
 224     FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
 225
 226   l = get_conf_word(d, where + PCI_DPC_CTL);
 227   printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
 228     PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
 229     FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
 230     FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
 231
 232   l = get_conf_word(d, where + PCI_DPC_STATUS);
 233   printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
 234     FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
 235     FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
 236
 237   l = get_conf_word(d, where + PCI_DPC_SOURCE);
 238   printf("\t\tSource:\t%04x\n", l);
 239 }
 240
 241 static void
 242 cap_acs(struct device *d, int where)
 243 {
 244   u16 w;
 245
 246   printf("Access Control Services\n");
 247   if (verbose < 2)
 248     return;
 249
 250   if (!config_fetch(d, where + PCI_ACS_CAP, 4))
 251     return;
 252
 253   w = get_conf_word(d, where + PCI_ACS_CAP);
 254   printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 255         "DirectTrans%c\n",
 256         FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
 257         FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
 258         FLAG(w, PCI_ACS_CAP_TRANS));
 259   w = get_conf_word(d, where + PCI_ACS_CTRL);
 260   printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
 261         "DirectTrans%c\n",
 262         FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
 263         FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
 264         FLAG(w, PCI_ACS_CTRL_TRANS));
 265 }
 266
 267 static void
 268 cap_ari(struct device *d, int where)
 269 {
 270   u16 w;
 271
 272   printf("Alternative Routing-ID Interpretation (ARI)\n");
 273   if (verbose < 2)
 274     return;
 275
 276   if (!config_fetch(d, where + PCI_ARI_CAP, 4))
 277     return;
 278
 279   w = get_conf_word(d, where + PCI_ARI_CAP);
 280   printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
 281         FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
 282         PCI_ARI_CAP_NFN(w));
 283   w = get_conf_word(d, where + PCI_ARI_CTRL);
 284   printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
 285         FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
 286         PCI_ARI_CTRL_FG(w));
 287 }
 288
 289 static void
 290 cap_ats(struct device *d, int where)
 291 {
 292   u16 w;
 293
 294   printf("Address Translation Service (ATS)\n");
 295   if (verbose < 2)
 296     return;
 297
 298   if (!config_fetch(d, where + PCI_ATS_CAP, 4))
 299     return;
 300
 301   w = get_conf_word(d, where + PCI_ATS_CAP);
 302   printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
 303   w = get_conf_word(d, where + PCI_ATS_CTRL);
 304   printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
 305         FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
 306 }
 307
 308 static void
 309 cap_pri(struct device *d, int where)
 310 {
 311   u16 w;
 312   u32 l;
 313
 314   printf("Page Request Interface (PRI)\n");
 315   if (verbose < 2)
 316     return;
 317
 318   if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
 319     return;
 320
 321   w = get_conf_word(d, where + PCI_PRI_CTRL);
 322   printf("\t\tPRICtl: Enable%c Reset%c\n",
 323         FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
 324   w = get_conf_word(d, where + PCI_PRI_STATUS);
 325   printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
 326         FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
 327         FLAG(w, PCI_PRI_STATUS_STOPPED));
 328   l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
 329   printf("\t\tPage Request Capacity: %08x, ", l);
 330   l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
 331   printf("Page Request Allocation: %08x\n", l);
 332 }
 333
 334 static void
 335 cap_pasid(struct device *d, int where)
 336 {
 337   u16 w;
 338
 339   printf("Process Address Space ID (PASID)\n");
 340   if (verbose < 2)
 341     return;
 342
 343   if (!config_fetch(d, where + PCI_PASID_CAP, 4))
 344     return;
 345
 346   w = get_conf_word(d, where + PCI_PASID_CAP);
 347   printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
 348         FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
 349         PCI_PASID_CAP_WIDTH(w));
 350   w = get_conf_word(d, where + PCI_PASID_CTRL);
 351   printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
 352         FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
 353         FLAG(w, PCI_PASID_CTRL_PRIV));
 354 }
 355
 356 static void
 357 cap_sriov(struct device *d, int where)
 358 {
 359   u16 b;
 360   u16 w;
 361   u32 l;
 362   int i;
 363
 364   printf("Single Root I/O Virtualization (SR-IOV)\n");
 365   if (verbose < 2)
 366     return;
 367
 368   if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
 369     return;
 370
 371   l = get_conf_long(d, where + PCI_IOV_CAP);
 372   printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
 373         FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
 374   w = get_conf_word(d, where + PCI_IOV_CTRL);
 375   printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
 376         FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
 377         FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
 378         FLAG(w, PCI_IOV_CTRL_ARI));
 379   w = get_conf_word(d, where + PCI_IOV_STATUS);
 380   printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
 381   w = get_conf_word(d, where + PCI_IOV_INITIALVF);
 382   printf("\t\tInitial VFs: %d, ", w);
 383   w = get_conf_word(d, where + PCI_IOV_TOTALVF);
 384   printf("Total VFs: %d, ", w);
 385   w = get_conf_word(d, where + PCI_IOV_NUMVF);
 386   printf("Number of VFs: %d, ", w);
 387   b = get_conf_byte(d, where + PCI_IOV_FDL);
 388   printf("Function Dependency Link: %02x\n", b);
 389   w = get_conf_word(d, where + PCI_IOV_OFFSET);
 390   printf("\t\tVF offset: %d, ", w);
 391   w = get_conf_word(d, where + PCI_IOV_STRIDE);
 392   printf("stride: %d, ", w);
 393   w = get_conf_word(d, where + PCI_IOV_DID);
 394   printf("Device ID: %04x\n", w);
 395   l = get_conf_long(d, where + PCI_IOV_SUPPS);
 396   printf("\t\tSupported Page Size: %08x, ", l);
 397   l = get_conf_long(d, where + PCI_IOV_SYSPS);
 398   printf("System Page Size: %08x\n", l);
 399
 400   for (i=0; i < PCI_IOV_NUM_BAR; i++)
 401     {
 402       u32 addr;
 403       int type;
 404       u32 h;
 405       l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
 406       if (l == 0xffffffff)
 407         l = 0;
 408       if (!l)
 409         continue;
 410       printf("\t\tRegion %d: Memory at ", i);
 411       addr = l & PCI_ADDR_MEM_MASK;
 412       type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 413       if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
 414         {
 415           i++;
 416           h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
 417           printf("%08x", h);
 418         }
 419       printf("%08x (%s-bit, %sprefetchable)\n",
 420         addr,
 421         (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
 422         (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
 423     }
 424
 425   l = get_conf_long(d, where + PCI_IOV_MSAO);
 426   printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
 427         PCI_IOV_MSA_BIR(l));
 428 }
 429
 430 static void
 431 cap_multicast(struct device *d, int where, int type)
 432 {
 433   u16 w;
 434   u32 l;
 435   u64 bar, rcv, block;
 436
 437   printf("Multicast\n");
 438   if (verbose < 2)
 439     return;
 440
 441   if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
 442     return;
 443
 444   w = get_conf_word(d, where + PCI_MCAST_CAP);
 445   printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
 446   if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
 447     printf(", WindowSz %d (%d bytes)",
 448       PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
 449   if (type == PCI_EXP_TYPE_ROOT_PORT ||
 450       type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
 451     printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
 452   w = get_conf_word(d, where + PCI_MCAST_CTRL);
 453   printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
 454     PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
 455   bar = get_conf_long(d, where + PCI_MCAST_BAR);
 456   l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
 457   bar |= (u64) l << 32;
 458   printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
 459     PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
 460   rcv = get_conf_long(d, where + PCI_MCAST_RCV);
 461   l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
 462   rcv |= (u64) l << 32;
 463   printf("\t\tMcastReceiveVec:      %016" PCI_U64_FMT_X "\n", rcv);
 464   block = get_conf_long(d, where + PCI_MCAST_BLOCK);
 465   l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
 466   block |= (u64) l << 32;
 467   printf("\t\tMcastBlockAllVec:     %016" PCI_U64_FMT_X "\n", block);
 468   block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
 469   l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
 470   block |= (u64) l << 32;
 471   printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
 472
 473   if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
 474     return;
 475   bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
 476   l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
 477   bar |= (u64) l << 32;
 478   printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
 479   if (PCI_MCAST_OVL_SIZE(bar) >= 6)
 480     printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
 481   else
 482     printf("(disabled)");
 483   printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
 484 }
 485
 486 static void
 487 cap_vc(struct device *d, int where)
 488 {
 489   u32 cr1, cr2;
 490   u16 ctrl, status;
 491   int evc_cnt;
 492   int arb_table_pos;
 493   int i, j;
 494   static const char ref_clocks[][6] = { "100ns" };
 495   static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
 496   static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
 497   char buf[8];
 498
 499   printf("Virtual Channel\n");
 500   if (verbose < 2)
 501     return;
 502
 503   if (!config_fetch(d, where + 4, 0x1c - 4))
 504     return;
 505
 506   cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
 507   cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
 508   ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
 509   status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
 510
 511   evc_cnt = BITS(cr1, 0, 3);
 512   printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
 513     BITS(cr1, 4, 3),
 514     TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
 515     1 << BITS(cr1, 10, 2));
 516
 517   printf("\t\tArb:");
 518   for (i=0; i<8; i++)
 519     if (arb_selects[i][0] != '?' || cr2 & (1 << i))
 520       printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
 521   arb_table_pos = BITS(cr2, 24, 8);
 522
 523   printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
 524   printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
 525
 526   if (arb_table_pos)
 527     {
 528       arb_table_pos = where + 16*arb_table_pos;
 529       printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
 530     }
 531
 532   for (i=0; i<=evc_cnt; i++)
 533     {
 534       int pos = where + PCI_VC_RES_CAP + 12*i;
 535       u32 rcap, rctrl;
 536       u16 rstatus;
 537       int pat_pos;
 538
 539       printf("\t\tVC%d:\t", i);
 540       if (!config_fetch(d, pos, 12))
 541         {
 542           printf("<unreadable>\n");
 543           continue;
 544         }
 545       rcap = get_conf_long(d, pos);
 546       rctrl = get_conf_long(d, pos+4);
 547       rstatus = get_conf_word(d, pos+10);
 548
 549       pat_pos = BITS(rcap, 24, 8);
 550       printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
 551         pat_pos,
 552         BITS(rcap, 16, 6) + 1,
 553         FLAG(rcap, 1 << 15));
 554
 555       printf("\t\t\tArb:");
 556       for (j=0; j<8; j++)
 557         if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
 558           printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
 559
 560       printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
 561         FLAG(rctrl, 1 << 31),
 562         BITS(rctrl, 24, 3),
 563         TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
 564         BITS(rctrl, 0, 8));
 565
 566       printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
 567         FLAG(rstatus, 2),
 568         FLAG(rstatus, 1));
 569
 570       if (pat_pos)
 571         printf("\t\t\tPort Arbitration Table <?>\n");
 572     }
 573 }
 574
 575 static void
 576 cap_rclink(struct device *d, int where)
 577 {
 578   u32 esd;
 579   int num_links;
 580   int i;
 581   static const char elt_types[][9] = { "Config", "Egress", "Internal" };
 582   char buf[8];
 583
 584   printf("Root Complex Link\n");
 585   if (verbose < 2)
 586     return;
 587
 588   if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
 589     return;
 590
 591   esd = get_conf_long(d, where + PCI_RCLINK_ESD);
 592   num_links = BITS(esd, 8, 8);
 593   printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
 594     BITS(esd, 24, 8),
 595     BITS(esd, 16, 8),
 596     TABLE(elt_types, BITS(esd, 0, 8), buf));
 597
 598   for (i=0; i<num_links; i++)
 599     {
 600       int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
 601       u32 desc;
 602       u32 addr_lo, addr_hi;
 603
 604       printf("\t\tLink%d:\t", i);
 605       if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
 606         {
 607           printf("<unreadable>\n");
 608           return;
 609         }
 610       desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
 611       addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
 612       addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
 613
 614       printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
 615         BITS(desc, 24, 8),
 616         BITS(desc, 16, 8),
 617         FLAG(desc, 4),
 618         ((desc & 2) ? "Config" : "MemMapped"),
 619         FLAG(desc, 1));
 620
 621       if (desc & 2)
 622         {
 623           int n = addr_lo & 7;
 624           if (!n)
 625             n = 8;
 626           printf("\t\t\tAddr:\t%02x:%02x.%d  CfgSpace=%08x%08x\n",
 627             BITS(addr_lo, 20, n),
 628             BITS(addr_lo, 15, 5),
 629             BITS(addr_lo, 12, 3),
 630             addr_hi, addr_lo);
 631         }
 632       else
 633         printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
 634     }
 635 }
 636
 637 static void
 638 cap_dvsec_cxl(struct device *d, int where)
 639 {
 640   u16 l;
 641
 642   printf(": CXL\n");
 643   if (verbose < 2)
 644     return;
 645
 646   if (!config_fetch(d, where + PCI_CXL_CAP, 12))
 647     return;
 648
 649   l = get_conf_word(d, where + PCI_CXL_CAP);
 650   printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
 651     FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM),
 652     FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL));
 653
 654   l = get_conf_word(d, where + PCI_CXL_CTRL);
 655   printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
 656     FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM),
 657     PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN),
 658     FLAG(l, PCI_CXL_CTRL_VIRAL));
 659
 660   l = get_conf_word(d, where + PCI_CXL_STATUS);
 661   printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL));
 662 }
 663
 664 static void
 665 cap_dvsec(struct device *d, int where)
 666 {
 667   printf("Designated Vendor-Specific: ");
 668   if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
 669     {
 670       printf("<unreadable>\n");
 671       return;
 672     }
 673
 674   u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
 675   u16 vendor = BITS(hdr, 0, 16);
 676   byte rev = BITS(hdr, 16, 4);
 677   u16 len = BITS(hdr, 20, 12);
 678
 679   u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
 680
 681   printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
 682   if (vendor == PCI_DVSEC_VENDOR_ID_CXL && id == PCI_DVSEC_ID_CXL && len >= 16)
 683     cap_dvsec_cxl(d, where);
 684   else
 685     printf(" <?>\n");
 686 }
 687
 688 static void
 689 cap_evendor(struct device *d, int where)
 690 {
 691   u32 hdr;
 692
 693   printf("Vendor Specific Information: ");
 694   if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
 695     {
 696       printf("<unreadable>\n");
 697       return;
 698     }
 699
 700   hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
 701   printf("ID=%04x Rev=%d Len=%03x <?>\n",
 702     BITS(hdr, 0, 16),
 703     BITS(hdr, 16, 4),
 704     BITS(hdr, 20, 12));
 705 }
 706
 707 static int l1pm_calc_pwron(int scale, int value)
 708 {
 709   switch (scale)
 710     {
 711       case 0:
 712         return 2 * value;
 713       case 1:
 714         return 10 * value;
 715       case 2:
 716         return 100 * value;
 717     }
 718   return -1;
 719 }
 720
 721 static void
 722 cap_l1pm(struct device *d, int where)
 723 {
 724   u32 l1_cap, val, scale;
 725   int time;
 726
 727   printf("L1 PM Substates\n");
 728
 729   if (verbose < 2)
 730     return;
 731
 732   if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
 733     {
 734       printf("\t\t<unreadable>\n");
 735       return;
 736     }
 737
 738   l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
 739   printf("\t\tL1SubCap: ");
 740   printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
 741     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
 742     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
 743     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
 744     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
 745     FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
 746
 747   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 748     {
 749       printf("\t\t\t  PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
 750       time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
 751       if (time != -1)
 752         printf("PortTPowerOnTime=%dus\n", time);
 753       else
 754         printf("PortTPowerOnTime=<error>\n");
 755     }
 756
 757   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
 758   printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
 759     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
 760     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
 761     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
 762     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
 763
 764   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 765     {
 766       printf("\t\t\t   T_CommonMode=%dus", BITS(val, 8, 8));
 767
 768       if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 769         {
 770           scale = BITS(val, 29, 3);
 771           if (scale > 5)
 772             printf(" LTR1.2_Threshold=<error>");
 773           else
 774             printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
 775         }
 776       printf("\n");
 777     }
 778
 779   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
 780   printf("\t\tL1SubCtl2:");
 781   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
 782     {
 783       time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
 784       if (time != -1)
 785         printf(" T_PwrOn=%dus", time);
 786       else
 787         printf(" T_PwrOn=<error>");
 788     }
 789   printf("\n");
 790 }
 791
 792 static void
 793 cap_ptm(struct device *d, int where)
 794 {
 795   u32 buff;
 796   u16 clock;
 797
 798   printf("Precision Time Measurement\n");
 799
 800   if (verbose < 2)
 801     return;
 802
 803   if (!config_fetch(d, where + 4, 8))
 804     {
 805       printf("\t\t<unreadable>\n");
 806       return;
 807     }
 808
 809   buff = get_conf_long(d, where + 4);
 810   printf("\t\tPTMCap: ");
 811   printf("Requester:%c Responder:%c Root:%c\n",
 812     FLAG(buff, 0x1),
 813     FLAG(buff, 0x2),
 814     FLAG(buff, 0x4));
 815
 816   clock = BITS(buff, 8, 8);
 817   printf("\t\tPTMClockGranularity: ");
 818   switch (clock)
 819     {
 820       case 0x00:
 821         printf("Unimplemented\n");
 822         break;
 823       case 0xff:
 824         printf("Greater than 254ns\n");
 825         break;
 826       default:
 827         printf("%huns\n", clock);
 828     }
 829
 830   buff = get_conf_long(d, where + 8);
 831   printf("\t\tPTMControl: ");
 832   printf("Enabled:%c RootSelected:%c\n",
 833     FLAG(buff, 0x1),
 834     FLAG(buff, 0x2));
 835
 836   clock = BITS(buff, 8, 8);
 837   printf("\t\tPTMEffectiveGranularity: ");
 838   switch (clock)
 839     {
 840       case 0x00:
 841         printf("Unknown\n");
 842         break;
 843       case 0xff:
 844         printf("Greater than 254ns\n");
 845         break;
 846       default:
 847         printf("%huns\n", clock);
 848     }
 849 }
 850
 851 static void
 852 print_rebar_range_size(int ld2_size)
 853 {
 854   // This function prints the input as a power-of-2 size value
 855   // It is biased with 1MB = 0, ...
 856   // Maximum resizable BAR value supported is 2^63 bytes = 43
 857   // for the extended resizable BAR capability definition
 858   // (otherwise it would stop at 2^28)
 859
 860   if (ld2_size >= 0 && ld2_size < 10)
 861     printf(" %dMB", (1 << ld2_size));
 862   else if (ld2_size >= 10 && ld2_size < 20)
 863     printf(" %dGB", (1 << (ld2_size-10)));
 864   else if (ld2_size >= 20 && ld2_size < 30)
 865     printf(" %dTB", (1 << (ld2_size-20)));
 866   else if (ld2_size >= 30 && ld2_size < 40)
 867     printf(" %dPB", (1 << (ld2_size-30)));
 868   else if (ld2_size >= 40 && ld2_size < 44)
 869     printf(" %dEB", (1 << (ld2_size-40)));
 870   else
 871     printf(" <unknown>");
 872 }
 873
 874 static void
 875 cap_rebar(struct device *d, int where, int virtual)
 876 {
 877   u32 sizes_buffer, control_buffer, ext_sizes, current_size;
 878   u16 bar_index, barcount, data_count;
 879   // If structure exists at least one bar is defined
 880   u16 num_bars = 1;
 881
 882   printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
 883
 884   if (verbose < 1)
 885     return;
 886
 887   // Go through all defined BAR definitions of the caps, at minimum 1
 888   // (loop also terminates if num_bars read from caps is > 6)
 889   for (barcount = 0; barcount < num_bars; barcount++)
 890     {
 891       where += 4;
 892
 893       // Get the next BAR configuration
 894       if (!config_fetch(d, where, 8))
 895         {
 896           printf("\t\t<unreadable>\n");
 897           return;
 898         }
 899
 900       sizes_buffer = get_conf_long(d, where) >> 4;
 901
 902       where += 4;
 903
 904       control_buffer = get_conf_long(d, where);
 905
 906       bar_index  = control_buffer & 0x07;
 907       current_size = (control_buffer >> 8) & 0x3f;
 908       ext_sizes = control_buffer >> 16;
 909
 910       if (barcount == 0)
 911         {
 912           // Only index 0 controlreg has the num_bar count definition
 913           num_bars = (control_buffer >> 5)  & 0x07;
 914           if (verbose == 1)
 915             {
 916               // Must be below or equal 6
 917               if (num_bars <= 6)
 918                 {
 919                   // Fewer resizable BARs than total supported BARs may be available,
 920                   // or the resizable BAR support may not start at BAR index 0.
 921                   // list how many resizable BARs are expected.
 922                   printf("\t\t%d resizable BAR%s available\n", num_bars, (num_bars == 1) ? "" : "s");
 923                 }
 924             }
 925             // If num_bars value is outside of the supported range, exit the parsing loop
 926             if (num_bars > 6)
 927               {
 928                 printf("\t\t<error in resizable BAR # value: %d is out of specification>", num_bars);
 929                 break;
 930               }
 931         }
 932
 933       // Resizable BAR list entry have an arbitrary index and current size
 934       printf("\t\tBAR %d, current size:", bar_index);
 935       print_rebar_range_size(current_size);
 936
 937       // Only print out the detail BAR sizes if vv is defined. Function modifies caps bits
 938       // to enumerate supported sizes, ext_sizes is only != 0 for devices with
 939       // extended resizable BAR capability, e.g. when > 128TB is needed
 940
 941       if ((verbose < 2) ||
 942           ((sizes_buffer == 0) && (ext_sizes == 0)))
 943         {
 944           printf("\n");
 945           continue;
 946         }
 947
 948       printf("\n\t\tsupported:");
 949
 950       for (data_count = 0; data_count < 28; data_count++)
 951         {
 952           if ((sizes_buffer & (1U << data_count)) != 0)
 953             {
 954               // Mark the supported size as processed
 955               sizes_buffer &= ~(1U << data_count);
 956               print_rebar_range_size(data_count);
 957             }
 958         }
 959
 960       // If a device needs > 128TB BAR, extended Resizable BAR feature is active and
 961       // ext_sizes is set. This is not common.
 962
 963       if (ext_sizes != 0)
 964         {
 965           for (data_count = 0; data_count < 16; data_count++)
 966             {
 967               if ((ext_sizes & (1U << data_count)) != 0)
 968                 {
 969                   // Mark the supported size as processed
 970                   ext_sizes &= ~(1U << data_count);
 971                   print_rebar_range_size((data_count + 28));
 972                 }
 973             }
 974         }
 975       printf("\n");
 976     }
 977 }
 978
 979 void
 980 show_ext_caps(struct device *d, int type)
 981 {
 982   int where = 0x100;
 983   char been_there[0x1000];
 984   memset(been_there, 0, 0x1000);
 985   do
 986     {
 987       u32 header;
 988       int id, version;
 989
 990       if (!config_fetch(d, where, 4))
 991         break;
 992       header = get_conf_long(d, where);
 993       if (!header)
 994         break;
 995       id = header & 0xffff;
 996       version = (header >> 16) & 0xf;
 997       printf("\tCapabilities: [%03x", where);
 998       if (verbose > 1)
 999         printf(" v%d", version);
1000       printf("] ");
1001       if (been_there[where]++)
1002         {
1003           printf("<chain looped>\n");
1004           break;
1005         }
1006       switch (id)
1007         {
1008           case PCI_EXT_CAP_ID_NULL:
1009             printf("Null\n");
1010             break;
1011           case PCI_EXT_CAP_ID_AER:
1012             cap_aer(d, where, type);
1013             break;
1014           case PCI_EXT_CAP_ID_DPC:
1015             cap_dpc(d, where);
1016             break;
1017           case PCI_EXT_CAP_ID_VC:
1018           case PCI_EXT_CAP_ID_VC2:
1019             cap_vc(d, where);
1020             break;
1021           case PCI_EXT_CAP_ID_DSN:
1022             cap_dsn(d, where);
1023             break;
1024           case PCI_EXT_CAP_ID_PB:
1025             printf("Power Budgeting <?>\n");
1026             break;
1027           case PCI_EXT_CAP_ID_RCLINK:
1028             cap_rclink(d, where);
1029             break;
1030           case PCI_EXT_CAP_ID_RCILINK:
1031             printf("Root Complex Internal Link <?>\n");
1032             break;
1033           case PCI_EXT_CAP_ID_RCECOLL:
1034             printf("Root Complex Event Collector <?>\n");
1035             break;
1036           case PCI_EXT_CAP_ID_MFVC:
1037             printf("Multi-Function Virtual Channel <?>\n");
1038             break;
1039           case PCI_EXT_CAP_ID_RCRB:
1040             printf("Root Complex Register Block <?>\n");
1041             break;
1042           case PCI_EXT_CAP_ID_VNDR:
1043             cap_evendor(d, where);
1044             break;
1045           case PCI_EXT_CAP_ID_ACS:
1046             cap_acs(d, where);
1047             break;
1048           case PCI_EXT_CAP_ID_ARI:
1049             cap_ari(d, where);
1050             break;
1051           case PCI_EXT_CAP_ID_ATS:
1052             cap_ats(d, where);
1053             break;
1054           case PCI_EXT_CAP_ID_SRIOV:
1055             cap_sriov(d, where);
1056             break;
1057           case PCI_EXT_CAP_ID_MRIOV:
1058             printf("Multi-Root I/O Virtualization <?>\n");
1059             break;
1060           case PCI_EXT_CAP_ID_MCAST:
1061             cap_multicast(d, where, type);
1062             break;
1063           case PCI_EXT_CAP_ID_PRI:
1064             cap_pri(d, where);
1065             break;
1066           case PCI_EXT_CAP_ID_REBAR:
1067             cap_rebar(d, where, 0);
1068             break;
1069           case PCI_EXT_CAP_ID_DPA:
1070             printf("Dynamic Power Allocation <?>\n");
1071             break;
1072           case PCI_EXT_CAP_ID_TPH:
1073             cap_tph(d, where);
1074             break;
1075           case PCI_EXT_CAP_ID_LTR:
1076             cap_ltr(d, where);
1077             break;
1078           case PCI_EXT_CAP_ID_SECPCI:
1079             cap_sec(d, where);
1080             break;
1081           case PCI_EXT_CAP_ID_PMUX:
1082             printf("Protocol Multiplexing <?>\n");
1083             break;
1084           case PCI_EXT_CAP_ID_PASID:
1085             cap_pasid(d, where);
1086             break;
1087           case PCI_EXT_CAP_ID_LNR:
1088             printf("LN Requester <?>\n");
1089             break;
1090           case PCI_EXT_CAP_ID_L1PM:
1091             cap_l1pm(d, where);
1092             break;
1093           case PCI_EXT_CAP_ID_PTM:
1094             cap_ptm(d, where);
1095             break;
1096           case PCI_EXT_CAP_ID_M_PCIE:
1097             printf("PCI Express over M_PHY <?>\n");
1098             break;
1099           case PCI_EXT_CAP_ID_FRS:
1100             printf("FRS Queueing <?>\n");
1101             break;
1102           case PCI_EXT_CAP_ID_RTR:
1103             printf("Readiness Time Reporting <?>\n");
1104             break;
1105           case PCI_EXT_CAP_ID_DVSEC:
1106             cap_dvsec(d, where);
1107             break;
1108           case PCI_EXT_CAP_ID_VF_REBAR:
1109             cap_rebar(d, where, 1);
1110             break;
1111           case PCI_EXT_CAP_ID_DLNK:
1112             printf("Data Link Feature <?>\n");
1113             break;
1114           case PCI_EXT_CAP_ID_16GT:
1115             printf("Physical Layer 16.0 GT/s <?>\n");
1116             break;
1117           case PCI_EXT_CAP_ID_LMR:
1118             printf("Lane Margining at the Receiver <?>\n");
1119             break;
1120           case PCI_EXT_CAP_ID_HIER_ID:
1121             printf("Hierarchy ID <?>\n");
1122             break;
1123           case PCI_EXT_CAP_ID_NPEM:
1124             printf("Native PCIe Enclosure Management <?>\n");
1125             break;
1126           default:
1127             printf("Extended Capability ID %#02x\n", id);
1128             break;
1129         }
1130       where = (header >> 20) & ~3;
1131     } while (where);
1132 }