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Subject: lspci: Display PASID required attribute in Page Status Register.
[thirdparty/pciutils.git] / ls-ecaps.c
1 /*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
4 * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13
14 #include "lspci.h"
15
16 static void
17 cap_tph(struct device *d, int where)
18 {
19 u32 tph_cap;
20 printf("Transaction Processing Hints\n");
21 if (verbose < 2)
22 return;
23
24 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
25 return;
26
27 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
28
29 if (tph_cap & PCI_TPH_INTVEC_SUP)
30 printf("\t\tInterrupt vector mode supported\n");
31 if (tph_cap & PCI_TPH_DEV_SUP)
32 printf("\t\tDevice specific mode supported\n");
33 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
34 printf("\t\tExtended requester support\n");
35
36 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
37 case PCI_TPH_ST_NONE:
38 printf("\t\tNo steering table available\n");
39 break;
40 case PCI_TPH_ST_CAP:
41 printf("\t\tSteering table in TPH capability structure\n");
42 break;
43 case PCI_TPH_ST_MSIX:
44 printf("\t\tSteering table in MSI-X table\n");
45 break;
46 default:
47 printf("\t\tReserved steering table location\n");
48 break;
49 }
50 }
51
52 static u32
53 cap_ltr_scale(u8 scale)
54 {
55 return 1 << (scale * 5);
56 }
57
58 static void
59 cap_ltr(struct device *d, int where)
60 {
61 u32 scale;
62 u16 snoop, nosnoop;
63 printf("Latency Tolerance Reporting\n");
64 if (verbose < 2)
65 return;
66
67 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
68 return;
69
70 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
71 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
72 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
73 ((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
74
75 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
76 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
77 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
78 ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
79 }
80
81 static void
82 cap_sec(struct device *d, int where)
83 {
84 u32 ctrl3, lane_err_stat;
85 u8 lane;
86 printf("Secondary PCI Express\n");
87 if (verbose < 2)
88 return;
89
90 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
91 return;
92
93 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
94 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
95 FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
96 FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
97
98 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
99 printf("\t\tLaneErrStat: ");
100 if (lane_err_stat)
101 {
102 printf("LaneErr at lane:");
103 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
104 if (BITS(lane_err_stat, 0, 1))
105 printf(" %u", lane);
106 }
107 else
108 printf("0");
109 printf("\n");
110 }
111
112 static void
113 cap_dsn(struct device *d, int where)
114 {
115 u32 t1, t2;
116 if (!config_fetch(d, where + 4, 8))
117 return;
118 t1 = get_conf_long(d, where + 4);
119 t2 = get_conf_long(d, where + 8);
120 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
121 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
122 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
123 }
124
125 static void
126 cap_aer(struct device *d, int where, int type)
127 {
128 u32 l, l0, l1, l2, l3;
129 u16 w;
130
131 printf("Advanced Error Reporting\n");
132 if (verbose < 2)
133 return;
134
135 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
136 return;
137
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
139 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
140 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
141 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
142 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
143 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
144 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
145 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
146 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
147 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
148 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
149 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
150 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
151 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
152 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
153 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
154 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
155 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
156 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
157 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
158 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
159 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
160 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
161 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
162 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
163 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
164 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
165 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
166 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
167 l = get_conf_long(d, where + PCI_ERR_CAP);
168 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
169 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
170 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
171 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
172 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
173 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
174
175 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
176 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
177 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
178 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
179 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
180
181 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
182 {
183 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
184 return;
185
186 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
187 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
188 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
189 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
190 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
191
192 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
193 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
194 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
195 FLAG(l, PCI_ERR_ROOT_COR_RCV),
196 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
197 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
198 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
199 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
200 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
201 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
202 PCI_ERR_MSG_NUM(l));
203
204 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
205 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
206
207 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
208 printf("ERR_FATAL/NONFATAL: %04x\n", w);
209 }
210 }
211
212 static void cap_dpc(struct device *d, int where)
213 {
214 u16 l;
215
216 printf("Downstream Port Containment\n");
217 if (verbose < 2)
218 return;
219
220 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
221 return;
222
223 l = get_conf_word(d, where + PCI_DPC_CAP);
224 printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
225 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
226 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
227
228 l = get_conf_word(d, where + PCI_DPC_CTL);
229 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
230 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
231 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
232 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
233
234 l = get_conf_word(d, where + PCI_DPC_STATUS);
235 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
236 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
237 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
238
239 l = get_conf_word(d, where + PCI_DPC_SOURCE);
240 printf("\t\tSource:\t%04x\n", l);
241 }
242
243 static void
244 cap_acs(struct device *d, int where)
245 {
246 u16 w;
247
248 printf("Access Control Services\n");
249 if (verbose < 2)
250 return;
251
252 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
253 return;
254
255 w = get_conf_word(d, where + PCI_ACS_CAP);
256 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
257 "DirectTrans%c\n",
258 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
259 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
260 FLAG(w, PCI_ACS_CAP_TRANS));
261 w = get_conf_word(d, where + PCI_ACS_CTRL);
262 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
263 "DirectTrans%c\n",
264 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
265 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
266 FLAG(w, PCI_ACS_CTRL_TRANS));
267 }
268
269 static void
270 cap_ari(struct device *d, int where)
271 {
272 u16 w;
273
274 printf("Alternative Routing-ID Interpretation (ARI)\n");
275 if (verbose < 2)
276 return;
277
278 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
279 return;
280
281 w = get_conf_word(d, where + PCI_ARI_CAP);
282 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
283 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
284 PCI_ARI_CAP_NFN(w));
285 w = get_conf_word(d, where + PCI_ARI_CTRL);
286 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
287 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
288 PCI_ARI_CTRL_FG(w));
289 }
290
291 static void
292 cap_ats(struct device *d, int where)
293 {
294 u16 w;
295
296 printf("Address Translation Service (ATS)\n");
297 if (verbose < 2)
298 return;
299
300 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
301 return;
302
303 w = get_conf_word(d, where + PCI_ATS_CAP);
304 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
305 w = get_conf_word(d, where + PCI_ATS_CTRL);
306 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
307 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
308 }
309
310 static void
311 cap_pri(struct device *d, int where)
312 {
313 u16 w;
314 u32 l;
315
316 printf("Page Request Interface (PRI)\n");
317 if (verbose < 2)
318 return;
319
320 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
321 return;
322
323 w = get_conf_word(d, where + PCI_PRI_CTRL);
324 printf("\t\tPRICtl: Enable%c Reset%c\n",
325 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
326 w = get_conf_word(d, where + PCI_PRI_STATUS);
327 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
328 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
329 FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID));
330 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
331 printf("\t\tPage Request Capacity: %08x, ", l);
332 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
333 printf("Page Request Allocation: %08x\n", l);
334 }
335
336 static void
337 cap_pasid(struct device *d, int where)
338 {
339 u16 w;
340
341 printf("Process Address Space ID (PASID)\n");
342 if (verbose < 2)
343 return;
344
345 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
346 return;
347
348 w = get_conf_word(d, where + PCI_PASID_CAP);
349 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
350 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
351 PCI_PASID_CAP_WIDTH(w));
352 w = get_conf_word(d, where + PCI_PASID_CTRL);
353 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
354 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
355 FLAG(w, PCI_PASID_CTRL_PRIV));
356 }
357
358 static void
359 cap_sriov(struct device *d, int where)
360 {
361 u16 b;
362 u16 w;
363 u32 l;
364 int i;
365
366 printf("Single Root I/O Virtualization (SR-IOV)\n");
367 if (verbose < 2)
368 return;
369
370 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
371 return;
372
373 l = get_conf_long(d, where + PCI_IOV_CAP);
374 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
375 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
376 w = get_conf_word(d, where + PCI_IOV_CTRL);
377 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
378 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
379 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
380 FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
381 w = get_conf_word(d, where + PCI_IOV_STATUS);
382 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
383 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
384 printf("\t\tInitial VFs: %d, ", w);
385 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
386 printf("Total VFs: %d, ", w);
387 w = get_conf_word(d, where + PCI_IOV_NUMVF);
388 printf("Number of VFs: %d, ", w);
389 b = get_conf_byte(d, where + PCI_IOV_FDL);
390 printf("Function Dependency Link: %02x\n", b);
391 w = get_conf_word(d, where + PCI_IOV_OFFSET);
392 printf("\t\tVF offset: %d, ", w);
393 w = get_conf_word(d, where + PCI_IOV_STRIDE);
394 printf("stride: %d, ", w);
395 w = get_conf_word(d, where + PCI_IOV_DID);
396 printf("Device ID: %04x\n", w);
397 l = get_conf_long(d, where + PCI_IOV_SUPPS);
398 printf("\t\tSupported Page Size: %08x, ", l);
399 l = get_conf_long(d, where + PCI_IOV_SYSPS);
400 printf("System Page Size: %08x\n", l);
401
402 for (i=0; i < PCI_IOV_NUM_BAR; i++)
403 {
404 u32 addr;
405 int type;
406 u32 h;
407 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
408 if (l == 0xffffffff)
409 l = 0;
410 if (!l)
411 continue;
412 printf("\t\tRegion %d: Memory at ", i);
413 addr = l & PCI_ADDR_MEM_MASK;
414 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
415 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
416 {
417 i++;
418 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
419 printf("%08x", h);
420 }
421 printf("%08x (%s-bit, %sprefetchable)\n",
422 addr,
423 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
424 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
425 }
426
427 l = get_conf_long(d, where + PCI_IOV_MSAO);
428 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
429 PCI_IOV_MSA_BIR(l));
430 }
431
432 static void
433 cap_multicast(struct device *d, int where, int type)
434 {
435 u16 w;
436 u32 l;
437 u64 bar, rcv, block;
438
439 printf("Multicast\n");
440 if (verbose < 2)
441 return;
442
443 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
444 return;
445
446 w = get_conf_word(d, where + PCI_MCAST_CAP);
447 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
448 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
449 printf(", WindowSz %d (%d bytes)",
450 PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
451 if (type == PCI_EXP_TYPE_ROOT_PORT ||
452 type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
453 printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
454 w = get_conf_word(d, where + PCI_MCAST_CTRL);
455 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
456 PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
457 bar = get_conf_long(d, where + PCI_MCAST_BAR);
458 l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
459 bar |= (u64) l << 32;
460 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
461 PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
462 rcv = get_conf_long(d, where + PCI_MCAST_RCV);
463 l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
464 rcv |= (u64) l << 32;
465 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
466 block = get_conf_long(d, where + PCI_MCAST_BLOCK);
467 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
468 block |= (u64) l << 32;
469 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
470 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
471 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
472 block |= (u64) l << 32;
473 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
474
475 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
476 return;
477 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
478 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
479 bar |= (u64) l << 32;
480 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
481 if (PCI_MCAST_OVL_SIZE(bar) >= 6)
482 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
483 else
484 printf("(disabled)");
485 printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
486 }
487
488 static void
489 cap_vc(struct device *d, int where)
490 {
491 u32 cr1, cr2;
492 u16 ctrl, status;
493 int evc_cnt;
494 int arb_table_pos;
495 int i, j;
496 static const char ref_clocks[][6] = { "100ns" };
497 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
498 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
499 char buf[8];
500
501 printf("Virtual Channel\n");
502 if (verbose < 2)
503 return;
504
505 if (!config_fetch(d, where + 4, 0x1c - 4))
506 return;
507
508 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
509 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
510 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
511 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
512
513 evc_cnt = BITS(cr1, 0, 3);
514 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
515 BITS(cr1, 4, 3),
516 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
517 1 << BITS(cr1, 10, 2));
518
519 printf("\t\tArb:");
520 for (i=0; i<8; i++)
521 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
522 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
523 arb_table_pos = BITS(cr2, 24, 8);
524
525 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
526 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
527
528 if (arb_table_pos)
529 {
530 arb_table_pos = where + 16*arb_table_pos;
531 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
532 }
533
534 for (i=0; i<=evc_cnt; i++)
535 {
536 int pos = where + PCI_VC_RES_CAP + 12*i;
537 u32 rcap, rctrl;
538 u16 rstatus;
539 int pat_pos;
540
541 printf("\t\tVC%d:\t", i);
542 if (!config_fetch(d, pos, 12))
543 {
544 printf("<unreadable>\n");
545 continue;
546 }
547 rcap = get_conf_long(d, pos);
548 rctrl = get_conf_long(d, pos+4);
549 rstatus = get_conf_word(d, pos+10);
550
551 pat_pos = BITS(rcap, 24, 8);
552 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
553 pat_pos,
554 BITS(rcap, 16, 7) + 1,
555 FLAG(rcap, 1 << 15));
556
557 printf("\t\t\tArb:");
558 for (j=0; j<8; j++)
559 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
560 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
561
562 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
563 FLAG(rctrl, 1 << 31),
564 BITS(rctrl, 24, 3),
565 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
566 BITS(rctrl, 0, 8));
567
568 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
569 FLAG(rstatus, 2),
570 FLAG(rstatus, 1));
571
572 if (pat_pos)
573 printf("\t\t\tPort Arbitration Table <?>\n");
574 }
575 }
576
577 static void
578 cap_rclink(struct device *d, int where)
579 {
580 u32 esd;
581 int num_links;
582 int i;
583 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
584 char buf[8];
585
586 printf("Root Complex Link\n");
587 if (verbose < 2)
588 return;
589
590 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
591 return;
592
593 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
594 num_links = BITS(esd, 8, 8);
595 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
596 BITS(esd, 24, 8),
597 BITS(esd, 16, 8),
598 TABLE(elt_types, BITS(esd, 0, 8), buf));
599
600 for (i=0; i<num_links; i++)
601 {
602 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
603 u32 desc;
604 u32 addr_lo, addr_hi;
605
606 printf("\t\tLink%d:\t", i);
607 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
608 {
609 printf("<unreadable>\n");
610 return;
611 }
612 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
613 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
614 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
615
616 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
617 BITS(desc, 24, 8),
618 BITS(desc, 16, 8),
619 FLAG(desc, 4),
620 ((desc & 2) ? "Config" : "MemMapped"),
621 FLAG(desc, 1));
622
623 if (desc & 2)
624 {
625 int n = addr_lo & 7;
626 if (!n)
627 n = 8;
628 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
629 BITS(addr_lo, 20, n),
630 BITS(addr_lo, 15, 5),
631 BITS(addr_lo, 12, 3),
632 addr_hi, addr_lo);
633 }
634 else
635 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
636 }
637 }
638
639 static void
640 cap_rcec(struct device *d, int where)
641 {
642 printf("Root Complex Event Collector Endpoint Association\n");
643 if (verbose < 2)
644 return;
645
646 if (!config_fetch(d, where, 12))
647 return;
648
649 u32 hdr = get_conf_long(d, where);
650 byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
651 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
652 printf("\t\tRCiEPBitmap: ");
653 if (bmap)
654 {
655 int prevmatched=0;
656 int adjcount=0;
657 int prevdev=0;
658 printf("RCiEP at Device(s):");
659 for (int dev=0; dev < 32; dev++)
660 {
661 if (BITS(bmap, dev, 1))
662 {
663 if (!adjcount)
664 printf("%s %u", (prevmatched) ? "," : "", dev);
665 adjcount++;
666 prevdev=dev;
667 prevmatched=1;
668 }
669 else
670 {
671 if (adjcount > 1)
672 printf("-%u", prevdev);
673 adjcount=0;
674 }
675 }
676 }
677 else
678 printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
679 printf("\n");
680
681 if (cap_ver < PCI_RCEC_BUSN_REG_VER)
682 return;
683
684 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
685 u8 lastbusn = BITS(busn, 16, 8);
686 u8 nextbusn = BITS(busn, 8, 8);
687
688 if ((lastbusn == 0x00) && (nextbusn == 0xff))
689 printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
690 else
691 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
692 }
693
694 static void
695 cxl_range(u64 base, u64 size, int n)
696 {
697 u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
698 const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
699 const char *class[] = { "DRAM", "Storage", "CDAT" };
700 u16 w;
701
702 w = (u16) size;
703
704 size &= ~0x0fffffffULL;
705
706 printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X"\n", n, base, base + size - 1);
707 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
708 FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
709 type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
710 interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
711 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
712 }
713
714 static void
715 dvsec_cxl_device(struct device *d, int rev, int where, int len)
716 {
717 u32 cache_size, cache_unit_size;
718 u64 range_base, range_size;
719 u16 w;
720
721 if (len < PCI_CXL_DEV_LEN)
722 return;
723
724 /* Legacy 1.1 revs aren't handled */
725 if (rev < 1)
726 return;
727
728 w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
729 printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
730 FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
731 FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
732
733 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
734 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
735 FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
736 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
737 FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
738
739 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
740 printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
741
742 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
743 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
744 FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
745
746 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
747 cache_unit_size = BITS(w, 0, 4);
748 cache_size = BITS(w, 8, 8);
749 switch (cache_unit_size)
750 {
751 case PCI_CXL_DEV_CAP2_CACHE_1M:
752 printf("\t\tCache Size: %08x\n", cache_size * (1<<20));
753 break;
754 case PCI_CXL_DEV_CAP2_CACHE_64K:
755 printf("\t\tCache Size: %08x\n", cache_size * (64<<10));
756 break;
757 case PCI_CXL_DEV_CAP2_CACHE_UNK:
758 printf("\t\tCache Size Not Reported\n");
759 break;
760 default:
761 printf("\t\tCache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
762 break;
763 }
764
765 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
766 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
767 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
768 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
769 cxl_range(range_base, range_size, 1);
770
771 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
772 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
773 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
774 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
775 cxl_range(range_base, range_size, 2);
776 }
777
778 static void
779 dvsec_cxl_port(struct device *d, int where, int len)
780 {
781 u16 w, m1, m2;
782 u8 b1, b2;
783
784 if (len < PCI_CXL_PORT_EXT_LEN)
785 return;
786
787 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
788 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
789
790 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
791 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
792 FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
793 FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
794 FLAG(w, PCI_CXL_PORT_VIRAL_EN));
795
796 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
797 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
798 printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
799 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
800 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
801 printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
802 }
803
804 static void
805 dvsec_cxl_register_locator(struct device *d, int where, int len)
806 {
807 static const char * const id_names[] = {
808 "empty",
809 "component registers",
810 "BAR virtualization",
811 "CXL device registers",
812 "CPMU registers",
813 };
814
815 for (int i=0; ; i++)
816 {
817 int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
818 if (pos + 7 >= where + len)
819 break;
820
821 u32 lo = get_conf_long(d, pos);
822 u32 hi = get_conf_long(d, pos + 4);
823
824 unsigned int bir = BITS(lo, 0, 3);
825 unsigned int block_id = BITS(lo, 8, 8);
826 u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
827
828 if (!block_id)
829 continue;
830
831 const char *id_name;
832 if (block_id < sizeof(id_names) / sizeof(*id_names))
833 id_name = id_names[block_id];
834 else if (block_id == 0xff)
835 id_name = "vendor-specific";
836 else
837 id_name = "<?>";
838
839 printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
840 }
841 }
842
843 static void
844 dvsec_cxl_gpf_device(struct device *d, int where)
845 {
846 u32 l;
847 u16 w, duration;
848 u8 time_base, time_scale;
849
850 w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
851 time_base = BITS(w, 0, 4);
852 time_scale = BITS(w, 8, 4);
853
854 switch (time_scale)
855 {
856 case PCI_CXL_GPF_DEV_100US:
857 case PCI_CXL_GPF_DEV_100MS:
858 duration = time_base * 100;
859 break;
860 case PCI_CXL_GPF_DEV_10US:
861 case PCI_CXL_GPF_DEV_10MS:
862 case PCI_CXL_GPF_DEV_10S:
863 duration = time_base * 10;
864 break;
865 case PCI_CXL_GPF_DEV_1US:
866 case PCI_CXL_GPF_DEV_1MS:
867 case PCI_CXL_GPF_DEV_1S:
868 duration = time_base;
869 break;
870 default:
871 /* Reserved */
872 printf("\t\tReserved time scale encoding %x\n", time_scale);
873 duration = time_base;
874 }
875
876 printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
877 (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
878 (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
879 (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
880
881 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
882 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
883 }
884
885 static void
886 dvsec_cxl_gpf_port(struct device *d, int where)
887 {
888 u16 w, timeout;
889 u8 time_base, time_scale;
890
891 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
892 time_base = BITS(w, 0, 4);
893 time_scale = BITS(w, 8, 4);
894
895 switch (time_scale)
896 {
897 case PCI_CXL_GPF_PORT_100US:
898 case PCI_CXL_GPF_PORT_100MS:
899 timeout = time_base * 100;
900 break;
901 case PCI_CXL_GPF_PORT_10US:
902 case PCI_CXL_GPF_PORT_10MS:
903 case PCI_CXL_GPF_PORT_10S:
904 timeout = time_base * 10;
905 break;
906 case PCI_CXL_GPF_PORT_1US:
907 case PCI_CXL_GPF_PORT_1MS:
908 case PCI_CXL_GPF_PORT_1S:
909 timeout = time_base;
910 break;
911 default:
912 /* Reserved */
913 printf("\t\tReserved time scale encoding %x\n", time_scale);
914 timeout = time_base;
915 }
916
917 printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
918 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
919 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
920 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
921
922 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
923 time_base = BITS(w, 0, 4);
924 time_scale = BITS(w, 8, 4);
925
926 switch (time_scale)
927 {
928 case PCI_CXL_GPF_PORT_100US:
929 case PCI_CXL_GPF_PORT_100MS:
930 timeout = time_base * 100;
931 break;
932 case PCI_CXL_GPF_PORT_10US:
933 case PCI_CXL_GPF_PORT_10MS:
934 case PCI_CXL_GPF_PORT_10S:
935 timeout = time_base * 10;
936 break;
937 case PCI_CXL_GPF_PORT_1US:
938 case PCI_CXL_GPF_PORT_1MS:
939 case PCI_CXL_GPF_PORT_1S:
940 timeout = time_base;
941 break;
942 default:
943 /* Reserved */
944 printf("\t\tReserved time scale encoding %x\n", time_scale);
945 timeout = time_base;
946 }
947
948 printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
949 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
950 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
951 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
952 }
953
954 static void
955 dvsec_cxl_flex_bus(struct device *d, int where, int rev)
956 {
957 u16 w;
958 u32 l, data;
959
960 if (rev < 1)
961 {
962 printf("\t\tRevision %d not supported\n", rev);
963 return;
964 }
965
966 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
967 printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
968 FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
969 FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
970 FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
971
972 if (rev > 1)
973 printf(" 256BFlit%c PBRFlit%c",
974 FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
975
976 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
977 printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
978 FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
979 FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
980 FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
981 FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
982 FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
983
984 if (rev > 1)
985 printf(" 256BFlit%c PBRFlit%c",
986 FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
987
988 w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
989 printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
990 FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
991 FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
992 FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
993 FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
994
995 if (rev > 1)
996 printf(" 256BFlit%c PBRFlit%c",
997 FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
998
999 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
1000 data = BITS(l, 0, 24);
1001 printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
1002
1003 if (rev > 1)
1004 {
1005 u8 nop;
1006
1007 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
1008 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
1009
1010 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
1011 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
1012
1013 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
1014 nop = BITS(l, 0, 2);
1015 printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
1016 }
1017 }
1018
1019 static void
1020 dvsec_cxl_mld(struct device *d, int where)
1021 {
1022 u16 w;
1023
1024 w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
1025
1026 /* Encodings greater than 16 are reserved */
1027 if (w && w <= PCI_CXL_MLD_MAX_LD)
1028 printf("\t\tNumLogDevs: %d\n", w);
1029 }
1030
1031 static void
1032 dvsec_cxl_function_map(struct device *d, int where)
1033 {
1034
1035 printf("\t\tFuncMap 0: %08x\n",
1036 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
1037
1038 printf("\t\tFuncMap 1: %08x\n",
1039 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
1040
1041 printf("\t\tFuncMap 2: %08x\n",
1042 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
1043
1044 printf("\t\tFuncMap 3: %08x\n",
1045 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
1046
1047 printf("\t\tFuncMap 4: %08x\n",
1048 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
1049
1050 printf("\t\tFuncMap 5: %08x\n",
1051 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
1052
1053 printf("\t\tFuncMap 6: %08x\n",
1054 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
1055
1056 printf("\t\tFuncMap 7: %08x\n",
1057 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
1058 }
1059
1060 static void
1061 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
1062 {
1063 printf(": CXL\n");
1064 if (verbose < 2)
1065 return;
1066
1067 if (!config_fetch(d, where, len))
1068 return;
1069
1070 switch (id)
1071 {
1072 case 0:
1073 dvsec_cxl_device(d, rev, where, len);
1074 break;
1075 case 2:
1076 dvsec_cxl_function_map(d, where);
1077 break;
1078 case 3:
1079 dvsec_cxl_port(d, where, len);
1080 break;
1081 case 4:
1082 dvsec_cxl_gpf_port(d, where);
1083 break;
1084 case 5:
1085 dvsec_cxl_gpf_device(d, where);
1086 break;
1087 case 7:
1088 dvsec_cxl_flex_bus(d, where, rev);
1089 break;
1090 case 8:
1091 dvsec_cxl_register_locator(d, where, len);
1092 break;
1093 case 9:
1094 dvsec_cxl_mld(d, where);
1095 break;
1096 default:
1097 printf("\t\tUnknown ID %04x\n", id);
1098 }
1099 }
1100
1101 static void
1102 cap_dvsec(struct device *d, int where)
1103 {
1104 printf("Designated Vendor-Specific: ");
1105 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
1106 {
1107 printf("<unreadable>\n");
1108 return;
1109 }
1110
1111 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
1112 u16 vendor = BITS(hdr, 0, 16);
1113 byte rev = BITS(hdr, 16, 4);
1114 u16 len = BITS(hdr, 20, 12);
1115
1116 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
1117
1118 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
1119 if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
1120 cap_dvsec_cxl(d, id, rev, where, len);
1121 else
1122 printf(" <?>\n");
1123 }
1124
1125 static void
1126 cap_evendor(struct device *d, int where)
1127 {
1128 u32 hdr;
1129
1130 printf("Vendor Specific Information: ");
1131 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
1132 {
1133 printf("<unreadable>\n");
1134 return;
1135 }
1136
1137 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
1138 printf("ID=%04x Rev=%d Len=%03x <?>\n",
1139 BITS(hdr, 0, 16),
1140 BITS(hdr, 16, 4),
1141 BITS(hdr, 20, 12));
1142 }
1143
1144 static int l1pm_calc_pwron(int scale, int value)
1145 {
1146 switch (scale)
1147 {
1148 case 0:
1149 return 2 * value;
1150 case 1:
1151 return 10 * value;
1152 case 2:
1153 return 100 * value;
1154 }
1155 return -1;
1156 }
1157
1158 static void
1159 cap_l1pm(struct device *d, int where)
1160 {
1161 u32 l1_cap, val, scale;
1162 int time;
1163
1164 printf("L1 PM Substates\n");
1165
1166 if (verbose < 2)
1167 return;
1168
1169 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
1170 {
1171 printf("\t\t<unreadable>\n");
1172 return;
1173 }
1174
1175 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
1176 printf("\t\tL1SubCap: ");
1177 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
1178 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
1179 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
1180 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
1181 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
1182 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
1183
1184 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1185 {
1186 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
1187 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
1188 if (time != -1)
1189 printf("PortTPowerOnTime=%dus\n", time);
1190 else
1191 printf("PortTPowerOnTime=<error>\n");
1192 }
1193
1194 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
1195 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
1196 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
1197 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
1198 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
1199 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
1200
1201 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1202 {
1203 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
1204
1205 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1206 {
1207 scale = BITS(val, 29, 3);
1208 if (scale > 5)
1209 printf(" LTR1.2_Threshold=<error>");
1210 else
1211 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale));
1212 }
1213 printf("\n");
1214 }
1215
1216 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
1217 printf("\t\tL1SubCtl2:");
1218 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1219 {
1220 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
1221 if (time != -1)
1222 printf(" T_PwrOn=%dus", time);
1223 else
1224 printf(" T_PwrOn=<error>");
1225 }
1226 printf("\n");
1227 }
1228
1229 static void
1230 cap_ptm(struct device *d, int where)
1231 {
1232 u32 buff;
1233 u16 clock;
1234
1235 printf("Precision Time Measurement\n");
1236
1237 if (verbose < 2)
1238 return;
1239
1240 if (!config_fetch(d, where + 4, 8))
1241 {
1242 printf("\t\t<unreadable>\n");
1243 return;
1244 }
1245
1246 buff = get_conf_long(d, where + 4);
1247 printf("\t\tPTMCap: ");
1248 printf("Requester%c Responder%c Root%c\n",
1249 FLAG(buff, 0x1),
1250 FLAG(buff, 0x2),
1251 FLAG(buff, 0x4));
1252
1253 clock = BITS(buff, 8, 8);
1254 printf("\t\tPTMClockGranularity: ");
1255 switch (clock)
1256 {
1257 case 0x00:
1258 printf("Unimplemented\n");
1259 break;
1260 case 0xff:
1261 printf("Greater than 254ns\n");
1262 break;
1263 default:
1264 printf("%huns\n", clock);
1265 }
1266
1267 buff = get_conf_long(d, where + 8);
1268 printf("\t\tPTMControl: ");
1269 printf("Enabled%c RootSelected%c\n",
1270 FLAG(buff, 0x1),
1271 FLAG(buff, 0x2));
1272
1273 clock = BITS(buff, 8, 8);
1274 printf("\t\tPTMEffectiveGranularity: ");
1275 switch (clock)
1276 {
1277 case 0x00:
1278 printf("Unknown\n");
1279 break;
1280 case 0xff:
1281 printf("Greater than 254ns\n");
1282 break;
1283 default:
1284 printf("%huns\n", clock);
1285 }
1286 }
1287
1288 static void
1289 print_rebar_range_size(int ld2_size)
1290 {
1291 // This function prints the input as a power-of-2 size value
1292 // It is biased with 1MB = 0, ...
1293 // Maximum resizable BAR value supported is 2^63 bytes = 43
1294 // for the extended resizable BAR capability definition
1295 // (otherwise it would stop at 2^28)
1296
1297 if (ld2_size >= 0 && ld2_size < 10)
1298 printf(" %dMB", (1 << ld2_size));
1299 else if (ld2_size >= 10 && ld2_size < 20)
1300 printf(" %dGB", (1 << (ld2_size-10)));
1301 else if (ld2_size >= 20 && ld2_size < 30)
1302 printf(" %dTB", (1 << (ld2_size-20)));
1303 else if (ld2_size >= 30 && ld2_size < 40)
1304 printf(" %dPB", (1 << (ld2_size-30)));
1305 else if (ld2_size >= 40 && ld2_size < 44)
1306 printf(" %dEB", (1 << (ld2_size-40)));
1307 else
1308 printf(" <unknown>");
1309 }
1310
1311 static void
1312 cap_rebar(struct device *d, int where, int virtual)
1313 {
1314 u32 sizes_buffer, control_buffer, ext_sizes, current_size;
1315 u16 bar_index, barcount, i;
1316 // If the structure exists, at least one bar is defined
1317 u16 num_bars = 1;
1318
1319 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1320
1321 if (verbose < 2)
1322 return;
1323
1324 // Go through all defined BAR definitions of the caps, at minimum 1
1325 // (loop also terminates if num_bars read from caps is > 6)
1326 for (barcount = 0; barcount < num_bars; barcount++)
1327 {
1328 where += 4;
1329
1330 // Get the next BAR configuration
1331 if (!config_fetch(d, where, 8))
1332 {
1333 printf("\t\t<unreadable>\n");
1334 return;
1335 }
1336
1337 sizes_buffer = get_conf_long(d, where) >> 4;
1338 where += 4;
1339 control_buffer = get_conf_long(d, where);
1340
1341 bar_index = BITS(control_buffer, 0, 3);
1342 current_size = BITS(control_buffer, 8, 6);
1343 ext_sizes = BITS(control_buffer, 16, 16);
1344
1345 if (barcount == 0)
1346 {
1347 // Only index 0 controlreg has the num_bar count definition
1348 num_bars = BITS(control_buffer, 5, 3);
1349 if (num_bars < 1 || num_bars > 6)
1350 {
1351 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars);
1352 break;
1353 }
1354 }
1355
1356 // Resizable BAR list entry have an arbitrary index and current size
1357 printf("\t\tBAR %d: current size:", bar_index);
1358 print_rebar_range_size(current_size);
1359
1360 if (sizes_buffer || ext_sizes)
1361 {
1362 printf(", supported:");
1363
1364 for (i=0; i<28; i++)
1365 if (sizes_buffer & (1U << i))
1366 print_rebar_range_size(i);
1367
1368 for (i=0; i<16; i++)
1369 if (ext_sizes & (1U << i))
1370 print_rebar_range_size(i + 28);
1371 }
1372
1373 printf("\n");
1374 }
1375 }
1376
1377 static void
1378 cap_doe(struct device *d, int where)
1379 {
1380 u32 l;
1381
1382 printf("Data Object Exchange\n");
1383
1384 if (verbose < 2)
1385 return;
1386
1387 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
1388 {
1389 printf("\t\t<unreadable>\n");
1390 return;
1391 }
1392
1393 l = get_conf_long(d, where + PCI_DOE_CAP);
1394 printf("\t\tDOECap: IntSup%c\n",
1395 FLAG(l, PCI_DOE_CAP_INT_SUPP));
1396 if (l & PCI_DOE_CAP_INT_SUPP)
1397 printf("\t\t\tIntMsgNum %d\n",
1398 PCI_DOE_CAP_INT_MSG(l));
1399
1400 l = get_conf_long(d, where + PCI_DOE_CTL);
1401 printf("\t\tDOECtl: IntEn%c\n",
1402 FLAG(l, PCI_DOE_CTL_INT));
1403
1404 l = get_conf_long(d, where + PCI_DOE_STS);
1405 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1406 FLAG(l, PCI_DOE_STS_BUSY),
1407 FLAG(l, PCI_DOE_STS_INT),
1408 FLAG(l, PCI_DOE_STS_ERROR),
1409 FLAG(l, PCI_DOE_STS_OBJECT_READY));
1410 }
1411
1412 void
1413 show_ext_caps(struct device *d, int type)
1414 {
1415 int where = 0x100;
1416 char been_there[0x1000];
1417 memset(been_there, 0, 0x1000);
1418 do
1419 {
1420 u32 header;
1421 int id, version;
1422
1423 if (!config_fetch(d, where, 4))
1424 break;
1425 header = get_conf_long(d, where);
1426 if (!header || header == 0xffffffff)
1427 break;
1428 id = header & 0xffff;
1429 version = (header >> 16) & 0xf;
1430 printf("\tCapabilities: [%03x", where);
1431 if (verbose > 1)
1432 printf(" v%d", version);
1433 printf("] ");
1434 if (been_there[where]++)
1435 {
1436 printf("<chain looped>\n");
1437 break;
1438 }
1439 switch (id)
1440 {
1441 case PCI_EXT_CAP_ID_NULL:
1442 printf("Null\n");
1443 break;
1444 case PCI_EXT_CAP_ID_AER:
1445 cap_aer(d, where, type);
1446 break;
1447 case PCI_EXT_CAP_ID_DPC:
1448 cap_dpc(d, where);
1449 break;
1450 case PCI_EXT_CAP_ID_VC:
1451 case PCI_EXT_CAP_ID_VC2:
1452 cap_vc(d, where);
1453 break;
1454 case PCI_EXT_CAP_ID_DSN:
1455 cap_dsn(d, where);
1456 break;
1457 case PCI_EXT_CAP_ID_PB:
1458 printf("Power Budgeting <?>\n");
1459 break;
1460 case PCI_EXT_CAP_ID_RCLINK:
1461 cap_rclink(d, where);
1462 break;
1463 case PCI_EXT_CAP_ID_RCILINK:
1464 printf("Root Complex Internal Link <?>\n");
1465 break;
1466 case PCI_EXT_CAP_ID_RCEC:
1467 cap_rcec(d, where);
1468 break;
1469 case PCI_EXT_CAP_ID_MFVC:
1470 printf("Multi-Function Virtual Channel <?>\n");
1471 break;
1472 case PCI_EXT_CAP_ID_RCRB:
1473 printf("Root Complex Register Block <?>\n");
1474 break;
1475 case PCI_EXT_CAP_ID_VNDR:
1476 cap_evendor(d, where);
1477 break;
1478 case PCI_EXT_CAP_ID_ACS:
1479 cap_acs(d, where);
1480 break;
1481 case PCI_EXT_CAP_ID_ARI:
1482 cap_ari(d, where);
1483 break;
1484 case PCI_EXT_CAP_ID_ATS:
1485 cap_ats(d, where);
1486 break;
1487 case PCI_EXT_CAP_ID_SRIOV:
1488 cap_sriov(d, where);
1489 break;
1490 case PCI_EXT_CAP_ID_MRIOV:
1491 printf("Multi-Root I/O Virtualization <?>\n");
1492 break;
1493 case PCI_EXT_CAP_ID_MCAST:
1494 cap_multicast(d, where, type);
1495 break;
1496 case PCI_EXT_CAP_ID_PRI:
1497 cap_pri(d, where);
1498 break;
1499 case PCI_EXT_CAP_ID_REBAR:
1500 cap_rebar(d, where, 0);
1501 break;
1502 case PCI_EXT_CAP_ID_DPA:
1503 printf("Dynamic Power Allocation <?>\n");
1504 break;
1505 case PCI_EXT_CAP_ID_TPH:
1506 cap_tph(d, where);
1507 break;
1508 case PCI_EXT_CAP_ID_LTR:
1509 cap_ltr(d, where);
1510 break;
1511 case PCI_EXT_CAP_ID_SECPCI:
1512 cap_sec(d, where);
1513 break;
1514 case PCI_EXT_CAP_ID_PMUX:
1515 printf("Protocol Multiplexing <?>\n");
1516 break;
1517 case PCI_EXT_CAP_ID_PASID:
1518 cap_pasid(d, where);
1519 break;
1520 case PCI_EXT_CAP_ID_LNR:
1521 printf("LN Requester <?>\n");
1522 break;
1523 case PCI_EXT_CAP_ID_L1PM:
1524 cap_l1pm(d, where);
1525 break;
1526 case PCI_EXT_CAP_ID_PTM:
1527 cap_ptm(d, where);
1528 break;
1529 case PCI_EXT_CAP_ID_M_PCIE:
1530 printf("PCI Express over M_PHY <?>\n");
1531 break;
1532 case PCI_EXT_CAP_ID_FRS:
1533 printf("FRS Queueing <?>\n");
1534 break;
1535 case PCI_EXT_CAP_ID_RTR:
1536 printf("Readiness Time Reporting <?>\n");
1537 break;
1538 case PCI_EXT_CAP_ID_DVSEC:
1539 cap_dvsec(d, where);
1540 break;
1541 case PCI_EXT_CAP_ID_VF_REBAR:
1542 cap_rebar(d, where, 1);
1543 break;
1544 case PCI_EXT_CAP_ID_DLNK:
1545 printf("Data Link Feature <?>\n");
1546 break;
1547 case PCI_EXT_CAP_ID_16GT:
1548 printf("Physical Layer 16.0 GT/s <?>\n");
1549 break;
1550 case PCI_EXT_CAP_ID_LMR:
1551 printf("Lane Margining at the Receiver <?>\n");
1552 break;
1553 case PCI_EXT_CAP_ID_HIER_ID:
1554 printf("Hierarchy ID <?>\n");
1555 break;
1556 case PCI_EXT_CAP_ID_NPEM:
1557 printf("Native PCIe Enclosure Management <?>\n");
1558 break;
1559 case PCI_EXT_CAP_ID_32GT:
1560 printf("Physical Layer 32.0 GT/s <?>\n");
1561 break;
1562 case PCI_EXT_CAP_ID_DOE:
1563 cap_doe(d, where);
1564 break;
1565 default:
1566 printf("Extended Capability ID %#02x\n", id);
1567 break;
1568 }
1569 where = (header >> 20) & ~3;
1570 } while (where);
1571 }
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